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intel_gtt.h revision 1.1.1.1
      1 /*	$NetBSD: intel_gtt.h,v 1.1.1.1 2021/12/18 20:15:32 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 /*
      5  * Copyright  2020 Intel Corporation
      6  *
      7  * Please try to maintain the following order within this file unless it makes
      8  * sense to do otherwise. From top to bottom:
      9  * 1. typedefs
     10  * 2. #defines, and macros
     11  * 3. structure definitions
     12  * 4. function prototypes
     13  *
     14  * Within each section, please try to order by generation in ascending order,
     15  * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
     16  */
     17 
     18 #ifndef __INTEL_GTT_H__
     19 #define __INTEL_GTT_H__
     20 
     21 #include <linux/io-mapping.h>
     22 #include <linux/kref.h>
     23 #include <linux/mm.h>
     24 #include <linux/pagevec.h>
     25 #include <linux/scatterlist.h>
     26 #include <linux/workqueue.h>
     27 
     28 #include <drm/drm_mm.h>
     29 
     30 #include "gt/intel_reset.h"
     31 #include "i915_gem_fence_reg.h"
     32 #include "i915_selftest.h"
     33 #include "i915_vma_types.h"
     34 
     35 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
     36 
     37 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
     38 #define DBG(...) trace_printk(__VA_ARGS__)
     39 #else
     40 #define DBG(...)
     41 #endif
     42 
     43 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
     44 
     45 #define I915_GTT_PAGE_SIZE_4K	BIT_ULL(12)
     46 #define I915_GTT_PAGE_SIZE_64K	BIT_ULL(16)
     47 #define I915_GTT_PAGE_SIZE_2M	BIT_ULL(21)
     48 
     49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
     50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
     51 
     52 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
     53 
     54 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
     55 
     56 #define I915_FENCE_REG_NONE -1
     57 #define I915_MAX_NUM_FENCES 32
     58 /* 32 fences + sign bit for FENCE_REG_NONE */
     59 #define I915_MAX_NUM_FENCE_BITS 6
     60 
     61 typedef u32 gen6_pte_t;
     62 typedef u64 gen8_pte_t;
     63 
     64 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
     65 
     66 #define I915_PTES(pte_len)		((unsigned int)(PAGE_SIZE / (pte_len)))
     67 #define I915_PTE_MASK(pte_len)		(I915_PTES(pte_len) - 1)
     68 #define I915_PDES			512
     69 #define I915_PDE_MASK			(I915_PDES - 1)
     70 
     71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
     72 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
     73 #define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
     74 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
     75 #define GEN6_PTE_CACHE_LLC		(2 << 1)
     76 #define GEN6_PTE_UNCACHED		(1 << 1)
     77 #define GEN6_PTE_VALID			REG_BIT(0)
     78 
     79 #define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
     80 #define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
     81 #define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
     82 #define GEN6_PDE_SHIFT			22
     83 #define GEN6_PDE_VALID			REG_BIT(0)
     84 #define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))
     85 
     86 #define GEN7_PTE_CACHE_L3_LLC		(3 << 1)
     87 
     88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES	REG_BIT(2)
     89 #define BYT_PTE_WRITEABLE		REG_BIT(1)
     90 
     91 /*
     92  * Cacheability Control is a 4-bit value. The low three bits are stored in bits
     93  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
     94  */
     95 #define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
     96 					 (((bits) & 0x8) << (11 - 3)))
     97 #define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
     98 #define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
     99 #define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
    100 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
    101 #define HSW_WT_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x7)
    102 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
    103 #define HSW_PTE_UNCACHED		(0)
    104 #define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
    105 #define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)
    106 
    107 /*
    108  * GEN8 32b style address is defined as a 3 level page table:
    109  * 31:30 | 29:21 | 20:12 |  11:0
    110  * PDPE  |  PDE  |  PTE  | offset
    111  * The difference as compared to normal x86 3 level page table is the PDPEs are
    112  * programmed via register.
    113  *
    114  * GEN8 48b style address is defined as a 4 level page table:
    115  * 47:39 | 38:30 | 29:21 | 20:12 |  11:0
    116  * PML4E | PDPE  |  PDE  |  PTE  | offset
    117  */
    118 #define GEN8_3LVL_PDPES			4
    119 
    120 #define PPAT_UNCACHED			(_PAGE_PWT | _PAGE_PCD)
    121 #define PPAT_CACHED_PDE			0 /* WB LLC */
    122 #define PPAT_CACHED			_PAGE_PAT /* WB LLCeLLC */
    123 #define PPAT_DISPLAY_ELLC		_PAGE_PCD /* WT eLLC */
    124 
    125 #define CHV_PPAT_SNOOP			REG_BIT(6)
    126 #define GEN8_PPAT_AGE(x)		((x)<<4)
    127 #define GEN8_PPAT_LLCeLLC		(3<<2)
    128 #define GEN8_PPAT_LLCELLC		(2<<2)
    129 #define GEN8_PPAT_LLC			(1<<2)
    130 #define GEN8_PPAT_WB			(3<<0)
    131 #define GEN8_PPAT_WT			(2<<0)
    132 #define GEN8_PPAT_WC			(1<<0)
    133 #define GEN8_PPAT_UC			(0<<0)
    134 #define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
    135 #define GEN8_PPAT(i, x)			((u64)(x) << ((i) * 8))
    136 
    137 #define GEN8_PDE_IPS_64K BIT(11)
    138 #define GEN8_PDE_PS_2M   BIT(7)
    139 
    140 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
    141 	__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
    142 
    143 struct i915_page_dma {
    144 	struct page *page;
    145 	union {
    146 		dma_addr_t daddr;
    147 
    148 		/*
    149 		 * For gen6/gen7 only. This is the offset in the GGTT
    150 		 * where the page directory entries for PPGTT begin
    151 		 */
    152 		u32 ggtt_offset;
    153 	};
    154 };
    155 
    156 struct i915_page_scratch {
    157 	struct i915_page_dma base;
    158 	u64 encode;
    159 };
    160 
    161 struct i915_page_table {
    162 	struct i915_page_dma base;
    163 	atomic_t used;
    164 };
    165 
    166 struct i915_page_directory {
    167 	struct i915_page_table pt;
    168 	spinlock_t lock;
    169 	void *entry[512];
    170 };
    171 
    172 #define __px_choose_expr(x, type, expr, other) \
    173 	__builtin_choose_expr( \
    174 	__builtin_types_compatible_p(typeof(x), type) || \
    175 	__builtin_types_compatible_p(typeof(x), const type), \
    176 	({ type __x = (type)(x); expr; }), \
    177 	other)
    178 
    179 #define px_base(px) \
    180 	__px_choose_expr(px, struct i915_page_dma *, __x, \
    181 	__px_choose_expr(px, struct i915_page_scratch *, &__x->base, \
    182 	__px_choose_expr(px, struct i915_page_table *, &__x->base, \
    183 	__px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \
    184 	(void)0))))
    185 #define px_dma(px) (px_base(px)->daddr)
    186 
    187 #define px_pt(px) \
    188 	__px_choose_expr(px, struct i915_page_table *, __x, \
    189 	__px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
    190 	(void)0))
    191 #define px_used(px) (&px_pt(px)->used)
    192 
    193 enum i915_cache_level;
    194 
    195 struct drm_i915_file_private;
    196 struct drm_i915_gem_object;
    197 struct i915_vma;
    198 struct intel_gt;
    199 
    200 struct i915_vma_ops {
    201 	/* Map an object into an address space with the given cache flags. */
    202 	int (*bind_vma)(struct i915_vma *vma,
    203 			enum i915_cache_level cache_level,
    204 			u32 flags);
    205 	/*
    206 	 * Unmap an object from an address space. This usually consists of
    207 	 * setting the valid PTE entries to a reserved scratch page.
    208 	 */
    209 	void (*unbind_vma)(struct i915_vma *vma);
    210 
    211 	int (*set_pages)(struct i915_vma *vma);
    212 	void (*clear_pages)(struct i915_vma *vma);
    213 };
    214 
    215 struct pagestash {
    216 	spinlock_t lock;
    217 	struct pagevec pvec;
    218 };
    219 
    220 void stash_init(struct pagestash *stash);
    221 
    222 struct i915_address_space {
    223 	struct kref ref;
    224 	struct rcu_work rcu;
    225 
    226 	struct drm_mm mm;
    227 	struct intel_gt *gt;
    228 	struct drm_i915_private *i915;
    229 	struct device *dma;
    230 	/*
    231 	 * Every address space belongs to a struct file - except for the global
    232 	 * GTT that is owned by the driver (and so @file is set to NULL). In
    233 	 * principle, no information should leak from one context to another
    234 	 * (or between files/processes etc) unless explicitly shared by the
    235 	 * owner. Tracking the owner is important in order to free up per-file
    236 	 * objects along with the file, to aide resource tracking, and to
    237 	 * assign blame.
    238 	 */
    239 	struct drm_i915_file_private *file;
    240 	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */
    241 	u64 reserved;		/* size addr space reserved */
    242 
    243 	unsigned int bind_async_flags;
    244 
    245 	/*
    246 	 * Each active user context has its own address space (in full-ppgtt).
    247 	 * Since the vm may be shared between multiple contexts, we count how
    248 	 * many contexts keep us "open". Once open hits zero, we are closed
    249 	 * and do not allow any new attachments, and proceed to shutdown our
    250 	 * vma and page directories.
    251 	 */
    252 	atomic_t open;
    253 
    254 	struct mutex mutex; /* protects vma and our lists */
    255 #define VM_CLASS_GGTT 0
    256 #define VM_CLASS_PPGTT 1
    257 
    258 	struct i915_page_scratch scratch[4];
    259 	unsigned int scratch_order;
    260 	unsigned int top;
    261 
    262 	/**
    263 	 * List of vma currently bound.
    264 	 */
    265 	struct list_head bound_list;
    266 
    267 	struct pagestash free_pages;
    268 
    269 	/* Global GTT */
    270 	bool is_ggtt:1;
    271 
    272 	/* Some systems require uncached updates of the page directories */
    273 	bool pt_kmap_wc:1;
    274 
    275 	/* Some systems support read-only mappings for GGTT and/or PPGTT */
    276 	bool has_read_only:1;
    277 
    278 	u64 (*pte_encode)(dma_addr_t addr,
    279 			  enum i915_cache_level level,
    280 			  u32 flags); /* Create a valid PTE */
    281 #define PTE_READ_ONLY	BIT(0)
    282 
    283 	int (*allocate_va_range)(struct i915_address_space *vm,
    284 				 u64 start, u64 length);
    285 	void (*clear_range)(struct i915_address_space *vm,
    286 			    u64 start, u64 length);
    287 	void (*insert_page)(struct i915_address_space *vm,
    288 			    dma_addr_t addr,
    289 			    u64 offset,
    290 			    enum i915_cache_level cache_level,
    291 			    u32 flags);
    292 	void (*insert_entries)(struct i915_address_space *vm,
    293 			       struct i915_vma *vma,
    294 			       enum i915_cache_level cache_level,
    295 			       u32 flags);
    296 	void (*cleanup)(struct i915_address_space *vm);
    297 
    298 	struct i915_vma_ops vma_ops;
    299 
    300 	I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
    301 	I915_SELFTEST_DECLARE(bool scrub_64K);
    302 };
    303 
    304 /*
    305  * The Graphics Translation Table is the way in which GEN hardware translates a
    306  * Graphics Virtual Address into a Physical Address. In addition to the normal
    307  * collateral associated with any va->pa translations GEN hardware also has a
    308  * portion of the GTT which can be mapped by the CPU and remain both coherent
    309  * and correct (in cases like swizzling). That region is referred to as GMADR in
    310  * the spec.
    311  */
    312 struct i915_ggtt {
    313 	struct i915_address_space vm;
    314 
    315 	struct io_mapping iomap;	/* Mapping to our CPU mappable region */
    316 	struct resource gmadr;          /* GMADR resource */
    317 	resource_size_t mappable_end;	/* End offset that we can CPU map */
    318 
    319 	/** "Graphics Stolen Memory" holds the global PTEs */
    320 	void __iomem *gsm;
    321 	void (*invalidate)(struct i915_ggtt *ggtt);
    322 
    323 	/** PPGTT used for aliasing the PPGTT with the GTT */
    324 	struct i915_ppgtt *alias;
    325 
    326 	bool do_idle_maps;
    327 
    328 	int mtrr;
    329 
    330 	/** Bit 6 swizzling required for X tiling */
    331 	u32 bit_6_swizzle_x;
    332 	/** Bit 6 swizzling required for Y tiling */
    333 	u32 bit_6_swizzle_y;
    334 
    335 	u32 pin_bias;
    336 
    337 	unsigned int num_fences;
    338 	struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
    339 	struct list_head fence_list;
    340 
    341 	/**
    342 	 * List of all objects in gtt_space, currently mmaped by userspace.
    343 	 * All objects within this list must also be on bound_list.
    344 	 */
    345 	struct list_head userfault_list;
    346 
    347 	/* Manual runtime pm autosuspend delay for user GGTT mmaps */
    348 	struct intel_wakeref_auto userfault_wakeref;
    349 
    350 	struct mutex error_mutex;
    351 	struct drm_mm_node error_capture;
    352 	struct drm_mm_node uc_fw;
    353 };
    354 
    355 struct i915_ppgtt {
    356 	struct i915_address_space vm;
    357 
    358 	struct i915_page_directory *pd;
    359 };
    360 
    361 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
    362 
    363 static inline bool
    364 i915_vm_is_4lvl(const struct i915_address_space *vm)
    365 {
    366 	return (vm->total - 1) >> 32;
    367 }
    368 
    369 static inline bool
    370 i915_vm_has_scratch_64K(struct i915_address_space *vm)
    371 {
    372 	return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
    373 }
    374 
    375 static inline bool
    376 i915_vm_has_cache_coloring(struct i915_address_space *vm)
    377 {
    378 	return i915_is_ggtt(vm) && vm->mm.color_adjust;
    379 }
    380 
    381 static inline struct i915_ggtt *
    382 i915_vm_to_ggtt(struct i915_address_space *vm)
    383 {
    384 	BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
    385 	GEM_BUG_ON(!i915_is_ggtt(vm));
    386 	return container_of(vm, struct i915_ggtt, vm);
    387 }
    388 
    389 static inline struct i915_ppgtt *
    390 i915_vm_to_ppgtt(struct i915_address_space *vm)
    391 {
    392 	BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
    393 	GEM_BUG_ON(i915_is_ggtt(vm));
    394 	return container_of(vm, struct i915_ppgtt, vm);
    395 }
    396 
    397 static inline struct i915_address_space *
    398 i915_vm_get(struct i915_address_space *vm)
    399 {
    400 	kref_get(&vm->ref);
    401 	return vm;
    402 }
    403 
    404 void i915_vm_release(struct kref *kref);
    405 
    406 static inline void i915_vm_put(struct i915_address_space *vm)
    407 {
    408 	kref_put(&vm->ref, i915_vm_release);
    409 }
    410 
    411 static inline struct i915_address_space *
    412 i915_vm_open(struct i915_address_space *vm)
    413 {
    414 	GEM_BUG_ON(!atomic_read(&vm->open));
    415 	atomic_inc(&vm->open);
    416 	return i915_vm_get(vm);
    417 }
    418 
    419 static inline bool
    420 i915_vm_tryopen(struct i915_address_space *vm)
    421 {
    422 	if (atomic_add_unless(&vm->open, 1, 0))
    423 		return i915_vm_get(vm);
    424 
    425 	return false;
    426 }
    427 
    428 void __i915_vm_close(struct i915_address_space *vm);
    429 
    430 static inline void
    431 i915_vm_close(struct i915_address_space *vm)
    432 {
    433 	GEM_BUG_ON(!atomic_read(&vm->open));
    434 	if (atomic_dec_and_test(&vm->open))
    435 		__i915_vm_close(vm);
    436 
    437 	i915_vm_put(vm);
    438 }
    439 
    440 void i915_address_space_init(struct i915_address_space *vm, int subclass);
    441 void i915_address_space_fini(struct i915_address_space *vm);
    442 
    443 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
    444 {
    445 	const u32 mask = NUM_PTE(pde_shift) - 1;
    446 
    447 	return (address >> PAGE_SHIFT) & mask;
    448 }
    449 
    450 /*
    451  * Helper to counts the number of PTEs within the given length. This count
    452  * does not cross a page table boundary, so the max value would be
    453  * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
    454  */
    455 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
    456 {
    457 	const u64 mask = ~((1ULL << pde_shift) - 1);
    458 	u64 end;
    459 
    460 	GEM_BUG_ON(length == 0);
    461 	GEM_BUG_ON(offset_in_page(addr | length));
    462 
    463 	end = addr + length;
    464 
    465 	if ((addr & mask) != (end & mask))
    466 		return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
    467 
    468 	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
    469 }
    470 
    471 static inline u32 i915_pde_index(u64 addr, u32 shift)
    472 {
    473 	return (addr >> shift) & I915_PDE_MASK;
    474 }
    475 
    476 static inline struct i915_page_table *
    477 i915_pt_entry(const struct i915_page_directory * const pd,
    478 	      const unsigned short n)
    479 {
    480 	return pd->entry[n];
    481 }
    482 
    483 static inline struct i915_page_directory *
    484 i915_pd_entry(const struct i915_page_directory * const pdp,
    485 	      const unsigned short n)
    486 {
    487 	return pdp->entry[n];
    488 }
    489 
    490 static inline dma_addr_t
    491 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
    492 {
    493 	struct i915_page_dma *pt = ppgtt->pd->entry[n];
    494 
    495 	return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top]));
    496 }
    497 
    498 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
    499 
    500 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
    501 int i915_ggtt_init_hw(struct drm_i915_private *i915);
    502 int i915_ggtt_enable_hw(struct drm_i915_private *i915);
    503 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
    504 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
    505 int i915_init_ggtt(struct drm_i915_private *i915);
    506 void i915_ggtt_driver_release(struct drm_i915_private *i915);
    507 
    508 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
    509 {
    510 	return ggtt->mappable_end > 0;
    511 }
    512 
    513 int i915_ppgtt_init_hw(struct intel_gt *gt);
    514 
    515 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
    516 
    517 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *i915);
    518 void i915_gem_restore_gtt_mappings(struct drm_i915_private *i915);
    519 
    520 u64 gen8_pte_encode(dma_addr_t addr,
    521 		    enum i915_cache_level level,
    522 		    u32 flags);
    523 
    524 int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
    525 void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
    526 
    527 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
    528 
    529 void
    530 fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count);
    531 
    532 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
    533 #define fill32_px(px, v) do {						\
    534 	u64 v__ = lower_32_bits(v);					\
    535 	fill_px((px), v__ << 32 | v__);					\
    536 } while (0)
    537 
    538 int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp);
    539 void cleanup_scratch_page(struct i915_address_space *vm);
    540 void free_scratch(struct i915_address_space *vm);
    541 
    542 struct i915_page_table *alloc_pt(struct i915_address_space *vm);
    543 struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
    544 struct i915_page_directory *__alloc_pd(size_t sz);
    545 
    546 void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd);
    547 
    548 #define free_px(vm, px) free_pd(vm, px_base(px))
    549 
    550 void
    551 __set_pd_entry(struct i915_page_directory * const pd,
    552 	       const unsigned short idx,
    553 	       struct i915_page_dma * const to,
    554 	       u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
    555 
    556 #define set_pd_entry(pd, idx, to) \
    557 	__set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode)
    558 
    559 void
    560 clear_pd_entry(struct i915_page_directory * const pd,
    561 	       const unsigned short idx,
    562 	       const struct i915_page_scratch * const scratch);
    563 
    564 bool
    565 release_pd_entry(struct i915_page_directory * const pd,
    566 		 const unsigned short idx,
    567 		 struct i915_page_table * const pt,
    568 		 const struct i915_page_scratch * const scratch);
    569 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
    570 
    571 int ggtt_set_pages(struct i915_vma *vma);
    572 int ppgtt_set_pages(struct i915_vma *vma);
    573 void clear_pages(struct i915_vma *vma);
    574 
    575 void gtt_write_workarounds(struct intel_gt *gt);
    576 
    577 void setup_private_pat(struct intel_uncore *uncore);
    578 
    579 static inline struct sgt_dma {
    580 	struct scatterlist *sg;
    581 	dma_addr_t dma, max;
    582 } sgt_dma(struct i915_vma *vma) {
    583 	struct scatterlist *sg = vma->pages->sgl;
    584 	dma_addr_t addr = sg_dma_address(sg);
    585 
    586 	return (struct sgt_dma){ sg, addr, addr + sg->length };
    587 }
    588 
    589 #endif
    590