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      1  1.1  riastrad /*	$NetBSD: intel_renderstate.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $	*/
      2  1.1  riastrad 
      3  1.1  riastrad /*
      4  1.1  riastrad  * Copyright  2014 Intel Corporation
      5  1.1  riastrad  *
      6  1.1  riastrad  * Permission is hereby granted, free of charge, to any person obtaining a
      7  1.1  riastrad  * copy of this software and associated documentation files (the "Software"),
      8  1.1  riastrad  * to deal in the Software without restriction, including without limitation
      9  1.1  riastrad  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  1.1  riastrad  * and/or sell copies of the Software, and to permit persons to whom the
     11  1.1  riastrad  * Software is furnished to do so, subject to the following conditions:
     12  1.1  riastrad  *
     13  1.1  riastrad  * The above copyright notice and this permission notice (including the next
     14  1.1  riastrad  * paragraph) shall be included in all copies or substantial portions of the
     15  1.1  riastrad  * Software.
     16  1.1  riastrad  *
     17  1.1  riastrad  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  1.1  riastrad  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  1.1  riastrad  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  1.1  riastrad  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  1.1  riastrad  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     22  1.1  riastrad  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
     23  1.1  riastrad  * IN THE SOFTWARE.
     24  1.1  riastrad  *
     25  1.1  riastrad  * Authors:
     26  1.1  riastrad  *    Mika Kuoppala <mika.kuoppala (at) intel.com>
     27  1.1  riastrad  *
     28  1.1  riastrad  */
     29  1.1  riastrad 
     30  1.1  riastrad #include <sys/cdefs.h>
     31  1.1  riastrad __KERNEL_RCSID(0, "$NetBSD: intel_renderstate.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
     32  1.1  riastrad 
     33  1.1  riastrad #include "i915_drv.h"
     34  1.1  riastrad #include "intel_renderstate.h"
     35  1.1  riastrad #include "intel_ring.h"
     36  1.1  riastrad 
     37  1.2  riastrad #include <linux/nbsd-namespace.h>
     38  1.2  riastrad 
     39  1.1  riastrad static const struct intel_renderstate_rodata *
     40  1.1  riastrad render_state_get_rodata(const struct intel_engine_cs *engine)
     41  1.1  riastrad {
     42  1.1  riastrad 	if (engine->class != RENDER_CLASS)
     43  1.1  riastrad 		return NULL;
     44  1.1  riastrad 
     45  1.1  riastrad 	switch (INTEL_GEN(engine->i915)) {
     46  1.1  riastrad 	case 6:
     47  1.1  riastrad 		return &gen6_null_state;
     48  1.1  riastrad 	case 7:
     49  1.1  riastrad 		return &gen7_null_state;
     50  1.1  riastrad 	case 8:
     51  1.1  riastrad 		return &gen8_null_state;
     52  1.1  riastrad 	case 9:
     53  1.1  riastrad 		return &gen9_null_state;
     54  1.1  riastrad 	}
     55  1.1  riastrad 
     56  1.1  riastrad 	return NULL;
     57  1.1  riastrad }
     58  1.1  riastrad 
     59  1.1  riastrad /*
     60  1.1  riastrad  * Macro to add commands to auxiliary batch.
     61  1.1  riastrad  * This macro only checks for page overflow before inserting the commands,
     62  1.1  riastrad  * this is sufficient as the null state generator makes the final batch
     63  1.1  riastrad  * with two passes to build command and state separately. At this point
     64  1.1  riastrad  * the size of both are known and it compacts them by relocating the state
     65  1.1  riastrad  * right after the commands taking care of alignment so we should sufficient
     66  1.1  riastrad  * space below them for adding new commands.
     67  1.1  riastrad  */
     68  1.1  riastrad #define OUT_BATCH(batch, i, val)				\
     69  1.1  riastrad 	do {							\
     70  1.1  riastrad 		if ((i) >= PAGE_SIZE / sizeof(u32))		\
     71  1.1  riastrad 			goto err;				\
     72  1.1  riastrad 		(batch)[(i)++] = (val);				\
     73  1.1  riastrad 	} while(0)
     74  1.1  riastrad 
     75  1.1  riastrad static int render_state_setup(struct intel_renderstate *so,
     76  1.1  riastrad 			      struct drm_i915_private *i915)
     77  1.1  riastrad {
     78  1.1  riastrad 	const struct intel_renderstate_rodata *rodata = so->rodata;
     79  1.1  riastrad 	unsigned int i = 0, reloc_index = 0;
     80  1.1  riastrad 	unsigned int needs_clflush;
     81  1.1  riastrad 	u32 *d;
     82  1.1  riastrad 	int ret;
     83  1.1  riastrad 
     84  1.1  riastrad 	ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush);
     85  1.1  riastrad 	if (ret)
     86  1.1  riastrad 		return ret;
     87  1.1  riastrad 
     88  1.1  riastrad 	d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
     89  1.1  riastrad 
     90  1.1  riastrad 	while (i < rodata->batch_items) {
     91  1.1  riastrad 		u32 s = rodata->batch[i];
     92  1.1  riastrad 
     93  1.1  riastrad 		if (i * 4  == rodata->reloc[reloc_index]) {
     94  1.1  riastrad 			u64 r = s + so->vma->node.start;
     95  1.1  riastrad 			s = lower_32_bits(r);
     96  1.1  riastrad 			if (HAS_64BIT_RELOC(i915)) {
     97  1.1  riastrad 				if (i + 1 >= rodata->batch_items ||
     98  1.1  riastrad 				    rodata->batch[i + 1] != 0)
     99  1.1  riastrad 					goto err;
    100  1.1  riastrad 
    101  1.1  riastrad 				d[i++] = s;
    102  1.1  riastrad 				s = upper_32_bits(r);
    103  1.1  riastrad 			}
    104  1.1  riastrad 
    105  1.1  riastrad 			reloc_index++;
    106  1.1  riastrad 		}
    107  1.1  riastrad 
    108  1.1  riastrad 		d[i++] = s;
    109  1.1  riastrad 	}
    110  1.1  riastrad 
    111  1.1  riastrad 	if (rodata->reloc[reloc_index] != -1) {
    112  1.1  riastrad 		DRM_ERROR("only %d relocs resolved\n", reloc_index);
    113  1.1  riastrad 		goto err;
    114  1.1  riastrad 	}
    115  1.1  riastrad 
    116  1.1  riastrad 	so->batch_offset = i915_ggtt_offset(so->vma);
    117  1.1  riastrad 	so->batch_size = rodata->batch_items * sizeof(u32);
    118  1.1  riastrad 
    119  1.1  riastrad 	while (i % CACHELINE_DWORDS)
    120  1.1  riastrad 		OUT_BATCH(d, i, MI_NOOP);
    121  1.1  riastrad 
    122  1.1  riastrad 	so->aux_offset = i * sizeof(u32);
    123  1.1  riastrad 
    124  1.1  riastrad 	if (HAS_POOLED_EU(i915)) {
    125  1.1  riastrad 		/*
    126  1.1  riastrad 		 * We always program 3x6 pool config but depending upon which
    127  1.1  riastrad 		 * subslice is disabled HW drops down to appropriate config
    128  1.1  riastrad 		 * shown below.
    129  1.1  riastrad 		 *
    130  1.1  riastrad 		 * In the below table 2x6 config always refers to
    131  1.1  riastrad 		 * fused-down version, native 2x6 is not available and can
    132  1.1  riastrad 		 * be ignored
    133  1.1  riastrad 		 *
    134  1.1  riastrad 		 * SNo  subslices config                eu pool configuration
    135  1.1  riastrad 		 * -----------------------------------------------------------
    136  1.1  riastrad 		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
    137  1.1  riastrad 		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
    138  1.1  riastrad 		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
    139  1.1  riastrad 		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
    140  1.1  riastrad 		 */
    141  1.1  riastrad 		u32 eu_pool_config = 0x00777000;
    142  1.1  riastrad 
    143  1.1  riastrad 		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
    144  1.1  riastrad 		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
    145  1.1  riastrad 		OUT_BATCH(d, i, eu_pool_config);
    146  1.1  riastrad 		OUT_BATCH(d, i, 0);
    147  1.1  riastrad 		OUT_BATCH(d, i, 0);
    148  1.1  riastrad 		OUT_BATCH(d, i, 0);
    149  1.1  riastrad 	}
    150  1.1  riastrad 
    151  1.1  riastrad 	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
    152  1.1  riastrad 	so->aux_size = i * sizeof(u32) - so->aux_offset;
    153  1.1  riastrad 	so->aux_offset += so->batch_offset;
    154  1.1  riastrad 	/*
    155  1.1  riastrad 	 * Since we are sending length, we need to strictly conform to
    156  1.1  riastrad 	 * all requirements. For Gen2 this must be a multiple of 8.
    157  1.1  riastrad 	 */
    158  1.1  riastrad 	so->aux_size = ALIGN(so->aux_size, 8);
    159  1.1  riastrad 
    160  1.1  riastrad 	if (needs_clflush)
    161  1.1  riastrad 		drm_clflush_virt_range(d, i * sizeof(u32));
    162  1.1  riastrad 	kunmap_atomic(d);
    163  1.1  riastrad 
    164  1.1  riastrad 	ret = 0;
    165  1.1  riastrad out:
    166  1.1  riastrad 	i915_gem_object_finish_access(so->vma->obj);
    167  1.1  riastrad 	return ret;
    168  1.1  riastrad 
    169  1.1  riastrad err:
    170  1.1  riastrad 	kunmap_atomic(d);
    171  1.1  riastrad 	ret = -EINVAL;
    172  1.1  riastrad 	goto out;
    173  1.1  riastrad }
    174  1.1  riastrad 
    175  1.1  riastrad #undef OUT_BATCH
    176  1.1  riastrad 
    177  1.1  riastrad int intel_renderstate_init(struct intel_renderstate *so,
    178  1.1  riastrad 			   struct intel_engine_cs *engine)
    179  1.1  riastrad {
    180  1.1  riastrad 	struct drm_i915_gem_object *obj;
    181  1.1  riastrad 	int err;
    182  1.1  riastrad 
    183  1.1  riastrad 	memset(so, 0, sizeof(*so));
    184  1.1  riastrad 
    185  1.1  riastrad 	so->rodata = render_state_get_rodata(engine);
    186  1.1  riastrad 	if (!so->rodata)
    187  1.1  riastrad 		return 0;
    188  1.1  riastrad 
    189  1.1  riastrad 	if (so->rodata->batch_items * 4 > PAGE_SIZE)
    190  1.1  riastrad 		return -EINVAL;
    191  1.1  riastrad 
    192  1.1  riastrad 	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
    193  1.1  riastrad 	if (IS_ERR(obj))
    194  1.1  riastrad 		return PTR_ERR(obj);
    195  1.1  riastrad 
    196  1.1  riastrad 	so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
    197  1.1  riastrad 	if (IS_ERR(so->vma)) {
    198  1.1  riastrad 		err = PTR_ERR(so->vma);
    199  1.1  riastrad 		goto err_obj;
    200  1.1  riastrad 	}
    201  1.1  riastrad 
    202  1.1  riastrad 	err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
    203  1.1  riastrad 	if (err)
    204  1.1  riastrad 		goto err_vma;
    205  1.1  riastrad 
    206  1.1  riastrad 	err = render_state_setup(so, engine->i915);
    207  1.1  riastrad 	if (err)
    208  1.1  riastrad 		goto err_unpin;
    209  1.1  riastrad 
    210  1.1  riastrad 	return 0;
    211  1.1  riastrad 
    212  1.1  riastrad err_unpin:
    213  1.1  riastrad 	i915_vma_unpin(so->vma);
    214  1.1  riastrad err_vma:
    215  1.1  riastrad 	i915_vma_close(so->vma);
    216  1.1  riastrad err_obj:
    217  1.1  riastrad 	i915_gem_object_put(obj);
    218  1.1  riastrad 	so->vma = NULL;
    219  1.1  riastrad 	return err;
    220  1.1  riastrad }
    221  1.1  riastrad 
    222  1.1  riastrad int intel_renderstate_emit(struct intel_renderstate *so,
    223  1.1  riastrad 			   struct i915_request *rq)
    224  1.1  riastrad {
    225  1.1  riastrad 	struct intel_engine_cs *engine = rq->engine;
    226  1.1  riastrad 	int err;
    227  1.1  riastrad 
    228  1.1  riastrad 	if (!so->vma)
    229  1.1  riastrad 		return 0;
    230  1.1  riastrad 
    231  1.1  riastrad 	err = engine->emit_bb_start(rq,
    232  1.1  riastrad 				    so->batch_offset, so->batch_size,
    233  1.1  riastrad 				    I915_DISPATCH_SECURE);
    234  1.1  riastrad 	if (err)
    235  1.1  riastrad 		return err;
    236  1.1  riastrad 
    237  1.1  riastrad 	if (so->aux_size > 8) {
    238  1.1  riastrad 		err = engine->emit_bb_start(rq,
    239  1.1  riastrad 					    so->aux_offset, so->aux_size,
    240  1.1  riastrad 					    I915_DISPATCH_SECURE);
    241  1.1  riastrad 		if (err)
    242  1.1  riastrad 			return err;
    243  1.1  riastrad 	}
    244  1.1  riastrad 
    245  1.1  riastrad 	i915_vma_lock(so->vma);
    246  1.1  riastrad 	err = i915_request_await_object(rq, so->vma->obj, false);
    247  1.1  riastrad 	if (err == 0)
    248  1.1  riastrad 		err = i915_vma_move_to_active(so->vma, rq, 0);
    249  1.1  riastrad 	i915_vma_unlock(so->vma);
    250  1.1  riastrad 
    251  1.1  riastrad 	return err;
    252  1.1  riastrad }
    253  1.1  riastrad 
    254  1.1  riastrad void intel_renderstate_fini(struct intel_renderstate *so)
    255  1.1  riastrad {
    256  1.1  riastrad 	i915_vma_unpin_and_release(&so->vma, 0);
    257  1.1  riastrad }
    258