11.4Sriastrad/* $NetBSD: intel_rps.h,v 1.4 2021/12/19 12:32:15 riastradh Exp $ */ 21.1Sriastrad 31.1Sriastrad/* 41.1Sriastrad * SPDX-License-Identifier: MIT 51.1Sriastrad * 61.1Sriastrad * Copyright © 2019 Intel Corporation 71.1Sriastrad */ 81.1Sriastrad 91.1Sriastrad#ifndef INTEL_RPS_H 101.1Sriastrad#define INTEL_RPS_H 111.1Sriastrad 121.1Sriastrad#include "intel_rps_types.h" 131.1Sriastrad 141.1Sriastradstruct i915_request; 151.1Sriastrad 161.1Sriastradvoid intel_rps_init_early(struct intel_rps *rps); 171.1Sriastradvoid intel_rps_init(struct intel_rps *rps); 181.4Sriastradvoid intel_rps_fini(struct intel_rps *rps); 191.1Sriastrad 201.1Sriastradvoid intel_rps_driver_register(struct intel_rps *rps); 211.1Sriastradvoid intel_rps_driver_unregister(struct intel_rps *rps); 221.1Sriastrad 231.1Sriastradvoid intel_rps_enable(struct intel_rps *rps); 241.1Sriastradvoid intel_rps_disable(struct intel_rps *rps); 251.1Sriastrad 261.1Sriastradvoid intel_rps_park(struct intel_rps *rps); 271.1Sriastradvoid intel_rps_unpark(struct intel_rps *rps); 281.1Sriastradvoid intel_rps_boost(struct i915_request *rq); 291.1Sriastrad 301.1Sriastradint intel_rps_set(struct intel_rps *rps, u8 val); 311.1Sriastradvoid intel_rps_mark_interactive(struct intel_rps *rps, bool interactive); 321.1Sriastrad 331.1Sriastradint intel_gpu_freq(struct intel_rps *rps, int val); 341.1Sriastradint intel_freq_opcode(struct intel_rps *rps, int val); 351.1Sriastradu32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); 361.1Sriastradu32 intel_rps_read_actual_frequency(struct intel_rps *rps); 371.1Sriastrad 381.1Sriastradvoid gen5_rps_irq_handler(struct intel_rps *rps); 391.1Sriastradvoid gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); 401.1Sriastradvoid gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); 411.1Sriastrad 421.3Sriastradextern spinlock_t mchdev_lock; 431.3Sriastrad 441.1Sriastrad#endif /* INTEL_RPS_H */ 45