gtt.h revision 1.3
1 /* $NetBSD: gtt.h,v 1.3 2021/12/19 01:24:25 riastradh Exp $ */ 2 3 /* 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Zhi Wang <zhi.a.wang (at) intel.com> 27 * Zhenyu Wang <zhenyuw (at) linux.intel.com> 28 * Xiao Zheng <xiao.zheng (at) intel.com> 29 * 30 * Contributors: 31 * Min He <min.he (at) intel.com> 32 * Bing Niu <bing.niu (at) intel.com> 33 * 34 */ 35 36 #ifndef _GVT_GTT_H_ 37 #define _GVT_GTT_H_ 38 39 #ifdef __NetBSD__ 40 #include <drm/bus_dma_hacks.h> 41 #include <x86/machdep.h> 42 #include <x86/pte.h> 43 #define _PAGE_PRESENT PG_V /* 0x01 PTE is present / valid */ 44 #define _PAGE_RW PG_RW /* 0x02 read/write */ 45 #define _PAGE_PWT PG_WT /* 0x08 write-through */ 46 #define _PAGE_PCD PG_N /* 0x10 page cache disabled / non-cacheable */ 47 #define _PAGE_PAT PG_PAT /* 0x80 page attribute table on PTE */ 48 #endif 49 50 #define I915_GTT_PAGE_SHIFT 12 51 52 struct intel_vgpu_mm; 53 54 #define INTEL_GVT_INVALID_ADDR (~0UL) 55 56 struct intel_gvt_gtt_entry { 57 u64 val64; 58 int type; 59 }; 60 61 struct intel_gvt_gtt_pte_ops { 62 int (*get_entry)(void *pt, 63 struct intel_gvt_gtt_entry *e, 64 unsigned long index, 65 bool hypervisor_access, 66 unsigned long gpa, 67 struct intel_vgpu *vgpu); 68 int (*set_entry)(void *pt, 69 struct intel_gvt_gtt_entry *e, 70 unsigned long index, 71 bool hypervisor_access, 72 unsigned long gpa, 73 struct intel_vgpu *vgpu); 74 bool (*test_present)(struct intel_gvt_gtt_entry *e); 75 void (*clear_present)(struct intel_gvt_gtt_entry *e); 76 void (*set_present)(struct intel_gvt_gtt_entry *e); 77 bool (*test_pse)(struct intel_gvt_gtt_entry *e); 78 void (*clear_pse)(struct intel_gvt_gtt_entry *e); 79 bool (*test_ips)(struct intel_gvt_gtt_entry *e); 80 void (*clear_ips)(struct intel_gvt_gtt_entry *e); 81 bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e); 82 void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e); 83 void (*set_64k_splited)(struct intel_gvt_gtt_entry *e); 84 void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn); 85 unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e); 86 }; 87 88 struct intel_gvt_gtt_gma_ops { 89 unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma); 90 unsigned long (*gma_to_pte_index)(unsigned long gma); 91 unsigned long (*gma_to_pde_index)(unsigned long gma); 92 unsigned long (*gma_to_l3_pdp_index)(unsigned long gma); 93 unsigned long (*gma_to_l4_pdp_index)(unsigned long gma); 94 unsigned long (*gma_to_pml4_index)(unsigned long gma); 95 }; 96 97 struct intel_gvt_gtt { 98 struct intel_gvt_gtt_pte_ops *pte_ops; 99 struct intel_gvt_gtt_gma_ops *gma_ops; 100 int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm); 101 void (*mm_free_page_table)(struct intel_vgpu_mm *mm); 102 struct list_head oos_page_use_list_head; 103 struct list_head oos_page_free_list_head; 104 struct mutex ppgtt_mm_lock; 105 struct list_head ppgtt_mm_lru_list_head; 106 107 struct page *scratch_page; 108 unsigned long scratch_mfn; 109 }; 110 111 enum intel_gvt_gtt_type { 112 GTT_TYPE_INVALID = 0, 113 114 GTT_TYPE_GGTT_PTE, 115 116 GTT_TYPE_PPGTT_PTE_4K_ENTRY, 117 GTT_TYPE_PPGTT_PTE_64K_ENTRY, 118 GTT_TYPE_PPGTT_PTE_2M_ENTRY, 119 GTT_TYPE_PPGTT_PTE_1G_ENTRY, 120 121 GTT_TYPE_PPGTT_PTE_ENTRY, 122 123 GTT_TYPE_PPGTT_PDE_ENTRY, 124 GTT_TYPE_PPGTT_PDP_ENTRY, 125 GTT_TYPE_PPGTT_PML4_ENTRY, 126 127 GTT_TYPE_PPGTT_ROOT_ENTRY, 128 129 GTT_TYPE_PPGTT_ROOT_L3_ENTRY, 130 GTT_TYPE_PPGTT_ROOT_L4_ENTRY, 131 132 GTT_TYPE_PPGTT_ENTRY, 133 134 GTT_TYPE_PPGTT_PTE_PT, 135 GTT_TYPE_PPGTT_PDE_PT, 136 GTT_TYPE_PPGTT_PDP_PT, 137 GTT_TYPE_PPGTT_PML4_PT, 138 139 GTT_TYPE_MAX, 140 }; 141 142 enum intel_gvt_mm_type { 143 INTEL_GVT_MM_GGTT, 144 INTEL_GVT_MM_PPGTT, 145 }; 146 147 #define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES 148 149 struct intel_gvt_partial_pte { 150 unsigned long offset; 151 u64 data; 152 struct list_head list; 153 }; 154 155 struct intel_vgpu_mm { 156 enum intel_gvt_mm_type type; 157 struct intel_vgpu *vgpu; 158 159 struct kref ref; 160 atomic_t pincount; 161 162 union { 163 struct { 164 enum intel_gvt_gtt_type root_entry_type; 165 /* 166 * The 4 PDPs in ring context. For 48bit addressing, 167 * only PDP0 is valid and point to PML4. For 32it 168 * addressing, all 4 are used as true PDPs. 169 */ 170 u64 guest_pdps[GVT_RING_CTX_NR_PDPS]; 171 u64 shadow_pdps[GVT_RING_CTX_NR_PDPS]; 172 bool shadowed; 173 174 struct list_head list; 175 struct list_head lru_list; 176 } ppgtt_mm; 177 struct { 178 void *virtual_ggtt; 179 struct list_head partial_pte_list; 180 } ggtt_mm; 181 }; 182 }; 183 184 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu, 185 enum intel_gvt_gtt_type root_entry_type, u64 pdps[]); 186 187 static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm) 188 { 189 kref_get(&mm->ref); 190 } 191 192 void _intel_vgpu_mm_release(struct kref *mm_ref); 193 194 static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm) 195 { 196 kref_put(&mm->ref, _intel_vgpu_mm_release); 197 } 198 199 static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm) 200 { 201 intel_vgpu_mm_put(mm); 202 } 203 204 struct intel_vgpu_guest_page; 205 206 struct intel_vgpu_scratch_pt { 207 struct page *page; 208 unsigned long page_mfn; 209 }; 210 211 struct intel_vgpu_gtt { 212 struct intel_vgpu_mm *ggtt_mm; 213 unsigned long active_ppgtt_mm_bitmap; 214 struct list_head ppgtt_mm_list_head; 215 struct radix_tree_root spt_tree; 216 struct list_head oos_page_list_head; 217 struct list_head post_shadow_list_head; 218 struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; 219 }; 220 221 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); 222 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); 223 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); 224 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); 225 226 int intel_gvt_init_gtt(struct intel_gvt *gvt); 227 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); 228 void intel_gvt_clean_gtt(struct intel_gvt *gvt); 229 230 struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, 231 int page_table_level, 232 void *root_entry); 233 234 struct intel_vgpu_oos_page { 235 struct intel_vgpu_ppgtt_spt *spt; 236 struct list_head list; 237 struct list_head vm_list; 238 int id; 239 void *mem; 240 }; 241 242 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512 243 244 /* Represent a vgpu shadow page table. */ 245 struct intel_vgpu_ppgtt_spt { 246 atomic_t refcount; 247 struct intel_vgpu *vgpu; 248 249 struct { 250 enum intel_gvt_gtt_type type; 251 bool pde_ips; /* for 64KB PTEs */ 252 void *vaddr; 253 struct page *page; 254 unsigned long mfn; 255 } shadow_page; 256 257 struct { 258 enum intel_gvt_gtt_type type; 259 bool pde_ips; /* for 64KB PTEs */ 260 unsigned long gfn; 261 unsigned long write_cnt; 262 struct intel_vgpu_oos_page *oos_page; 263 } guest_page; 264 265 DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE); 266 struct list_head post_shadow_list; 267 }; 268 269 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu); 270 271 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu); 272 273 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm); 274 275 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm); 276 277 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, 278 unsigned long gma); 279 280 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, 281 u64 pdps[]); 282 283 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu, 284 enum intel_gvt_gtt_type root_entry_type, u64 pdps[]); 285 286 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]); 287 288 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, 289 unsigned int off, void *p_data, unsigned int bytes); 290 291 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, 292 unsigned int off, void *p_data, unsigned int bytes); 293 294 #endif /* _GVT_GTT_H_ */ 295
Indexes created Tue Oct 28 12:10:06 GMT 2025