i915_cmd_parser.c revision 1.4.18.2
1 /* $NetBSD: i915_cmd_parser.c,v 1.4.18.2 2018/09/30 01:45:53 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Brad Volkin <bradley.d.volkin (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: i915_cmd_parser.c,v 1.4.18.2 2018/09/30 01:45:53 pgoyette Exp $"); 32 33 #include "i915_drv.h" 34 35 /** 36 * DOC: batch buffer command parser 37 * 38 * Motivation: 39 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 40 * require userspace code to submit batches containing commands such as 41 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 42 * generations of the hardware will noop these commands in "unsecure" batches 43 * (which includes all userspace batches submitted via i915) even though the 44 * commands may be safe and represent the intended programming model of the 45 * device. 46 * 47 * The software command parser is similar in operation to the command parsing 48 * done in hardware for unsecure batches. However, the software parser allows 49 * some operations that would be noop'd by hardware, if the parser determines 50 * the operation is safe, and submits the batch as "secure" to prevent hardware 51 * parsing. 52 * 53 * Threats: 54 * At a high level, the hardware (and software) checks attempt to prevent 55 * granting userspace undue privileges. There are three categories of privilege. 56 * 57 * First, commands which are explicitly defined as privileged or which should 58 * only be used by the kernel driver. The parser generally rejects such 59 * commands, though it may allow some from the drm master process. 60 * 61 * Second, commands which access registers. To support correct/enhanced 62 * userspace functionality, particularly certain OpenGL extensions, the parser 63 * provides a whitelist of registers which userspace may safely access (for both 64 * normal and drm master processes). 65 * 66 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 67 * The parser always rejects such commands. 68 * 69 * The majority of the problematic commands fall in the MI_* range, with only a 70 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). 71 * 72 * Implementation: 73 * Each ring maintains tables of commands and registers which the parser uses in 74 * scanning batch buffers submitted to that ring. 75 * 76 * Since the set of commands that the parser must check for is significantly 77 * smaller than the number of commands supported, the parser tables contain only 78 * those commands required by the parser. This generally works because command 79 * opcode ranges have standard command length encodings. So for commands that 80 * the parser does not need to check, it can easily skip them. This is 81 * implemented via a per-ring length decoding vfunc. 82 * 83 * Unfortunately, there are a number of commands that do not follow the standard 84 * length encoding for their opcode range, primarily amongst the MI_* commands. 85 * To handle this, the parser provides a way to define explicit "skip" entries 86 * in the per-ring command tables. 87 * 88 * Other command table entries map fairly directly to high level categories 89 * mentioned above: rejected, master-only, register whitelist. The parser 90 * implements a number of checks, including the privileged memory checks, via a 91 * general bitmasking mechanism. 92 */ 93 94 #define STD_MI_OPCODE_MASK 0xFF800000 95 #define STD_3D_OPCODE_MASK 0xFFFF0000 96 #define STD_2D_OPCODE_MASK 0xFFC00000 97 #define STD_MFX_OPCODE_MASK 0xFFFF0000 98 99 #define CMD(op, opm, f, lm, fl, ...) \ 100 { \ 101 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 102 .cmd = { (op), (opm) }, \ 103 .length = { (lm) }, \ 104 __VA_ARGS__ \ 105 } 106 107 /* Convenience macros to compress the tables */ 108 #define SMI STD_MI_OPCODE_MASK 109 #define S3D STD_3D_OPCODE_MASK 110 #define S2D STD_2D_OPCODE_MASK 111 #define SMFX STD_MFX_OPCODE_MASK 112 #define F true 113 #define S CMD_DESC_SKIP 114 #define R CMD_DESC_REJECT 115 #define W CMD_DESC_REGISTER 116 #define B CMD_DESC_BITMASK 117 #define M CMD_DESC_MASTER 118 119 /* Command Mask Fixed Len Action 120 ---------------------------------------------------------- */ 121 static const struct drm_i915_cmd_descriptor common_cmds[] = { 122 CMD( MI_NOOP, SMI, F, 1, S ), 123 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 124 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 125 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 126 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 127 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 128 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 129 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 130 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 131 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 132 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 133 .reg = { .offset = 1, .mask = 0x007FFFFC }, 134 .bits = {{ 135 .offset = 0, 136 .mask = MI_GLOBAL_GTT, 137 .expected = 0, 138 }}, ), 139 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 140 .reg = { .offset = 1, .mask = 0x007FFFFC }, 141 .bits = {{ 142 .offset = 0, 143 .mask = MI_GLOBAL_GTT, 144 .expected = 0, 145 }}, ), 146 /* 147 * MI_BATCH_BUFFER_START requires some special handling. It's not 148 * really a 'skip' action but it doesn't seem like it's worth adding 149 * a new action. See i915_parse_cmds(). 150 */ 151 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 152 }; 153 154 static const struct drm_i915_cmd_descriptor render_cmds[] = { 155 CMD( MI_FLUSH, SMI, F, 1, S ), 156 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 157 CMD( MI_PREDICATE, SMI, F, 1, S ), 158 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 159 CMD( MI_SET_APPID, SMI, F, 1, S ), 160 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 161 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 162 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 163 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 164 .bits = {{ 165 .offset = 0, 166 .mask = MI_GLOBAL_GTT, 167 .expected = 0, 168 }}, ), 169 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 170 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 171 .bits = {{ 172 .offset = 0, 173 .mask = MI_GLOBAL_GTT, 174 .expected = 0, 175 }}, ), 176 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 177 .bits = {{ 178 .offset = 1, 179 .mask = MI_REPORT_PERF_COUNT_GGTT, 180 .expected = 0, 181 }}, ), 182 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 183 .bits = {{ 184 .offset = 0, 185 .mask = MI_GLOBAL_GTT, 186 .expected = 0, 187 }}, ), 188 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 189 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 190 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 191 .bits = {{ 192 .offset = 2, 193 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 194 .expected = 0, 195 }}, ), 196 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 197 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 198 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 199 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 200 .bits = {{ 201 .offset = 1, 202 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 203 .expected = 0, 204 }, 205 { 206 .offset = 1, 207 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 208 PIPE_CONTROL_STORE_DATA_INDEX), 209 .expected = 0, 210 .condition_offset = 1, 211 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 212 }}, ), 213 }; 214 215 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 216 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 217 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 218 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 219 CMD( MI_SET_APPID, SMI, F, 1, S ), 220 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 221 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 222 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 223 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), 224 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 225 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 226 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 227 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 228 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 229 230 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 231 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 232 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 233 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 234 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 235 }; 236 237 static const struct drm_i915_cmd_descriptor video_cmds[] = { 238 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 239 CMD( MI_SET_APPID, SMI, F, 1, S ), 240 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 241 .bits = {{ 242 .offset = 0, 243 .mask = MI_GLOBAL_GTT, 244 .expected = 0, 245 }}, ), 246 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 247 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 248 .bits = {{ 249 .offset = 0, 250 .mask = MI_FLUSH_DW_NOTIFY, 251 .expected = 0, 252 }, 253 { 254 .offset = 1, 255 .mask = MI_FLUSH_DW_USE_GTT, 256 .expected = 0, 257 .condition_offset = 0, 258 .condition_mask = MI_FLUSH_DW_OP_MASK, 259 }, 260 { 261 .offset = 0, 262 .mask = MI_FLUSH_DW_STORE_INDEX, 263 .expected = 0, 264 .condition_offset = 0, 265 .condition_mask = MI_FLUSH_DW_OP_MASK, 266 }}, ), 267 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 268 .bits = {{ 269 .offset = 0, 270 .mask = MI_GLOBAL_GTT, 271 .expected = 0, 272 }}, ), 273 /* 274 * MFX_WAIT doesn't fit the way we handle length for most commands. 275 * It has a length field but it uses a non-standard length bias. 276 * It is always 1 dword though, so just treat it as fixed length. 277 */ 278 CMD( MFX_WAIT, SMFX, F, 1, S ), 279 }; 280 281 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 282 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 283 CMD( MI_SET_APPID, SMI, F, 1, S ), 284 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 285 .bits = {{ 286 .offset = 0, 287 .mask = MI_GLOBAL_GTT, 288 .expected = 0, 289 }}, ), 290 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 291 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 292 .bits = {{ 293 .offset = 0, 294 .mask = MI_FLUSH_DW_NOTIFY, 295 .expected = 0, 296 }, 297 { 298 .offset = 1, 299 .mask = MI_FLUSH_DW_USE_GTT, 300 .expected = 0, 301 .condition_offset = 0, 302 .condition_mask = MI_FLUSH_DW_OP_MASK, 303 }, 304 { 305 .offset = 0, 306 .mask = MI_FLUSH_DW_STORE_INDEX, 307 .expected = 0, 308 .condition_offset = 0, 309 .condition_mask = MI_FLUSH_DW_OP_MASK, 310 }}, ), 311 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 312 .bits = {{ 313 .offset = 0, 314 .mask = MI_GLOBAL_GTT, 315 .expected = 0, 316 }}, ), 317 }; 318 319 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 320 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 321 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 322 .bits = {{ 323 .offset = 0, 324 .mask = MI_GLOBAL_GTT, 325 .expected = 0, 326 }}, ), 327 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 328 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 329 .bits = {{ 330 .offset = 0, 331 .mask = MI_FLUSH_DW_NOTIFY, 332 .expected = 0, 333 }, 334 { 335 .offset = 1, 336 .mask = MI_FLUSH_DW_USE_GTT, 337 .expected = 0, 338 .condition_offset = 0, 339 .condition_mask = MI_FLUSH_DW_OP_MASK, 340 }, 341 { 342 .offset = 0, 343 .mask = MI_FLUSH_DW_STORE_INDEX, 344 .expected = 0, 345 .condition_offset = 0, 346 .condition_mask = MI_FLUSH_DW_OP_MASK, 347 }}, ), 348 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 349 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 350 }; 351 352 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 353 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 354 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 355 }; 356 357 #undef CMD 358 #undef SMI 359 #undef S3D 360 #undef S2D 361 #undef SMFX 362 #undef F 363 #undef S 364 #undef R 365 #undef W 366 #undef B 367 #undef M 368 369 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 370 { common_cmds, ARRAY_SIZE(common_cmds) }, 371 { render_cmds, ARRAY_SIZE(render_cmds) }, 372 }; 373 374 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 375 { common_cmds, ARRAY_SIZE(common_cmds) }, 376 { render_cmds, ARRAY_SIZE(render_cmds) }, 377 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 378 }; 379 380 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 381 { common_cmds, ARRAY_SIZE(common_cmds) }, 382 { video_cmds, ARRAY_SIZE(video_cmds) }, 383 }; 384 385 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 386 { common_cmds, ARRAY_SIZE(common_cmds) }, 387 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 388 }; 389 390 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 391 { common_cmds, ARRAY_SIZE(common_cmds) }, 392 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 393 }; 394 395 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 396 { common_cmds, ARRAY_SIZE(common_cmds) }, 397 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 398 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 399 }; 400 401 /* 402 * Register whitelists, sorted by increasing register offset. 403 */ 404 405 /* 406 * An individual whitelist entry granting access to register addr. If 407 * mask is non-zero the argument of immediate register writes will be 408 * AND-ed with mask, and the command will be rejected if the result 409 * doesn't match value. 410 * 411 * Registers with non-zero mask are only allowed to be written using 412 * LRI. 413 */ 414 struct drm_i915_reg_descriptor { 415 u32 addr; 416 u32 mask; 417 u32 value; 418 }; 419 420 /* Convenience macro for adding 32-bit registers. */ 421 #define REG32(address, ...) \ 422 { .addr = address, __VA_ARGS__ } 423 424 /* 425 * Convenience macro for adding 64-bit registers. 426 * 427 * Some registers that userspace accesses are 64 bits. The register 428 * access commands only allow 32-bit accesses. Hence, we have to include 429 * entries for both halves of the 64-bit registers. 430 */ 431 #define REG64(addr) \ 432 REG32(addr), REG32(addr + sizeof(u32)) 433 434 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 435 REG64(GPGPU_THREADS_DISPATCHED), 436 REG64(HS_INVOCATION_COUNT), 437 REG64(DS_INVOCATION_COUNT), 438 REG64(IA_VERTICES_COUNT), 439 REG64(IA_PRIMITIVES_COUNT), 440 REG64(VS_INVOCATION_COUNT), 441 REG64(GS_INVOCATION_COUNT), 442 REG64(GS_PRIMITIVES_COUNT), 443 REG64(CL_INVOCATION_COUNT), 444 REG64(CL_PRIMITIVES_COUNT), 445 REG64(PS_INVOCATION_COUNT), 446 REG64(PS_DEPTH_COUNT), 447 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ 448 REG64(MI_PREDICATE_SRC0), 449 REG64(MI_PREDICATE_SRC1), 450 REG32(GEN7_3DPRIM_END_OFFSET), 451 REG32(GEN7_3DPRIM_START_VERTEX), 452 REG32(GEN7_3DPRIM_VERTEX_COUNT), 453 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 454 REG32(GEN7_3DPRIM_START_INSTANCE), 455 REG32(GEN7_3DPRIM_BASE_VERTEX), 456 REG32(GEN7_GPGPU_DISPATCHDIMX), 457 REG32(GEN7_GPGPU_DISPATCHDIMY), 458 REG32(GEN7_GPGPU_DISPATCHDIMZ), 459 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), 460 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), 461 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), 462 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), 463 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), 464 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), 465 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), 466 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), 467 REG32(GEN7_SO_WRITE_OFFSET(0)), 468 REG32(GEN7_SO_WRITE_OFFSET(1)), 469 REG32(GEN7_SO_WRITE_OFFSET(2)), 470 REG32(GEN7_SO_WRITE_OFFSET(3)), 471 REG32(GEN7_L3SQCREG1), 472 REG32(GEN7_L3CNTLREG2), 473 REG32(GEN7_L3CNTLREG3), 474 REG32(HSW_SCRATCH1, 475 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 476 .value = 0), 477 REG32(HSW_ROW_CHICKEN3, 478 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 479 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 480 .value = 0), 481 }; 482 483 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 484 REG32(BCS_SWCTRL), 485 }; 486 487 static const struct drm_i915_reg_descriptor ivb_master_regs[] = { 488 REG32(FORCEWAKE_MT), 489 REG32(DERRMR), 490 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), 491 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), 492 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), 493 }; 494 495 static const struct drm_i915_reg_descriptor hsw_master_regs[] = { 496 REG32(FORCEWAKE_MT), 497 REG32(DERRMR), 498 }; 499 500 #undef REG64 501 #undef REG32 502 503 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 504 { 505 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 506 u32 subclient = 507 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 508 509 if (client == INSTR_MI_CLIENT) 510 return 0x3F; 511 else if (client == INSTR_RC_CLIENT) { 512 if (subclient == INSTR_MEDIA_SUBCLIENT) 513 return 0xFFFF; 514 else 515 return 0xFF; 516 } 517 518 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 519 return 0; 520 } 521 522 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 523 { 524 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 525 u32 subclient = 526 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 527 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 528 529 if (client == INSTR_MI_CLIENT) 530 return 0x3F; 531 else if (client == INSTR_RC_CLIENT) { 532 if (subclient == INSTR_MEDIA_SUBCLIENT) { 533 if (op == 6) 534 return 0xFFFF; 535 else 536 return 0xFFF; 537 } else 538 return 0xFF; 539 } 540 541 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 542 return 0; 543 } 544 545 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 546 { 547 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 548 549 if (client == INSTR_MI_CLIENT) 550 return 0x3F; 551 else if (client == INSTR_BC_CLIENT) 552 return 0xFF; 553 554 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 555 return 0; 556 } 557 558 __diagused 559 static bool validate_cmds_sorted(struct intel_engine_cs *ring, 560 const struct drm_i915_cmd_table *cmd_tables, 561 int cmd_table_count) 562 { 563 int i; 564 bool ret = true; 565 566 if (!cmd_tables || cmd_table_count == 0) 567 return true; 568 569 for (i = 0; i < cmd_table_count; i++) { 570 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 571 u32 previous = 0; 572 int j; 573 574 for (j = 0; j < table->count; j++) { 575 const struct drm_i915_cmd_descriptor *desc = 576 &table->table[j]; 577 u32 curr = desc->cmd.value & desc->cmd.mask; 578 579 if (curr < previous) { 580 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 581 ring->id, i, j, curr, previous); 582 ret = false; 583 } 584 585 previous = curr; 586 } 587 } 588 589 return ret; 590 } 591 592 static bool check_sorted(int ring_id, 593 const struct drm_i915_reg_descriptor *reg_table, 594 int reg_count) 595 { 596 int i; 597 u32 previous = 0; 598 bool ret = true; 599 600 for (i = 0; i < reg_count; i++) { 601 u32 curr = reg_table[i].addr; 602 603 if (curr < previous) { 604 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", 605 ring_id, i, curr, previous); 606 ret = false; 607 } 608 609 previous = curr; 610 } 611 612 return ret; 613 } 614 615 __diagused 616 static bool validate_regs_sorted(struct intel_engine_cs *ring) 617 { 618 return check_sorted(ring->id, ring->reg_table, ring->reg_count) && 619 check_sorted(ring->id, ring->master_reg_table, 620 ring->master_reg_count); 621 } 622 623 struct cmd_node { 624 const struct drm_i915_cmd_descriptor *desc; 625 struct hlist_node node; 626 }; 627 628 /* 629 * Different command ranges have different numbers of bits for the opcode. For 630 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 631 * problem is that, for example, MI commands use bits 22:16 for other fields 632 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 633 * we mask a command from a batch it could hash to the wrong bucket due to 634 * non-opcode bits being set. But if we don't include those bits, some 3D 635 * commands may hash to the same bucket due to not including opcode bits that 636 * make the command unique. For now, we will risk hashing to the same bucket. 637 * 638 * If we attempt to generate a perfect hash, we should be able to look at bits 639 * 31:29 of a command from a batch buffer and use the full mask for that 640 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. 641 */ 642 #define CMD_HASH_MASK STD_MI_OPCODE_MASK 643 644 static int init_hash_table(struct intel_engine_cs *ring, 645 const struct drm_i915_cmd_table *cmd_tables, 646 int cmd_table_count) 647 { 648 int i, j; 649 650 hash_init(ring->cmd_hash); 651 652 for (i = 0; i < cmd_table_count; i++) { 653 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 654 655 for (j = 0; j < table->count; j++) { 656 const struct drm_i915_cmd_descriptor *desc = 657 &table->table[j]; 658 struct cmd_node *desc_node = 659 kmalloc(sizeof(*desc_node), GFP_KERNEL); 660 661 if (!desc_node) 662 return -ENOMEM; 663 664 desc_node->desc = desc; 665 hash_add(ring->cmd_hash, &desc_node->node, 666 desc->cmd.value & CMD_HASH_MASK); 667 } 668 } 669 670 return 0; 671 } 672 673 static void fini_hash_table(struct intel_engine_cs *ring) 674 { 675 struct hlist_node *tmp; 676 struct cmd_node *desc_node; 677 int i; 678 679 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) { 680 hash_del(&desc_node->node); 681 kfree(desc_node); 682 } 683 } 684 685 /** 686 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer 687 * @ring: the ringbuffer to initialize 688 * 689 * Optionally initializes fields related to batch buffer command parsing in the 690 * struct intel_engine_cs based on whether the platform requires software 691 * command parsing. 692 * 693 * Return: non-zero if initialization fails 694 */ 695 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring) 696 { 697 const struct drm_i915_cmd_table *cmd_tables; 698 int cmd_table_count; 699 int ret; 700 701 if (!IS_GEN7(ring->dev)) 702 return 0; 703 704 switch (ring->id) { 705 case RCS: 706 if (IS_HASWELL(ring->dev)) { 707 cmd_tables = hsw_render_ring_cmds; 708 cmd_table_count = 709 ARRAY_SIZE(hsw_render_ring_cmds); 710 } else { 711 cmd_tables = gen7_render_cmds; 712 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 713 } 714 715 ring->reg_table = gen7_render_regs; 716 ring->reg_count = ARRAY_SIZE(gen7_render_regs); 717 718 if (IS_HASWELL(ring->dev)) { 719 ring->master_reg_table = hsw_master_regs; 720 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 721 } else { 722 ring->master_reg_table = ivb_master_regs; 723 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 724 } 725 726 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 727 break; 728 case VCS: 729 cmd_tables = gen7_video_cmds; 730 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 731 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 732 break; 733 case BCS: 734 if (IS_HASWELL(ring->dev)) { 735 cmd_tables = hsw_blt_ring_cmds; 736 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 737 } else { 738 cmd_tables = gen7_blt_cmds; 739 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 740 } 741 742 ring->reg_table = gen7_blt_regs; 743 ring->reg_count = ARRAY_SIZE(gen7_blt_regs); 744 745 if (IS_HASWELL(ring->dev)) { 746 ring->master_reg_table = hsw_master_regs; 747 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 748 } else { 749 ring->master_reg_table = ivb_master_regs; 750 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 751 } 752 753 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 754 break; 755 case VECS: 756 cmd_tables = hsw_vebox_cmds; 757 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 758 /* VECS can use the same length_mask function as VCS */ 759 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 760 break; 761 default: 762 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", 763 ring->id); 764 BUG(); 765 } 766 767 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count)); 768 BUG_ON(!validate_regs_sorted(ring)); 769 770 WARN_ON(!hash_empty(ring->cmd_hash)); 771 772 ret = init_hash_table(ring, cmd_tables, cmd_table_count); 773 if (ret) { 774 DRM_ERROR("CMD: cmd_parser_init failed!\n"); 775 fini_hash_table(ring); 776 return ret; 777 } 778 779 ring->needs_cmd_parser = true; 780 781 return 0; 782 } 783 784 /** 785 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields 786 * @ring: the ringbuffer to clean up 787 * 788 * Releases any resources related to command parsing that may have been 789 * initialized for the specified ring. 790 */ 791 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring) 792 { 793 if (!ring->needs_cmd_parser) 794 return; 795 796 fini_hash_table(ring); 797 } 798 799 static const struct drm_i915_cmd_descriptor* 800 find_cmd_in_table(struct intel_engine_cs *ring, 801 u32 cmd_header) 802 { 803 struct cmd_node *desc_node; 804 805 hash_for_each_possible(ring->cmd_hash, desc_node, node, 806 cmd_header & CMD_HASH_MASK) { 807 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 808 u32 masked_cmd = desc->cmd.mask & cmd_header; 809 u32 masked_value = desc->cmd.value & desc->cmd.mask; 810 811 if (masked_cmd == masked_value) 812 return desc; 813 } 814 815 return NULL; 816 } 817 818 /* 819 * Returns a pointer to a descriptor for the command specified by cmd_header. 820 * 821 * The caller must supply space for a default descriptor via the default_desc 822 * parameter. If no descriptor for the specified command exists in the ring's 823 * command parser tables, this function fills in default_desc based on the 824 * ring's default length encoding and returns default_desc. 825 */ 826 static const struct drm_i915_cmd_descriptor* 827 find_cmd(struct intel_engine_cs *ring, 828 u32 cmd_header, 829 struct drm_i915_cmd_descriptor *default_desc) 830 { 831 const struct drm_i915_cmd_descriptor *desc; 832 u32 mask; 833 834 desc = find_cmd_in_table(ring, cmd_header); 835 if (desc) 836 return desc; 837 838 mask = ring->get_cmd_length_mask(cmd_header); 839 if (!mask) 840 return NULL; 841 842 BUG_ON(!default_desc); 843 default_desc->flags = CMD_DESC_SKIP; 844 default_desc->length.mask = mask; 845 846 return default_desc; 847 } 848 849 static const struct drm_i915_reg_descriptor * 850 find_reg(const struct drm_i915_reg_descriptor *table, 851 int count, u32 addr) 852 { 853 if (table) { 854 int i; 855 856 for (i = 0; i < count; i++) { 857 if (table[i].addr == addr) 858 return &table[i]; 859 } 860 } 861 862 return NULL; 863 } 864 865 #ifndef __NetBSD__ 866 static u32 *vmap_batch(struct drm_i915_gem_object *obj, 867 unsigned start, unsigned len) 868 { 869 int i; 870 void *addr = NULL; 871 struct sg_page_iter sg_iter; 872 int first_page = start >> PAGE_SHIFT; 873 int last_page = (len + start + 4095) >> PAGE_SHIFT; 874 int npages = last_page - first_page; 875 struct page **pages; 876 877 pages = drm_malloc_ab(npages, sizeof(*pages)); 878 if (pages == NULL) { 879 DRM_DEBUG_DRIVER("Failed to get space for pages\n"); 880 goto finish; 881 } 882 883 i = 0; 884 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) { 885 pages[i++] = sg_page_iter_page(&sg_iter); 886 if (i == npages) 887 break; 888 } 889 890 addr = vmap(pages, i, 0, PAGE_KERNEL); 891 if (addr == NULL) { 892 DRM_DEBUG_DRIVER("Failed to vmap pages\n"); 893 goto finish; 894 } 895 896 finish: 897 if (pages) 898 drm_free_large(pages); 899 return (u32*)addr; 900 } 901 #endif /* __NetBSD__ */ 902 903 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */ 904 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, 905 struct drm_i915_gem_object *src_obj, 906 u32 batch_start_offset, 907 u32 batch_len) 908 { 909 int needs_clflush = 0; 910 const void *src_base, *src; 911 void *dst = NULL; 912 int ret; 913 914 if (batch_len > dest_obj->base.size || 915 batch_len + batch_start_offset > src_obj->base.size) 916 return ERR_PTR(-E2BIG); 917 918 if (WARN_ON(dest_obj->pages_pin_count == 0)) 919 return ERR_PTR(-ENODEV); 920 921 ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush); 922 if (ret) { 923 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n"); 924 return ERR_PTR(ret); 925 } 926 927 #ifdef __NetBSD__ 928 const u32 srcstart = rounddown(batch_start_offset, PAGE_SIZE); 929 const u32 srclen = roundup(batch_start_offset + batch_len, PAGE_SIZE) 930 - srcstart; 931 vaddr_t srcva = 0; /* hint */ 932 933 /* Acquire a reference for uvm_map to consume. */ 934 uao_reference(src_obj->base.filp); 935 936 /* XXX errno NetBSD->Linux */ 937 ret = -uvm_map(kernel_map, &srcva, srclen, src_obj->base.filp, 938 srcstart, PAGE_SIZE, UVM_MAPFLAG(UVM_PROT_RW, UVM_PROT_RW, 939 UVM_INH_NONE, UVM_ADV_SEQUENTIAL, UVM_FLAG_NOWAIT)); 940 if (ret) { 941 uao_detach(src_obj->base.filp); 942 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch: %d\n", ret); 943 goto unpin_src; 944 } 945 src_base = (const void *)srcva; 946 #else 947 src_base = vmap_batch(src_obj, batch_start_offset, batch_len); 948 if (!src_base) { 949 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); 950 ret = -ENOMEM; 951 goto unpin_src; 952 } 953 #endif 954 955 ret = i915_gem_object_set_to_cpu_domain(dest_obj, true); 956 if (ret) { 957 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n"); 958 goto unmap_src; 959 } 960 961 #ifdef __NetBSD__ 962 const u32 dststart = rounddown(0, PAGE_SIZE); 963 const u32 dstlen = roundup(0 + batch_len, PAGE_SIZE) - dststart; 964 vaddr_t dstva = 0; /* hint */ 965 966 /* Acquire a reference for uvm_map to consume. */ 967 uao_reference(dest_obj->base.filp); 968 969 /* XXX errno NetBSD->Linux */ 970 ret = -uvm_map(kernel_map, &dstva, dstlen, dest_obj->base.filp, 971 dststart, PAGE_SIZE, UVM_MAPFLAG(UVM_PROT_RW, UVM_PROT_RW, 972 UVM_INH_NONE, UVM_ADV_SEQUENTIAL, UVM_FLAG_NOWAIT)); 973 if (ret) { 974 uao_detach(dest_obj->base.filp); 975 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch: %d\n", ret); 976 goto unmap_src; 977 } 978 dst = (void *)dstva; 979 #else 980 dst = vmap_batch(dest_obj, 0, batch_len); 981 if (!dst) { 982 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n"); 983 ret = -ENOMEM; 984 goto unmap_src; 985 } 986 #endif 987 988 src = (const char *)src_base + offset_in_page(batch_start_offset); 989 if (needs_clflush) 990 drm_clflush_virt_range(src, batch_len); 991 992 #ifdef __NetBSD__ 993 ret = -kcopy(src, dst, batch_len); 994 if (ret) { 995 uvm_unmap(kernel_map, dstva, dstva + dstlen); 996 goto unmap_src; 997 } 998 #else 999 memcpy(dst, src, batch_len); 1000 #endif 1001 1002 unmap_src: 1003 #ifdef __NetBSD__ 1004 uvm_unmap(kernel_map, srcva, srcva + srclen); 1005 #else 1006 vunmap(src_base); 1007 #endif 1008 unpin_src: 1009 i915_gem_object_unpin_pages(src_obj); 1010 1011 return ret ? ERR_PTR(ret) : dst; 1012 } 1013 1014 /** 1015 * i915_needs_cmd_parser() - should a given ring use software command parsing? 1016 * @ring: the ring in question 1017 * 1018 * Only certain platforms require software batch buffer command parsing, and 1019 * only when enabled via module parameter. 1020 * 1021 * Return: true if the ring requires software command parsing 1022 */ 1023 bool i915_needs_cmd_parser(struct intel_engine_cs *ring) 1024 { 1025 if (!ring->needs_cmd_parser) 1026 return false; 1027 1028 if (!USES_PPGTT(ring->dev)) 1029 return false; 1030 1031 return (i915.enable_cmd_parser == 1); 1032 } 1033 1034 static bool check_cmd(const struct intel_engine_cs *ring, 1035 const struct drm_i915_cmd_descriptor *desc, 1036 const u32 *cmd, u32 length, 1037 const bool is_master, 1038 bool *oacontrol_set) 1039 { 1040 if (desc->flags & CMD_DESC_REJECT) { 1041 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1042 return false; 1043 } 1044 1045 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 1046 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 1047 *cmd); 1048 return false; 1049 } 1050 1051 if (desc->flags & CMD_DESC_REGISTER) { 1052 /* 1053 * Get the distance between individual register offset 1054 * fields if the command can perform more than one 1055 * access at a time. 1056 */ 1057 const u32 step = desc->reg.step ? desc->reg.step : length; 1058 u32 offset; 1059 1060 for (offset = desc->reg.offset; offset < length; 1061 offset += step) { 1062 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1063 const struct drm_i915_reg_descriptor *reg = 1064 find_reg(ring->reg_table, ring->reg_count, 1065 reg_addr); 1066 1067 if (!reg && is_master) 1068 reg = find_reg(ring->master_reg_table, 1069 ring->master_reg_count, 1070 reg_addr); 1071 1072 if (!reg) { 1073 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", 1074 reg_addr, *cmd, ring->id); 1075 return false; 1076 } 1077 1078 /* 1079 * OACONTROL requires some special handling for 1080 * writes. We want to make sure that any batch which 1081 * enables OA also disables it before the end of the 1082 * batch. The goal is to prevent one process from 1083 * snooping on the perf data from another process. To do 1084 * that, we need to check the value that will be written 1085 * to the register. Hence, limit OACONTROL writes to 1086 * only MI_LOAD_REGISTER_IMM commands. 1087 */ 1088 if (reg_addr == OACONTROL) { 1089 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1090 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); 1091 return false; 1092 } 1093 1094 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) 1095 *oacontrol_set = (cmd[offset + 1] != 0); 1096 } 1097 1098 /* 1099 * Check the value written to the register against the 1100 * allowed mask/value pair given in the whitelist entry. 1101 */ 1102 if (reg->mask) { 1103 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1104 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1105 reg_addr); 1106 return false; 1107 } 1108 1109 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1110 (offset + 2 > length || 1111 (cmd[offset + 1] & reg->mask) != reg->value)) { 1112 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1113 reg_addr); 1114 return false; 1115 } 1116 } 1117 } 1118 } 1119 1120 if (desc->flags & CMD_DESC_BITMASK) { 1121 int i; 1122 1123 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1124 u32 dword; 1125 1126 if (desc->bits[i].mask == 0) 1127 break; 1128 1129 if (desc->bits[i].condition_mask != 0) { 1130 u32 offset = 1131 desc->bits[i].condition_offset; 1132 u32 condition = cmd[offset] & 1133 desc->bits[i].condition_mask; 1134 1135 if (condition == 0) 1136 continue; 1137 } 1138 1139 dword = cmd[desc->bits[i].offset] & 1140 desc->bits[i].mask; 1141 1142 if (dword != desc->bits[i].expected) { 1143 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", 1144 *cmd, 1145 desc->bits[i].mask, 1146 desc->bits[i].expected, 1147 dword, ring->id); 1148 return false; 1149 } 1150 } 1151 } 1152 1153 return true; 1154 } 1155 1156 #define LENGTH_BIAS 2 1157 1158 /** 1159 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1160 * @ring: the ring on which the batch is to execute 1161 * @batch_obj: the batch buffer in question 1162 * @shadow_batch_obj: copy of the batch buffer in question 1163 * @batch_start_offset: byte offset in the batch at which execution starts 1164 * @batch_len: length of the commands in batch_obj 1165 * @is_master: is the submitting process the drm master? 1166 * 1167 * Parses the specified batch buffer looking for privilege violations as 1168 * described in the overview. 1169 * 1170 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1171 * if the batch appears legal but should use hardware parsing 1172 */ 1173 int i915_parse_cmds(struct intel_engine_cs *ring, 1174 struct drm_i915_gem_object *batch_obj, 1175 struct drm_i915_gem_object *shadow_batch_obj, 1176 u32 batch_start_offset, 1177 u32 batch_len, 1178 bool is_master) 1179 { 1180 u32 *cmd, *batch_base, *batch_end; 1181 static const struct drm_i915_cmd_descriptor zero_default_desc; 1182 struct drm_i915_cmd_descriptor default_desc = zero_default_desc; 1183 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ 1184 int ret = 0; 1185 1186 batch_base = copy_batch(shadow_batch_obj, batch_obj, 1187 batch_start_offset, batch_len); 1188 if (IS_ERR(batch_base)) { 1189 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1190 return PTR_ERR(batch_base); 1191 } 1192 1193 /* 1194 * We use the batch length as size because the shadow object is as 1195 * large or larger and copy_batch() will write MI_NOPs to the extra 1196 * space. Parsing should be faster in some cases this way. 1197 */ 1198 batch_end = batch_base + (batch_len / sizeof(*batch_end)); 1199 1200 cmd = batch_base; 1201 while (cmd < batch_end) { 1202 const struct drm_i915_cmd_descriptor *desc; 1203 u32 length; 1204 1205 if (*cmd == MI_BATCH_BUFFER_END) 1206 break; 1207 1208 desc = find_cmd(ring, *cmd, &default_desc); 1209 if (!desc) { 1210 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1211 *cmd); 1212 ret = -EINVAL; 1213 break; 1214 } 1215 1216 /* 1217 * If the batch buffer contains a chained batch, return an 1218 * error that tells the caller to abort and dispatch the 1219 * workload as a non-secure batch. 1220 */ 1221 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1222 ret = -EACCES; 1223 break; 1224 } 1225 1226 if (desc->flags & CMD_DESC_FIXED) 1227 length = desc->length.fixed; 1228 else 1229 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1230 1231 if ((batch_end - cmd) < length) { 1232 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1233 *cmd, 1234 length, 1235 batch_end - cmd); 1236 ret = -EINVAL; 1237 break; 1238 } 1239 1240 if (!check_cmd(ring, desc, cmd, length, is_master, 1241 &oacontrol_set)) { 1242 ret = -EINVAL; 1243 break; 1244 } 1245 1246 cmd += length; 1247 } 1248 1249 if (oacontrol_set) { 1250 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); 1251 ret = -EINVAL; 1252 } 1253 1254 if (cmd >= batch_end) { 1255 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1256 ret = -EINVAL; 1257 } 1258 1259 #ifdef __NetBSD__ 1260 uvm_unmap(kernel_map, (vaddr_t)batch_base, 1261 (vaddr_t)batch_base + roundup(batch_len, PAGE_SIZE)); 1262 #else 1263 vunmap(batch_base); 1264 #endif 1265 1266 return ret; 1267 } 1268 1269 /** 1270 * i915_cmd_parser_get_version() - get the cmd parser version number 1271 * 1272 * The cmd parser maintains a simple increasing integer version number suitable 1273 * for passing to userspace clients to determine what operations are permitted. 1274 * 1275 * Return: the current version number of the cmd parser 1276 */ 1277 int i915_cmd_parser_get_version(void) 1278 { 1279 /* 1280 * Command parser version history 1281 * 1282 * 1. Initial version. Checks batches and reports violations, but leaves 1283 * hardware parsing enabled (so does not allow new use cases). 1284 * 2. Allow access to the MI_PREDICATE_SRC0 and 1285 * MI_PREDICATE_SRC1 registers. 1286 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1287 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1288 * 5. GPGPU dispatch compute indirect registers. 1289 */ 1290 return 5; 1291 } 1292
Indexes created Thu Oct 02 07:10:07 GMT 2025