i915_cmd_parser.c revision 1.9
1 /* $NetBSD: i915_cmd_parser.c,v 1.9 2018/08/27 14:43:48 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Brad Volkin <bradley.d.volkin (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: i915_cmd_parser.c,v 1.9 2018/08/27 14:43:48 riastradh Exp $"); 32 33 #include "i915_drv.h" 34 35 /** 36 * DOC: batch buffer command parser 37 * 38 * Motivation: 39 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 40 * require userspace code to submit batches containing commands such as 41 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 42 * generations of the hardware will noop these commands in "unsecure" batches 43 * (which includes all userspace batches submitted via i915) even though the 44 * commands may be safe and represent the intended programming model of the 45 * device. 46 * 47 * The software command parser is similar in operation to the command parsing 48 * done in hardware for unsecure batches. However, the software parser allows 49 * some operations that would be noop'd by hardware, if the parser determines 50 * the operation is safe, and submits the batch as "secure" to prevent hardware 51 * parsing. 52 * 53 * Threats: 54 * At a high level, the hardware (and software) checks attempt to prevent 55 * granting userspace undue privileges. There are three categories of privilege. 56 * 57 * First, commands which are explicitly defined as privileged or which should 58 * only be used by the kernel driver. The parser generally rejects such 59 * commands, though it may allow some from the drm master process. 60 * 61 * Second, commands which access registers. To support correct/enhanced 62 * userspace functionality, particularly certain OpenGL extensions, the parser 63 * provides a whitelist of registers which userspace may safely access (for both 64 * normal and drm master processes). 65 * 66 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 67 * The parser always rejects such commands. 68 * 69 * The majority of the problematic commands fall in the MI_* range, with only a 70 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). 71 * 72 * Implementation: 73 * Each ring maintains tables of commands and registers which the parser uses in 74 * scanning batch buffers submitted to that ring. 75 * 76 * Since the set of commands that the parser must check for is significantly 77 * smaller than the number of commands supported, the parser tables contain only 78 * those commands required by the parser. This generally works because command 79 * opcode ranges have standard command length encodings. So for commands that 80 * the parser does not need to check, it can easily skip them. This is 81 * implemented via a per-ring length decoding vfunc. 82 * 83 * Unfortunately, there are a number of commands that do not follow the standard 84 * length encoding for their opcode range, primarily amongst the MI_* commands. 85 * To handle this, the parser provides a way to define explicit "skip" entries 86 * in the per-ring command tables. 87 * 88 * Other command table entries map fairly directly to high level categories 89 * mentioned above: rejected, master-only, register whitelist. The parser 90 * implements a number of checks, including the privileged memory checks, via a 91 * general bitmasking mechanism. 92 */ 93 94 #define STD_MI_OPCODE_MASK 0xFF800000 95 #define STD_3D_OPCODE_MASK 0xFFFF0000 96 #define STD_2D_OPCODE_MASK 0xFFC00000 97 #define STD_MFX_OPCODE_MASK 0xFFFF0000 98 99 #define CMD(op, opm, f, lm, fl, ...) \ 100 { \ 101 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 102 .cmd = { (op), (opm) }, \ 103 .length = { (lm) }, \ 104 __VA_ARGS__ \ 105 } 106 107 /* Convenience macros to compress the tables */ 108 #define SMI STD_MI_OPCODE_MASK 109 #define S3D STD_3D_OPCODE_MASK 110 #define S2D STD_2D_OPCODE_MASK 111 #define SMFX STD_MFX_OPCODE_MASK 112 #define F true 113 #define S CMD_DESC_SKIP 114 #define R CMD_DESC_REJECT 115 #define W CMD_DESC_REGISTER 116 #define B CMD_DESC_BITMASK 117 #define M CMD_DESC_MASTER 118 119 /* Command Mask Fixed Len Action 120 ---------------------------------------------------------- */ 121 static const struct drm_i915_cmd_descriptor common_cmds[] = { 122 CMD( MI_NOOP, SMI, F, 1, S ), 123 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 124 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 125 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 126 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 127 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 128 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 129 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 130 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 131 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 132 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 133 .reg = { .offset = 1, .mask = 0x007FFFFC }, 134 .bits = {{ 135 .offset = 0, 136 .mask = MI_GLOBAL_GTT, 137 .expected = 0, 138 }}, ), 139 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 140 .reg = { .offset = 1, .mask = 0x007FFFFC }, 141 .bits = {{ 142 .offset = 0, 143 .mask = MI_GLOBAL_GTT, 144 .expected = 0, 145 }}, ), 146 /* 147 * MI_BATCH_BUFFER_START requires some special handling. It's not 148 * really a 'skip' action but it doesn't seem like it's worth adding 149 * a new action. See i915_parse_cmds(). 150 */ 151 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 152 }; 153 154 static const struct drm_i915_cmd_descriptor render_cmds[] = { 155 CMD( MI_FLUSH, SMI, F, 1, S ), 156 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 157 CMD( MI_PREDICATE, SMI, F, 1, S ), 158 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 159 CMD( MI_SET_APPID, SMI, F, 1, S ), 160 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 161 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 162 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 163 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 164 .bits = {{ 165 .offset = 0, 166 .mask = MI_GLOBAL_GTT, 167 .expected = 0, 168 }}, ), 169 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 170 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 171 .bits = {{ 172 .offset = 0, 173 .mask = MI_GLOBAL_GTT, 174 .expected = 0, 175 }}, ), 176 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 177 .bits = {{ 178 .offset = 1, 179 .mask = MI_REPORT_PERF_COUNT_GGTT, 180 .expected = 0, 181 }}, ), 182 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 183 .bits = {{ 184 .offset = 0, 185 .mask = MI_GLOBAL_GTT, 186 .expected = 0, 187 }}, ), 188 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 189 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 190 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 191 .bits = {{ 192 .offset = 2, 193 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 194 .expected = 0, 195 }}, ), 196 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 197 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 198 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 199 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 200 .bits = {{ 201 .offset = 1, 202 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 203 .expected = 0, 204 }, 205 { 206 .offset = 1, 207 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 208 PIPE_CONTROL_STORE_DATA_INDEX), 209 .expected = 0, 210 .condition_offset = 1, 211 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 212 }}, ), 213 }; 214 215 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 216 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 217 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 218 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 219 CMD( MI_SET_APPID, SMI, F, 1, S ), 220 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 221 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 222 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 223 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), 224 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 225 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 226 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 227 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 228 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 229 230 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 231 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 232 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 233 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 234 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 235 }; 236 237 static const struct drm_i915_cmd_descriptor video_cmds[] = { 238 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 239 CMD( MI_SET_APPID, SMI, F, 1, S ), 240 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 241 .bits = {{ 242 .offset = 0, 243 .mask = MI_GLOBAL_GTT, 244 .expected = 0, 245 }}, ), 246 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 247 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 248 .bits = {{ 249 .offset = 0, 250 .mask = MI_FLUSH_DW_NOTIFY, 251 .expected = 0, 252 }, 253 { 254 .offset = 1, 255 .mask = MI_FLUSH_DW_USE_GTT, 256 .expected = 0, 257 .condition_offset = 0, 258 .condition_mask = MI_FLUSH_DW_OP_MASK, 259 }, 260 { 261 .offset = 0, 262 .mask = MI_FLUSH_DW_STORE_INDEX, 263 .expected = 0, 264 .condition_offset = 0, 265 .condition_mask = MI_FLUSH_DW_OP_MASK, 266 }}, ), 267 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 268 .bits = {{ 269 .offset = 0, 270 .mask = MI_GLOBAL_GTT, 271 .expected = 0, 272 }}, ), 273 /* 274 * MFX_WAIT doesn't fit the way we handle length for most commands. 275 * It has a length field but it uses a non-standard length bias. 276 * It is always 1 dword though, so just treat it as fixed length. 277 */ 278 CMD( MFX_WAIT, SMFX, F, 1, S ), 279 }; 280 281 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 282 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 283 CMD( MI_SET_APPID, SMI, F, 1, S ), 284 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 285 .bits = {{ 286 .offset = 0, 287 .mask = MI_GLOBAL_GTT, 288 .expected = 0, 289 }}, ), 290 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 291 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 292 .bits = {{ 293 .offset = 0, 294 .mask = MI_FLUSH_DW_NOTIFY, 295 .expected = 0, 296 }, 297 { 298 .offset = 1, 299 .mask = MI_FLUSH_DW_USE_GTT, 300 .expected = 0, 301 .condition_offset = 0, 302 .condition_mask = MI_FLUSH_DW_OP_MASK, 303 }, 304 { 305 .offset = 0, 306 .mask = MI_FLUSH_DW_STORE_INDEX, 307 .expected = 0, 308 .condition_offset = 0, 309 .condition_mask = MI_FLUSH_DW_OP_MASK, 310 }}, ), 311 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 312 .bits = {{ 313 .offset = 0, 314 .mask = MI_GLOBAL_GTT, 315 .expected = 0, 316 }}, ), 317 }; 318 319 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 320 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 321 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 322 .bits = {{ 323 .offset = 0, 324 .mask = MI_GLOBAL_GTT, 325 .expected = 0, 326 }}, ), 327 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 328 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 329 .bits = {{ 330 .offset = 0, 331 .mask = MI_FLUSH_DW_NOTIFY, 332 .expected = 0, 333 }, 334 { 335 .offset = 1, 336 .mask = MI_FLUSH_DW_USE_GTT, 337 .expected = 0, 338 .condition_offset = 0, 339 .condition_mask = MI_FLUSH_DW_OP_MASK, 340 }, 341 { 342 .offset = 0, 343 .mask = MI_FLUSH_DW_STORE_INDEX, 344 .expected = 0, 345 .condition_offset = 0, 346 .condition_mask = MI_FLUSH_DW_OP_MASK, 347 }}, ), 348 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 349 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 350 }; 351 352 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 353 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 354 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 355 }; 356 357 #undef CMD 358 #undef SMI 359 #undef S3D 360 #undef S2D 361 #undef SMFX 362 #undef F 363 #undef S 364 #undef R 365 #undef W 366 #undef B 367 #undef M 368 369 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 370 { common_cmds, ARRAY_SIZE(common_cmds) }, 371 { render_cmds, ARRAY_SIZE(render_cmds) }, 372 }; 373 374 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 375 { common_cmds, ARRAY_SIZE(common_cmds) }, 376 { render_cmds, ARRAY_SIZE(render_cmds) }, 377 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 378 }; 379 380 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 381 { common_cmds, ARRAY_SIZE(common_cmds) }, 382 { video_cmds, ARRAY_SIZE(video_cmds) }, 383 }; 384 385 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 386 { common_cmds, ARRAY_SIZE(common_cmds) }, 387 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 388 }; 389 390 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 391 { common_cmds, ARRAY_SIZE(common_cmds) }, 392 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 393 }; 394 395 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 396 { common_cmds, ARRAY_SIZE(common_cmds) }, 397 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 398 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 399 }; 400 401 /* 402 * Register whitelists, sorted by increasing register offset. 403 */ 404 405 /* 406 * An individual whitelist entry granting access to register addr. If 407 * mask is non-zero the argument of immediate register writes will be 408 * AND-ed with mask, and the command will be rejected if the result 409 * doesn't match value. 410 * 411 * Registers with non-zero mask are only allowed to be written using 412 * LRI. 413 */ 414 struct drm_i915_reg_descriptor { 415 u32 addr; 416 u32 mask; 417 u32 value; 418 }; 419 420 /* Convenience macro for adding 32-bit registers. */ 421 #define REG32(address, ...) \ 422 { .addr = address, __VA_ARGS__ } 423 424 /* 425 * Convenience macro for adding 64-bit registers. 426 * 427 * Some registers that userspace accesses are 64 bits. The register 428 * access commands only allow 32-bit accesses. Hence, we have to include 429 * entries for both halves of the 64-bit registers. 430 */ 431 #define REG64(addr) \ 432 REG32(addr), REG32(addr + sizeof(u32)) 433 434 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 435 REG64(GPGPU_THREADS_DISPATCHED), 436 REG64(HS_INVOCATION_COUNT), 437 REG64(DS_INVOCATION_COUNT), 438 REG64(IA_VERTICES_COUNT), 439 REG64(IA_PRIMITIVES_COUNT), 440 REG64(VS_INVOCATION_COUNT), 441 REG64(GS_INVOCATION_COUNT), 442 REG64(GS_PRIMITIVES_COUNT), 443 REG64(CL_INVOCATION_COUNT), 444 REG64(CL_PRIMITIVES_COUNT), 445 REG64(PS_INVOCATION_COUNT), 446 REG64(PS_DEPTH_COUNT), 447 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ 448 REG64(MI_PREDICATE_SRC0), 449 REG64(MI_PREDICATE_SRC1), 450 REG32(GEN7_3DPRIM_END_OFFSET), 451 REG32(GEN7_3DPRIM_START_VERTEX), 452 REG32(GEN7_3DPRIM_VERTEX_COUNT), 453 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 454 REG32(GEN7_3DPRIM_START_INSTANCE), 455 REG32(GEN7_3DPRIM_BASE_VERTEX), 456 REG32(GEN7_GPGPU_DISPATCHDIMX), 457 REG32(GEN7_GPGPU_DISPATCHDIMY), 458 REG32(GEN7_GPGPU_DISPATCHDIMZ), 459 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), 460 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), 461 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), 462 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), 463 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), 464 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), 465 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), 466 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), 467 REG32(GEN7_SO_WRITE_OFFSET(0)), 468 REG32(GEN7_SO_WRITE_OFFSET(1)), 469 REG32(GEN7_SO_WRITE_OFFSET(2)), 470 REG32(GEN7_SO_WRITE_OFFSET(3)), 471 REG32(GEN7_L3SQCREG1), 472 REG32(GEN7_L3CNTLREG2), 473 REG32(GEN7_L3CNTLREG3), 474 REG32(HSW_SCRATCH1, 475 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 476 .value = 0), 477 REG32(HSW_ROW_CHICKEN3, 478 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 479 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 480 .value = 0), 481 }; 482 483 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 484 REG32(BCS_SWCTRL), 485 }; 486 487 static const struct drm_i915_reg_descriptor ivb_master_regs[] = { 488 REG32(FORCEWAKE_MT), 489 REG32(DERRMR), 490 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), 491 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), 492 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), 493 }; 494 495 static const struct drm_i915_reg_descriptor hsw_master_regs[] = { 496 REG32(FORCEWAKE_MT), 497 REG32(DERRMR), 498 }; 499 500 #undef REG64 501 #undef REG32 502 503 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 504 { 505 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 506 u32 subclient = 507 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 508 509 if (client == INSTR_MI_CLIENT) 510 return 0x3F; 511 else if (client == INSTR_RC_CLIENT) { 512 if (subclient == INSTR_MEDIA_SUBCLIENT) 513 return 0xFFFF; 514 else 515 return 0xFF; 516 } 517 518 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 519 return 0; 520 } 521 522 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 523 { 524 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 525 u32 subclient = 526 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 527 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 528 529 if (client == INSTR_MI_CLIENT) 530 return 0x3F; 531 else if (client == INSTR_RC_CLIENT) { 532 if (subclient == INSTR_MEDIA_SUBCLIENT) { 533 if (op == 6) 534 return 0xFFFF; 535 else 536 return 0xFFF; 537 } else 538 return 0xFF; 539 } 540 541 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 542 return 0; 543 } 544 545 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 546 { 547 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 548 549 if (client == INSTR_MI_CLIENT) 550 return 0x3F; 551 else if (client == INSTR_BC_CLIENT) 552 return 0xFF; 553 554 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 555 return 0; 556 } 557 558 static bool validate_cmds_sorted(struct intel_engine_cs *ring, 559 const struct drm_i915_cmd_table *cmd_tables, 560 int cmd_table_count) 561 { 562 int i; 563 bool ret = true; 564 565 if (!cmd_tables || cmd_table_count == 0) 566 return true; 567 568 for (i = 0; i < cmd_table_count; i++) { 569 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 570 u32 previous = 0; 571 int j; 572 573 for (j = 0; j < table->count; j++) { 574 const struct drm_i915_cmd_descriptor *desc = 575 &table->table[j]; 576 u32 curr = desc->cmd.value & desc->cmd.mask; 577 578 if (curr < previous) { 579 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 580 ring->id, i, j, curr, previous); 581 ret = false; 582 } 583 584 previous = curr; 585 } 586 } 587 588 return ret; 589 } 590 591 static bool check_sorted(int ring_id, 592 const struct drm_i915_reg_descriptor *reg_table, 593 int reg_count) 594 { 595 int i; 596 u32 previous = 0; 597 bool ret = true; 598 599 for (i = 0; i < reg_count; i++) { 600 u32 curr = reg_table[i].addr; 601 602 if (curr < previous) { 603 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", 604 ring_id, i, curr, previous); 605 ret = false; 606 } 607 608 previous = curr; 609 } 610 611 return ret; 612 } 613 614 static bool validate_regs_sorted(struct intel_engine_cs *ring) 615 { 616 return check_sorted(ring->id, ring->reg_table, ring->reg_count) && 617 check_sorted(ring->id, ring->master_reg_table, 618 ring->master_reg_count); 619 } 620 621 struct cmd_node { 622 const struct drm_i915_cmd_descriptor *desc; 623 struct hlist_node node; 624 }; 625 626 /* 627 * Different command ranges have different numbers of bits for the opcode. For 628 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 629 * problem is that, for example, MI commands use bits 22:16 for other fields 630 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 631 * we mask a command from a batch it could hash to the wrong bucket due to 632 * non-opcode bits being set. But if we don't include those bits, some 3D 633 * commands may hash to the same bucket due to not including opcode bits that 634 * make the command unique. For now, we will risk hashing to the same bucket. 635 * 636 * If we attempt to generate a perfect hash, we should be able to look at bits 637 * 31:29 of a command from a batch buffer and use the full mask for that 638 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. 639 */ 640 #define CMD_HASH_MASK STD_MI_OPCODE_MASK 641 642 static int init_hash_table(struct intel_engine_cs *ring, 643 const struct drm_i915_cmd_table *cmd_tables, 644 int cmd_table_count) 645 { 646 int i, j; 647 648 hash_init(ring->cmd_hash); 649 650 for (i = 0; i < cmd_table_count; i++) { 651 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 652 653 for (j = 0; j < table->count; j++) { 654 const struct drm_i915_cmd_descriptor *desc = 655 &table->table[j]; 656 struct cmd_node *desc_node = 657 kmalloc(sizeof(*desc_node), GFP_KERNEL); 658 659 if (!desc_node) 660 return -ENOMEM; 661 662 desc_node->desc = desc; 663 hash_add(ring->cmd_hash, &desc_node->node, 664 desc->cmd.value & CMD_HASH_MASK); 665 } 666 } 667 668 return 0; 669 } 670 671 static void fini_hash_table(struct intel_engine_cs *ring) 672 { 673 struct hlist_node *tmp; 674 struct cmd_node *desc_node; 675 int i; 676 677 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) { 678 hash_del(&desc_node->node); 679 kfree(desc_node); 680 } 681 } 682 683 /** 684 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer 685 * @ring: the ringbuffer to initialize 686 * 687 * Optionally initializes fields related to batch buffer command parsing in the 688 * struct intel_engine_cs based on whether the platform requires software 689 * command parsing. 690 * 691 * Return: non-zero if initialization fails 692 */ 693 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring) 694 { 695 const struct drm_i915_cmd_table *cmd_tables; 696 int cmd_table_count; 697 int ret; 698 699 if (!IS_GEN7(ring->dev)) 700 return 0; 701 702 switch (ring->id) { 703 case RCS: 704 if (IS_HASWELL(ring->dev)) { 705 cmd_tables = hsw_render_ring_cmds; 706 cmd_table_count = 707 ARRAY_SIZE(hsw_render_ring_cmds); 708 } else { 709 cmd_tables = gen7_render_cmds; 710 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 711 } 712 713 ring->reg_table = gen7_render_regs; 714 ring->reg_count = ARRAY_SIZE(gen7_render_regs); 715 716 if (IS_HASWELL(ring->dev)) { 717 ring->master_reg_table = hsw_master_regs; 718 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 719 } else { 720 ring->master_reg_table = ivb_master_regs; 721 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 722 } 723 724 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 725 break; 726 case VCS: 727 cmd_tables = gen7_video_cmds; 728 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 729 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 730 break; 731 case BCS: 732 if (IS_HASWELL(ring->dev)) { 733 cmd_tables = hsw_blt_ring_cmds; 734 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 735 } else { 736 cmd_tables = gen7_blt_cmds; 737 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 738 } 739 740 ring->reg_table = gen7_blt_regs; 741 ring->reg_count = ARRAY_SIZE(gen7_blt_regs); 742 743 if (IS_HASWELL(ring->dev)) { 744 ring->master_reg_table = hsw_master_regs; 745 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 746 } else { 747 ring->master_reg_table = ivb_master_regs; 748 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 749 } 750 751 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 752 break; 753 case VECS: 754 cmd_tables = hsw_vebox_cmds; 755 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 756 /* VECS can use the same length_mask function as VCS */ 757 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 758 break; 759 default: 760 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", 761 ring->id); 762 BUG(); 763 } 764 765 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count)); 766 BUG_ON(!validate_regs_sorted(ring)); 767 768 WARN_ON(!hash_empty(ring->cmd_hash)); 769 770 ret = init_hash_table(ring, cmd_tables, cmd_table_count); 771 if (ret) { 772 DRM_ERROR("CMD: cmd_parser_init failed!\n"); 773 fini_hash_table(ring); 774 return ret; 775 } 776 777 ring->needs_cmd_parser = true; 778 779 return 0; 780 } 781 782 /** 783 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields 784 * @ring: the ringbuffer to clean up 785 * 786 * Releases any resources related to command parsing that may have been 787 * initialized for the specified ring. 788 */ 789 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring) 790 { 791 if (!ring->needs_cmd_parser) 792 return; 793 794 fini_hash_table(ring); 795 } 796 797 static const struct drm_i915_cmd_descriptor* 798 find_cmd_in_table(struct intel_engine_cs *ring, 799 u32 cmd_header) 800 { 801 struct cmd_node *desc_node; 802 803 hash_for_each_possible(ring->cmd_hash, desc_node, node, 804 cmd_header & CMD_HASH_MASK) { 805 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 806 u32 masked_cmd = desc->cmd.mask & cmd_header; 807 u32 masked_value = desc->cmd.value & desc->cmd.mask; 808 809 if (masked_cmd == masked_value) 810 return desc; 811 } 812 813 return NULL; 814 } 815 816 /* 817 * Returns a pointer to a descriptor for the command specified by cmd_header. 818 * 819 * The caller must supply space for a default descriptor via the default_desc 820 * parameter. If no descriptor for the specified command exists in the ring's 821 * command parser tables, this function fills in default_desc based on the 822 * ring's default length encoding and returns default_desc. 823 */ 824 static const struct drm_i915_cmd_descriptor* 825 find_cmd(struct intel_engine_cs *ring, 826 u32 cmd_header, 827 struct drm_i915_cmd_descriptor *default_desc) 828 { 829 const struct drm_i915_cmd_descriptor *desc; 830 u32 mask; 831 832 desc = find_cmd_in_table(ring, cmd_header); 833 if (desc) 834 return desc; 835 836 mask = ring->get_cmd_length_mask(cmd_header); 837 if (!mask) 838 return NULL; 839 840 BUG_ON(!default_desc); 841 default_desc->flags = CMD_DESC_SKIP; 842 default_desc->length.mask = mask; 843 844 return default_desc; 845 } 846 847 static const struct drm_i915_reg_descriptor * 848 find_reg(const struct drm_i915_reg_descriptor *table, 849 int count, u32 addr) 850 { 851 if (table) { 852 int i; 853 854 for (i = 0; i < count; i++) { 855 if (table[i].addr == addr) 856 return &table[i]; 857 } 858 } 859 860 return NULL; 861 } 862 863 static u32 *vmap_batch(struct drm_i915_gem_object *obj, 864 unsigned start, unsigned len) 865 { 866 #ifdef __NetBSD__ 867 vaddr_t va = 0; 868 int error; 869 870 error = uvm_map(kernel_map, &va, len, obj->base.filp, start, 871 sizeof(u32), UVM_MAPFLAG(UVM_PROT_RW, UVM_PROT_RW, UVM_INH_NONE, 872 UVM_ADV_SEQUENTIAL, UVM_FLAG_NOWAIT)); 873 if (error) 874 return NULL; 875 876 return (void *)va; 877 #else 878 int i; 879 void *addr = NULL; 880 struct sg_page_iter sg_iter; 881 int first_page = start >> PAGE_SHIFT; 882 int last_page = (len + start + 4095) >> PAGE_SHIFT; 883 int npages = last_page - first_page; 884 struct page **pages; 885 886 pages = drm_malloc_ab(npages, sizeof(*pages)); 887 if (pages == NULL) { 888 DRM_DEBUG_DRIVER("Failed to get space for pages\n"); 889 goto finish; 890 } 891 892 i = 0; 893 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) { 894 pages[i++] = sg_page_iter_page(&sg_iter); 895 if (i == npages) 896 break; 897 } 898 899 addr = vmap(pages, i, 0, PAGE_KERNEL); 900 if (addr == NULL) { 901 DRM_DEBUG_DRIVER("Failed to vmap pages\n"); 902 goto finish; 903 } 904 905 finish: 906 if (pages) 907 drm_free_large(pages); 908 return (u32*)addr; 909 #endif /* __NetBSD__ */ 910 } 911 912 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */ 913 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, 914 struct drm_i915_gem_object *src_obj, 915 u32 batch_start_offset, 916 u32 batch_len) 917 { 918 int needs_clflush = 0; 919 void *src_base, *src; 920 void *dst = NULL; 921 int ret; 922 923 if (batch_len > dest_obj->base.size || 924 batch_len + batch_start_offset > src_obj->base.size) 925 return ERR_PTR(-E2BIG); 926 927 if (WARN_ON(dest_obj->pages_pin_count == 0)) 928 return ERR_PTR(-ENODEV); 929 930 ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush); 931 if (ret) { 932 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n"); 933 return ERR_PTR(ret); 934 } 935 936 src_base = vmap_batch(src_obj, batch_start_offset, batch_len); 937 if (!src_base) { 938 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); 939 ret = -ENOMEM; 940 goto unpin_src; 941 } 942 943 ret = i915_gem_object_set_to_cpu_domain(dest_obj, true); 944 if (ret) { 945 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n"); 946 goto unmap_src; 947 } 948 949 dst = vmap_batch(dest_obj, 0, batch_len); 950 if (!dst) { 951 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n"); 952 ret = -ENOMEM; 953 goto unmap_src; 954 } 955 956 src = (char *)src_base + offset_in_page(batch_start_offset); 957 if (needs_clflush) 958 drm_clflush_virt_range(src, batch_len); 959 960 memcpy(dst, src, batch_len); 961 962 unmap_src: 963 #ifdef __NetBSD__ 964 uvm_unmap(kernel_map, (vaddr_t)src_base, batch_len); 965 #else 966 vunmap(src_base); 967 #endif 968 unpin_src: 969 i915_gem_object_unpin_pages(src_obj); 970 971 return ret ? ERR_PTR(ret) : dst; 972 } 973 974 /** 975 * i915_needs_cmd_parser() - should a given ring use software command parsing? 976 * @ring: the ring in question 977 * 978 * Only certain platforms require software batch buffer command parsing, and 979 * only when enabled via module parameter. 980 * 981 * Return: true if the ring requires software command parsing 982 */ 983 bool i915_needs_cmd_parser(struct intel_engine_cs *ring) 984 { 985 if (!ring->needs_cmd_parser) 986 return false; 987 988 if (!USES_PPGTT(ring->dev)) 989 return false; 990 991 return (i915.enable_cmd_parser == 1); 992 } 993 994 static bool check_cmd(const struct intel_engine_cs *ring, 995 const struct drm_i915_cmd_descriptor *desc, 996 const u32 *cmd, u32 length, 997 const bool is_master, 998 bool *oacontrol_set) 999 { 1000 if (desc->flags & CMD_DESC_REJECT) { 1001 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1002 return false; 1003 } 1004 1005 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 1006 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 1007 *cmd); 1008 return false; 1009 } 1010 1011 if (desc->flags & CMD_DESC_REGISTER) { 1012 /* 1013 * Get the distance between individual register offset 1014 * fields if the command can perform more than one 1015 * access at a time. 1016 */ 1017 const u32 step = desc->reg.step ? desc->reg.step : length; 1018 u32 offset; 1019 1020 for (offset = desc->reg.offset; offset < length; 1021 offset += step) { 1022 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1023 const struct drm_i915_reg_descriptor *reg = 1024 find_reg(ring->reg_table, ring->reg_count, 1025 reg_addr); 1026 1027 if (!reg && is_master) 1028 reg = find_reg(ring->master_reg_table, 1029 ring->master_reg_count, 1030 reg_addr); 1031 1032 if (!reg) { 1033 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", 1034 reg_addr, *cmd, ring->id); 1035 return false; 1036 } 1037 1038 /* 1039 * OACONTROL requires some special handling for 1040 * writes. We want to make sure that any batch which 1041 * enables OA also disables it before the end of the 1042 * batch. The goal is to prevent one process from 1043 * snooping on the perf data from another process. To do 1044 * that, we need to check the value that will be written 1045 * to the register. Hence, limit OACONTROL writes to 1046 * only MI_LOAD_REGISTER_IMM commands. 1047 */ 1048 if (reg_addr == OACONTROL) { 1049 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1050 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); 1051 return false; 1052 } 1053 1054 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) 1055 *oacontrol_set = (cmd[offset + 1] != 0); 1056 } 1057 1058 /* 1059 * Check the value written to the register against the 1060 * allowed mask/value pair given in the whitelist entry. 1061 */ 1062 if (reg->mask) { 1063 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1064 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1065 reg_addr); 1066 return false; 1067 } 1068 1069 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1070 (offset + 2 > length || 1071 (cmd[offset + 1] & reg->mask) != reg->value)) { 1072 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1073 reg_addr); 1074 return false; 1075 } 1076 } 1077 } 1078 } 1079 1080 if (desc->flags & CMD_DESC_BITMASK) { 1081 int i; 1082 1083 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1084 u32 dword; 1085 1086 if (desc->bits[i].mask == 0) 1087 break; 1088 1089 if (desc->bits[i].condition_mask != 0) { 1090 u32 offset = 1091 desc->bits[i].condition_offset; 1092 u32 condition = cmd[offset] & 1093 desc->bits[i].condition_mask; 1094 1095 if (condition == 0) 1096 continue; 1097 } 1098 1099 dword = cmd[desc->bits[i].offset] & 1100 desc->bits[i].mask; 1101 1102 if (dword != desc->bits[i].expected) { 1103 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", 1104 *cmd, 1105 desc->bits[i].mask, 1106 desc->bits[i].expected, 1107 dword, ring->id); 1108 return false; 1109 } 1110 } 1111 } 1112 1113 return true; 1114 } 1115 1116 #define LENGTH_BIAS 2 1117 1118 /** 1119 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1120 * @ring: the ring on which the batch is to execute 1121 * @batch_obj: the batch buffer in question 1122 * @shadow_batch_obj: copy of the batch buffer in question 1123 * @batch_start_offset: byte offset in the batch at which execution starts 1124 * @batch_len: length of the commands in batch_obj 1125 * @is_master: is the submitting process the drm master? 1126 * 1127 * Parses the specified batch buffer looking for privilege violations as 1128 * described in the overview. 1129 * 1130 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1131 * if the batch appears legal but should use hardware parsing 1132 */ 1133 int i915_parse_cmds(struct intel_engine_cs *ring, 1134 struct drm_i915_gem_object *batch_obj, 1135 struct drm_i915_gem_object *shadow_batch_obj, 1136 u32 batch_start_offset, 1137 u32 batch_len, 1138 bool is_master) 1139 { 1140 u32 *cmd, *batch_base, *batch_end; 1141 static const struct drm_i915_cmd_descriptor zero_default_desc; 1142 struct drm_i915_cmd_descriptor default_desc = zero_default_desc; 1143 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ 1144 int ret = 0; 1145 1146 batch_base = copy_batch(shadow_batch_obj, batch_obj, 1147 batch_start_offset, batch_len); 1148 if (IS_ERR(batch_base)) { 1149 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1150 return PTR_ERR(batch_base); 1151 } 1152 1153 /* 1154 * We use the batch length as size because the shadow object is as 1155 * large or larger and copy_batch() will write MI_NOPs to the extra 1156 * space. Parsing should be faster in some cases this way. 1157 */ 1158 batch_end = batch_base + (batch_len / sizeof(*batch_end)); 1159 1160 cmd = batch_base; 1161 while (cmd < batch_end) { 1162 const struct drm_i915_cmd_descriptor *desc; 1163 u32 length; 1164 1165 if (*cmd == MI_BATCH_BUFFER_END) 1166 break; 1167 1168 desc = find_cmd(ring, *cmd, &default_desc); 1169 if (!desc) { 1170 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1171 *cmd); 1172 ret = -EINVAL; 1173 break; 1174 } 1175 1176 /* 1177 * If the batch buffer contains a chained batch, return an 1178 * error that tells the caller to abort and dispatch the 1179 * workload as a non-secure batch. 1180 */ 1181 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1182 ret = -EACCES; 1183 break; 1184 } 1185 1186 if (desc->flags & CMD_DESC_FIXED) 1187 length = desc->length.fixed; 1188 else 1189 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1190 1191 if ((batch_end - cmd) < length) { 1192 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1193 *cmd, 1194 length, 1195 batch_end - cmd); 1196 ret = -EINVAL; 1197 break; 1198 } 1199 1200 if (!check_cmd(ring, desc, cmd, length, is_master, 1201 &oacontrol_set)) { 1202 ret = -EINVAL; 1203 break; 1204 } 1205 1206 cmd += length; 1207 } 1208 1209 if (oacontrol_set) { 1210 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); 1211 ret = -EINVAL; 1212 } 1213 1214 if (cmd >= batch_end) { 1215 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1216 ret = -EINVAL; 1217 } 1218 1219 #ifdef __NetBSD__ 1220 uvm_unmap(kernel_map, (vaddr_t)batch_base, batch_obj->base.size); 1221 #else 1222 vunmap(batch_base); 1223 #endif 1224 1225 return ret; 1226 } 1227 1228 /** 1229 * i915_cmd_parser_get_version() - get the cmd parser version number 1230 * 1231 * The cmd parser maintains a simple increasing integer version number suitable 1232 * for passing to userspace clients to determine what operations are permitted. 1233 * 1234 * Return: the current version number of the cmd parser 1235 */ 1236 int i915_cmd_parser_get_version(void) 1237 { 1238 /* 1239 * Command parser version history 1240 * 1241 * 1. Initial version. Checks batches and reports violations, but leaves 1242 * hardware parsing enabled (so does not allow new use cases). 1243 * 2. Allow access to the MI_PREDICATE_SRC0 and 1244 * MI_PREDICATE_SRC1 registers. 1245 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1246 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1247 * 5. GPGPU dispatch compute indirect registers. 1248 */ 1249 return 5; 1250 } 1251
Indexes created Thu Oct 02 01:09:59 GMT 2025