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i915_drv.c revision 1.1.1.1.2.3
      1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
      2  */
      3 /*
      4  *
      5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
      6  * All Rights Reserved.
      7  *
      8  * Permission is hereby granted, free of charge, to any person obtaining a
      9  * copy of this software and associated documentation files (the
     10  * "Software"), to deal in the Software without restriction, including
     11  * without limitation the rights to use, copy, modify, merge, publish,
     12  * distribute, sub license, and/or sell copies of the Software, and to
     13  * permit persons to whom the Software is furnished to do so, subject to
     14  * the following conditions:
     15  *
     16  * The above copyright notice and this permission notice (including the
     17  * next paragraph) shall be included in all copies or substantial portions
     18  * of the Software.
     19  *
     20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
     21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
     23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
     24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     27  *
     28  */
     29 
     30 #include <linux/device.h>
     31 #include <drm/drmP.h>
     32 #include <drm/i915_drm.h>
     33 #include "i915_drv.h"
     34 #include "i915_trace.h"
     35 #include "intel_drv.h"
     36 
     37 #include <linux/console.h>
     38 #include <linux/module.h>
     39 #include <drm/drm_crtc_helper.h>
     40 
     41 static int i915_modeset __read_mostly = -1;
     42 module_param_named(modeset, i915_modeset, int, 0400);
     43 MODULE_PARM_DESC(modeset,
     44 		"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
     45 		"1=on, -1=force vga console preference [default])");
     46 
     47 unsigned int i915_fbpercrtc __always_unused = 0;
     48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
     49 
     50 int i915_panel_ignore_lid __read_mostly = 1;
     51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
     52 MODULE_PARM_DESC(panel_ignore_lid,
     53 		"Override lid status (0=autodetect, 1=autodetect disabled [default], "
     54 		"-1=force lid closed, -2=force lid open)");
     55 
     56 unsigned int i915_powersave __read_mostly = 1;
     57 module_param_named(powersave, i915_powersave, int, 0600);
     58 MODULE_PARM_DESC(powersave,
     59 		"Enable powersavings, fbc, downclocking, etc. (default: true)");
     60 
     61 int i915_semaphores __read_mostly = -1;
     62 module_param_named(semaphores, i915_semaphores, int, 0600);
     63 MODULE_PARM_DESC(semaphores,
     64 		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
     65 
     66 int i915_enable_rc6 __read_mostly = -1;
     67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
     68 MODULE_PARM_DESC(i915_enable_rc6,
     69 		"Enable power-saving render C-state 6. "
     70 		"Different stages can be selected via bitmask values "
     71 		"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
     72 		"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
     73 		"default: -1 (use per-chip default)");
     74 
     75 int i915_enable_fbc __read_mostly = -1;
     76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
     77 MODULE_PARM_DESC(i915_enable_fbc,
     78 		"Enable frame buffer compression for power savings "
     79 		"(default: -1 (use per-chip default))");
     80 
     81 unsigned int i915_lvds_downclock __read_mostly = 0;
     82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
     83 MODULE_PARM_DESC(lvds_downclock,
     84 		"Use panel (LVDS/eDP) downclocking for power savings "
     85 		"(default: false)");
     86 
     87 int i915_lvds_channel_mode __read_mostly;
     88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
     89 MODULE_PARM_DESC(lvds_channel_mode,
     90 		 "Specify LVDS channel mode "
     91 		 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
     92 
     93 int i915_panel_use_ssc __read_mostly = -1;
     94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
     95 MODULE_PARM_DESC(lvds_use_ssc,
     96 		"Use Spread Spectrum Clock with panels [LVDS/eDP] "
     97 		"(default: auto from VBT)");
     98 
     99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
    100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
    101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
    102 		"Override/Ignore selection of SDVO panel mode in the VBT "
    103 		"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
    104 
    105 static bool i915_try_reset __read_mostly = true;
    106 module_param_named(reset, i915_try_reset, bool, 0600);
    107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
    108 
    109 bool i915_enable_hangcheck __read_mostly = true;
    110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
    111 MODULE_PARM_DESC(enable_hangcheck,
    112 		"Periodically check GPU activity for detecting hangs. "
    113 		"WARNING: Disabling this can cause system wide hangs. "
    114 		"(default: true)");
    115 
    116 int i915_enable_ppgtt __read_mostly = -1;
    117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
    118 MODULE_PARM_DESC(i915_enable_ppgtt,
    119 		"Enable PPGTT (default: true)");
    120 
    121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
    122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
    123 MODULE_PARM_DESC(preliminary_hw_support,
    124 		"Enable preliminary hardware support. "
    125 		"Enable Haswell and ValleyView Support. "
    126 		"(default: false)");
    127 
    128 static struct drm_driver driver;
    129 extern int intel_agp_enabled;
    130 
    131 #define INTEL_VGA_DEVICE(id, info) {		\
    132 	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
    133 	.class_mask = 0xff0000,			\
    134 	.vendor = 0x8086,			\
    135 	.device = id,				\
    136 	.subvendor = PCI_ANY_ID,		\
    137 	.subdevice = PCI_ANY_ID,		\
    138 	.driver_data = (unsigned long) info }
    139 
    140 static const struct intel_device_info intel_i830_info = {
    141 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
    142 	.has_overlay = 1, .overlay_needs_physical = 1,
    143 };
    144 
    145 static const struct intel_device_info intel_845g_info = {
    146 	.gen = 2,
    147 	.has_overlay = 1, .overlay_needs_physical = 1,
    148 };
    149 
    150 static const struct intel_device_info intel_i85x_info = {
    151 	.gen = 2, .is_i85x = 1, .is_mobile = 1,
    152 	.cursor_needs_physical = 1,
    153 	.has_overlay = 1, .overlay_needs_physical = 1,
    154 };
    155 
    156 static const struct intel_device_info intel_i865g_info = {
    157 	.gen = 2,
    158 	.has_overlay = 1, .overlay_needs_physical = 1,
    159 };
    160 
    161 static const struct intel_device_info intel_i915g_info = {
    162 	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
    163 	.has_overlay = 1, .overlay_needs_physical = 1,
    164 };
    165 static const struct intel_device_info intel_i915gm_info = {
    166 	.gen = 3, .is_mobile = 1,
    167 	.cursor_needs_physical = 1,
    168 	.has_overlay = 1, .overlay_needs_physical = 1,
    169 	.supports_tv = 1,
    170 };
    171 static const struct intel_device_info intel_i945g_info = {
    172 	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
    173 	.has_overlay = 1, .overlay_needs_physical = 1,
    174 };
    175 static const struct intel_device_info intel_i945gm_info = {
    176 	.gen = 3, .is_i945gm = 1, .is_mobile = 1,
    177 	.has_hotplug = 1, .cursor_needs_physical = 1,
    178 	.has_overlay = 1, .overlay_needs_physical = 1,
    179 	.supports_tv = 1,
    180 };
    181 
    182 static const struct intel_device_info intel_i965g_info = {
    183 	.gen = 4, .is_broadwater = 1,
    184 	.has_hotplug = 1,
    185 	.has_overlay = 1,
    186 };
    187 
    188 static const struct intel_device_info intel_i965gm_info = {
    189 	.gen = 4, .is_crestline = 1,
    190 	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
    191 	.has_overlay = 1,
    192 	.supports_tv = 1,
    193 };
    194 
    195 static const struct intel_device_info intel_g33_info = {
    196 	.gen = 3, .is_g33 = 1,
    197 	.need_gfx_hws = 1, .has_hotplug = 1,
    198 	.has_overlay = 1,
    199 };
    200 
    201 static const struct intel_device_info intel_g45_info = {
    202 	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
    203 	.has_pipe_cxsr = 1, .has_hotplug = 1,
    204 	.has_bsd_ring = 1,
    205 };
    206 
    207 static const struct intel_device_info intel_gm45_info = {
    208 	.gen = 4, .is_g4x = 1,
    209 	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
    210 	.has_pipe_cxsr = 1, .has_hotplug = 1,
    211 	.supports_tv = 1,
    212 	.has_bsd_ring = 1,
    213 };
    214 
    215 static const struct intel_device_info intel_pineview_info = {
    216 	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
    217 	.need_gfx_hws = 1, .has_hotplug = 1,
    218 	.has_overlay = 1,
    219 };
    220 
    221 static const struct intel_device_info intel_ironlake_d_info = {
    222 	.gen = 5,
    223 	.need_gfx_hws = 1, .has_hotplug = 1,
    224 	.has_bsd_ring = 1,
    225 };
    226 
    227 static const struct intel_device_info intel_ironlake_m_info = {
    228 	.gen = 5, .is_mobile = 1,
    229 	.need_gfx_hws = 1, .has_hotplug = 1,
    230 	.has_fbc = 1,
    231 	.has_bsd_ring = 1,
    232 };
    233 
    234 static const struct intel_device_info intel_sandybridge_d_info = {
    235 	.gen = 6,
    236 	.need_gfx_hws = 1, .has_hotplug = 1,
    237 	.has_bsd_ring = 1,
    238 	.has_blt_ring = 1,
    239 	.has_llc = 1,
    240 	.has_force_wake = 1,
    241 };
    242 
    243 static const struct intel_device_info intel_sandybridge_m_info = {
    244 	.gen = 6, .is_mobile = 1,
    245 	.need_gfx_hws = 1, .has_hotplug = 1,
    246 	.has_fbc = 1,
    247 	.has_bsd_ring = 1,
    248 	.has_blt_ring = 1,
    249 	.has_llc = 1,
    250 	.has_force_wake = 1,
    251 };
    252 
    253 static const struct intel_device_info intel_ivybridge_d_info = {
    254 	.is_ivybridge = 1, .gen = 7,
    255 	.need_gfx_hws = 1, .has_hotplug = 1,
    256 	.has_bsd_ring = 1,
    257 	.has_blt_ring = 1,
    258 	.has_llc = 1,
    259 	.has_force_wake = 1,
    260 };
    261 
    262 static const struct intel_device_info intel_ivybridge_m_info = {
    263 	.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
    264 	.need_gfx_hws = 1, .has_hotplug = 1,
    265 	.has_fbc = 0,	/* FBC is not enabled on Ivybridge mobile yet */
    266 	.has_bsd_ring = 1,
    267 	.has_blt_ring = 1,
    268 	.has_llc = 1,
    269 	.has_force_wake = 1,
    270 };
    271 
    272 static const struct intel_device_info intel_valleyview_m_info = {
    273 	.gen = 7, .is_mobile = 1,
    274 	.need_gfx_hws = 1, .has_hotplug = 1,
    275 	.has_fbc = 0,
    276 	.has_bsd_ring = 1,
    277 	.has_blt_ring = 1,
    278 	.is_valleyview = 1,
    279 };
    280 
    281 static const struct intel_device_info intel_valleyview_d_info = {
    282 	.gen = 7,
    283 	.need_gfx_hws = 1, .has_hotplug = 1,
    284 	.has_fbc = 0,
    285 	.has_bsd_ring = 1,
    286 	.has_blt_ring = 1,
    287 	.is_valleyview = 1,
    288 };
    289 
    290 static const struct intel_device_info intel_haswell_d_info = {
    291 	.is_haswell = 1, .gen = 7,
    292 	.need_gfx_hws = 1, .has_hotplug = 1,
    293 	.has_bsd_ring = 1,
    294 	.has_blt_ring = 1,
    295 	.has_llc = 1,
    296 	.has_force_wake = 1,
    297 };
    298 
    299 static const struct intel_device_info intel_haswell_m_info = {
    300 	.is_haswell = 1, .gen = 7, .is_mobile = 1,
    301 	.need_gfx_hws = 1, .has_hotplug = 1,
    302 	.has_bsd_ring = 1,
    303 	.has_blt_ring = 1,
    304 	.has_llc = 1,
    305 	.has_force_wake = 1,
    306 };
    307 
    308 static const struct pci_device_id pciidlist[] = {		/* aka */
    309 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
    310 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
    311 	INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),		/* I855_GM */
    312 	INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
    313 	INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),		/* I865_G */
    314 	INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),		/* I915_G */
    315 	INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),		/* E7221_G */
    316 	INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),		/* I915_GM */
    317 	INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),		/* I945_G */
    318 	INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),		/* I945_GM */
    319 	INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),		/* I945_GME */
    320 	INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),		/* I946_GZ */
    321 	INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),		/* G35_G */
    322 	INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),		/* I965_Q */
    323 	INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),		/* I965_G */
    324 	INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),		/* Q35_G */
    325 	INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),		/* G33_G */
    326 	INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),		/* Q33_G */
    327 	INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),		/* I965_GM */
    328 	INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),		/* I965_GME */
    329 	INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),		/* GM45_G */
    330 	INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),		/* IGD_E_G */
    331 	INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),		/* Q45_G */
    332 	INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),		/* G45_G */
    333 	INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),		/* G41_G */
    334 	INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),		/* B43_G */
    335 	INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),		/* B43_G.1 */
    336 	INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
    337 	INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
    338 	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
    339 	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
    340 	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
    341 	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
    342 	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
    343 	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
    344 	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
    345 	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
    346 	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
    347 	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
    348 	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
    349 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
    350 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
    351 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
    352 	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
    353 	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
    354 	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
    355 	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
    356 	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
    357 	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
    358 	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
    359 	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
    360 	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
    361 	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
    362 	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
    363 	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
    364 	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
    365 	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
    366 	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
    367 	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
    368 	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
    369 	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
    370 	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
    371 	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
    372 	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
    373 	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
    374 	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
    375 	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
    376 	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
    377 	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
    378 	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
    379 	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
    380 	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
    381 	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
    382 	INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
    383 	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
    384 	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
    385 	INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
    386 	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
    387 	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
    388 	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
    389 	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
    390 	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
    391 	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
    392 	{0, 0, 0}
    393 };
    394 
    395 #if defined(CONFIG_DRM_I915_KMS)
    396 MODULE_DEVICE_TABLE(pci, pciidlist);
    397 #endif
    398 
    399 void intel_detect_pch(struct drm_device *dev)
    400 {
    401 	struct drm_i915_private *dev_priv = dev->dev_private;
    402 	struct pci_dev *pch;
    403 
    404 	/*
    405 	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
    406 	 * make graphics device passthrough work easy for VMM, that only
    407 	 * need to expose ISA bridge to let driver know the real hardware
    408 	 * underneath. This is a requirement from virtualization team.
    409 	 */
    410 	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
    411 	if (pch) {
    412 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
    413 			unsigned short id;
    414 			id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
    415 			dev_priv->pch_id = id;
    416 
    417 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
    418 				dev_priv->pch_type = PCH_IBX;
    419 				dev_priv->num_pch_pll = 2;
    420 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
    421 				WARN_ON(!IS_GEN5(dev));
    422 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
    423 				dev_priv->pch_type = PCH_CPT;
    424 				dev_priv->num_pch_pll = 2;
    425 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
    426 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
    427 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
    428 				/* PantherPoint is CPT compatible */
    429 				dev_priv->pch_type = PCH_CPT;
    430 				dev_priv->num_pch_pll = 2;
    431 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
    432 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
    433 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
    434 				dev_priv->pch_type = PCH_LPT;
    435 				dev_priv->num_pch_pll = 0;
    436 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
    437 				WARN_ON(!IS_HASWELL(dev));
    438 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
    439 				dev_priv->pch_type = PCH_LPT;
    440 				dev_priv->num_pch_pll = 0;
    441 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
    442 				WARN_ON(!IS_HASWELL(dev));
    443 			}
    444 			BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
    445 		}
    446 		pci_dev_put(pch);
    447 	}
    448 }
    449 
    450 bool i915_semaphore_is_enabled(struct drm_device *dev)
    451 {
    452 	if (INTEL_INFO(dev)->gen < 6)
    453 		return 0;
    454 
    455 	if (i915_semaphores >= 0)
    456 		return i915_semaphores;
    457 
    458 #ifdef CONFIG_INTEL_IOMMU
    459 	/* Enable semaphores on SNB when IO remapping is off */
    460 	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
    461 		return false;
    462 #endif
    463 
    464 	return 1;
    465 }
    466 
    467 static int i915_drm_freeze(struct drm_device *dev)
    468 {
    469 	struct drm_i915_private *dev_priv = dev->dev_private;
    470 
    471 	drm_kms_helper_poll_disable(dev);
    472 
    473 	pci_save_state(dev->pdev);
    474 
    475 	/* If KMS is active, we do the leavevt stuff here */
    476 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
    477 		int error = i915_gem_idle(dev);
    478 		if (error) {
    479 			dev_err(&dev->pdev->dev,
    480 				"GEM idle failed, resume might fail\n");
    481 			return error;
    482 		}
    483 
    484 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
    485 
    486 		intel_modeset_disable(dev);
    487 
    488 		drm_irq_uninstall(dev);
    489 	}
    490 
    491 	i915_save_state(dev);
    492 
    493 	intel_opregion_fini(dev);
    494 
    495 	/* Modeset on resume, not lid events */
    496 	dev_priv->modeset_on_lid = 0;
    497 
    498 	console_lock();
    499 	intel_fbdev_set_suspend(dev, 1);
    500 	console_unlock();
    501 
    502 	return 0;
    503 }
    504 
    505 int i915_suspend(struct drm_device *dev, pm_message_t state)
    506 {
    507 	int error;
    508 
    509 	if (!dev || !dev->dev_private) {
    510 		DRM_ERROR("dev: %p\n", dev);
    511 		DRM_ERROR("DRM not initialized, aborting suspend.\n");
    512 		return -ENODEV;
    513 	}
    514 
    515 	if (state.event == PM_EVENT_PRETHAW)
    516 		return 0;
    517 
    518 
    519 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
    520 		return 0;
    521 
    522 	error = i915_drm_freeze(dev);
    523 	if (error)
    524 		return error;
    525 
    526 	if (state.event == PM_EVENT_SUSPEND) {
    527 		/* Shut down the device */
    528 		pci_disable_device(dev->pdev);
    529 		pci_set_power_state(dev->pdev, PCI_D3hot);
    530 	}
    531 
    532 	return 0;
    533 }
    534 
    535 void intel_console_resume(struct work_struct *work)
    536 {
    537 	struct drm_i915_private *dev_priv =
    538 		container_of(work, struct drm_i915_private,
    539 			     console_resume_work);
    540 	struct drm_device *dev = dev_priv->dev;
    541 
    542 	console_lock();
    543 	intel_fbdev_set_suspend(dev, 0);
    544 	console_unlock();
    545 }
    546 
    547 static int __i915_drm_thaw(struct drm_device *dev)
    548 {
    549 	struct drm_i915_private *dev_priv = dev->dev_private;
    550 	int error = 0;
    551 
    552 	i915_restore_state(dev);
    553 	intel_opregion_setup(dev);
    554 
    555 	/* KMS EnterVT equivalent */
    556 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
    557 		intel_init_pch_refclk(dev);
    558 
    559 		mutex_lock(&dev->struct_mutex);
    560 		dev_priv->mm.suspended = 0;
    561 
    562 		error = i915_gem_init_hw(dev);
    563 		mutex_unlock(&dev->struct_mutex);
    564 
    565 		intel_modeset_init_hw(dev);
    566 		intel_modeset_setup_hw_state(dev, false);
    567 		drm_irq_install(dev);
    568 	}
    569 
    570 	intel_opregion_init(dev);
    571 
    572 	dev_priv->modeset_on_lid = 0;
    573 
    574 	/*
    575 	 * The console lock can be pretty contented on resume due
    576 	 * to all the printk activity.  Try to keep it out of the hot
    577 	 * path of resume if possible.
    578 	 */
    579 	if (console_trylock()) {
    580 		intel_fbdev_set_suspend(dev, 0);
    581 		console_unlock();
    582 	} else {
    583 		schedule_work(&dev_priv->console_resume_work);
    584 	}
    585 
    586 	return error;
    587 }
    588 
    589 static int i915_drm_thaw(struct drm_device *dev)
    590 {
    591 	int error = 0;
    592 
    593 	intel_gt_reset(dev);
    594 
    595 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
    596 		mutex_lock(&dev->struct_mutex);
    597 		i915_gem_restore_gtt_mappings(dev);
    598 		mutex_unlock(&dev->struct_mutex);
    599 	}
    600 
    601 	__i915_drm_thaw(dev);
    602 
    603 	return error;
    604 }
    605 
    606 int i915_resume(struct drm_device *dev)
    607 {
    608 	struct drm_i915_private *dev_priv = dev->dev_private;
    609 	int ret;
    610 
    611 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
    612 		return 0;
    613 
    614 	if (pci_enable_device(dev->pdev))
    615 		return -EIO;
    616 
    617 	pci_set_master(dev->pdev);
    618 
    619 	intel_gt_reset(dev);
    620 
    621 	/*
    622 	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
    623 	 * earlier) need this since the BIOS might clear all our scratch PTEs.
    624 	 */
    625 	if (drm_core_check_feature(dev, DRIVER_MODESET) &&
    626 	    !dev_priv->opregion.header) {
    627 		mutex_lock(&dev->struct_mutex);
    628 		i915_gem_restore_gtt_mappings(dev);
    629 		mutex_unlock(&dev->struct_mutex);
    630 	}
    631 
    632 	ret = __i915_drm_thaw(dev);
    633 	if (ret)
    634 		return ret;
    635 
    636 	drm_kms_helper_poll_enable(dev);
    637 	return 0;
    638 }
    639 
    640 static int i8xx_do_reset(struct drm_device *dev)
    641 {
    642 	struct drm_i915_private *dev_priv = dev->dev_private;
    643 
    644 	if (IS_I85X(dev))
    645 		return -ENODEV;
    646 
    647 	I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
    648 	POSTING_READ(D_STATE);
    649 
    650 	if (IS_I830(dev) || IS_845G(dev)) {
    651 		I915_WRITE(DEBUG_RESET_I830,
    652 			   DEBUG_RESET_DISPLAY |
    653 			   DEBUG_RESET_RENDER |
    654 			   DEBUG_RESET_FULL);
    655 		POSTING_READ(DEBUG_RESET_I830);
    656 		msleep(1);
    657 
    658 		I915_WRITE(DEBUG_RESET_I830, 0);
    659 		POSTING_READ(DEBUG_RESET_I830);
    660 	}
    661 
    662 	msleep(1);
    663 
    664 	I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
    665 	POSTING_READ(D_STATE);
    666 
    667 	return 0;
    668 }
    669 
    670 static int i965_reset_complete(struct drm_device *dev)
    671 {
    672 	u8 gdrst;
    673 	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
    674 	return (gdrst & GRDOM_RESET_ENABLE) == 0;
    675 }
    676 
    677 static int i965_do_reset(struct drm_device *dev)
    678 {
    679 	int ret;
    680 	u8 gdrst;
    681 
    682 	/*
    683 	 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
    684 	 * well as the reset bit (GR/bit 0).  Setting the GR bit
    685 	 * triggers the reset; when done, the hardware will clear it.
    686 	 */
    687 	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
    688 	pci_write_config_byte(dev->pdev, I965_GDRST,
    689 			      gdrst | GRDOM_RENDER |
    690 			      GRDOM_RESET_ENABLE);
    691 	ret =  wait_for(i965_reset_complete(dev), 500);
    692 	if (ret)
    693 		return ret;
    694 
    695 	/* We can't reset render&media without also resetting display ... */
    696 	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
    697 	pci_write_config_byte(dev->pdev, I965_GDRST,
    698 			      gdrst | GRDOM_MEDIA |
    699 			      GRDOM_RESET_ENABLE);
    700 
    701 	return wait_for(i965_reset_complete(dev), 500);
    702 }
    703 
    704 static int ironlake_do_reset(struct drm_device *dev)
    705 {
    706 	struct drm_i915_private *dev_priv = dev->dev_private;
    707 	u32 gdrst;
    708 	int ret;
    709 
    710 	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
    711 	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
    712 		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
    713 	ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
    714 	if (ret)
    715 		return ret;
    716 
    717 	/* We can't reset render&media without also resetting display ... */
    718 	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
    719 	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
    720 		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
    721 	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
    722 }
    723 
    724 static int gen6_do_reset(struct drm_device *dev)
    725 {
    726 	struct drm_i915_private *dev_priv = dev->dev_private;
    727 	int	ret;
    728 	unsigned long irqflags;
    729 
    730 	/* Hold gt_lock across reset to prevent any register access
    731 	 * with forcewake not set correctly
    732 	 */
    733 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
    734 
    735 	/* Reset the chip */
    736 
    737 	/* GEN6_GDRST is not in the gt power well, no need to check
    738 	 * for fifo space for the write or forcewake the chip for
    739 	 * the read
    740 	 */
    741 	I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
    742 
    743 	/* Spin waiting for the device to ack the reset request */
    744 	ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
    745 
    746 	/* If reset with a user forcewake, try to restore, otherwise turn it off */
    747 	if (dev_priv->forcewake_count)
    748 		dev_priv->gt.force_wake_get(dev_priv);
    749 	else
    750 		dev_priv->gt.force_wake_put(dev_priv);
    751 
    752 	/* Restore fifo count */
    753 	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
    754 
    755 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
    756 	return ret;
    757 }
    758 
    759 int intel_gpu_reset(struct drm_device *dev)
    760 {
    761 	struct drm_i915_private *dev_priv = dev->dev_private;
    762 	int ret = -ENODEV;
    763 
    764 	switch (INTEL_INFO(dev)->gen) {
    765 	case 7:
    766 	case 6:
    767 		ret = gen6_do_reset(dev);
    768 		break;
    769 	case 5:
    770 		ret = ironlake_do_reset(dev);
    771 		break;
    772 	case 4:
    773 		ret = i965_do_reset(dev);
    774 		break;
    775 	case 2:
    776 		ret = i8xx_do_reset(dev);
    777 		break;
    778 	}
    779 
    780 	/* Also reset the gpu hangman. */
    781 	if (dev_priv->stop_rings) {
    782 		DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
    783 		dev_priv->stop_rings = 0;
    784 		if (ret == -ENODEV) {
    785 			DRM_ERROR("Reset not implemented, but ignoring "
    786 				  "error for simulated gpu hangs\n");
    787 			ret = 0;
    788 		}
    789 	}
    790 
    791 	return ret;
    792 }
    793 
    794 /**
    795  * i915_reset - reset chip after a hang
    796  * @dev: drm device to reset
    797  *
    798  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
    799  * reset or otherwise an error code.
    800  *
    801  * Procedure is fairly simple:
    802  *   - reset the chip using the reset reg
    803  *   - re-init context state
    804  *   - re-init hardware status page
    805  *   - re-init ring buffer
    806  *   - re-init interrupt state
    807  *   - re-init display
    808  */
    809 int i915_reset(struct drm_device *dev)
    810 {
    811 	drm_i915_private_t *dev_priv = dev->dev_private;
    812 	int ret;
    813 
    814 	if (!i915_try_reset)
    815 		return 0;
    816 
    817 	mutex_lock(&dev->struct_mutex);
    818 
    819 	i915_gem_reset(dev);
    820 
    821 	ret = -ENODEV;
    822 	if (get_seconds() - dev_priv->last_gpu_reset < 5)
    823 		DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
    824 	else
    825 		ret = intel_gpu_reset(dev);
    826 
    827 	dev_priv->last_gpu_reset = get_seconds();
    828 	if (ret) {
    829 		DRM_ERROR("Failed to reset chip.\n");
    830 		mutex_unlock(&dev->struct_mutex);
    831 		return ret;
    832 	}
    833 
    834 	/* Ok, now get things going again... */
    835 
    836 	/*
    837 	 * Everything depends on having the GTT running, so we need to start
    838 	 * there.  Fortunately we don't need to do this unless we reset the
    839 	 * chip at a PCI level.
    840 	 *
    841 	 * Next we need to restore the context, but we don't use those
    842 	 * yet either...
    843 	 *
    844 	 * Ring buffer needs to be re-initialized in the KMS case, or if X
    845 	 * was running at the time of the reset (i.e. we weren't VT
    846 	 * switched away).
    847 	 */
    848 	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
    849 			!dev_priv->mm.suspended) {
    850 		struct intel_ring_buffer *ring;
    851 		int i;
    852 
    853 		dev_priv->mm.suspended = 0;
    854 
    855 		i915_gem_init_swizzling(dev);
    856 
    857 		for_each_ring(ring, dev_priv, i)
    858 			ring->init(ring);
    859 
    860 		i915_gem_context_init(dev);
    861 		i915_gem_init_ppgtt(dev);
    862 
    863 		/*
    864 		 * It would make sense to re-init all the other hw state, at
    865 		 * least the rps/rc6/emon init done within modeset_init_hw. For
    866 		 * some unknown reason, this blows up my ilk, so don't.
    867 		 */
    868 
    869 		mutex_unlock(&dev->struct_mutex);
    870 
    871 		drm_irq_uninstall(dev);
    872 		drm_irq_install(dev);
    873 	} else {
    874 		mutex_unlock(&dev->struct_mutex);
    875 	}
    876 
    877 	return 0;
    878 }
    879 
    880 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
    881 {
    882 	struct intel_device_info *intel_info =
    883 		(struct intel_device_info *) ent->driver_data;
    884 
    885 	if (intel_info->is_valleyview)
    886 		if(!i915_preliminary_hw_support) {
    887 			DRM_ERROR("Preliminary hardware support disabled\n");
    888 			return -ENODEV;
    889 		}
    890 
    891 	/* Only bind to function 0 of the device. Early generations
    892 	 * used function 1 as a placeholder for multi-head. This causes
    893 	 * us confusion instead, especially on the systems where both
    894 	 * functions have the same PCI-ID!
    895 	 */
    896 	if (PCI_FUNC(pdev->devfn))
    897 		return -ENODEV;
    898 
    899 	/* We've managed to ship a kms-enabled ddx that shipped with an XvMC
    900 	 * implementation for gen3 (and only gen3) that used legacy drm maps
    901 	 * (gasp!) to share buffers between X and the client. Hence we need to
    902 	 * keep around the fake agp stuff for gen3, even when kms is enabled. */
    903 	if (intel_info->gen != 3) {
    904 		driver.driver_features &=
    905 			~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
    906 	} else if (!intel_agp_enabled) {
    907 		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
    908 		return -ENODEV;
    909 	}
    910 
    911 	return drm_get_pci_dev(pdev, ent, &driver);
    912 }
    913 
    914 static void
    915 i915_pci_remove(struct pci_dev *pdev)
    916 {
    917 	struct drm_device *dev = pci_get_drvdata(pdev);
    918 
    919 	drm_put_dev(dev);
    920 }
    921 
    922 static int i915_pm_suspend(struct device *dev)
    923 {
    924 	struct pci_dev *pdev = to_pci_dev(dev);
    925 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
    926 	int error;
    927 
    928 	if (!drm_dev || !drm_dev->dev_private) {
    929 		dev_err(dev, "DRM not initialized, aborting suspend.\n");
    930 		return -ENODEV;
    931 	}
    932 
    933 	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
    934 		return 0;
    935 
    936 	error = i915_drm_freeze(drm_dev);
    937 	if (error)
    938 		return error;
    939 
    940 	pci_disable_device(pdev);
    941 	pci_set_power_state(pdev, PCI_D3hot);
    942 
    943 	return 0;
    944 }
    945 
    946 static int i915_pm_resume(struct device *dev)
    947 {
    948 	struct pci_dev *pdev = to_pci_dev(dev);
    949 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
    950 
    951 	return i915_resume(drm_dev);
    952 }
    953 
    954 static int i915_pm_freeze(struct device *dev)
    955 {
    956 	struct pci_dev *pdev = to_pci_dev(dev);
    957 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
    958 
    959 	if (!drm_dev || !drm_dev->dev_private) {
    960 		dev_err(dev, "DRM not initialized, aborting suspend.\n");
    961 		return -ENODEV;
    962 	}
    963 
    964 	return i915_drm_freeze(drm_dev);
    965 }
    966 
    967 static int i915_pm_thaw(struct device *dev)
    968 {
    969 	struct pci_dev *pdev = to_pci_dev(dev);
    970 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
    971 
    972 	return i915_drm_thaw(drm_dev);
    973 }
    974 
    975 static int i915_pm_poweroff(struct device *dev)
    976 {
    977 	struct pci_dev *pdev = to_pci_dev(dev);
    978 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
    979 
    980 	return i915_drm_freeze(drm_dev);
    981 }
    982 
    983 static const struct dev_pm_ops i915_pm_ops = {
    984 	.suspend = i915_pm_suspend,
    985 	.resume = i915_pm_resume,
    986 	.freeze = i915_pm_freeze,
    987 	.thaw = i915_pm_thaw,
    988 	.poweroff = i915_pm_poweroff,
    989 	.restore = i915_pm_resume,
    990 };
    991 
    992 static const struct vm_operations_struct i915_gem_vm_ops = {
    993 	.fault = i915_gem_fault,
    994 	.open = drm_gem_vm_open,
    995 	.close = drm_gem_vm_close,
    996 };
    997 
    998 static const struct file_operations i915_driver_fops = {
    999 	.owner = THIS_MODULE,
   1000 	.open = drm_open,
   1001 	.release = drm_release,
   1002 	.unlocked_ioctl = drm_ioctl,
   1003 	.mmap = drm_gem_mmap,
   1004 	.poll = drm_poll,
   1005 	.fasync = drm_fasync,
   1006 	.read = drm_read,
   1007 #ifdef CONFIG_COMPAT
   1008 	.compat_ioctl = i915_compat_ioctl,
   1009 #endif
   1010 	.llseek = noop_llseek,
   1011 };
   1012 
   1013 static struct drm_driver driver = {
   1014 	/* Don't use MTRRs here; the Xserver or userspace app should
   1015 	 * deal with them for Intel hardware.
   1016 	 */
   1017 	.driver_features =
   1018 	    DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
   1019 	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
   1020 	.load = i915_driver_load,
   1021 	.unload = i915_driver_unload,
   1022 	.open = i915_driver_open,
   1023 	.lastclose = i915_driver_lastclose,
   1024 	.preclose = i915_driver_preclose,
   1025 	.postclose = i915_driver_postclose,
   1026 
   1027 	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
   1028 	.suspend = i915_suspend,
   1029 	.resume = i915_resume,
   1030 
   1031 	.device_is_agp = i915_driver_device_is_agp,
   1032 	.master_create = i915_master_create,
   1033 	.master_destroy = i915_master_destroy,
   1034 #if defined(CONFIG_DEBUG_FS)
   1035 	.debugfs_init = i915_debugfs_init,
   1036 	.debugfs_cleanup = i915_debugfs_cleanup,
   1037 #endif
   1038 	.gem_init_object = i915_gem_init_object,
   1039 	.gem_free_object = i915_gem_free_object,
   1040 	.gem_vm_ops = &i915_gem_vm_ops,
   1041 
   1042 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
   1043 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
   1044 	.gem_prime_export = i915_gem_prime_export,
   1045 	.gem_prime_import = i915_gem_prime_import,
   1046 
   1047 	.dumb_create = i915_gem_dumb_create,
   1048 	.dumb_map_offset = i915_gem_mmap_gtt,
   1049 	.dumb_destroy = i915_gem_dumb_destroy,
   1050 	.ioctls = i915_ioctls,
   1051 	.fops = &i915_driver_fops,
   1052 	.name = DRIVER_NAME,
   1053 	.desc = DRIVER_DESC,
   1054 	.date = DRIVER_DATE,
   1055 	.major = DRIVER_MAJOR,
   1056 	.minor = DRIVER_MINOR,
   1057 	.patchlevel = DRIVER_PATCHLEVEL,
   1058 };
   1059 
   1060 static struct pci_driver i915_pci_driver = {
   1061 	.name = DRIVER_NAME,
   1062 	.id_table = pciidlist,
   1063 	.probe = i915_pci_probe,
   1064 	.remove = i915_pci_remove,
   1065 	.driver.pm = &i915_pm_ops,
   1066 };
   1067 
   1068 static int __init i915_init(void)
   1069 {
   1070 	driver.num_ioctls = i915_max_ioctl;
   1071 
   1072 	/*
   1073 	 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
   1074 	 * explicitly disabled with the module pararmeter.
   1075 	 *
   1076 	 * Otherwise, just follow the parameter (defaulting to off).
   1077 	 *
   1078 	 * Allow optional vga_text_mode_force boot option to override
   1079 	 * the default behavior.
   1080 	 */
   1081 #if defined(CONFIG_DRM_I915_KMS)
   1082 	if (i915_modeset != 0)
   1083 		driver.driver_features |= DRIVER_MODESET;
   1084 #endif
   1085 	if (i915_modeset == 1)
   1086 		driver.driver_features |= DRIVER_MODESET;
   1087 
   1088 #ifdef CONFIG_VGA_CONSOLE
   1089 	if (vgacon_text_force() && i915_modeset == -1)
   1090 		driver.driver_features &= ~DRIVER_MODESET;
   1091 #endif
   1092 
   1093 	if (!(driver.driver_features & DRIVER_MODESET))
   1094 		driver.get_vblank_timestamp = NULL;
   1095 
   1096 	return drm_pci_init(&driver, &i915_pci_driver);
   1097 }
   1098 
   1099 static void __exit i915_exit(void)
   1100 {
   1101 	drm_pci_exit(&driver, &i915_pci_driver);
   1102 }
   1103 
   1104 module_init(i915_init);
   1105 module_exit(i915_exit);
   1106 
   1107 MODULE_AUTHOR(DRIVER_AUTHOR);
   1108 MODULE_DESCRIPTION(DRIVER_DESC);
   1109 MODULE_LICENSE("GPL and additional rights");
   1110 
   1111 /* We give fast paths for the really cool registers */
   1112 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
   1113 	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
   1114 	 ((reg) < 0x40000) &&            \
   1115 	 ((reg) != FORCEWAKE))
   1116 
   1117 static bool IS_DISPLAYREG(u32 reg)
   1118 {
   1119 	/*
   1120 	 * This should make it easier to transition modules over to the
   1121 	 * new register block scheme, since we can do it incrementally.
   1122 	 */
   1123 	if (reg >= VLV_DISPLAY_BASE)
   1124 		return false;
   1125 
   1126 	if (reg >= RENDER_RING_BASE &&
   1127 	    reg < RENDER_RING_BASE + 0xff)
   1128 		return false;
   1129 	if (reg >= GEN6_BSD_RING_BASE &&
   1130 	    reg < GEN6_BSD_RING_BASE + 0xff)
   1131 		return false;
   1132 	if (reg >= BLT_RING_BASE &&
   1133 	    reg < BLT_RING_BASE + 0xff)
   1134 		return false;
   1135 
   1136 	if (reg == PGTBL_ER)
   1137 		return false;
   1138 
   1139 	if (reg >= IPEIR_I965 &&
   1140 	    reg < HWSTAM)
   1141 		return false;
   1142 
   1143 	if (reg == MI_MODE)
   1144 		return false;
   1145 
   1146 	if (reg == GFX_MODE_GEN7)
   1147 		return false;
   1148 
   1149 	if (reg == RENDER_HWS_PGA_GEN7 ||
   1150 	    reg == BSD_HWS_PGA_GEN7 ||
   1151 	    reg == BLT_HWS_PGA_GEN7)
   1152 		return false;
   1153 
   1154 	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
   1155 	    reg == GEN6_BSD_RNCID)
   1156 		return false;
   1157 
   1158 	if (reg == GEN6_BLITTER_ECOSKPD)
   1159 		return false;
   1160 
   1161 	if (reg >= 0x4000c &&
   1162 	    reg <= 0x4002c)
   1163 		return false;
   1164 
   1165 	if (reg >= 0x4f000 &&
   1166 	    reg <= 0x4f08f)
   1167 		return false;
   1168 
   1169 	if (reg >= 0x4f100 &&
   1170 	    reg <= 0x4f11f)
   1171 		return false;
   1172 
   1173 	if (reg >= VLV_MASTER_IER &&
   1174 	    reg <= GEN6_PMIER)
   1175 		return false;
   1176 
   1177 	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
   1178 	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
   1179 		return false;
   1180 
   1181 	if (reg >= VLV_IIR_RW &&
   1182 	    reg <= VLV_ISR)
   1183 		return false;
   1184 
   1185 	if (reg == FORCEWAKE_VLV ||
   1186 	    reg == FORCEWAKE_ACK_VLV)
   1187 		return false;
   1188 
   1189 	if (reg == GEN6_GDRST)
   1190 		return false;
   1191 
   1192 	switch (reg) {
   1193 	case _3D_CHICKEN3:
   1194 	case IVB_CHICKEN3:
   1195 	case GEN7_COMMON_SLICE_CHICKEN1:
   1196 	case GEN7_L3CNTLREG1:
   1197 	case GEN7_L3_CHICKEN_MODE_REGISTER:
   1198 	case GEN7_ROW_CHICKEN2:
   1199 	case GEN7_L3SQCREG4:
   1200 	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
   1201 	case GEN7_HALF_SLICE_CHICKEN1:
   1202 	case GEN6_MBCTL:
   1203 	case GEN6_UCGCTL2:
   1204 		return false;
   1205 	default:
   1206 		break;
   1207 	}
   1208 
   1209 	return true;
   1210 }
   1211 
   1212 static void
   1213 ilk_dummy_write(struct drm_i915_private *dev_priv)
   1214 {
   1215 	/* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
   1216 	 * chip from rc6 before touching it for real. MI_MODE is masked, hence
   1217 	 * harmless to write 0 into. */
   1218 	I915_WRITE_NOTRACE(MI_MODE, 0);
   1219 }
   1220 
   1221 #ifdef __NetBSD__
   1222 #define __i915_read(x, y) \
   1223 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
   1224 	u##x val = 0; \
   1225 	if (IS_GEN5(dev_priv->dev)) \
   1226 		ilk_dummy_write(dev_priv); \
   1227 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
   1228 		unsigned long irqflags; \
   1229 		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
   1230 		if (dev_priv->forcewake_count == 0) \
   1231 			dev_priv->gt.force_wake_get(dev_priv); \
   1232 		val = DRM_READ##x(dev_priv->regs_map, reg); \
   1233 		if (dev_priv->forcewake_count == 0) \
   1234 			dev_priv->gt.force_wake_put(dev_priv); \
   1235 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
   1236 	} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
   1237 		val = DRM_READ##x(dev_priv->regs_map, reg + 0x180000);	\
   1238 	} else { \
   1239 		val = DRM_READ##x(dev_priv->regs_map, reg); \
   1240 	} \
   1241 	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
   1242 	return val; \
   1243 }
   1244 #else
   1245 #define __i915_read(x, y) \
   1246 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
   1247 	u##x val = 0; \
   1248 	if (IS_GEN5(dev_priv->dev)) \
   1249 		ilk_dummy_write(dev_priv); \
   1250 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
   1251 		unsigned long irqflags; \
   1252 		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
   1253 		if (dev_priv->forcewake_count == 0) \
   1254 			dev_priv->gt.force_wake_get(dev_priv); \
   1255 		val = read##y(dev_priv->regs + reg); \
   1256 		if (dev_priv->forcewake_count == 0) \
   1257 			dev_priv->gt.force_wake_put(dev_priv); \
   1258 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
   1259 	} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
   1260 		val = read##y(dev_priv->regs + reg + 0x180000);		\
   1261 	} else { \
   1262 		val = read##y(dev_priv->regs + reg); \
   1263 	} \
   1264 	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
   1265 	return val; \
   1266 }
   1267 #endif
   1268 
   1269 __i915_read(8, b)
   1270 __i915_read(16, w)
   1271 __i915_read(32, l)
   1272 __i915_read(64, q)
   1273 #undef __i915_read
   1274 
   1275 #ifdef __NetBSD__
   1276 #define __i915_write(x, y) \
   1277 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
   1278 	u32 __fifo_ret = 0; \
   1279 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
   1280 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
   1281 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
   1282 	} \
   1283 	if (IS_GEN5(dev_priv->dev)) \
   1284 		ilk_dummy_write(dev_priv); \
   1285 	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
   1286 		DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
   1287 		I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
   1288 	} \
   1289 	if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
   1290 		DRM_WRITE##x(dev_priv->regs_map, reg + 0x180000, val);	\
   1291 	} else {							\
   1292 		DRM_WRITE##x(dev_priv->regs_map, reg, val);		\
   1293 	}								\
   1294 	if (unlikely(__fifo_ret)) { \
   1295 		gen6_gt_check_fifodbg(dev_priv); \
   1296 	} \
   1297 	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
   1298 		DRM_ERROR("Unclaimed write to %x\n", reg); \
   1299 		DRM_WRITE32(dev_priv->regs_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
   1300 	} \
   1301 }
   1302 #else
   1303 #define __i915_write(x, y) \
   1304 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
   1305 	u32 __fifo_ret = 0; \
   1306 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
   1307 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
   1308 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
   1309 	} \
   1310 	if (IS_GEN5(dev_priv->dev)) \
   1311 		ilk_dummy_write(dev_priv); \
   1312 	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
   1313 		DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
   1314 		I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
   1315 	} \
   1316 	if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
   1317 		write##y(val, dev_priv->regs + reg + 0x180000);		\
   1318 	} else {							\
   1319 		write##y(val, dev_priv->regs + reg);			\
   1320 	}								\
   1321 	if (unlikely(__fifo_ret)) { \
   1322 		gen6_gt_check_fifodbg(dev_priv); \
   1323 	} \
   1324 	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
   1325 		DRM_ERROR("Unclaimed write to %x\n", reg); \
   1326 		writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);	\
   1327 	} \
   1328 }
   1329 #endif
   1330 
   1331 __i915_write(8, b)
   1332 __i915_write(16, w)
   1333 __i915_write(32, l)
   1334 __i915_write(64, q)
   1335 #undef __i915_write
   1336 
   1337 static const struct register_whitelist {
   1338 	uint64_t offset;
   1339 	uint32_t size;
   1340 	uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
   1341 } whitelist[] = {
   1342 	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
   1343 };
   1344 
   1345 int i915_reg_read_ioctl(struct drm_device *dev,
   1346 			void *data, struct drm_file *file)
   1347 {
   1348 	struct drm_i915_private *dev_priv = dev->dev_private;
   1349 	struct drm_i915_reg_read *reg = data;
   1350 	struct register_whitelist const *entry = whitelist;
   1351 	int i;
   1352 
   1353 	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
   1354 		if (entry->offset == reg->offset &&
   1355 		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
   1356 			break;
   1357 	}
   1358 
   1359 	if (i == ARRAY_SIZE(whitelist))
   1360 		return -EINVAL;
   1361 
   1362 	switch (entry->size) {
   1363 	case 8:
   1364 		reg->val = I915_READ64(reg->offset);
   1365 		break;
   1366 	case 4:
   1367 		reg->val = I915_READ(reg->offset);
   1368 		break;
   1369 	case 2:
   1370 		reg->val = I915_READ16(reg->offset);
   1371 		break;
   1372 	case 1:
   1373 		reg->val = I915_READ8(reg->offset);
   1374 		break;
   1375 	default:
   1376 		WARN_ON(1);
   1377 		return -EINVAL;
   1378 	}
   1379 
   1380 	return 0;
   1381 }
   1382