i915_gem_gtt.c revision 1.15.4.1
1 /* $NetBSD: i915_gem_gtt.c,v 1.15.4.1 2019/12/12 21:00:32 martin Exp $ */ 2 3 /* 4 * Copyright 2010 Daniel Vetter 5 * Copyright 2011-2014 Intel Corporation 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24 * IN THE SOFTWARE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: i915_gem_gtt.c,v 1.15.4.1 2019/12/12 21:00:32 martin Exp $"); 30 31 #include <linux/bitmap.h> 32 #include <linux/err.h> 33 #include <linux/seq_file.h> 34 #include <drm/drmP.h> 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include "i915_vgpu.h" 38 #include "i915_trace.h" 39 #include "intel_drv.h" 40 41 #ifdef __NetBSD__ 42 #include <drm/bus_dma_hacks.h> 43 #include <x86/machdep.h> 44 #include <x86/pte.h> 45 #define _PAGE_PRESENT PG_V /* 0x01 PTE is present / valid */ 46 #define _PAGE_RW PG_RW /* 0x02 read/write */ 47 #define _PAGE_PWT PG_WT /* 0x08 write-through */ 48 #define _PAGE_PCD PG_N /* 0x10 page cache disabled / non-cacheable */ 49 #define _PAGE_PAT PG_PAT /* 0x80 page attribute table on PTE */ 50 #endif 51 52 /** 53 * DOC: Global GTT views 54 * 55 * Background and previous state 56 * 57 * Historically objects could exists (be bound) in global GTT space only as 58 * singular instances with a view representing all of the object's backing pages 59 * in a linear fashion. This view will be called a normal view. 60 * 61 * To support multiple views of the same object, where the number of mapped 62 * pages is not equal to the backing store, or where the layout of the pages 63 * is not linear, concept of a GGTT view was added. 64 * 65 * One example of an alternative view is a stereo display driven by a single 66 * image. In this case we would have a framebuffer looking like this 67 * (2x2 pages): 68 * 69 * 12 70 * 34 71 * 72 * Above would represent a normal GGTT view as normally mapped for GPU or CPU 73 * rendering. In contrast, fed to the display engine would be an alternative 74 * view which could look something like this: 75 * 76 * 1212 77 * 3434 78 * 79 * In this example both the size and layout of pages in the alternative view is 80 * different from the normal view. 81 * 82 * Implementation and usage 83 * 84 * GGTT views are implemented using VMAs and are distinguished via enum 85 * i915_ggtt_view_type and struct i915_ggtt_view. 86 * 87 * A new flavour of core GEM functions which work with GGTT bound objects were 88 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid 89 * renaming in large amounts of code. They take the struct i915_ggtt_view 90 * parameter encapsulating all metadata required to implement a view. 91 * 92 * As a helper for callers which are only interested in the normal view, 93 * globally const i915_ggtt_view_normal singleton instance exists. All old core 94 * GEM API functions, the ones not taking the view parameter, are operating on, 95 * or with the normal GGTT view. 96 * 97 * Code wanting to add or use a new GGTT view needs to: 98 * 99 * 1. Add a new enum with a suitable name. 100 * 2. Extend the metadata in the i915_ggtt_view structure if required. 101 * 3. Add support to i915_get_vma_pages(). 102 * 103 * New views are required to build a scatter-gather table from within the 104 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and 105 * exists for the lifetime of an VMA. 106 * 107 * Core API is designed to have copy semantics which means that passed in 108 * struct i915_ggtt_view does not need to be persistent (left around after 109 * calling the core API functions). 110 * 111 */ 112 113 static int 114 i915_get_ggtt_vma_pages(struct i915_vma *vma); 115 116 const struct i915_ggtt_view i915_ggtt_view_normal; 117 const struct i915_ggtt_view i915_ggtt_view_rotated = { 118 .type = I915_GGTT_VIEW_ROTATED 119 }; 120 121 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 122 { 123 bool has_aliasing_ppgtt; 124 bool has_full_ppgtt; 125 126 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; 127 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; 128 129 if (intel_vgpu_active(dev)) 130 has_full_ppgtt = false; /* emulation is too hard */ 131 132 /* 133 * We don't allow disabling PPGTT for gen9+ as it's a requirement for 134 * execlists, the sole mechanism available to submit work. 135 */ 136 if (INTEL_INFO(dev)->gen < 9 && 137 (enable_ppgtt == 0 || !has_aliasing_ppgtt)) 138 return 0; 139 140 /* Full PPGTT is required by the Gen9 cmdparser */ 141 if (enable_ppgtt == 1 && INTEL_INFO(dev)->gen != 9) 142 return 1; 143 144 if (enable_ppgtt == 2 && has_full_ppgtt) 145 return 2; 146 147 #ifdef CONFIG_INTEL_IOMMU 148 /* Disable ppgtt on SNB if VT-d is on. */ 149 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { 150 DRM_INFO("Disabling PPGTT because VT-d is on\n"); 151 return 0; 152 } 153 #endif 154 155 /* Early VLV doesn't have this */ 156 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && 157 dev->pdev->revision < 0xb) { 158 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); 159 return 0; 160 } 161 162 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) 163 return 2; 164 else 165 return has_aliasing_ppgtt ? 1 : 0; 166 } 167 168 static int ppgtt_bind_vma(struct i915_vma *vma, 169 enum i915_cache_level cache_level, 170 u32 unused) 171 { 172 u32 pte_flags = 0; 173 174 /* Applicable to VLV, and gen8+ */ 175 pte_flags = 0; 176 if (vma->obj->gt_ro) 177 pte_flags |= PTE_READ_ONLY; 178 179 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, 180 cache_level, pte_flags); 181 182 return 0; 183 } 184 185 static void ppgtt_unbind_vma(struct i915_vma *vma) 186 { 187 vma->vm->clear_range(vma->vm, 188 vma->node.start, 189 vma->obj->base.size, 190 true); 191 } 192 193 static gen8_pte_t gen8_pte_encode(dma_addr_t addr, 194 enum i915_cache_level level, 195 bool valid, u32 flags) 196 { 197 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; 198 pte |= addr; 199 200 if (unlikely(flags & PTE_READ_ONLY)) 201 pte &= ~_PAGE_RW; 202 203 switch (level) { 204 case I915_CACHE_NONE: 205 pte |= PPAT_UNCACHED_INDEX; 206 break; 207 case I915_CACHE_WT: 208 pte |= PPAT_DISPLAY_ELLC_INDEX; 209 break; 210 default: 211 pte |= PPAT_CACHED_INDEX; 212 break; 213 } 214 215 return pte; 216 } 217 218 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, 219 const enum i915_cache_level level) 220 { 221 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; 222 pde |= addr; 223 if (level != I915_CACHE_NONE) 224 pde |= PPAT_CACHED_PDE_INDEX; 225 else 226 pde |= PPAT_UNCACHED_INDEX; 227 return pde; 228 } 229 230 #define gen8_pdpe_encode gen8_pde_encode 231 #define gen8_pml4e_encode gen8_pde_encode 232 233 static gen6_pte_t snb_pte_encode(dma_addr_t addr, 234 enum i915_cache_level level, 235 bool valid, u32 unused) 236 { 237 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 238 pte |= GEN6_PTE_ADDR_ENCODE(addr); 239 240 switch (level) { 241 case I915_CACHE_L3_LLC: 242 case I915_CACHE_LLC: 243 pte |= GEN6_PTE_CACHE_LLC; 244 break; 245 case I915_CACHE_NONE: 246 pte |= GEN6_PTE_UNCACHED; 247 break; 248 default: 249 MISSING_CASE(level); 250 } 251 252 return pte; 253 } 254 255 static gen6_pte_t ivb_pte_encode(dma_addr_t addr, 256 enum i915_cache_level level, 257 bool valid, u32 unused) 258 { 259 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 260 pte |= GEN6_PTE_ADDR_ENCODE(addr); 261 262 switch (level) { 263 case I915_CACHE_L3_LLC: 264 pte |= GEN7_PTE_CACHE_L3_LLC; 265 break; 266 case I915_CACHE_LLC: 267 pte |= GEN6_PTE_CACHE_LLC; 268 break; 269 case I915_CACHE_NONE: 270 pte |= GEN6_PTE_UNCACHED; 271 break; 272 default: 273 MISSING_CASE(level); 274 } 275 276 return pte; 277 } 278 279 static gen6_pte_t byt_pte_encode(dma_addr_t addr, 280 enum i915_cache_level level, 281 bool valid, u32 flags) 282 { 283 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 284 pte |= GEN6_PTE_ADDR_ENCODE(addr); 285 286 if (!(flags & PTE_READ_ONLY)) 287 pte |= BYT_PTE_WRITEABLE; 288 289 if (level != I915_CACHE_NONE) 290 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; 291 292 return pte; 293 } 294 295 static gen6_pte_t hsw_pte_encode(dma_addr_t addr, 296 enum i915_cache_level level, 297 bool valid, u32 unused) 298 { 299 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 300 pte |= HSW_PTE_ADDR_ENCODE(addr); 301 302 if (level != I915_CACHE_NONE) 303 pte |= HSW_WB_LLC_AGE3; 304 305 return pte; 306 } 307 308 static gen6_pte_t iris_pte_encode(dma_addr_t addr, 309 enum i915_cache_level level, 310 bool valid, u32 unused) 311 { 312 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 313 pte |= HSW_PTE_ADDR_ENCODE(addr); 314 315 switch (level) { 316 case I915_CACHE_NONE: 317 break; 318 case I915_CACHE_WT: 319 pte |= HSW_WT_ELLC_LLC_AGE3; 320 break; 321 default: 322 pte |= HSW_WB_ELLC_LLC_AGE3; 323 break; 324 } 325 326 return pte; 327 } 328 329 static void *kmap_page_dma(struct i915_page_dma *); 330 static void kunmap_page_dma(struct drm_device *, void *); 331 332 static int __setup_page_dma(struct drm_device *dev, 333 struct i915_page_dma *p, gfp_t flags) 334 { 335 #ifdef __NetBSD__ 336 int busdmaflags = 0; 337 int error; 338 int nseg = 1; 339 340 if (flags & __GFP_WAIT) 341 busdmaflags |= BUS_DMA_WAITOK; 342 else 343 busdmaflags |= BUS_DMA_NOWAIT; 344 345 error = bus_dmamem_alloc(dev->dmat, PAGE_SIZE, PAGE_SIZE, 0, &p->seg, 346 nseg, &nseg, busdmaflags); 347 if (error) { 348 fail0: p->map = NULL; 349 return -error; /* XXX errno NetBSD->Linux */ 350 } 351 KASSERT(nseg == 1); 352 error = bus_dmamap_create(dev->dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 353 busdmaflags, &p->map); 354 if (error) { 355 fail1: bus_dmamem_free(dev->dmat, &p->seg, 1); 356 goto fail0; 357 } 358 error = bus_dmamap_load_raw(dev->dmat, p->map, &p->seg, 1, PAGE_SIZE, 359 busdmaflags); 360 if (error) { 361 fail2: __unused 362 bus_dmamap_destroy(dev->dmat, p->map); 363 goto fail1; 364 } 365 366 if (flags & __GFP_ZERO) { 367 void *va = kmap_page_dma(p); 368 memset(va, 0, PAGE_SIZE); 369 kunmap_page_dma(dev, va); 370 } 371 #else 372 struct device *device = &dev->pdev->dev; 373 374 p->page = alloc_page(flags); 375 if (!p->page) 376 return -ENOMEM; 377 378 p->daddr = dma_map_page(device, 379 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); 380 381 if (dma_mapping_error(device, p->daddr)) { 382 __free_page(p->page); 383 return -EINVAL; 384 } 385 #endif 386 387 return 0; 388 } 389 390 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) 391 { 392 return __setup_page_dma(dev, p, GFP_KERNEL); 393 } 394 395 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) 396 { 397 #ifdef __NetBSD__ 398 if (WARN_ON(!p->map)) 399 return; 400 401 bus_dmamap_unload(dev->dmat, p->map); 402 bus_dmamap_destroy(dev->dmat, p->map); 403 bus_dmamem_free(dev->dmat, &p->seg, 1); 404 p->map = NULL; 405 #else 406 if (WARN_ON(!p->page)) 407 return; 408 409 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); 410 __free_page(p->page); 411 memset(p, 0, sizeof(*p)); 412 #endif 413 } 414 415 static void *kmap_page_dma(struct i915_page_dma *p) 416 { 417 #ifdef __NetBSD__ 418 return kmap_atomic(container_of(PHYS_TO_VM_PAGE(p->seg.ds_addr), 419 struct page, p_vmp)); 420 #else 421 return kmap_atomic(p->page); 422 #endif 423 } 424 425 /* We use the flushing unmap only with ppgtt structures: 426 * page directories, page tables and scratch pages. 427 */ 428 static void kunmap_page_dma(struct drm_device *dev, void *vaddr) 429 { 430 /* There are only few exceptions for gen >=6. chv and bxt. 431 * And we are not sure about the latter so play safe for now. 432 */ 433 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) 434 drm_clflush_virt_range(vaddr, PAGE_SIZE); 435 436 kunmap_atomic(vaddr); 437 } 438 439 #define kmap_px(px) kmap_page_dma(px_base(px)) 440 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) 441 442 #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) 443 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) 444 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) 445 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) 446 447 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, 448 const uint64_t val) 449 { 450 int i; 451 uint64_t * const vaddr = kmap_page_dma(p); 452 453 for (i = 0; i < 512; i++) 454 vaddr[i] = val; 455 456 kunmap_page_dma(dev, vaddr); 457 } 458 459 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, 460 const uint32_t val32) 461 { 462 uint64_t v = val32; 463 464 v = v << 32 | val32; 465 466 fill_page_dma(dev, p, v); 467 } 468 469 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev) 470 { 471 struct i915_page_scratch *sp; 472 int ret; 473 474 sp = kzalloc(sizeof(*sp), GFP_KERNEL); 475 if (sp == NULL) 476 return ERR_PTR(-ENOMEM); 477 478 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); 479 if (ret) { 480 kfree(sp); 481 return ERR_PTR(ret); 482 } 483 484 #ifndef __NetBSD__ /* XXX ??? */ 485 set_pages_uc(px_page(sp), 1); 486 #endif 487 488 return sp; 489 } 490 491 static void free_scratch_page(struct drm_device *dev, 492 struct i915_page_scratch *sp) 493 { 494 #ifndef __NetBSD__ /* XXX ??? */ 495 set_pages_wb(px_page(sp), 1); 496 #endif 497 498 cleanup_px(dev, sp); 499 kfree(sp); 500 } 501 502 static struct i915_page_table *alloc_pt(struct drm_device *dev) 503 { 504 struct i915_page_table *pt; 505 const size_t count = INTEL_INFO(dev)->gen >= 8 ? 506 GEN8_PTES : GEN6_PTES; 507 int ret = -ENOMEM; 508 509 pt = kzalloc(sizeof(*pt), GFP_KERNEL); 510 if (!pt) 511 return ERR_PTR(-ENOMEM); 512 513 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), 514 GFP_KERNEL); 515 516 if (!pt->used_ptes) 517 goto fail_bitmap; 518 519 ret = setup_px(dev, pt); 520 if (ret) 521 goto fail_page_m; 522 523 return pt; 524 525 fail_page_m: 526 kfree(pt->used_ptes); 527 fail_bitmap: 528 kfree(pt); 529 530 return ERR_PTR(ret); 531 } 532 533 static void free_pt(struct drm_device *dev, struct i915_page_table *pt) 534 { 535 cleanup_px(dev, pt); 536 kfree(pt->used_ptes); 537 kfree(pt); 538 } 539 540 static void gen8_initialize_pt(struct i915_address_space *vm, 541 struct i915_page_table *pt) 542 { 543 gen8_pte_t scratch_pte; 544 545 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), 546 I915_CACHE_LLC, true, 0); 547 548 fill_px(vm->dev, pt, scratch_pte); 549 } 550 551 static void gen6_initialize_pt(struct i915_address_space *vm, 552 struct i915_page_table *pt) 553 { 554 gen6_pte_t scratch_pte; 555 556 WARN_ON(px_dma(vm->scratch_page) == 0); 557 558 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), 559 I915_CACHE_LLC, true, 0); 560 561 fill32_px(vm->dev, pt, scratch_pte); 562 } 563 564 static struct i915_page_directory *alloc_pd(struct drm_device *dev) 565 { 566 struct i915_page_directory *pd; 567 int ret = -ENOMEM; 568 569 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 570 if (!pd) 571 return ERR_PTR(-ENOMEM); 572 573 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), 574 sizeof(*pd->used_pdes), GFP_KERNEL); 575 if (!pd->used_pdes) 576 goto fail_bitmap; 577 578 ret = setup_px(dev, pd); 579 if (ret) 580 goto fail_page_m; 581 582 return pd; 583 584 fail_page_m: 585 kfree(pd->used_pdes); 586 fail_bitmap: 587 kfree(pd); 588 589 return ERR_PTR(ret); 590 } 591 592 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) 593 { 594 if (px_page(pd)) { 595 cleanup_px(dev, pd); 596 kfree(pd->used_pdes); 597 kfree(pd); 598 } 599 } 600 601 static void gen8_initialize_pd(struct i915_address_space *vm, 602 struct i915_page_directory *pd) 603 { 604 gen8_pde_t scratch_pde; 605 606 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); 607 608 fill_px(vm->dev, pd, scratch_pde); 609 } 610 611 static int __pdp_init(struct drm_device *dev, 612 struct i915_page_directory_pointer *pdp) 613 { 614 size_t pdpes = I915_PDPES_PER_PDP(dev); 615 616 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), 617 sizeof(unsigned long), 618 GFP_KERNEL); 619 if (!pdp->used_pdpes) 620 return -ENOMEM; 621 622 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), 623 GFP_KERNEL); 624 if (!pdp->page_directory) { 625 kfree(pdp->used_pdpes); 626 /* the PDP might be the statically allocated top level. Keep it 627 * as clean as possible */ 628 pdp->used_pdpes = NULL; 629 return -ENOMEM; 630 } 631 632 return 0; 633 } 634 635 static void __pdp_fini(struct i915_page_directory_pointer *pdp) 636 { 637 kfree(pdp->used_pdpes); 638 kfree(pdp->page_directory); 639 pdp->page_directory = NULL; 640 } 641 642 static struct 643 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) 644 { 645 struct i915_page_directory_pointer *pdp; 646 int ret = -ENOMEM; 647 648 WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); 649 650 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); 651 if (!pdp) 652 return ERR_PTR(-ENOMEM); 653 654 ret = __pdp_init(dev, pdp); 655 if (ret) 656 goto fail_bitmap; 657 658 ret = setup_px(dev, pdp); 659 if (ret) 660 goto fail_page_m; 661 662 return pdp; 663 664 fail_page_m: 665 __pdp_fini(pdp); 666 fail_bitmap: 667 kfree(pdp); 668 669 return ERR_PTR(ret); 670 } 671 672 static void free_pdp(struct drm_device *dev, 673 struct i915_page_directory_pointer *pdp) 674 { 675 __pdp_fini(pdp); 676 if (USES_FULL_48BIT_PPGTT(dev)) { 677 cleanup_px(dev, pdp); 678 kfree(pdp); 679 } 680 } 681 682 static void gen8_initialize_pdp(struct i915_address_space *vm, 683 struct i915_page_directory_pointer *pdp) 684 { 685 gen8_ppgtt_pdpe_t scratch_pdpe; 686 687 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); 688 689 fill_px(vm->dev, pdp, scratch_pdpe); 690 } 691 692 static void gen8_initialize_pml4(struct i915_address_space *vm, 693 struct i915_pml4 *pml4) 694 { 695 gen8_ppgtt_pml4e_t scratch_pml4e; 696 697 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), 698 I915_CACHE_LLC); 699 700 fill_px(vm->dev, pml4, scratch_pml4e); 701 } 702 703 static void 704 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, 705 struct i915_page_directory_pointer *pdp, 706 struct i915_page_directory *pd, 707 int index) 708 { 709 gen8_ppgtt_pdpe_t *page_directorypo; 710 711 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) 712 return; 713 714 page_directorypo = kmap_px(pdp); 715 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); 716 kunmap_px(ppgtt, page_directorypo); 717 } 718 719 static void 720 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, 721 struct i915_pml4 *pml4, 722 struct i915_page_directory_pointer *pdp, 723 int index) 724 { 725 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); 726 727 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); 728 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); 729 kunmap_px(ppgtt, pagemap); 730 } 731 732 /* Broadwell Page Directory Pointer Descriptors */ 733 static int gen8_write_pdp(struct drm_i915_gem_request *req, 734 unsigned entry, 735 dma_addr_t addr) 736 { 737 struct intel_engine_cs *ring = req->ring; 738 int ret; 739 740 BUG_ON(entry >= 4); 741 742 ret = intel_ring_begin(req, 6); 743 if (ret) 744 return ret; 745 746 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 747 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); 748 intel_ring_emit(ring, upper_32_bits(addr)); 749 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 750 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); 751 intel_ring_emit(ring, lower_32_bits(addr)); 752 intel_ring_advance(ring); 753 754 return 0; 755 } 756 757 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, 758 struct drm_i915_gem_request *req) 759 { 760 int i, ret; 761 762 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { 763 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 764 765 ret = gen8_write_pdp(req, i, pd_daddr); 766 if (ret) 767 return ret; 768 } 769 770 return 0; 771 } 772 773 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, 774 struct drm_i915_gem_request *req) 775 { 776 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); 777 } 778 779 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm, 780 struct i915_page_directory_pointer *pdp, 781 uint64_t start, 782 uint64_t length, 783 gen8_pte_t scratch_pte) 784 { 785 struct i915_hw_ppgtt *ppgtt = 786 container_of(vm, struct i915_hw_ppgtt, base); 787 gen8_pte_t *pt_vaddr; 788 unsigned pdpe = gen8_pdpe_index(start); 789 unsigned pde = gen8_pde_index(start); 790 unsigned pte = gen8_pte_index(start); 791 unsigned num_entries = length >> PAGE_SHIFT; 792 unsigned last_pte, i; 793 794 if (WARN_ON(!pdp)) 795 return; 796 797 while (num_entries) { 798 struct i915_page_directory *pd; 799 struct i915_page_table *pt; 800 801 if (WARN_ON(!pdp->page_directory[pdpe])) 802 break; 803 804 pd = pdp->page_directory[pdpe]; 805 806 if (WARN_ON(!pd->page_table[pde])) 807 break; 808 809 pt = pd->page_table[pde]; 810 811 if (WARN_ON(!px_page(pt))) 812 break; 813 814 last_pte = pte + num_entries; 815 if (last_pte > GEN8_PTES) 816 last_pte = GEN8_PTES; 817 818 pt_vaddr = kmap_px(pt); 819 820 for (i = pte; i < last_pte; i++) { 821 pt_vaddr[i] = scratch_pte; 822 num_entries--; 823 } 824 825 kunmap_px(ppgtt, pt_vaddr); 826 827 pte = 0; 828 if (++pde == I915_PDES) { 829 if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) 830 break; 831 pde = 0; 832 } 833 } 834 } 835 836 static void gen8_ppgtt_clear_range(struct i915_address_space *vm, 837 uint64_t start, 838 uint64_t length, 839 bool use_scratch) 840 { 841 struct i915_hw_ppgtt *ppgtt = 842 container_of(vm, struct i915_hw_ppgtt, base); 843 gen8_pte_t scratch_pte = 844 gen8_pte_encode(px_dma(vm->scratch_page), 845 I915_CACHE_LLC, use_scratch, 0); 846 847 if (!USES_FULL_48BIT_PPGTT(vm->dev)) { 848 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length, 849 scratch_pte); 850 } else { 851 uint64_t templ4, pml4e; 852 struct i915_page_directory_pointer *pdp; 853 854 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) { 855 gen8_ppgtt_clear_pte_range(vm, pdp, start, length, 856 scratch_pte); 857 } 858 } 859 } 860 861 #ifdef __NetBSD__ 862 static void 863 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, 864 struct i915_page_directory_pointer *pdp, bus_dmamap_t dmamap, 865 unsigned *segp, uint64_t start, enum i915_cache_level cache_level, 866 u32 flags) 867 { 868 struct i915_hw_ppgtt *ppgtt = 869 container_of(vm, struct i915_hw_ppgtt, base); 870 gen8_pte_t *pt_vaddr; 871 unsigned pdpe = gen8_pdpe_index(start); 872 unsigned pde = gen8_pde_index(start); 873 unsigned pte = gen8_pte_index(start); 874 875 pt_vaddr = NULL; 876 for (; *segp < dmamap->dm_nsegs; (*segp)++) { 877 KASSERT(dmamap->dm_segs[*segp].ds_len == PAGE_SIZE); 878 if (pt_vaddr == NULL) { 879 struct i915_page_directory *pd = 880 pdp->page_directory[pdpe]; 881 struct i915_page_table *pt = pd->page_table[pde]; 882 pt_vaddr = kmap_px(pt); 883 } 884 pt_vaddr[pte] = gen8_pte_encode(dmamap->dm_segs[*segp].ds_addr, 885 cache_level, true, flags); 886 if (++pte == GEN8_PTES) { 887 kunmap_px(ppgtt, pt_vaddr); 888 pt_vaddr = NULL; 889 if (++pde == I915_PDES) { 890 if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) 891 break; 892 pde = 0; 893 } 894 pte = 0; 895 } 896 } 897 if (pt_vaddr) 898 kunmap_px(ppgtt, pt_vaddr); 899 } 900 #else 901 static void 902 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, 903 struct i915_page_directory_pointer *pdp, 904 struct sg_page_iter *sg_iter, 905 uint64_t start, 906 enum i915_cache_level cache_level, 907 u32 flags) 908 { 909 struct i915_hw_ppgtt *ppgtt = 910 container_of(vm, struct i915_hw_ppgtt, base); 911 gen8_pte_t *pt_vaddr; 912 unsigned pdpe = gen8_pdpe_index(start); 913 unsigned pde = gen8_pde_index(start); 914 unsigned pte = gen8_pte_index(start); 915 916 pt_vaddr = NULL; 917 918 while (__sg_page_iter_next(sg_iter)) { 919 if (pt_vaddr == NULL) { 920 struct i915_page_directory *pd = pdp->page_directory[pdpe]; 921 struct i915_page_table *pt = pd->page_table[pde]; 922 pt_vaddr = kmap_px(pt); 923 } 924 925 pt_vaddr[pte] = 926 gen8_pte_encode(sg_page_iter_dma_address(sg_iter), 927 cache_level, true, flags); 928 if (++pte == GEN8_PTES) { 929 kunmap_px(ppgtt, pt_vaddr); 930 pt_vaddr = NULL; 931 if (++pde == I915_PDES) { 932 if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) 933 break; 934 pde = 0; 935 } 936 pte = 0; 937 } 938 } 939 940 if (pt_vaddr) 941 kunmap_px(ppgtt, pt_vaddr); 942 } 943 #endif 944 945 #ifdef __NetBSD__ 946 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, 947 bus_dmamap_t dmamap, uint64_t start, enum i915_cache_level cache_level, 948 u32 flags) 949 { 950 struct i915_hw_ppgtt *ppgtt = 951 container_of(vm, struct i915_hw_ppgtt, base); 952 unsigned seg = 0; 953 954 if (!USES_FULL_48BIT_PPGTT(vm->dev)) { 955 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, dmamap, &seg, 956 start, cache_level, flags); 957 } else { 958 struct i915_page_directory_pointer *pdp; 959 uint64_t templ4, pml4e; 960 uint64_t length = dmamap->dm_mapsize; 961 962 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, 963 pml4e) { 964 gen8_ppgtt_insert_pte_entries(vm, pdp, dmamap, &seg, 965 start, cache_level, flags); 966 } 967 } 968 } 969 #else 970 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, 971 struct sg_table *pages, 972 uint64_t start, 973 enum i915_cache_level cache_level, 974 u32 flags) 975 { 976 struct i915_hw_ppgtt *ppgtt = 977 container_of(vm, struct i915_hw_ppgtt, base); 978 struct sg_page_iter sg_iter; 979 980 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); 981 982 if (!USES_FULL_48BIT_PPGTT(vm->dev)) { 983 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, 984 cache_level, flags); 985 } else { 986 struct i915_page_directory_pointer *pdp; 987 uint64_t templ4, pml4e; 988 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; 989 990 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) { 991 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, 992 start, cache_level, flags); 993 } 994 } 995 } 996 #endif 997 998 static void gen8_free_page_tables(struct drm_device *dev, 999 struct i915_page_directory *pd) 1000 { 1001 int i; 1002 1003 if (!px_page(pd)) 1004 return; 1005 1006 for_each_set_bit(i, pd->used_pdes, I915_PDES) { 1007 if (WARN_ON(!pd->page_table[i])) 1008 continue; 1009 1010 free_pt(dev, pd->page_table[i]); 1011 pd->page_table[i] = NULL; 1012 } 1013 } 1014 1015 static int gen8_init_scratch(struct i915_address_space *vm) 1016 { 1017 struct drm_device *dev = vm->dev; 1018 1019 vm->scratch_page = alloc_scratch_page(dev); 1020 if (IS_ERR(vm->scratch_page)) 1021 return PTR_ERR(vm->scratch_page); 1022 1023 vm->scratch_pt = alloc_pt(dev); 1024 if (IS_ERR(vm->scratch_pt)) { 1025 free_scratch_page(dev, vm->scratch_page); 1026 return PTR_ERR(vm->scratch_pt); 1027 } 1028 1029 vm->scratch_pd = alloc_pd(dev); 1030 if (IS_ERR(vm->scratch_pd)) { 1031 free_pt(dev, vm->scratch_pt); 1032 free_scratch_page(dev, vm->scratch_page); 1033 return PTR_ERR(vm->scratch_pd); 1034 } 1035 1036 if (USES_FULL_48BIT_PPGTT(dev)) { 1037 vm->scratch_pdp = alloc_pdp(dev); 1038 if (IS_ERR(vm->scratch_pdp)) { 1039 free_pd(dev, vm->scratch_pd); 1040 free_pt(dev, vm->scratch_pt); 1041 free_scratch_page(dev, vm->scratch_page); 1042 return PTR_ERR(vm->scratch_pdp); 1043 } 1044 } 1045 1046 gen8_initialize_pt(vm, vm->scratch_pt); 1047 gen8_initialize_pd(vm, vm->scratch_pd); 1048 if (USES_FULL_48BIT_PPGTT(dev)) 1049 gen8_initialize_pdp(vm, vm->scratch_pdp); 1050 1051 return 0; 1052 } 1053 1054 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) 1055 { 1056 enum vgt_g2v_type msg; 1057 struct drm_device *dev = ppgtt->base.dev; 1058 struct drm_i915_private *dev_priv = dev->dev_private; 1059 unsigned int offset = vgtif_reg(pdp0_lo); 1060 int i; 1061 1062 if (USES_FULL_48BIT_PPGTT(dev)) { 1063 u64 daddr = px_dma(&ppgtt->pml4); 1064 1065 I915_WRITE(offset, lower_32_bits(daddr)); 1066 I915_WRITE(offset + 4, upper_32_bits(daddr)); 1067 1068 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : 1069 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); 1070 } else { 1071 for (i = 0; i < GEN8_LEGACY_PDPES; i++) { 1072 u64 daddr = i915_page_dir_dma_addr(ppgtt, i); 1073 1074 I915_WRITE(offset, lower_32_bits(daddr)); 1075 I915_WRITE(offset + 4, upper_32_bits(daddr)); 1076 1077 offset += 8; 1078 } 1079 1080 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : 1081 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); 1082 } 1083 1084 I915_WRITE(vgtif_reg(g2v_notify), msg); 1085 1086 return 0; 1087 } 1088 1089 static void gen8_free_scratch(struct i915_address_space *vm) 1090 { 1091 struct drm_device *dev = vm->dev; 1092 1093 if (USES_FULL_48BIT_PPGTT(dev)) 1094 free_pdp(dev, vm->scratch_pdp); 1095 free_pd(dev, vm->scratch_pd); 1096 free_pt(dev, vm->scratch_pt); 1097 free_scratch_page(dev, vm->scratch_page); 1098 } 1099 1100 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, 1101 struct i915_page_directory_pointer *pdp) 1102 { 1103 int i; 1104 1105 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { 1106 if (WARN_ON(!pdp->page_directory[i])) 1107 continue; 1108 1109 gen8_free_page_tables(dev, pdp->page_directory[i]); 1110 free_pd(dev, pdp->page_directory[i]); 1111 } 1112 1113 free_pdp(dev, pdp); 1114 } 1115 1116 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) 1117 { 1118 int i; 1119 1120 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { 1121 if (WARN_ON(!ppgtt->pml4.pdps[i])) 1122 continue; 1123 1124 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); 1125 } 1126 1127 cleanup_px(ppgtt->base.dev, &ppgtt->pml4); 1128 } 1129 1130 static void gen8_ppgtt_cleanup(struct i915_address_space *vm) 1131 { 1132 struct i915_hw_ppgtt *ppgtt = 1133 container_of(vm, struct i915_hw_ppgtt, base); 1134 1135 if (intel_vgpu_active(vm->dev)) 1136 gen8_ppgtt_notify_vgt(ppgtt, false); 1137 1138 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) 1139 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); 1140 else 1141 gen8_ppgtt_cleanup_4lvl(ppgtt); 1142 1143 gen8_free_scratch(vm); 1144 } 1145 1146 /** 1147 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. 1148 * @vm: Master vm structure. 1149 * @pd: Page directory for this address range. 1150 * @start: Starting virtual address to begin allocations. 1151 * @length: Size of the allocations. 1152 * @new_pts: Bitmap set by function with new allocations. Likely used by the 1153 * caller to free on error. 1154 * 1155 * Allocate the required number of page tables. Extremely similar to 1156 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by 1157 * the page directory boundary (instead of the page directory pointer). That 1158 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is 1159 * possible, and likely that the caller will need to use multiple calls of this 1160 * function to achieve the appropriate allocation. 1161 * 1162 * Return: 0 if success; negative error code otherwise. 1163 */ 1164 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, 1165 struct i915_page_directory *pd, 1166 uint64_t start, 1167 uint64_t length, 1168 unsigned long *new_pts) 1169 { 1170 struct drm_device *dev = vm->dev; 1171 struct i915_page_table *pt; 1172 uint64_t temp; 1173 uint32_t pde; 1174 1175 gen8_for_each_pde(pt, pd, start, length, temp, pde) { 1176 /* Don't reallocate page tables */ 1177 if (test_bit(pde, pd->used_pdes)) { 1178 /* Scratch is never allocated this way */ 1179 WARN_ON(pt == vm->scratch_pt); 1180 continue; 1181 } 1182 1183 pt = alloc_pt(dev); 1184 if (IS_ERR(pt)) 1185 goto unwind_out; 1186 1187 gen8_initialize_pt(vm, pt); 1188 pd->page_table[pde] = pt; 1189 __set_bit(pde, new_pts); 1190 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); 1191 } 1192 1193 return 0; 1194 1195 unwind_out: 1196 for_each_set_bit(pde, new_pts, I915_PDES) 1197 free_pt(dev, pd->page_table[pde]); 1198 1199 return -ENOMEM; 1200 } 1201 1202 /** 1203 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. 1204 * @vm: Master vm structure. 1205 * @pdp: Page directory pointer for this address range. 1206 * @start: Starting virtual address to begin allocations. 1207 * @length: Size of the allocations. 1208 * @new_pds: Bitmap set by function with new allocations. Likely used by the 1209 * caller to free on error. 1210 * 1211 * Allocate the required number of page directories starting at the pde index of 1212 * @start, and ending at the pde index @start + @length. This function will skip 1213 * over already allocated page directories within the range, and only allocate 1214 * new ones, setting the appropriate pointer within the pdp as well as the 1215 * correct position in the bitmap @new_pds. 1216 * 1217 * The function will only allocate the pages within the range for a give page 1218 * directory pointer. In other words, if @start + @length straddles a virtually 1219 * addressed PDP boundary (512GB for 4k pages), there will be more allocations 1220 * required by the caller, This is not currently possible, and the BUG in the 1221 * code will prevent it. 1222 * 1223 * Return: 0 if success; negative error code otherwise. 1224 */ 1225 static int 1226 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, 1227 struct i915_page_directory_pointer *pdp, 1228 uint64_t start, 1229 uint64_t length, 1230 unsigned long *new_pds) 1231 { 1232 struct drm_device *dev = vm->dev; 1233 struct i915_page_directory *pd; 1234 uint64_t temp; 1235 uint32_t pdpe; 1236 uint32_t pdpes = I915_PDPES_PER_PDP(dev); 1237 1238 WARN_ON(!bitmap_empty(new_pds, pdpes)); 1239 1240 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { 1241 if (test_bit(pdpe, pdp->used_pdpes)) 1242 continue; 1243 1244 pd = alloc_pd(dev); 1245 if (IS_ERR(pd)) 1246 goto unwind_out; 1247 1248 gen8_initialize_pd(vm, pd); 1249 pdp->page_directory[pdpe] = pd; 1250 __set_bit(pdpe, new_pds); 1251 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); 1252 } 1253 1254 return 0; 1255 1256 unwind_out: 1257 for_each_set_bit(pdpe, new_pds, pdpes) 1258 free_pd(dev, pdp->page_directory[pdpe]); 1259 1260 return -ENOMEM; 1261 } 1262 1263 /** 1264 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. 1265 * @vm: Master vm structure. 1266 * @pml4: Page map level 4 for this address range. 1267 * @start: Starting virtual address to begin allocations. 1268 * @length: Size of the allocations. 1269 * @new_pdps: Bitmap set by function with new allocations. Likely used by the 1270 * caller to free on error. 1271 * 1272 * Allocate the required number of page directory pointers. Extremely similar to 1273 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). 1274 * The main difference is here we are limited by the pml4 boundary (instead of 1275 * the page directory pointer). 1276 * 1277 * Return: 0 if success; negative error code otherwise. 1278 */ 1279 static int 1280 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, 1281 struct i915_pml4 *pml4, 1282 uint64_t start, 1283 uint64_t length, 1284 unsigned long *new_pdps) 1285 { 1286 struct drm_device *dev = vm->dev; 1287 struct i915_page_directory_pointer *pdp; 1288 uint64_t temp; 1289 uint32_t pml4e; 1290 1291 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); 1292 1293 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) { 1294 if (!test_bit(pml4e, pml4->used_pml4es)) { 1295 pdp = alloc_pdp(dev); 1296 if (IS_ERR(pdp)) 1297 goto unwind_out; 1298 1299 gen8_initialize_pdp(vm, pdp); 1300 pml4->pdps[pml4e] = pdp; 1301 __set_bit(pml4e, new_pdps); 1302 trace_i915_page_directory_pointer_entry_alloc(vm, 1303 pml4e, 1304 start, 1305 GEN8_PML4E_SHIFT); 1306 } 1307 } 1308 1309 return 0; 1310 1311 unwind_out: 1312 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) 1313 free_pdp(dev, pml4->pdps[pml4e]); 1314 1315 return -ENOMEM; 1316 } 1317 1318 static void 1319 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) 1320 { 1321 kfree(new_pts); 1322 kfree(new_pds); 1323 } 1324 1325 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both 1326 * of these are based on the number of PDPEs in the system. 1327 */ 1328 static 1329 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, 1330 unsigned long **new_pts, 1331 uint32_t pdpes) 1332 { 1333 unsigned long *pds; 1334 unsigned long *pts; 1335 1336 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); 1337 if (!pds) 1338 return -ENOMEM; 1339 1340 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), 1341 GFP_TEMPORARY); 1342 if (!pts) 1343 goto err_out; 1344 1345 *new_pds = pds; 1346 *new_pts = pts; 1347 1348 return 0; 1349 1350 err_out: 1351 free_gen8_temp_bitmaps(pds, pts); 1352 return -ENOMEM; 1353 } 1354 1355 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify 1356 * the page table structures, we mark them dirty so that 1357 * context switching/execlist queuing code takes extra steps 1358 * to ensure that tlbs are flushed. 1359 */ 1360 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) 1361 { 1362 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; 1363 } 1364 1365 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, 1366 struct i915_page_directory_pointer *pdp, 1367 uint64_t start, 1368 uint64_t length) 1369 { 1370 struct i915_hw_ppgtt *ppgtt = 1371 container_of(vm, struct i915_hw_ppgtt, base); 1372 unsigned long *new_page_dirs, *new_page_tables; 1373 struct drm_device *dev = vm->dev; 1374 struct i915_page_directory *pd; 1375 const uint64_t orig_start = start; 1376 const uint64_t orig_length = length; 1377 uint64_t temp; 1378 uint32_t pdpe; 1379 uint32_t pdpes = I915_PDPES_PER_PDP(dev); 1380 int ret; 1381 1382 /* Wrap is never okay since we can only represent 48b, and we don't 1383 * actually use the other side of the canonical address space. 1384 */ 1385 if (WARN_ON(start + length < start)) 1386 return -ENODEV; 1387 1388 if (WARN_ON(start + length > vm->total)) 1389 return -ENODEV; 1390 1391 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); 1392 if (ret) 1393 return ret; 1394 1395 /* Do the allocations first so we can easily bail out */ 1396 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, 1397 new_page_dirs); 1398 if (ret) { 1399 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); 1400 return ret; 1401 } 1402 1403 /* For every page directory referenced, allocate page tables */ 1404 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { 1405 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, 1406 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); 1407 if (ret) 1408 goto err_out; 1409 } 1410 1411 start = orig_start; 1412 length = orig_length; 1413 1414 /* Allocations have completed successfully, so set the bitmaps, and do 1415 * the mappings. */ 1416 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { 1417 gen8_pde_t *const page_directory = kmap_px(pd); 1418 struct i915_page_table *pt; 1419 uint64_t pd_len = length; 1420 uint64_t pd_start = start; 1421 uint32_t pde; 1422 1423 /* Every pd should be allocated, we just did that above. */ 1424 WARN_ON(!pd); 1425 1426 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { 1427 /* Same reasoning as pd */ 1428 WARN_ON(!pt); 1429 WARN_ON(!pd_len); 1430 WARN_ON(!gen8_pte_count(pd_start, pd_len)); 1431 1432 /* Set our used ptes within the page table */ 1433 bitmap_set(pt->used_ptes, 1434 gen8_pte_index(pd_start), 1435 gen8_pte_count(pd_start, pd_len)); 1436 1437 /* Our pde is now pointing to the pagetable, pt */ 1438 __set_bit(pde, pd->used_pdes); 1439 1440 /* Map the PDE to the page table */ 1441 page_directory[pde] = gen8_pde_encode(px_dma(pt), 1442 I915_CACHE_LLC); 1443 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, 1444 gen8_pte_index(start), 1445 gen8_pte_count(start, length), 1446 GEN8_PTES); 1447 1448 /* NB: We haven't yet mapped ptes to pages. At this 1449 * point we're still relying on insert_entries() */ 1450 } 1451 1452 kunmap_px(ppgtt, page_directory); 1453 __set_bit(pdpe, pdp->used_pdpes); 1454 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); 1455 } 1456 1457 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); 1458 mark_tlbs_dirty(ppgtt); 1459 return 0; 1460 1461 err_out: 1462 while (pdpe--) { 1463 for_each_set_bit(temp, new_page_tables + pdpe * 1464 BITS_TO_LONGS(I915_PDES), I915_PDES) 1465 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); 1466 } 1467 1468 for_each_set_bit(pdpe, new_page_dirs, pdpes) 1469 free_pd(dev, pdp->page_directory[pdpe]); 1470 1471 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); 1472 mark_tlbs_dirty(ppgtt); 1473 return ret; 1474 } 1475 1476 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, 1477 struct i915_pml4 *pml4, 1478 uint64_t start, 1479 uint64_t length) 1480 { 1481 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); 1482 struct i915_hw_ppgtt *ppgtt = 1483 container_of(vm, struct i915_hw_ppgtt, base); 1484 struct i915_page_directory_pointer *pdp; 1485 uint64_t temp, pml4e; 1486 int ret = 0; 1487 1488 /* Do the pml4 allocations first, so we don't need to track the newly 1489 * allocated tables below the pdp */ 1490 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); 1491 1492 /* The pagedirectory and pagetable allocations are done in the shared 3 1493 * and 4 level code. Just allocate the pdps. 1494 */ 1495 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, 1496 new_pdps); 1497 if (ret) 1498 return ret; 1499 1500 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, 1501 "The allocation has spanned more than 512GB. " 1502 "It is highly likely this is incorrect."); 1503 1504 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) { 1505 WARN_ON(!pdp); 1506 1507 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); 1508 if (ret) 1509 goto err_out; 1510 1511 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); 1512 } 1513 1514 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, 1515 GEN8_PML4ES_PER_PML4); 1516 1517 return 0; 1518 1519 err_out: 1520 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) 1521 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); 1522 1523 return ret; 1524 } 1525 1526 static int gen8_alloc_va_range(struct i915_address_space *vm, 1527 uint64_t start, uint64_t length) 1528 { 1529 struct i915_hw_ppgtt *ppgtt = 1530 container_of(vm, struct i915_hw_ppgtt, base); 1531 1532 if (USES_FULL_48BIT_PPGTT(vm->dev)) 1533 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); 1534 else 1535 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); 1536 } 1537 1538 #ifndef __NetBSD__ /* XXX debugfs */ 1539 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, 1540 uint64_t start, uint64_t length, 1541 gen8_pte_t scratch_pte, 1542 struct seq_file *m) 1543 { 1544 struct i915_page_directory *pd; 1545 uint64_t temp; 1546 uint32_t pdpe; 1547 1548 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { 1549 struct i915_page_table *pt; 1550 uint64_t pd_len = length; 1551 uint64_t pd_start = start; 1552 uint32_t pde; 1553 1554 if (!test_bit(pdpe, pdp->used_pdpes)) 1555 continue; 1556 1557 seq_printf(m, "\tPDPE #%d\n", pdpe); 1558 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { 1559 uint32_t pte; 1560 gen8_pte_t *pt_vaddr; 1561 1562 if (!test_bit(pde, pd->used_pdes)) 1563 continue; 1564 1565 pt_vaddr = kmap_px(pt); 1566 for (pte = 0; pte < GEN8_PTES; pte += 4) { 1567 uint64_t va = 1568 (pdpe << GEN8_PDPE_SHIFT) | 1569 (pde << GEN8_PDE_SHIFT) | 1570 (pte << GEN8_PTE_SHIFT); 1571 int i; 1572 bool found = false; 1573 1574 for (i = 0; i < 4; i++) 1575 if (pt_vaddr[pte + i] != scratch_pte) 1576 found = true; 1577 if (!found) 1578 continue; 1579 1580 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); 1581 for (i = 0; i < 4; i++) { 1582 if (pt_vaddr[pte + i] != scratch_pte) 1583 seq_printf(m, " %llx", pt_vaddr[pte + i]); 1584 else 1585 seq_puts(m, " SCRATCH "); 1586 } 1587 seq_puts(m, "\n"); 1588 } 1589 /* don't use kunmap_px, it could trigger 1590 * an unnecessary flush. 1591 */ 1592 kunmap_atomic(pt_vaddr); 1593 } 1594 } 1595 } 1596 1597 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) 1598 { 1599 struct i915_address_space *vm = &ppgtt->base; 1600 uint64_t start = ppgtt->base.start; 1601 uint64_t length = ppgtt->base.total; 1602 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), 1603 I915_CACHE_LLC, true, 0); 1604 1605 if (!USES_FULL_48BIT_PPGTT(vm->dev)) { 1606 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); 1607 } else { 1608 uint64_t templ4, pml4e; 1609 struct i915_pml4 *pml4 = &ppgtt->pml4; 1610 struct i915_page_directory_pointer *pdp; 1611 1612 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) { 1613 if (!test_bit(pml4e, pml4->used_pml4es)) 1614 continue; 1615 1616 seq_printf(m, " PML4E #%llu\n", pml4e); 1617 gen8_dump_pdp(pdp, start, length, scratch_pte, m); 1618 } 1619 } 1620 } 1621 #endif 1622 1623 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) 1624 { 1625 unsigned long *new_page_dirs, *new_page_tables; 1626 uint32_t pdpes = I915_PDPES_PER_PDP(dev); 1627 int ret; 1628 1629 /* We allocate temp bitmap for page tables for no gain 1630 * but as this is for init only, lets keep the things simple 1631 */ 1632 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); 1633 if (ret) 1634 return ret; 1635 1636 /* Allocate for all pdps regardless of how the ppgtt 1637 * was defined. 1638 */ 1639 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, 1640 0, 1ULL << 32, 1641 new_page_dirs); 1642 if (!ret) 1643 *ppgtt->pdp.used_pdpes = *new_page_dirs; 1644 1645 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); 1646 1647 return ret; 1648 } 1649 1650 /* 1651 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers 1652 * with a net effect resembling a 2-level page table in normal x86 terms. Each 1653 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address 1654 * space. 1655 * 1656 */ 1657 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 1658 { 1659 int ret; 1660 1661 ret = gen8_init_scratch(&ppgtt->base); 1662 if (ret) 1663 return ret; 1664 1665 ppgtt->base.start = 0; 1666 ppgtt->base.cleanup = gen8_ppgtt_cleanup; 1667 ppgtt->base.allocate_va_range = gen8_alloc_va_range; 1668 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; 1669 ppgtt->base.clear_range = gen8_ppgtt_clear_range; 1670 ppgtt->base.unbind_vma = ppgtt_unbind_vma; 1671 ppgtt->base.bind_vma = ppgtt_bind_vma; 1672 1673 /* 1674 * From bdw, there is support for read-only pages in the PPGTT. 1675 * 1676 * XXX GVT is not honouring the lack of RW in the PTE bits. 1677 */ 1678 ppgtt->base.has_read_only = !intel_vgpu_active(ppgtt->base.dev); 1679 1680 #ifndef __NetBSD__ /* XXX debugfs */ 1681 ppgtt->debug_dump = gen8_dump_ppgtt; 1682 #endif 1683 1684 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { 1685 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); 1686 if (ret) 1687 goto free_scratch; 1688 1689 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); 1690 1691 ppgtt->base.total = 1ULL << 48; 1692 ppgtt->switch_mm = gen8_48b_mm_switch; 1693 } else { 1694 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); 1695 if (ret) 1696 goto free_scratch; 1697 1698 ppgtt->base.total = 1ULL << 32; 1699 ppgtt->switch_mm = gen8_legacy_mm_switch; 1700 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, 1701 0, 0, 1702 GEN8_PML4E_SHIFT); 1703 1704 if (intel_vgpu_active(ppgtt->base.dev)) { 1705 ret = gen8_preallocate_top_level_pdps(ppgtt); 1706 if (ret) 1707 goto free_scratch; 1708 } 1709 } 1710 1711 if (intel_vgpu_active(ppgtt->base.dev)) 1712 gen8_ppgtt_notify_vgt(ppgtt, true); 1713 1714 return 0; 1715 1716 free_scratch: 1717 gen8_free_scratch(&ppgtt->base); 1718 return ret; 1719 } 1720 1721 #ifndef __NetBSD__ /* XXX debugfs */ 1722 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) 1723 { 1724 struct i915_address_space *vm = &ppgtt->base; 1725 struct i915_page_table *unused; 1726 gen6_pte_t scratch_pte; 1727 uint32_t pd_entry; 1728 uint32_t pte, pde, temp; 1729 uint32_t start = ppgtt->base.start, length = ppgtt->base.total; 1730 1731 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), 1732 I915_CACHE_LLC, true, 0); 1733 1734 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { 1735 u32 expected; 1736 gen6_pte_t *pt_vaddr; 1737 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); 1738 pd_entry = readl(ppgtt->pd_addr + pde); 1739 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); 1740 1741 if (pd_entry != expected) 1742 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", 1743 pde, 1744 pd_entry, 1745 expected); 1746 seq_printf(m, "\tPDE: %x\n", pd_entry); 1747 1748 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); 1749 1750 for (pte = 0; pte < GEN6_PTES; pte+=4) { 1751 unsigned long va = 1752 (pde * PAGE_SIZE * GEN6_PTES) + 1753 (pte * PAGE_SIZE); 1754 int i; 1755 bool found = false; 1756 for (i = 0; i < 4; i++) 1757 if (pt_vaddr[pte + i] != scratch_pte) 1758 found = true; 1759 if (!found) 1760 continue; 1761 1762 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); 1763 for (i = 0; i < 4; i++) { 1764 if (pt_vaddr[pte + i] != scratch_pte) 1765 seq_printf(m, " %08x", pt_vaddr[pte + i]); 1766 else 1767 seq_puts(m, " SCRATCH "); 1768 } 1769 seq_puts(m, "\n"); 1770 } 1771 kunmap_px(ppgtt, pt_vaddr); 1772 } 1773 } 1774 #endif 1775 1776 /* Write pde (index) from the page directory @pd to the page table @pt */ 1777 static void gen6_write_pde(struct i915_page_directory *pd, 1778 const int pde, struct i915_page_table *pt) 1779 { 1780 /* Caller needs to make sure the write completes if necessary */ 1781 struct i915_hw_ppgtt *ppgtt = 1782 container_of(pd, struct i915_hw_ppgtt, pd); 1783 #ifdef __NetBSD__ 1784 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; 1785 const bus_space_tag_t bst = dev_priv->gtt.bst; 1786 const bus_space_handle_t bsh = dev_priv->gtt.bsh; 1787 const bus_addr_t pd_base = ppgtt->pd.base.ggtt_offset; 1788 #endif 1789 u32 pd_entry; 1790 1791 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); 1792 pd_entry |= GEN6_PDE_VALID; 1793 1794 #ifdef __NetBSD__ 1795 CTASSERT(sizeof(gen6_pte_t) == 4); 1796 bus_space_write_4(bst, bsh, pd_base + 4*pde, pd_entry); 1797 #else 1798 writel(pd_entry, ppgtt->pd_addr + pde); 1799 #endif 1800 } 1801 1802 /* Write all the page tables found in the ppgtt structure to incrementing page 1803 * directories. */ 1804 static void gen6_write_page_range(struct drm_i915_private *dev_priv, 1805 struct i915_page_directory *pd, 1806 uint32_t start, uint32_t length) 1807 { 1808 struct i915_page_table *pt; 1809 uint32_t pde, temp; 1810 1811 gen6_for_each_pde(pt, pd, start, length, temp, pde) 1812 gen6_write_pde(pd, pde, pt); 1813 1814 /* Make sure write is complete before other code can use this page 1815 * table. Also require for WC mapped PTEs */ 1816 #ifdef __NetBSD__ 1817 bus_space_read_4(dev_priv->gtt.bst, dev_priv->gtt.bsh, 0); 1818 #else 1819 readl(dev_priv->gtt.gsm); 1820 #endif 1821 } 1822 1823 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) 1824 { 1825 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); 1826 1827 return (ppgtt->pd.base.ggtt_offset / 64) << 16; 1828 } 1829 1830 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 1831 struct drm_i915_gem_request *req) 1832 { 1833 struct intel_engine_cs *ring = req->ring; 1834 int ret; 1835 1836 /* NB: TLBs must be flushed and invalidated before a switch */ 1837 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 1838 if (ret) 1839 return ret; 1840 1841 ret = intel_ring_begin(req, 6); 1842 if (ret) 1843 return ret; 1844 1845 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); 1846 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); 1847 intel_ring_emit(ring, PP_DIR_DCLV_2G); 1848 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); 1849 intel_ring_emit(ring, get_pd_offset(ppgtt)); 1850 intel_ring_emit(ring, MI_NOOP); 1851 intel_ring_advance(ring); 1852 1853 return 0; 1854 } 1855 1856 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, 1857 struct drm_i915_gem_request *req) 1858 { 1859 struct intel_engine_cs *ring = req->ring; 1860 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); 1861 1862 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 1863 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); 1864 return 0; 1865 } 1866 1867 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 1868 struct drm_i915_gem_request *req) 1869 { 1870 struct intel_engine_cs *ring = req->ring; 1871 int ret; 1872 1873 /* NB: TLBs must be flushed and invalidated before a switch */ 1874 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 1875 if (ret) 1876 return ret; 1877 1878 ret = intel_ring_begin(req, 6); 1879 if (ret) 1880 return ret; 1881 1882 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); 1883 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); 1884 intel_ring_emit(ring, PP_DIR_DCLV_2G); 1885 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); 1886 intel_ring_emit(ring, get_pd_offset(ppgtt)); 1887 intel_ring_emit(ring, MI_NOOP); 1888 intel_ring_advance(ring); 1889 1890 /* XXX: RCS is the only one to auto invalidate the TLBs? */ 1891 if (ring->id != RCS) { 1892 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 1893 if (ret) 1894 return ret; 1895 } 1896 1897 return 0; 1898 } 1899 1900 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, 1901 struct drm_i915_gem_request *req) 1902 { 1903 struct intel_engine_cs *ring = req->ring; 1904 struct drm_device *dev = ppgtt->base.dev; 1905 struct drm_i915_private *dev_priv = dev->dev_private; 1906 1907 1908 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 1909 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); 1910 1911 POSTING_READ(RING_PP_DIR_DCLV(ring)); 1912 1913 return 0; 1914 } 1915 1916 static void gen8_ppgtt_enable(struct drm_device *dev) 1917 { 1918 struct drm_i915_private *dev_priv = dev->dev_private; 1919 struct intel_engine_cs *ring; 1920 int j; 1921 1922 for_each_ring(ring, dev_priv, j) { 1923 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; 1924 I915_WRITE(RING_MODE_GEN7(ring), 1925 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); 1926 } 1927 } 1928 1929 static void gen7_ppgtt_enable(struct drm_device *dev) 1930 { 1931 struct drm_i915_private *dev_priv = dev->dev_private; 1932 struct intel_engine_cs *ring; 1933 uint32_t ecochk, ecobits; 1934 int i; 1935 1936 ecobits = I915_READ(GAC_ECO_BITS); 1937 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); 1938 1939 ecochk = I915_READ(GAM_ECOCHK); 1940 if (IS_HASWELL(dev)) { 1941 ecochk |= ECOCHK_PPGTT_WB_HSW; 1942 } else { 1943 ecochk |= ECOCHK_PPGTT_LLC_IVB; 1944 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; 1945 } 1946 I915_WRITE(GAM_ECOCHK, ecochk); 1947 1948 for_each_ring(ring, dev_priv, i) { 1949 /* GFX_MODE is per-ring on gen7+ */ 1950 I915_WRITE(RING_MODE_GEN7(ring), 1951 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 1952 } 1953 } 1954 1955 static void gen6_ppgtt_enable(struct drm_device *dev) 1956 { 1957 struct drm_i915_private *dev_priv = dev->dev_private; 1958 uint32_t ecochk, gab_ctl, ecobits; 1959 1960 ecobits = I915_READ(GAC_ECO_BITS); 1961 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | 1962 ECOBITS_PPGTT_CACHE64B); 1963 1964 gab_ctl = I915_READ(GAB_CTL); 1965 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); 1966 1967 ecochk = I915_READ(GAM_ECOCHK); 1968 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); 1969 1970 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 1971 } 1972 1973 /* PPGTT support for Sandybdrige/Gen6 and later */ 1974 static void gen6_ppgtt_clear_range(struct i915_address_space *vm, 1975 uint64_t start, 1976 uint64_t length, 1977 bool use_scratch) 1978 { 1979 struct i915_hw_ppgtt *ppgtt = 1980 container_of(vm, struct i915_hw_ppgtt, base); 1981 gen6_pte_t *pt_vaddr, scratch_pte; 1982 unsigned first_entry = start >> PAGE_SHIFT; 1983 unsigned num_entries = length >> PAGE_SHIFT; 1984 unsigned act_pt = first_entry / GEN6_PTES; 1985 unsigned first_pte = first_entry % GEN6_PTES; 1986 unsigned last_pte, i; 1987 1988 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), 1989 I915_CACHE_LLC, true, 0); 1990 1991 while (num_entries) { 1992 last_pte = first_pte + num_entries; 1993 if (last_pte > GEN6_PTES) 1994 last_pte = GEN6_PTES; 1995 1996 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); 1997 1998 for (i = first_pte; i < last_pte; i++) 1999 pt_vaddr[i] = scratch_pte; 2000 2001 kunmap_px(ppgtt, pt_vaddr); 2002 2003 num_entries -= last_pte - first_pte; 2004 first_pte = 0; 2005 act_pt++; 2006 } 2007 } 2008 2009 #ifdef __NetBSD__ 2010 static void 2011 gen6_ppgtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap, 2012 uint64_t start, enum i915_cache_level cache_level, uint32_t flags) 2013 { 2014 struct i915_hw_ppgtt *ppgtt = 2015 container_of(vm, struct i915_hw_ppgtt, base); 2016 gen6_pte_t *pt_vaddr; 2017 unsigned first_entry = start >> PAGE_SHIFT; 2018 unsigned act_pt = first_entry / GEN6_PTES; 2019 unsigned act_pte = first_entry % GEN6_PTES; 2020 unsigned seg; 2021 2022 pt_vaddr = NULL; 2023 KASSERT(0 < dmamap->dm_nsegs); 2024 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 2025 KASSERT(dmamap->dm_segs[seg].ds_len == PAGE_SIZE); 2026 if (pt_vaddr == NULL) 2027 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); 2028 pt_vaddr[act_pte] = 2029 vm->pte_encode(dmamap->dm_segs[seg].ds_addr, cache_level, 2030 true, flags); 2031 if (++act_pte == GEN6_PTES) { 2032 kunmap_px(ppgtt, pt_vaddr); 2033 pt_vaddr = NULL; 2034 act_pt++; 2035 act_pte = 0; 2036 } 2037 } 2038 if (pt_vaddr) 2039 kunmap_px(ppgtt, pt_vaddr); 2040 } 2041 #else 2042 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, 2043 struct sg_table *pages, 2044 uint64_t start, 2045 enum i915_cache_level cache_level, u32 flags) 2046 { 2047 struct i915_hw_ppgtt *ppgtt = 2048 container_of(vm, struct i915_hw_ppgtt, base); 2049 gen6_pte_t *pt_vaddr; 2050 unsigned first_entry = start >> PAGE_SHIFT; 2051 unsigned act_pt = first_entry / GEN6_PTES; 2052 unsigned act_pte = first_entry % GEN6_PTES; 2053 struct sg_page_iter sg_iter; 2054 2055 pt_vaddr = NULL; 2056 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 2057 if (pt_vaddr == NULL) 2058 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); 2059 2060 pt_vaddr[act_pte] = 2061 vm->pte_encode(sg_page_iter_dma_address(&sg_iter), 2062 cache_level, true, flags); 2063 2064 if (++act_pte == GEN6_PTES) { 2065 kunmap_px(ppgtt, pt_vaddr); 2066 pt_vaddr = NULL; 2067 act_pt++; 2068 act_pte = 0; 2069 } 2070 } 2071 if (pt_vaddr) 2072 kunmap_px(ppgtt, pt_vaddr); 2073 } 2074 #endif 2075 2076 static int gen6_alloc_va_range(struct i915_address_space *vm, 2077 uint64_t start_in, uint64_t length_in) 2078 { 2079 DECLARE_BITMAP(new_page_tables, I915_PDES); 2080 struct drm_device *dev = vm->dev; 2081 struct drm_i915_private *dev_priv = dev->dev_private; 2082 struct i915_hw_ppgtt *ppgtt = 2083 container_of(vm, struct i915_hw_ppgtt, base); 2084 struct i915_page_table *pt; 2085 uint32_t start, length, start_save, length_save; 2086 uint32_t pde, temp; 2087 int ret; 2088 2089 if (WARN_ON(start_in + length_in > ppgtt->base.total)) 2090 return -ENODEV; 2091 2092 start = start_save = start_in; 2093 length = length_save = length_in; 2094 2095 bitmap_zero(new_page_tables, I915_PDES); 2096 2097 /* The allocation is done in two stages so that we can bail out with 2098 * minimal amount of pain. The first stage finds new page tables that 2099 * need allocation. The second stage marks use ptes within the page 2100 * tables. 2101 */ 2102 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { 2103 if (pt != vm->scratch_pt) { 2104 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); 2105 continue; 2106 } 2107 2108 /* We've already allocated a page table */ 2109 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); 2110 2111 pt = alloc_pt(dev); 2112 if (IS_ERR(pt)) { 2113 ret = PTR_ERR(pt); 2114 goto unwind_out; 2115 } 2116 2117 gen6_initialize_pt(vm, pt); 2118 2119 ppgtt->pd.page_table[pde] = pt; 2120 __set_bit(pde, new_page_tables); 2121 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); 2122 } 2123 2124 start = start_save; 2125 length = length_save; 2126 2127 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { 2128 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); 2129 2130 bitmap_zero(tmp_bitmap, GEN6_PTES); 2131 bitmap_set(tmp_bitmap, gen6_pte_index(start), 2132 gen6_pte_count(start, length)); 2133 2134 if (__test_and_clear_bit(pde, new_page_tables)) 2135 gen6_write_pde(&ppgtt->pd, pde, pt); 2136 2137 trace_i915_page_table_entry_map(vm, pde, pt, 2138 gen6_pte_index(start), 2139 gen6_pte_count(start, length), 2140 GEN6_PTES); 2141 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, 2142 GEN6_PTES); 2143 } 2144 2145 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); 2146 2147 /* Make sure write is complete before other code can use this page 2148 * table. Also require for WC mapped PTEs */ 2149 #ifdef __NetBSD__ 2150 bus_space_read_4(dev_priv->gtt.bst, dev_priv->gtt.bsh, 0); 2151 #else 2152 readl(dev_priv->gtt.gsm); 2153 #endif 2154 2155 mark_tlbs_dirty(ppgtt); 2156 return 0; 2157 2158 unwind_out: 2159 for_each_set_bit(pde, new_page_tables, I915_PDES) { 2160 struct i915_page_table *pt = ppgtt->pd.page_table[pde]; 2161 2162 ppgtt->pd.page_table[pde] = vm->scratch_pt; 2163 free_pt(vm->dev, pt); 2164 } 2165 2166 mark_tlbs_dirty(ppgtt); 2167 return ret; 2168 } 2169 2170 static int gen6_init_scratch(struct i915_address_space *vm) 2171 { 2172 struct drm_device *dev = vm->dev; 2173 2174 vm->scratch_page = alloc_scratch_page(dev); 2175 if (IS_ERR(vm->scratch_page)) 2176 return PTR_ERR(vm->scratch_page); 2177 2178 vm->scratch_pt = alloc_pt(dev); 2179 if (IS_ERR(vm->scratch_pt)) { 2180 free_scratch_page(dev, vm->scratch_page); 2181 return PTR_ERR(vm->scratch_pt); 2182 } 2183 2184 gen6_initialize_pt(vm, vm->scratch_pt); 2185 2186 return 0; 2187 } 2188 2189 static void gen6_free_scratch(struct i915_address_space *vm) 2190 { 2191 struct drm_device *dev = vm->dev; 2192 2193 free_pt(dev, vm->scratch_pt); 2194 free_scratch_page(dev, vm->scratch_page); 2195 } 2196 2197 static void gen6_ppgtt_cleanup(struct i915_address_space *vm) 2198 { 2199 struct i915_hw_ppgtt *ppgtt = 2200 container_of(vm, struct i915_hw_ppgtt, base); 2201 struct i915_page_table *pt; 2202 uint32_t pde; 2203 2204 drm_mm_remove_node(&ppgtt->node); 2205 2206 gen6_for_all_pdes(pt, ppgtt, pde) { 2207 if (pt != vm->scratch_pt) 2208 free_pt(ppgtt->base.dev, pt); 2209 } 2210 2211 gen6_free_scratch(vm); 2212 } 2213 2214 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) 2215 { 2216 struct i915_address_space *vm = &ppgtt->base; 2217 struct drm_device *dev = ppgtt->base.dev; 2218 struct drm_i915_private *dev_priv = dev->dev_private; 2219 bool retried = false; 2220 int ret; 2221 2222 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The 2223 * allocator works in address space sizes, so it's multiplied by page 2224 * size. We allocate at the top of the GTT to avoid fragmentation. 2225 */ 2226 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); 2227 2228 ret = gen6_init_scratch(vm); 2229 if (ret) 2230 return ret; 2231 2232 alloc: 2233 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, 2234 &ppgtt->node, GEN6_PD_SIZE, 2235 GEN6_PD_ALIGN, 0, 2236 0, dev_priv->gtt.base.total, 2237 DRM_MM_TOPDOWN); 2238 if (ret == -ENOSPC && !retried) { 2239 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, 2240 GEN6_PD_SIZE, GEN6_PD_ALIGN, 2241 I915_CACHE_NONE, 2242 0, dev_priv->gtt.base.total, 2243 0); 2244 if (ret) 2245 goto err_out; 2246 2247 retried = true; 2248 goto alloc; 2249 } 2250 2251 if (ret) 2252 goto err_out; 2253 2254 2255 if (ppgtt->node.start < dev_priv->gtt.mappable_end) 2256 DRM_DEBUG("Forced to use aperture for PDEs\n"); 2257 2258 return 0; 2259 2260 err_out: 2261 gen6_free_scratch(vm); 2262 return ret; 2263 } 2264 2265 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) 2266 { 2267 return gen6_ppgtt_allocate_page_directories(ppgtt); 2268 } 2269 2270 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, 2271 uint64_t start, uint64_t length) 2272 { 2273 struct i915_page_table *unused __unused; 2274 uint32_t pde, temp; 2275 2276 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) 2277 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; 2278 } 2279 2280 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 2281 { 2282 struct drm_device *dev = ppgtt->base.dev; 2283 struct drm_i915_private *dev_priv = dev->dev_private; 2284 int ret; 2285 2286 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; 2287 if (IS_GEN6(dev)) { 2288 ppgtt->switch_mm = gen6_mm_switch; 2289 } else if (IS_HASWELL(dev)) { 2290 ppgtt->switch_mm = hsw_mm_switch; 2291 } else if (IS_GEN7(dev)) { 2292 ppgtt->switch_mm = gen7_mm_switch; 2293 } else 2294 BUG(); 2295 2296 if (intel_vgpu_active(dev)) 2297 ppgtt->switch_mm = vgpu_mm_switch; 2298 2299 ret = gen6_ppgtt_alloc(ppgtt); 2300 if (ret) 2301 return ret; 2302 2303 ppgtt->base.allocate_va_range = gen6_alloc_va_range; 2304 ppgtt->base.clear_range = gen6_ppgtt_clear_range; 2305 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; 2306 ppgtt->base.unbind_vma = ppgtt_unbind_vma; 2307 ppgtt->base.bind_vma = ppgtt_bind_vma; 2308 ppgtt->base.cleanup = gen6_ppgtt_cleanup; 2309 ppgtt->base.start = 0; 2310 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; 2311 #ifndef __NetBSD__ 2312 ppgtt->debug_dump = gen6_dump_ppgtt; 2313 #endif 2314 2315 ppgtt->pd.base.ggtt_offset = 2316 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); 2317 2318 #ifndef __NetBSD__ 2319 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + 2320 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); 2321 #endif 2322 2323 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); 2324 2325 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); 2326 2327 DRM_DEBUG_DRIVER("Allocated pde space (%"PRId64"M) at GTT entry: %"PRIx64"\n", 2328 ppgtt->node.size >> 20, 2329 ppgtt->node.start / PAGE_SIZE); 2330 2331 DRM_DEBUG("Adding PPGTT at offset %x\n", 2332 ppgtt->pd.base.ggtt_offset << 10); 2333 2334 return 0; 2335 } 2336 2337 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) 2338 { 2339 ppgtt->base.dev = dev; 2340 2341 if (INTEL_INFO(dev)->gen < 8) 2342 return gen6_ppgtt_init(ppgtt); 2343 else 2344 return gen8_ppgtt_init(ppgtt); 2345 } 2346 2347 static void i915_address_space_init(struct i915_address_space *vm, 2348 struct drm_i915_private *dev_priv) 2349 { 2350 drm_mm_init(&vm->mm, vm->start, vm->total); 2351 vm->dev = dev_priv->dev; 2352 INIT_LIST_HEAD(&vm->active_list); 2353 INIT_LIST_HEAD(&vm->inactive_list); 2354 list_add_tail(&vm->global_link, &dev_priv->vm_list); 2355 } 2356 2357 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) 2358 { 2359 struct drm_i915_private *dev_priv = dev->dev_private; 2360 int ret = 0; 2361 2362 ret = __hw_ppgtt_init(dev, ppgtt); 2363 if (ret == 0) { 2364 kref_init(&ppgtt->ref); 2365 i915_address_space_init(&ppgtt->base, dev_priv); 2366 } 2367 2368 return ret; 2369 } 2370 2371 int i915_ppgtt_init_hw(struct drm_device *dev) 2372 { 2373 /* In the case of execlists, PPGTT is enabled by the context descriptor 2374 * and the PDPs are contained within the context itself. We don't 2375 * need to do anything here. */ 2376 if (i915.enable_execlists) 2377 return 0; 2378 2379 if (!USES_PPGTT(dev)) 2380 return 0; 2381 2382 if (IS_GEN6(dev)) 2383 gen6_ppgtt_enable(dev); 2384 else if (IS_GEN7(dev)) 2385 gen7_ppgtt_enable(dev); 2386 else if (INTEL_INFO(dev)->gen >= 8) 2387 gen8_ppgtt_enable(dev); 2388 else 2389 MISSING_CASE(INTEL_INFO(dev)->gen); 2390 2391 return 0; 2392 } 2393 2394 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) 2395 { 2396 struct drm_i915_private *dev_priv = req->ring->dev->dev_private; 2397 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2398 2399 if (i915.enable_execlists) 2400 return 0; 2401 2402 if (!ppgtt) 2403 return 0; 2404 2405 return ppgtt->switch_mm(ppgtt, req); 2406 } 2407 2408 struct i915_hw_ppgtt * 2409 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) 2410 { 2411 struct i915_hw_ppgtt *ppgtt; 2412 int ret; 2413 2414 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 2415 if (!ppgtt) 2416 return ERR_PTR(-ENOMEM); 2417 2418 ret = i915_ppgtt_init(dev, ppgtt); 2419 if (ret) { 2420 kfree(ppgtt); 2421 return ERR_PTR(ret); 2422 } 2423 2424 ppgtt->file_priv = fpriv; 2425 2426 trace_i915_ppgtt_create(&ppgtt->base); 2427 2428 return ppgtt; 2429 } 2430 2431 void i915_ppgtt_release(struct kref *kref) 2432 { 2433 struct i915_hw_ppgtt *ppgtt = 2434 container_of(kref, struct i915_hw_ppgtt, ref); 2435 2436 trace_i915_ppgtt_release(&ppgtt->base); 2437 2438 /* vmas should already be unbound */ 2439 WARN_ON(!list_empty(&ppgtt->base.active_list)); 2440 WARN_ON(!list_empty(&ppgtt->base.inactive_list)); 2441 2442 list_del(&ppgtt->base.global_link); 2443 drm_mm_takedown(&ppgtt->base.mm); 2444 2445 ppgtt->base.cleanup(&ppgtt->base); 2446 kfree(ppgtt); 2447 } 2448 2449 extern int intel_iommu_gfx_mapped; 2450 /* Certain Gen5 chipsets require require idling the GPU before 2451 * unmapping anything from the GTT when VT-d is enabled. 2452 */ 2453 static bool needs_idle_maps(struct drm_device *dev) 2454 { 2455 #ifdef CONFIG_INTEL_IOMMU 2456 /* Query intel_iommu to see if we need the workaround. Presumably that 2457 * was loaded first. 2458 */ 2459 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) 2460 return true; 2461 #endif 2462 return false; 2463 } 2464 2465 static bool do_idling(struct drm_i915_private *dev_priv) 2466 { 2467 bool ret = dev_priv->mm.interruptible; 2468 2469 if (unlikely(dev_priv->gtt.do_idle_maps)) { 2470 dev_priv->mm.interruptible = false; 2471 if (i915_gpu_idle(dev_priv->dev)) { 2472 DRM_ERROR("Couldn't idle GPU\n"); 2473 /* Wait a bit, in hopes it avoids the hang */ 2474 udelay(10); 2475 } 2476 } 2477 2478 return ret; 2479 } 2480 2481 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) 2482 { 2483 if (unlikely(dev_priv->gtt.do_idle_maps)) 2484 dev_priv->mm.interruptible = interruptible; 2485 } 2486 2487 void i915_check_and_clear_faults(struct drm_device *dev) 2488 { 2489 struct drm_i915_private *dev_priv = dev->dev_private; 2490 struct intel_engine_cs *ring; 2491 int i; 2492 2493 if (INTEL_INFO(dev)->gen < 6) 2494 return; 2495 2496 for_each_ring(ring, dev_priv, i) { 2497 u32 fault_reg; 2498 fault_reg = I915_READ(RING_FAULT_REG(ring)); 2499 if (fault_reg & RING_FAULT_VALID) { 2500 DRM_DEBUG_DRIVER("Unexpected fault\n" 2501 "\tAddr: 0x%08"PRIx32"\n" 2502 "\tAddress space: %s\n" 2503 "\tSource ID: %d\n" 2504 "\tType: %d\n", 2505 fault_reg & PAGE_MASK, 2506 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", 2507 RING_FAULT_SRCID(fault_reg), 2508 RING_FAULT_FAULT_TYPE(fault_reg)); 2509 I915_WRITE(RING_FAULT_REG(ring), 2510 fault_reg & ~RING_FAULT_VALID); 2511 } 2512 } 2513 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); 2514 } 2515 2516 static void i915_ggtt_flush(struct drm_i915_private *dev_priv) 2517 { 2518 if (INTEL_INFO(dev_priv->dev)->gen < 6) { 2519 intel_gtt_chipset_flush(); 2520 } else { 2521 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 2522 POSTING_READ(GFX_FLSH_CNTL_GEN6); 2523 } 2524 } 2525 2526 void i915_gem_suspend_gtt_mappings(struct drm_device *dev) 2527 { 2528 struct drm_i915_private *dev_priv = dev->dev_private; 2529 2530 /* Don't bother messing with faults pre GEN6 as we have little 2531 * documentation supporting that it's a good idea. 2532 */ 2533 if (INTEL_INFO(dev)->gen < 6) 2534 return; 2535 2536 i915_check_and_clear_faults(dev); 2537 2538 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 2539 dev_priv->gtt.base.start, 2540 dev_priv->gtt.base.total, 2541 true); 2542 2543 i915_ggtt_flush(dev_priv); 2544 } 2545 2546 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) 2547 { 2548 #ifdef __NetBSD__ 2549 KASSERT(0 < obj->base.size); 2550 /* XXX errno NetBSD->Linux */ 2551 return -bus_dmamap_load_pglist(obj->base.dev->dmat, obj->pages, 2552 &obj->pageq, obj->base.size, BUS_DMA_NOWAIT); 2553 #else 2554 if (!dma_map_sg(&obj->base.dev->pdev->dev, 2555 obj->pages->sgl, obj->pages->nents, 2556 PCI_DMA_BIDIRECTIONAL)) 2557 return -ENOSPC; 2558 2559 return 0; 2560 #endif 2561 } 2562 2563 #ifdef __NetBSD__ 2564 static gen8_pte_t 2565 gen8_get_pte(bus_space_tag_t bst, bus_space_handle_t bsh, unsigned i) 2566 { 2567 CTASSERT(_BYTE_ORDER == _LITTLE_ENDIAN); /* x86 */ 2568 CTASSERT(sizeof(gen8_pte_t) == 8); 2569 #ifdef _LP64 /* XXX How to detect bus_space_read_8? */ 2570 return bus_space_read_8(bst, bsh, 8*i); 2571 #else 2572 /* 2573 * XXX I'm not sure this case can actually happen in practice: 2574 * 32-bit gen8 chipsets? 2575 */ 2576 return bus_space_read_4(bst, bsh, 8*i) | 2577 ((uint64_t)bus_space_read_4(bst, bsh, 8*i + 4) << 32); 2578 #endif 2579 } 2580 2581 static inline void 2582 gen8_set_pte(bus_space_tag_t bst, bus_space_handle_t bsh, unsigned i, 2583 gen8_pte_t pte) 2584 { 2585 CTASSERT(_BYTE_ORDER == _LITTLE_ENDIAN); /* x86 */ 2586 CTASSERT(sizeof(gen8_pte_t) == 8); 2587 #ifdef _LP64 /* XXX How to detect bus_space_write_8? */ 2588 bus_space_write_8(bst, bsh, 8*i, pte); 2589 #else 2590 bus_space_write_4(bst, bsh, 8*i, (uint32_t)pte); 2591 bus_space_write_4(bst, bsh, 8*i + 4, (uint32_t)(pte >> 32)); 2592 #endif 2593 } 2594 #else 2595 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) 2596 { 2597 #ifdef writeq 2598 writeq(pte, addr); 2599 #else 2600 iowrite32((u32)pte, addr); 2601 iowrite32(pte >> 32, addr + 4); 2602 #endif 2603 } 2604 #endif 2605 2606 #ifdef __NetBSD__ 2607 static void 2608 gen8_ggtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap, 2609 uint64_t start, enum i915_cache_level level, uint32_t flags) 2610 { 2611 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2612 unsigned first_entry = start >> PAGE_SHIFT; 2613 const bus_space_tag_t bst = dev_priv->gtt.bst; 2614 const bus_space_handle_t bsh = dev_priv->gtt.bsh; 2615 unsigned i; 2616 2617 KASSERT(0 < dmamap->dm_nsegs); 2618 for (i = 0; i < dmamap->dm_nsegs; i++) { 2619 KASSERT(dmamap->dm_segs[i].ds_len == PAGE_SIZE); 2620 gen8_set_pte(bst, bsh, first_entry + i, 2621 gen8_pte_encode(dmamap->dm_segs[i].ds_addr, level, true, flags)); 2622 } 2623 if (0 < i) { 2624 /* Posting read. */ 2625 WARN_ON(gen8_get_pte(bst, bsh, (first_entry + i - 1)) 2626 != gen8_pte_encode(dmamap->dm_segs[i - 1].ds_addr, level, 2627 true, flags)); 2628 } 2629 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 2630 POSTING_READ(GFX_FLSH_CNTL_GEN6); 2631 } 2632 #else 2633 static void gen8_ggtt_insert_entries(struct i915_address_space *vm, 2634 struct sg_table *st, 2635 uint64_t start, 2636 enum i915_cache_level level, u32 flags) 2637 { 2638 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2639 unsigned first_entry = start >> PAGE_SHIFT; 2640 gen8_pte_t __iomem *gtt_entries = 2641 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 2642 int i = 0; 2643 struct sg_page_iter sg_iter; 2644 dma_addr_t addr = 0; /* shut up gcc */ 2645 2646 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 2647 addr = sg_dma_address(sg_iter.sg) + 2648 (sg_iter.sg_pgoffset << PAGE_SHIFT); 2649 gen8_set_pte(>t_entries[i], 2650 gen8_pte_encode(addr, level, true, flags)); 2651 i++; 2652 } 2653 2654 /* 2655 * XXX: This serves as a posting read to make sure that the PTE has 2656 * actually been updated. There is some concern that even though 2657 * registers and PTEs are within the same BAR that they are potentially 2658 * of NUMA access patterns. Therefore, even with the way we assume 2659 * hardware should work, we must keep this posting read for paranoia. 2660 */ 2661 if (i != 0) 2662 WARN_ON(readq(>t_entries[i-1]) 2663 != gen8_pte_encode(addr, level, true, flags)); 2664 2665 /* This next bit makes the above posting read even more important. We 2666 * want to flush the TLBs only after we're certain all the PTE updates 2667 * have finished. 2668 */ 2669 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 2670 POSTING_READ(GFX_FLSH_CNTL_GEN6); 2671 } 2672 #endif 2673 2674 /* 2675 * Binds an object into the global gtt with the specified cache level. The object 2676 * will be accessible to the GPU via commands whose operands reference offsets 2677 * within the global GTT as well as accessible by the GPU through the GMADR 2678 * mapped BAR (dev_priv->mm.gtt->gtt). 2679 */ 2680 #ifdef __NetBSD__ 2681 static void 2682 gen6_ggtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap, 2683 uint64_t start, enum i915_cache_level level, uint32_t flags) 2684 { 2685 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2686 unsigned first_entry = start >> PAGE_SHIFT; 2687 const bus_space_tag_t bst = dev_priv->gtt.bst; 2688 const bus_space_handle_t bsh = dev_priv->gtt.bsh; 2689 unsigned i; 2690 2691 KASSERT(0 < dmamap->dm_nsegs); 2692 for (i = 0; i < dmamap->dm_nsegs; i++) { 2693 KASSERT(dmamap->dm_segs[i].ds_len == PAGE_SIZE); 2694 CTASSERT(sizeof(gen6_pte_t) == 4); 2695 bus_space_write_4(bst, bsh, 4*(first_entry + i), 2696 vm->pte_encode(dmamap->dm_segs[i].ds_addr, level, true, 2697 flags)); 2698 } 2699 if (0 < i) { 2700 /* Posting read. */ 2701 WARN_ON(bus_space_read_4(bst, bsh, 4*(first_entry + i - 1)) 2702 != vm->pte_encode(dmamap->dm_segs[i - 1].ds_addr, level, 2703 true, flags)); 2704 } 2705 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 2706 POSTING_READ(GFX_FLSH_CNTL_GEN6); 2707 } 2708 #else 2709 static void gen6_ggtt_insert_entries(struct i915_address_space *vm, 2710 struct sg_table *st, 2711 uint64_t start, 2712 enum i915_cache_level level, u32 flags) 2713 { 2714 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2715 unsigned first_entry = start >> PAGE_SHIFT; 2716 gen6_pte_t __iomem *gtt_entries = 2717 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 2718 int i = 0; 2719 struct sg_page_iter sg_iter; 2720 dma_addr_t addr = 0; 2721 2722 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 2723 addr = sg_page_iter_dma_address(&sg_iter); 2724 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); 2725 i++; 2726 } 2727 2728 /* XXX: This serves as a posting read to make sure that the PTE has 2729 * actually been updated. There is some concern that even though 2730 * registers and PTEs are within the same BAR that they are potentially 2731 * of NUMA access patterns. Therefore, even with the way we assume 2732 * hardware should work, we must keep this posting read for paranoia. 2733 */ 2734 if (i != 0) { 2735 unsigned long gtt = readl(>t_entries[i-1]); 2736 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); 2737 } 2738 2739 /* This next bit makes the above posting read even more important. We 2740 * want to flush the TLBs only after we're certain all the PTE updates 2741 * have finished. 2742 */ 2743 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 2744 POSTING_READ(GFX_FLSH_CNTL_GEN6); 2745 } 2746 #endif 2747 2748 static void gen8_ggtt_clear_range(struct i915_address_space *vm, 2749 uint64_t start, 2750 uint64_t length, 2751 bool use_scratch) 2752 { 2753 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2754 unsigned first_entry = start >> PAGE_SHIFT; 2755 unsigned num_entries = length >> PAGE_SHIFT; 2756 #ifdef __NetBSD__ 2757 const bus_space_tag_t bst = dev_priv->gtt.bst; 2758 const bus_space_handle_t bsh = dev_priv->gtt.bsh; 2759 gen8_pte_t scratch_pte; 2760 #else 2761 gen8_pte_t scratch_pte, __iomem *gtt_base = 2762 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 2763 #endif 2764 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 2765 int i; 2766 2767 if (WARN(num_entries > max_entries, 2768 "First entry = %d; Num entries = %d (max=%d)\n", 2769 first_entry, num_entries, max_entries)) 2770 num_entries = max_entries; 2771 2772 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), 2773 I915_CACHE_LLC, 2774 use_scratch, 0); 2775 #ifdef __NetBSD__ 2776 for (i = 0; i < num_entries; i++) 2777 gen8_set_pte(bst, bsh, first_entry + i, scratch_pte); 2778 (void)gen8_get_pte(bst, bsh, first_entry); 2779 #else 2780 for (i = 0; i < num_entries; i++) 2781 gen8_set_pte(>t_base[i], scratch_pte); 2782 readl(gtt_base); 2783 #endif 2784 } 2785 2786 static void gen6_ggtt_clear_range(struct i915_address_space *vm, 2787 uint64_t start, 2788 uint64_t length, 2789 bool use_scratch) 2790 { 2791 struct drm_i915_private *dev_priv = vm->dev->dev_private; 2792 unsigned first_entry = start >> PAGE_SHIFT; 2793 unsigned num_entries = length >> PAGE_SHIFT; 2794 #ifdef __NetBSD__ 2795 const bus_space_tag_t bst = dev_priv->gtt.bst; 2796 const bus_space_handle_t bsh = dev_priv->gtt.bsh; 2797 gen8_pte_t scratch_pte; 2798 #else 2799 gen6_pte_t scratch_pte, __iomem *gtt_base = 2800 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 2801 #endif 2802 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 2803 int i; 2804 2805 if (WARN(num_entries > max_entries, 2806 "First entry = %d; Num entries = %d (max=%d)\n", 2807 first_entry, num_entries, max_entries)) 2808 num_entries = max_entries; 2809 2810 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), 2811 I915_CACHE_LLC, use_scratch, 0); 2812 2813 #ifdef __NetBSD__ 2814 CTASSERT(sizeof(gen6_pte_t) == 4); 2815 for (i = 0; i < num_entries; i++) 2816 bus_space_write_4(bst, bsh, 4*(first_entry + i), scratch_pte); 2817 (void)bus_space_read_4(bst, bsh, 4*first_entry); 2818 #else 2819 for (i = 0; i < num_entries; i++) 2820 iowrite32(scratch_pte, >t_base[i]); 2821 readl(gtt_base); 2822 #endif 2823 } 2824 2825 static void i915_ggtt_insert_entries(struct i915_address_space *vm, 2826 #ifdef __NetBSD__ 2827 bus_dmamap_t pages, 2828 #else 2829 struct sg_table *pages, 2830 #endif 2831 uint64_t start, 2832 enum i915_cache_level cache_level, u32 unused) 2833 { 2834 unsigned int flags = (cache_level == I915_CACHE_NONE) ? 2835 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; 2836 2837 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); 2838 } 2839 2840 static void i915_ggtt_clear_range(struct i915_address_space *vm, 2841 uint64_t start, 2842 uint64_t length, 2843 bool unused) 2844 { 2845 unsigned first_entry = start >> PAGE_SHIFT; 2846 unsigned num_entries = length >> PAGE_SHIFT; 2847 intel_gtt_clear_range(first_entry, num_entries); 2848 } 2849 2850 static int ggtt_bind_vma(struct i915_vma *vma, 2851 enum i915_cache_level cache_level, 2852 u32 flags) 2853 { 2854 struct drm_i915_gem_object *obj = vma->obj; 2855 u32 pte_flags = 0; 2856 int ret; 2857 2858 ret = i915_get_ggtt_vma_pages(vma); 2859 if (ret) 2860 return ret; 2861 2862 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */ 2863 pte_flags = 0; 2864 if (obj->gt_ro) 2865 pte_flags |= PTE_READ_ONLY; 2866 2867 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages, 2868 vma->node.start, 2869 cache_level, pte_flags); 2870 2871 /* 2872 * Without aliasing PPGTT there's no difference between 2873 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally 2874 * upgrade to both bound if we bind either to avoid double-binding. 2875 */ 2876 vma->bound |= GLOBAL_BIND | LOCAL_BIND; 2877 2878 return 0; 2879 } 2880 2881 static int aliasing_gtt_bind_vma(struct i915_vma *vma, 2882 enum i915_cache_level cache_level, 2883 u32 flags) 2884 { 2885 struct drm_device *dev = vma->vm->dev; 2886 struct drm_i915_private *dev_priv = dev->dev_private; 2887 struct drm_i915_gem_object *obj = vma->obj; 2888 #ifdef __NetBSD__ 2889 bus_dmamap_t pages = obj->pages; 2890 #else 2891 struct sg_table *pages = obj->pages; 2892 #endif 2893 u32 pte_flags = 0; 2894 int ret; 2895 2896 ret = i915_get_ggtt_vma_pages(vma); 2897 if (ret) 2898 return ret; 2899 pages = vma->ggtt_view.pages; 2900 2901 /* Currently applicable only to VLV */ 2902 if (obj->gt_ro) 2903 pte_flags |= PTE_READ_ONLY; 2904 2905 2906 if (flags & GLOBAL_BIND) { 2907 vma->vm->insert_entries(vma->vm, pages, 2908 vma->node.start, 2909 cache_level, pte_flags); 2910 } 2911 2912 if (flags & LOCAL_BIND) { 2913 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; 2914 appgtt->base.insert_entries(&appgtt->base, pages, 2915 vma->node.start, 2916 cache_level, pte_flags); 2917 } 2918 2919 return 0; 2920 } 2921 2922 static void ggtt_unbind_vma(struct i915_vma *vma) 2923 { 2924 struct drm_device *dev = vma->vm->dev; 2925 struct drm_i915_private *dev_priv = dev->dev_private; 2926 struct drm_i915_gem_object *obj = vma->obj; 2927 const uint64_t size = min_t(uint64_t, 2928 obj->base.size, 2929 vma->node.size); 2930 2931 if (vma->bound & GLOBAL_BIND) { 2932 vma->vm->clear_range(vma->vm, 2933 vma->node.start, 2934 size, 2935 true); 2936 } 2937 2938 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { 2939 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; 2940 2941 appgtt->base.clear_range(&appgtt->base, 2942 vma->node.start, 2943 size, 2944 true); 2945 } 2946 } 2947 2948 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) 2949 { 2950 struct drm_device *dev = obj->base.dev; 2951 struct drm_i915_private *dev_priv = dev->dev_private; 2952 bool interruptible; 2953 2954 interruptible = do_idling(dev_priv); 2955 2956 #ifdef __NetBSD__ 2957 bus_dmamap_unload(dev->dmat, obj->pages); 2958 #else 2959 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents, 2960 PCI_DMA_BIDIRECTIONAL); 2961 #endif 2962 2963 undo_idling(dev_priv, interruptible); 2964 } 2965 2966 static void i915_gtt_color_adjust(struct drm_mm_node *node, 2967 unsigned long color, 2968 u64 *start, 2969 u64 *end) 2970 { 2971 if (node->color != color) 2972 *start += 4096; 2973 2974 if (!list_empty(&node->node_list)) { 2975 node = list_entry(node->node_list.next, 2976 struct drm_mm_node, 2977 node_list); 2978 if (node->allocated && node->color != color) 2979 *end -= 4096; 2980 } 2981 } 2982 2983 static int i915_gem_setup_global_gtt(struct drm_device *dev, 2984 u64 start, 2985 u64 mappable_end, 2986 u64 end) 2987 { 2988 /* Let GEM Manage all of the aperture. 2989 * 2990 * However, leave one page at the end still bound to the scratch page. 2991 * There are a number of places where the hardware apparently prefetches 2992 * past the end of the object, and we've seen multiple hangs with the 2993 * GPU head pointer stuck in a batchbuffer bound at the last page of the 2994 * aperture. One page should be enough to keep any prefetching inside 2995 * of the aperture. 2996 */ 2997 struct drm_i915_private *dev_priv = dev->dev_private; 2998 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; 2999 struct drm_mm_node *entry; 3000 struct drm_i915_gem_object *obj; 3001 unsigned long hole_start, hole_end; 3002 int ret; 3003 3004 BUG_ON(mappable_end > end); 3005 3006 ggtt_vm->start = start; 3007 3008 /* Subtract the guard page before address space initialization to 3009 * shrink the range used by drm_mm */ 3010 ggtt_vm->total = end - start - PAGE_SIZE; 3011 i915_address_space_init(ggtt_vm, dev_priv); 3012 ggtt_vm->total += PAGE_SIZE; 3013 3014 /* Only VLV supports read-only GGTT mappings */ 3015 ggtt_vm->has_read_only = IS_VALLEYVIEW(dev_priv); 3016 3017 if (intel_vgpu_active(dev)) { 3018 ret = intel_vgt_balloon(dev); 3019 if (ret) 3020 return ret; 3021 } 3022 3023 if (!HAS_LLC(dev)) 3024 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust; 3025 3026 /* Mark any preallocated objects as occupied */ 3027 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 3028 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); 3029 3030 DRM_DEBUG_KMS("reserving preallocated space: %"PRIx64" + %zx\n", 3031 i915_gem_obj_ggtt_offset(obj), obj->base.size); 3032 3033 WARN_ON(i915_gem_obj_ggtt_bound(obj)); 3034 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); 3035 if (ret) { 3036 DRM_DEBUG_KMS("Reservation failed: %i\n", ret); 3037 return ret; 3038 } 3039 vma->bound |= GLOBAL_BIND; 3040 __i915_vma_set_map_and_fenceable(vma); 3041 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list); 3042 } 3043 3044 /* Clear any non-preallocated blocks */ 3045 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { 3046 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", 3047 hole_start, hole_end); 3048 ggtt_vm->clear_range(ggtt_vm, hole_start, 3049 hole_end - hole_start, true); 3050 } 3051 3052 /* And finally clear the reserved guard page */ 3053 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); 3054 3055 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { 3056 struct i915_hw_ppgtt *ppgtt; 3057 3058 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 3059 if (!ppgtt) 3060 return -ENOMEM; 3061 3062 ret = __hw_ppgtt_init(dev, ppgtt); 3063 if (ret) { 3064 ppgtt->base.cleanup(&ppgtt->base); 3065 kfree(ppgtt); 3066 return ret; 3067 } 3068 3069 if (ppgtt->base.allocate_va_range) 3070 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, 3071 ppgtt->base.total); 3072 if (ret) { 3073 ppgtt->base.cleanup(&ppgtt->base); 3074 kfree(ppgtt); 3075 return ret; 3076 } 3077 3078 ppgtt->base.clear_range(&ppgtt->base, 3079 ppgtt->base.start, 3080 ppgtt->base.total, 3081 true); 3082 3083 dev_priv->mm.aliasing_ppgtt = ppgtt; 3084 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma); 3085 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma; 3086 } 3087 3088 return 0; 3089 } 3090 3091 void i915_gem_init_global_gtt(struct drm_device *dev) 3092 { 3093 struct drm_i915_private *dev_priv = dev->dev_private; 3094 u64 gtt_size, mappable_size; 3095 3096 gtt_size = dev_priv->gtt.base.total; 3097 mappable_size = dev_priv->gtt.mappable_end; 3098 3099 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); 3100 } 3101 3102 void i915_global_gtt_cleanup(struct drm_device *dev) 3103 { 3104 struct drm_i915_private *dev_priv = dev->dev_private; 3105 struct i915_address_space *vm = &dev_priv->gtt.base; 3106 3107 if (dev_priv->mm.aliasing_ppgtt) { 3108 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 3109 3110 ppgtt->base.cleanup(&ppgtt->base); 3111 kfree(ppgtt); 3112 } 3113 3114 if (drm_mm_initialized(&vm->mm)) { 3115 if (intel_vgpu_active(dev)) 3116 intel_vgt_deballoon(); 3117 3118 drm_mm_takedown(&vm->mm); 3119 list_del(&vm->global_link); 3120 } 3121 3122 vm->cleanup(vm); 3123 } 3124 3125 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) 3126 { 3127 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; 3128 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; 3129 return snb_gmch_ctl << 20; 3130 } 3131 3132 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) 3133 { 3134 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; 3135 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 3136 if (bdw_gmch_ctl) 3137 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 3138 3139 #ifdef CONFIG_X86_32 3140 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ 3141 if (bdw_gmch_ctl > 4) 3142 bdw_gmch_ctl = 4; 3143 #endif 3144 3145 return bdw_gmch_ctl << 20; 3146 } 3147 3148 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) 3149 { 3150 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; 3151 gmch_ctrl &= SNB_GMCH_GGMS_MASK; 3152 3153 if (gmch_ctrl) 3154 return 1 << (20 + gmch_ctrl); 3155 3156 return 0; 3157 } 3158 3159 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) 3160 { 3161 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; 3162 snb_gmch_ctl &= SNB_GMCH_GMS_MASK; 3163 return snb_gmch_ctl << 25; /* 32 MB units */ 3164 } 3165 3166 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) 3167 { 3168 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; 3169 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; 3170 return bdw_gmch_ctl << 25; /* 32 MB units */ 3171 } 3172 3173 static size_t chv_get_stolen_size(u16 gmch_ctrl) 3174 { 3175 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; 3176 gmch_ctrl &= SNB_GMCH_GMS_MASK; 3177 3178 /* 3179 * 0x0 to 0x10: 32MB increments starting at 0MB 3180 * 0x11 to 0x16: 4MB increments starting at 8MB 3181 * 0x17 to 0x1d: 4MB increments start at 36MB 3182 */ 3183 if (gmch_ctrl < 0x11) 3184 return gmch_ctrl << 25; 3185 else if (gmch_ctrl < 0x17) 3186 return (gmch_ctrl - 0x11 + 2) << 22; 3187 else 3188 return (gmch_ctrl - 0x17 + 9) << 22; 3189 } 3190 3191 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) 3192 { 3193 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; 3194 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; 3195 3196 if (gen9_gmch_ctl < 0xf0) 3197 return gen9_gmch_ctl << 25; /* 32 MB units */ 3198 else 3199 /* 4MB increments starting at 0xf0 for 4MB */ 3200 return (gen9_gmch_ctl - 0xf0 + 1) << 22; 3201 } 3202 3203 static int ggtt_probe_common(struct drm_device *dev, 3204 size_t gtt_size) 3205 { 3206 struct drm_i915_private *dev_priv = dev->dev_private; 3207 struct i915_page_scratch *scratch_page; 3208 phys_addr_t gtt_phys_addr; 3209 3210 /* For Modern GENs the PTEs and register space are split in the BAR */ 3211 gtt_phys_addr = pci_resource_start(dev->pdev, 0) + 3212 (pci_resource_len(dev->pdev, 0) / 2); 3213 3214 #ifdef __NetBSD__ 3215 int ret; 3216 dev_priv->gtt.bst = dev->pdev->pd_pa.pa_memt; 3217 /* XXX errno NetBSD->Linux */ 3218 ret = -bus_space_map(dev_priv->gtt.bst, gtt_phys_addr, gtt_size, 3219 IS_BROXTON(dev) ? 0 : BUS_SPACE_MAP_PREFETCHABLE, 3220 &dev_priv->gtt.bsh); 3221 if (ret) { 3222 DRM_ERROR("Failed to map the graphics translation table: %d\n", 3223 ret); 3224 return ret; 3225 } 3226 dev_priv->gtt.size = gtt_size; 3227 #else 3228 /* 3229 * On BXT writes larger than 64 bit to the GTT pagetable range will be 3230 * dropped. For WC mappings in general we have 64 byte burst writes 3231 * when the WC buffer is flushed, so we can't use it, but have to 3232 * resort to an uncached mapping. The WC issue is easily caught by the 3233 * readback check when writing GTT PTE entries. 3234 */ 3235 if (IS_BROXTON(dev)) 3236 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); 3237 else 3238 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); 3239 if (!dev_priv->gtt.gsm) { 3240 DRM_ERROR("Failed to map the gtt page table\n"); 3241 return -ENOMEM; 3242 } 3243 #endif 3244 3245 scratch_page = alloc_scratch_page(dev); 3246 if (IS_ERR(scratch_page)) { 3247 DRM_ERROR("Scratch setup failed\n"); 3248 /* iounmap will also get called at remove, but meh */ 3249 #ifdef __NetBSD__ 3250 bus_space_unmap(dev_priv->gtt.bst, dev_priv->gtt.bsh, 3251 dev_priv->gtt.size); 3252 #else 3253 iounmap(dev_priv->gtt.gsm); 3254 #endif 3255 return PTR_ERR(scratch_page); 3256 } 3257 3258 dev_priv->gtt.base.scratch_page = scratch_page; 3259 3260 return 0; 3261 } 3262 3263 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 3264 * bits. When using advanced contexts each context stores its own PAT, but 3265 * writing this data shouldn't be harmful even in those cases. */ 3266 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) 3267 { 3268 uint64_t pat; 3269 3270 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 3271 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 3272 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ 3273 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 3274 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 3275 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 3276 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 3277 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 3278 3279 if (!USES_PPGTT(dev_priv->dev)) 3280 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, 3281 * so RTL will always use the value corresponding to 3282 * pat_sel = 000". 3283 * So let's disable cache for GGTT to avoid screen corruptions. 3284 * MOCS still can be used though. 3285 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work 3286 * before this patch, i.e. the same uncached + snooping access 3287 * like on gen6/7 seems to be in effect. 3288 * - So this just fixes blitter/render access. Again it looks 3289 * like it's not just uncached access, but uncached + snooping. 3290 * So we can still hold onto all our assumptions wrt cpu 3291 * clflushing on LLC machines. 3292 */ 3293 pat = GEN8_PPAT(0, GEN8_PPAT_UC); 3294 3295 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b 3296 * write would work. */ 3297 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); 3298 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); 3299 } 3300 3301 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) 3302 { 3303 uint64_t pat; 3304 3305 /* 3306 * Map WB on BDW to snooped on CHV. 3307 * 3308 * Only the snoop bit has meaning for CHV, the rest is 3309 * ignored. 3310 * 3311 * The hardware will never snoop for certain types of accesses: 3312 * - CPU GTT (GMADR->GGTT->no snoop->memory) 3313 * - PPGTT page tables 3314 * - some other special cycles 3315 * 3316 * As with BDW, we also need to consider the following for GT accesses: 3317 * "For GGTT, there is NO pat_sel[2:0] from the entry, 3318 * so RTL will always use the value corresponding to 3319 * pat_sel = 000". 3320 * Which means we must set the snoop bit in PAT entry 0 3321 * in order to keep the global status page working. 3322 */ 3323 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 3324 GEN8_PPAT(1, 0) | 3325 GEN8_PPAT(2, 0) | 3326 GEN8_PPAT(3, 0) | 3327 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 3328 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 3329 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 3330 GEN8_PPAT(7, CHV_PPAT_SNOOP); 3331 3332 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); 3333 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); 3334 } 3335 3336 static int gen8_gmch_probe(struct drm_device *dev, 3337 u64 *gtt_total, 3338 size_t *stolen, 3339 phys_addr_t *mappable_base, 3340 u64 *mappable_end) 3341 { 3342 struct drm_i915_private *dev_priv = dev->dev_private; 3343 u64 gtt_size; 3344 u16 snb_gmch_ctl; 3345 int ret; 3346 3347 /* TODO: We're not aware of mappable constraints on gen8 yet */ 3348 *mappable_base = pci_resource_start(dev->pdev, 2); 3349 *mappable_end = pci_resource_len(dev->pdev, 2); 3350 3351 #ifndef __NetBSD__ 3352 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) 3353 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); 3354 #endif 3355 3356 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 3357 3358 if (INTEL_INFO(dev)->gen >= 9) { 3359 *stolen = gen9_get_stolen_size(snb_gmch_ctl); 3360 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); 3361 } else if (IS_CHERRYVIEW(dev)) { 3362 *stolen = chv_get_stolen_size(snb_gmch_ctl); 3363 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); 3364 } else { 3365 *stolen = gen8_get_stolen_size(snb_gmch_ctl); 3366 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); 3367 } 3368 3369 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; 3370 3371 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) 3372 chv_setup_private_ppat(dev_priv); 3373 else 3374 bdw_setup_private_ppat(dev_priv); 3375 3376 ret = ggtt_probe_common(dev, gtt_size); 3377 3378 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; 3379 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; 3380 dev_priv->gtt.base.bind_vma = ggtt_bind_vma; 3381 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; 3382 3383 /* XXX 39-bit addresses? Really? See pci_set_dma_mask above... */ 3384 dev_priv->gtt.max_paddr = __BITS(38, 0); 3385 3386 return ret; 3387 } 3388 3389 static int gen6_gmch_probe(struct drm_device *dev, 3390 u64 *gtt_total, 3391 size_t *stolen, 3392 phys_addr_t *mappable_base, 3393 u64 *mappable_end) 3394 { 3395 struct drm_i915_private *dev_priv = dev->dev_private; 3396 unsigned int gtt_size; 3397 u16 snb_gmch_ctl; 3398 int ret; 3399 3400 *mappable_base = pci_resource_start(dev->pdev, 2); 3401 *mappable_end = pci_resource_len(dev->pdev, 2); 3402 3403 /* 64/512MB is the current min/max we actually know of, but this is just 3404 * a coarse sanity check. 3405 */ 3406 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { 3407 DRM_ERROR("Unknown GMADR size (%"PRIx64")\n", 3408 dev_priv->gtt.mappable_end); 3409 return -ENXIO; 3410 } 3411 3412 #ifndef __NetBSD__ 3413 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) 3414 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); 3415 #endif 3416 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 3417 3418 *stolen = gen6_get_stolen_size(snb_gmch_ctl); 3419 3420 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); 3421 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; 3422 3423 ret = ggtt_probe_common(dev, gtt_size); 3424 3425 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; 3426 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; 3427 dev_priv->gtt.base.bind_vma = ggtt_bind_vma; 3428 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; 3429 3430 dev_priv->gtt.max_paddr = __BITS(39, 0); 3431 3432 return ret; 3433 } 3434 3435 static void gen6_gmch_remove(struct i915_address_space *vm) 3436 { 3437 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 3438 3439 #ifdef __NetBSD__ 3440 bus_space_unmap(gtt->bst, gtt->bsh, gtt->size); 3441 #else 3442 iounmap(gtt->gsm); 3443 #endif 3444 free_scratch_page(vm->dev, vm->scratch_page); 3445 } 3446 3447 static int i915_gmch_probe(struct drm_device *dev, 3448 u64 *gtt_total, 3449 size_t *stolen, 3450 phys_addr_t *mappable_base, 3451 u64 *mappable_end) 3452 { 3453 struct drm_i915_private *dev_priv = dev->dev_private; 3454 int ret; 3455 3456 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); 3457 if (!ret) { 3458 DRM_ERROR("failed to set up gmch\n"); 3459 return -EIO; 3460 } 3461 3462 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); 3463 3464 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); 3465 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; 3466 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; 3467 dev_priv->gtt.base.bind_vma = ggtt_bind_vma; 3468 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; 3469 3470 if (unlikely(dev_priv->gtt.do_idle_maps)) 3471 DRM_INFO("applying Ironlake quirks for intel_iommu\n"); 3472 3473 if (INTEL_INFO(dev)->gen <= 2) 3474 dev_priv->gtt.max_paddr = __BITS(29, 0); 3475 else if ((INTEL_INFO(dev)->gen <= 3) || 3476 IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 3477 dev_priv->gtt.max_paddr = __BITS(31, 0); 3478 else if (INTEL_INFO(dev)->gen <= 5) 3479 dev_priv->gtt.max_paddr = __BITS(35, 0); 3480 else 3481 dev_priv->gtt.max_paddr = __BITS(39, 0); 3482 3483 return 0; 3484 } 3485 3486 static void i915_gmch_remove(struct i915_address_space *vm) 3487 { 3488 intel_gmch_remove(); 3489 } 3490 3491 int i915_gem_gtt_init(struct drm_device *dev) 3492 { 3493 struct drm_i915_private *dev_priv = dev->dev_private; 3494 struct i915_gtt *gtt = &dev_priv->gtt; 3495 int ret; 3496 3497 if (INTEL_INFO(dev)->gen <= 5) { 3498 gtt->gtt_probe = i915_gmch_probe; 3499 gtt->base.cleanup = i915_gmch_remove; 3500 } else if (INTEL_INFO(dev)->gen < 8) { 3501 gtt->gtt_probe = gen6_gmch_probe; 3502 gtt->base.cleanup = gen6_gmch_remove; 3503 if (IS_HASWELL(dev) && dev_priv->ellc_size) 3504 gtt->base.pte_encode = iris_pte_encode; 3505 else if (IS_HASWELL(dev)) 3506 gtt->base.pte_encode = hsw_pte_encode; 3507 else if (IS_VALLEYVIEW(dev)) 3508 gtt->base.pte_encode = byt_pte_encode; 3509 else if (INTEL_INFO(dev)->gen >= 7) 3510 gtt->base.pte_encode = ivb_pte_encode; 3511 else 3512 gtt->base.pte_encode = snb_pte_encode; 3513 } else { 3514 dev_priv->gtt.gtt_probe = gen8_gmch_probe; 3515 dev_priv->gtt.base.cleanup = gen6_gmch_remove; 3516 } 3517 3518 gtt->base.dev = dev; 3519 3520 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, 3521 >t->mappable_base, >t->mappable_end); 3522 if (ret) 3523 return ret; 3524 3525 #ifdef __NetBSD__ 3526 dev_priv->gtt.pgfl = x86_select_freelist(dev_priv->gtt.max_paddr); 3527 ret = drm_limit_dma_space(dev, 0, dev_priv->gtt.max_paddr); 3528 if (ret) { 3529 DRM_ERROR("Unable to limit DMA paddr allocations: %d!\n", ret); 3530 gtt->base.cleanup(>t->base); 3531 return ret; 3532 } 3533 #endif 3534 3535 /* GMADR is the PCI mmio aperture into the global GTT. */ 3536 DRM_INFO("Memory usable by graphics device = %"PRIu64"M\n", 3537 gtt->base.total >> 20); 3538 DRM_DEBUG_DRIVER("GMADR size = %"PRId64"M\n", gtt->mappable_end >> 20); 3539 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); 3540 #ifdef CONFIG_INTEL_IOMMU 3541 if (intel_iommu_gfx_mapped) 3542 DRM_INFO("VT-d active for gfx access\n"); 3543 #endif 3544 /* 3545 * i915.enable_ppgtt is read-only, so do an early pass to validate the 3546 * user's requested state against the hardware/driver capabilities. We 3547 * do this now so that we can print out any log messages once rather 3548 * than every time we check intel_enable_ppgtt(). 3549 */ 3550 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); 3551 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); 3552 3553 return 0; 3554 } 3555 3556 void i915_gem_restore_gtt_mappings(struct drm_device *dev) 3557 { 3558 struct drm_i915_private *dev_priv = dev->dev_private; 3559 struct drm_i915_gem_object *obj; 3560 struct i915_address_space *vm; 3561 struct i915_vma *vma; 3562 bool flush; 3563 3564 i915_check_and_clear_faults(dev); 3565 3566 /* First fill our portion of the GTT with scratch pages */ 3567 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 3568 dev_priv->gtt.base.start, 3569 dev_priv->gtt.base.total, 3570 true); 3571 3572 /* Cache flush objects bound into GGTT and rebind them. */ 3573 vm = &dev_priv->gtt.base; 3574 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 3575 flush = false; 3576 list_for_each_entry(vma, &obj->vma_list, vma_link) { 3577 if (vma->vm != vm) 3578 continue; 3579 3580 WARN_ON(i915_vma_bind(vma, obj->cache_level, 3581 PIN_UPDATE)); 3582 3583 flush = true; 3584 } 3585 3586 if (flush) 3587 i915_gem_clflush_object(obj, obj->pin_display); 3588 } 3589 3590 if (INTEL_INFO(dev)->gen >= 8) { 3591 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) 3592 chv_setup_private_ppat(dev_priv); 3593 else 3594 bdw_setup_private_ppat(dev_priv); 3595 3596 return; 3597 } 3598 3599 if (USES_PPGTT(dev)) { 3600 list_for_each_entry(vm, &dev_priv->vm_list, global_link) { 3601 /* TODO: Perhaps it shouldn't be gen6 specific */ 3602 3603 struct i915_hw_ppgtt *ppgtt = 3604 container_of(vm, struct i915_hw_ppgtt, 3605 base); 3606 3607 if (i915_is_ggtt(vm)) 3608 ppgtt = dev_priv->mm.aliasing_ppgtt; 3609 3610 gen6_write_page_range(dev_priv, &ppgtt->pd, 3611 0, ppgtt->base.total); 3612 } 3613 } 3614 3615 i915_ggtt_flush(dev_priv); 3616 } 3617 3618 static struct i915_vma * 3619 __i915_gem_vma_create(struct drm_i915_gem_object *obj, 3620 struct i915_address_space *vm, 3621 const struct i915_ggtt_view *ggtt_view) 3622 { 3623 struct i915_vma *vma; 3624 3625 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) 3626 return ERR_PTR(-EINVAL); 3627 3628 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); 3629 if (vma == NULL) 3630 return ERR_PTR(-ENOMEM); 3631 3632 INIT_LIST_HEAD(&vma->vma_link); 3633 INIT_LIST_HEAD(&vma->mm_list); 3634 INIT_LIST_HEAD(&vma->exec_list); 3635 vma->vm = vm; 3636 vma->obj = obj; 3637 3638 if (i915_is_ggtt(vm)) 3639 vma->ggtt_view = *ggtt_view; 3640 3641 list_add_tail(&vma->vma_link, &obj->vma_list); 3642 if (!i915_is_ggtt(vm)) 3643 i915_ppgtt_get(i915_vm_to_ppgtt(vm)); 3644 3645 return vma; 3646 } 3647 3648 struct i915_vma * 3649 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 3650 struct i915_address_space *vm) 3651 { 3652 struct i915_vma *vma; 3653 3654 vma = i915_gem_obj_to_vma(obj, vm); 3655 if (!vma) 3656 vma = __i915_gem_vma_create(obj, vm, 3657 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); 3658 3659 return vma; 3660 } 3661 3662 struct i915_vma * 3663 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, 3664 const struct i915_ggtt_view *view) 3665 { 3666 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); 3667 struct i915_vma *vma; 3668 3669 if (WARN_ON(!view)) 3670 return ERR_PTR(-EINVAL); 3671 3672 vma = i915_gem_obj_to_ggtt_view(obj, view); 3673 3674 if (IS_ERR(vma)) 3675 return vma; 3676 3677 if (!vma) 3678 vma = __i915_gem_vma_create(obj, ggtt, view); 3679 3680 return vma; 3681 3682 } 3683 3684 #ifndef __NetBSD__ 3685 static struct scatterlist * 3686 rotate_pages(dma_addr_t *in, unsigned int offset, 3687 unsigned int width, unsigned int height, 3688 struct sg_table *st, struct scatterlist *sg) 3689 { 3690 unsigned int column, row; 3691 unsigned int src_idx; 3692 3693 if (!sg) { 3694 st->nents = 0; 3695 sg = st->sgl; 3696 } 3697 3698 for (column = 0; column < width; column++) { 3699 src_idx = width * (height - 1) + column; 3700 for (row = 0; row < height; row++) { 3701 st->nents++; 3702 /* We don't need the pages, but need to initialize 3703 * the entries so the sg list can be happily traversed. 3704 * The only thing we need are DMA addresses. 3705 */ 3706 sg_set_page(sg, NULL, PAGE_SIZE, 0); 3707 sg_dma_address(sg) = in[offset + src_idx]; 3708 sg_dma_len(sg) = PAGE_SIZE; 3709 sg = sg_next(sg); 3710 src_idx -= width; 3711 } 3712 } 3713 3714 return sg; 3715 } 3716 3717 static struct sg_table * 3718 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, 3719 struct drm_i915_gem_object *obj) 3720 { 3721 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; 3722 unsigned int size_pages = rot_info->size >> PAGE_SHIFT; 3723 unsigned int size_pages_uv; 3724 struct sg_page_iter sg_iter; 3725 unsigned long i; 3726 dma_addr_t *page_addr_list; 3727 struct sg_table *st; 3728 unsigned int uv_start_page; 3729 struct scatterlist *sg; 3730 int ret = -ENOMEM; 3731 3732 /* Allocate a temporary list of source pages for random access. */ 3733 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, 3734 sizeof(dma_addr_t)); 3735 if (!page_addr_list) 3736 return ERR_PTR(ret); 3737 3738 /* Account for UV plane with NV12. */ 3739 if (rot_info->pixel_format == DRM_FORMAT_NV12) 3740 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT; 3741 else 3742 size_pages_uv = 0; 3743 3744 /* Allocate target SG list. */ 3745 st = kmalloc(sizeof(*st), GFP_KERNEL); 3746 if (!st) 3747 goto err_st_alloc; 3748 3749 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL); 3750 if (ret) 3751 goto err_sg_alloc; 3752 3753 /* Populate source page list from the object. */ 3754 i = 0; 3755 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 3756 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); 3757 i++; 3758 } 3759 3760 /* Rotate the pages. */ 3761 sg = rotate_pages(page_addr_list, 0, 3762 rot_info->width_pages, rot_info->height_pages, 3763 st, NULL); 3764 3765 /* Append the UV plane if NV12. */ 3766 if (rot_info->pixel_format == DRM_FORMAT_NV12) { 3767 uv_start_page = size_pages; 3768 3769 /* Check for tile-row un-alignment. */ 3770 if (offset_in_page(rot_info->uv_offset)) 3771 uv_start_page--; 3772 3773 rot_info->uv_start_page = uv_start_page; 3774 3775 rotate_pages(page_addr_list, uv_start_page, 3776 rot_info->width_pages_uv, 3777 rot_info->height_pages_uv, 3778 st, sg); 3779 } 3780 3781 DRM_DEBUG_KMS( 3782 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n", 3783 obj->base.size, rot_info->pitch, rot_info->height, 3784 rot_info->pixel_format, rot_info->width_pages, 3785 rot_info->height_pages, size_pages + size_pages_uv, 3786 size_pages); 3787 3788 drm_free_large(page_addr_list); 3789 3790 return st; 3791 3792 err_sg_alloc: 3793 kfree(st); 3794 err_st_alloc: 3795 drm_free_large(page_addr_list); 3796 3797 DRM_DEBUG_KMS( 3798 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n", 3799 obj->base.size, ret, rot_info->pitch, rot_info->height, 3800 rot_info->pixel_format, rot_info->width_pages, 3801 rot_info->height_pages, size_pages + size_pages_uv, 3802 size_pages); 3803 return ERR_PTR(ret); 3804 } 3805 3806 static struct sg_table * 3807 intel_partial_pages(const struct i915_ggtt_view *view, 3808 struct drm_i915_gem_object *obj) 3809 { 3810 struct sg_table *st; 3811 struct scatterlist *sg; 3812 struct sg_page_iter obj_sg_iter; 3813 int ret = -ENOMEM; 3814 3815 st = kmalloc(sizeof(*st), GFP_KERNEL); 3816 if (!st) 3817 goto err_st_alloc; 3818 3819 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); 3820 if (ret) 3821 goto err_sg_alloc; 3822 3823 sg = st->sgl; 3824 st->nents = 0; 3825 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, 3826 view->params.partial.offset) 3827 { 3828 if (st->nents >= view->params.partial.size) 3829 break; 3830 3831 sg_set_page(sg, NULL, PAGE_SIZE, 0); 3832 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); 3833 sg_dma_len(sg) = PAGE_SIZE; 3834 3835 sg = sg_next(sg); 3836 st->nents++; 3837 } 3838 3839 return st; 3840 3841 err_sg_alloc: 3842 kfree(st); 3843 err_st_alloc: 3844 return ERR_PTR(ret); 3845 } 3846 #endif 3847 3848 static int 3849 i915_get_ggtt_vma_pages(struct i915_vma *vma) 3850 { 3851 int ret = 0; 3852 3853 if (vma->ggtt_view.pages) 3854 return 0; 3855 3856 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) 3857 vma->ggtt_view.pages = vma->obj->pages; 3858 #ifndef __NetBSD__ 3859 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) 3860 vma->ggtt_view.pages = 3861 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); 3862 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) 3863 vma->ggtt_view.pages = 3864 intel_partial_pages(&vma->ggtt_view, vma->obj); 3865 #endif 3866 else 3867 WARN_ONCE(1, "GGTT view %u not implemented!\n", 3868 vma->ggtt_view.type); 3869 3870 if (!vma->ggtt_view.pages) { 3871 DRM_ERROR("Failed to get pages for GGTT view type %u!\n", 3872 vma->ggtt_view.type); 3873 ret = -EINVAL; 3874 } else if (IS_ERR(vma->ggtt_view.pages)) { 3875 ret = PTR_ERR(vma->ggtt_view.pages); 3876 vma->ggtt_view.pages = NULL; 3877 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", 3878 vma->ggtt_view.type, ret); 3879 } 3880 3881 return ret; 3882 } 3883 3884 /** 3885 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. 3886 * @vma: VMA to map 3887 * @cache_level: mapping cache level 3888 * @flags: flags like global or local mapping 3889 * 3890 * DMA addresses are taken from the scatter-gather table of this object (or of 3891 * this VMA in case of non-default GGTT views) and PTE entries set up. 3892 * Note that DMA addresses are also the only part of the SG table we care about. 3893 */ 3894 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 3895 u32 flags) 3896 { 3897 int ret; 3898 u32 bind_flags; 3899 3900 if (WARN_ON(flags == 0)) 3901 return -EINVAL; 3902 3903 bind_flags = 0; 3904 if (flags & PIN_GLOBAL) 3905 bind_flags |= GLOBAL_BIND; 3906 if (flags & PIN_USER) 3907 bind_flags |= LOCAL_BIND; 3908 3909 if (flags & PIN_UPDATE) 3910 bind_flags |= vma->bound; 3911 else 3912 bind_flags &= ~vma->bound; 3913 3914 if (bind_flags == 0) 3915 return 0; 3916 3917 if (vma->bound == 0 && vma->vm->allocate_va_range) { 3918 trace_i915_va_alloc(vma->vm, 3919 vma->node.start, 3920 vma->node.size, 3921 VM_TO_TRACE_NAME(vma->vm)); 3922 3923 /* XXX: i915_vma_pin() will fix this +- hack */ 3924 vma->pin_count++; 3925 ret = vma->vm->allocate_va_range(vma->vm, 3926 vma->node.start, 3927 vma->node.size); 3928 vma->pin_count--; 3929 if (ret) 3930 return ret; 3931 } 3932 3933 ret = vma->vm->bind_vma(vma, cache_level, bind_flags); 3934 if (ret) 3935 return ret; 3936 3937 vma->bound |= bind_flags; 3938 3939 return 0; 3940 } 3941 3942 /** 3943 * i915_ggtt_view_size - Get the size of a GGTT view. 3944 * @obj: Object the view is of. 3945 * @view: The view in question. 3946 * 3947 * @return The size of the GGTT view in bytes. 3948 */ 3949 size_t 3950 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 3951 const struct i915_ggtt_view *view) 3952 { 3953 if (view->type == I915_GGTT_VIEW_NORMAL) { 3954 return obj->base.size; 3955 } else if (view->type == I915_GGTT_VIEW_ROTATED) { 3956 return view->rotation_info.size; 3957 } else if (view->type == I915_GGTT_VIEW_PARTIAL) { 3958 return view->params.partial.size << PAGE_SHIFT; 3959 } else { 3960 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); 3961 return obj->base.size; 3962 } 3963 } 3964
Indexes created Sun Oct 26 17:10:13 GMT 2025