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i915_pvinfo.h revision 1.1 
      1 /*	$NetBSD: i915_pvinfo.h,v 1.1 2021/12/18 20:15:25 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  */
     25 
     26 #ifndef _I915_PVINFO_H_
     27 #define _I915_PVINFO_H_
     28 
     29 #include <linux/types.h>
     30 
     31 /* The MMIO offset of the shared info between guest and host emulator */
     32 #define VGT_PVINFO_PAGE	0x78000
     33 #define VGT_PVINFO_SIZE	0x1000
     34 
     35 /*
     36  * The following structure pages are defined in GEN MMIO space
     37  * for virtualization. (One page for now)
     38  */
     39 #define VGT_MAGIC         0x4776544776544776ULL	/* 'vGTvGTvG' */
     40 #define VGT_VERSION_MAJOR 1
     41 #define VGT_VERSION_MINOR 0
     42 
     43 /*
     44  * notifications from guest to vgpu device model
     45  */
     46 enum vgt_g2v_type {
     47 	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
     48 	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
     49 	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
     50 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
     51 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
     52 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
     53 	VGT_G2V_MAX,
     54 };
     55 
     56 /*
     57  * VGT capabilities type
     58  */
     59 #define VGT_CAPS_FULL_PPGTT		BIT(2)
     60 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
     61 #define VGT_CAPS_HUGE_GTT		BIT(4)
     62 
     63 struct vgt_if {
     64 	u64 magic;		/* VGT_MAGIC */
     65 	u16 version_major;
     66 	u16 version_minor;
     67 	u32 vgt_id;		/* ID of vGT instance */
     68 	u32 vgt_caps;		/* VGT capabilities */
     69 	u32 rsv1[11];		/* pad to offset 0x40 */
     70 	/*
     71 	 *  Data structure to describe the balooning info of resources.
     72 	 *  Each VM can only have one portion of continuous area for now.
     73 	 *  (May support scattered resource in future)
     74 	 *  (starting from offset 0x40)
     75 	 */
     76 	struct {
     77 		/* Aperture register balooning */
     78 		struct {
     79 			u32 base;
     80 			u32 size;
     81 		} mappable_gmadr;	/* aperture */
     82 		/* GMADR register balooning */
     83 		struct {
     84 			u32 base;
     85 			u32 size;
     86 		} nonmappable_gmadr;	/* non aperture */
     87 		/* allowed fence registers */
     88 		u32 fence_num;
     89 		u32 rsv2[3];
     90 	} avail_rs;		/* available/assigned resource */
     91 	u32 rsv3[0x200 - 24];	/* pad to half page */
     92 	/*
     93 	 * The bottom half page is for response from Gfx driver to hypervisor.
     94 	 */
     95 	u32 rsv4;
     96 	u32 display_ready;	/* ready for display owner switch */
     97 
     98 	u32 rsv5[4];
     99 
    100 	u32 g2v_notify;
    101 	u32 rsv6[5];
    102 
    103 	u32 cursor_x_hot;
    104 	u32 cursor_y_hot;
    105 
    106 	struct {
    107 		u32 lo;
    108 		u32 hi;
    109 	} pdp[4];
    110 
    111 	u32 execlist_context_descriptor_lo;
    112 	u32 execlist_context_descriptor_hi;
    113 
    114 	u32  rsv7[0x200 - 24];    /* pad to one page */
    115 } __packed;
    116 
    117 #define vgtif_offset(x) (offsetof(struct vgt_if, x))
    118 
    119 #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
    120 
    121 /* vGPU display status to be used by the host side */
    122 #define VGT_DRV_DISPLAY_NOT_READY 0
    123 #define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
    124 
    125 #endif /* _I915_PVINFO_H_ */
    126