1 1.2 riastrad /* $NetBSD: i915_suspend.c,v 1.3 2021/12/18 23:45:28 riastradh Exp $ */ 2 1.2 riastrad 3 1.1 riastrad /* 4 1.1 riastrad * 5 1.1 riastrad * Copyright 2008 (c) Intel Corporation 6 1.1 riastrad * Jesse Barnes <jbarnes (at) virtuousgeek.org> 7 1.1 riastrad * 8 1.1 riastrad * Permission is hereby granted, free of charge, to any person obtaining a 9 1.1 riastrad * copy of this software and associated documentation files (the 10 1.1 riastrad * "Software"), to deal in the Software without restriction, including 11 1.1 riastrad * without limitation the rights to use, copy, modify, merge, publish, 12 1.1 riastrad * distribute, sub license, and/or sell copies of the Software, and to 13 1.1 riastrad * permit persons to whom the Software is furnished to do so, subject to 14 1.1 riastrad * the following conditions: 15 1.1 riastrad * 16 1.1 riastrad * The above copyright notice and this permission notice (including the 17 1.1 riastrad * next paragraph) shall be included in all copies or substantial portions 18 1.1 riastrad * of the Software. 19 1.1 riastrad * 20 1.1 riastrad * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 1.1 riastrad * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 1.1 riastrad * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 1.1 riastrad * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 1.1 riastrad * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 1.1 riastrad * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 1.1 riastrad * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 1.1 riastrad */ 28 1.1 riastrad 29 1.2 riastrad #include <sys/cdefs.h> 30 1.2 riastrad __KERNEL_RCSID(0, "$NetBSD: i915_suspend.c,v 1.3 2021/12/18 23:45:28 riastradh Exp $"); 31 1.2 riastrad 32 1.1 riastrad #include <drm/i915_drm.h> 33 1.3 riastrad 34 1.3 riastrad #include "display/intel_fbc.h" 35 1.3 riastrad #include "display/intel_gmbus.h" 36 1.3 riastrad #include "display/intel_vga.h" 37 1.3 riastrad 38 1.3 riastrad #include "i915_drv.h" 39 1.1 riastrad #include "i915_reg.h" 40 1.3 riastrad #include "i915_suspend.h" 41 1.1 riastrad 42 1.3 riastrad static void i915_save_display(struct drm_i915_private *dev_priv) 43 1.1 riastrad { 44 1.1 riastrad /* Display arbitration control */ 45 1.3 riastrad if (INTEL_GEN(dev_priv) <= 4) 46 1.2 riastrad dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); 47 1.1 riastrad 48 1.2 riastrad /* save FBC interval */ 49 1.3 riastrad if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) 50 1.2 riastrad dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); 51 1.1 riastrad } 52 1.1 riastrad 53 1.3 riastrad static void i915_restore_display(struct drm_i915_private *dev_priv) 54 1.1 riastrad { 55 1.1 riastrad /* Display arbitration */ 56 1.3 riastrad if (INTEL_GEN(dev_priv) <= 4) 57 1.2 riastrad I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); 58 1.1 riastrad 59 1.2 riastrad /* only restore FBC info on the platform that supports FBC*/ 60 1.3 riastrad intel_fbc_global_disable(dev_priv); 61 1.1 riastrad 62 1.2 riastrad /* restore FBC interval */ 63 1.3 riastrad if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) 64 1.2 riastrad I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); 65 1.1 riastrad 66 1.3 riastrad intel_vga_redisable(dev_priv); 67 1.1 riastrad } 68 1.1 riastrad 69 1.3 riastrad int i915_save_state(struct drm_i915_private *dev_priv) 70 1.1 riastrad { 71 1.3 riastrad struct pci_dev *pdev = dev_priv->drm.pdev; 72 1.1 riastrad int i; 73 1.1 riastrad 74 1.3 riastrad i915_save_display(dev_priv); 75 1.1 riastrad 76 1.3 riastrad if (IS_GEN(dev_priv, 4)) 77 1.3 riastrad pci_read_config_word(pdev, GCDGMBUS, 78 1.2 riastrad &dev_priv->regfile.saveGCDGMBUS); 79 1.1 riastrad 80 1.1 riastrad /* Cache mode state */ 81 1.3 riastrad if (INTEL_GEN(dev_priv) < 7) 82 1.2 riastrad dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 83 1.1 riastrad 84 1.1 riastrad /* Memory Arbitration state */ 85 1.1 riastrad dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 86 1.1 riastrad 87 1.1 riastrad /* Scratch space */ 88 1.3 riastrad if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { 89 1.2 riastrad for (i = 0; i < 7; i++) { 90 1.2 riastrad dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); 91 1.2 riastrad dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 92 1.2 riastrad } 93 1.2 riastrad for (i = 0; i < 3; i++) 94 1.2 riastrad dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); 95 1.3 riastrad } else if (IS_GEN(dev_priv, 2)) { 96 1.2 riastrad for (i = 0; i < 7; i++) 97 1.2 riastrad dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 98 1.3 riastrad } else if (HAS_GMCH(dev_priv)) { 99 1.2 riastrad for (i = 0; i < 16; i++) { 100 1.2 riastrad dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); 101 1.2 riastrad dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 102 1.2 riastrad } 103 1.2 riastrad for (i = 0; i < 3; i++) 104 1.2 riastrad dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); 105 1.1 riastrad } 106 1.1 riastrad 107 1.1 riastrad return 0; 108 1.1 riastrad } 109 1.1 riastrad 110 1.3 riastrad int i915_restore_state(struct drm_i915_private *dev_priv) 111 1.1 riastrad { 112 1.3 riastrad struct pci_dev *pdev = dev_priv->drm.pdev; 113 1.1 riastrad int i; 114 1.1 riastrad 115 1.3 riastrad if (IS_GEN(dev_priv, 4)) 116 1.3 riastrad pci_write_config_word(pdev, GCDGMBUS, 117 1.2 riastrad dev_priv->regfile.saveGCDGMBUS); 118 1.3 riastrad i915_restore_display(dev_priv); 119 1.1 riastrad 120 1.1 riastrad /* Cache mode state */ 121 1.3 riastrad if (INTEL_GEN(dev_priv) < 7) 122 1.2 riastrad I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 123 1.2 riastrad 0xffff0000); 124 1.1 riastrad 125 1.1 riastrad /* Memory arbitration state */ 126 1.1 riastrad I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); 127 1.1 riastrad 128 1.2 riastrad /* Scratch space */ 129 1.3 riastrad if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { 130 1.2 riastrad for (i = 0; i < 7; i++) { 131 1.2 riastrad I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); 132 1.2 riastrad I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 133 1.2 riastrad } 134 1.2 riastrad for (i = 0; i < 3; i++) 135 1.2 riastrad I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); 136 1.3 riastrad } else if (IS_GEN(dev_priv, 2)) { 137 1.2 riastrad for (i = 0; i < 7; i++) 138 1.2 riastrad I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 139 1.3 riastrad } else if (HAS_GMCH(dev_priv)) { 140 1.2 riastrad for (i = 0; i < 16; i++) { 141 1.2 riastrad I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); 142 1.2 riastrad I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 143 1.2 riastrad } 144 1.2 riastrad for (i = 0; i < 3; i++) 145 1.2 riastrad I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); 146 1.1 riastrad } 147 1.1 riastrad 148 1.3 riastrad intel_gmbus_reset(dev_priv); 149 1.1 riastrad 150 1.1 riastrad return 0; 151 1.1 riastrad } 152