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i915_vgpu.h revision 1.1 
      1 /*	$NetBSD: i915_vgpu.h,v 1.1 2018/08/27 01:34:54 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  */
     25 
     26 #ifndef _I915_VGPU_H_
     27 #define _I915_VGPU_H_
     28 
     29 /* The MMIO offset of the shared info between guest and host emulator */
     30 #define VGT_PVINFO_PAGE	0x78000
     31 #define VGT_PVINFO_SIZE	0x1000
     32 
     33 /*
     34  * The following structure pages are defined in GEN MMIO space
     35  * for virtualization. (One page for now)
     36  */
     37 #define VGT_MAGIC         0x4776544776544776ULL	/* 'vGTvGTvG' */
     38 #define VGT_VERSION_MAJOR 1
     39 #define VGT_VERSION_MINOR 0
     40 
     41 #define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
     42 #define INTEL_VGT_IF_VERSION \
     43 	INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
     44 
     45 /*
     46  * notifications from guest to vgpu device model
     47  */
     48 enum vgt_g2v_type {
     49 	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
     50 	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
     51 	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
     52 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
     53 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
     54 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
     55 	VGT_G2V_MAX,
     56 };
     57 
     58 struct vgt_if {
     59 	uint64_t magic;		/* VGT_MAGIC */
     60 	uint16_t version_major;
     61 	uint16_t version_minor;
     62 	uint32_t vgt_id;	/* ID of vGT instance */
     63 	uint32_t rsv1[12];	/* pad to offset 0x40 */
     64 	/*
     65 	 *  Data structure to describe the balooning info of resources.
     66 	 *  Each VM can only have one portion of continuous area for now.
     67 	 *  (May support scattered resource in future)
     68 	 *  (starting from offset 0x40)
     69 	 */
     70 	struct {
     71 		/* Aperture register balooning */
     72 		struct {
     73 			uint32_t base;
     74 			uint32_t size;
     75 		} mappable_gmadr;	/* aperture */
     76 		/* GMADR register balooning */
     77 		struct {
     78 			uint32_t base;
     79 			uint32_t size;
     80 		} nonmappable_gmadr;	/* non aperture */
     81 		/* allowed fence registers */
     82 		uint32_t fence_num;
     83 		uint32_t rsv2[3];
     84 	} avail_rs;		/* available/assigned resource */
     85 	uint32_t rsv3[0x200 - 24];	/* pad to half page */
     86 	/*
     87 	 * The bottom half page is for response from Gfx driver to hypervisor.
     88 	 */
     89 	uint32_t rsv4;
     90 	uint32_t display_ready;	/* ready for display owner switch */
     91 
     92 	uint32_t rsv5[4];
     93 
     94 	uint32_t g2v_notify;
     95 	uint32_t rsv6[7];
     96 
     97 	uint32_t pdp0_lo;
     98 	uint32_t pdp0_hi;
     99 	uint32_t pdp1_lo;
    100 	uint32_t pdp1_hi;
    101 	uint32_t pdp2_lo;
    102 	uint32_t pdp2_hi;
    103 	uint32_t pdp3_lo;
    104 	uint32_t pdp3_hi;
    105 
    106 	uint32_t execlist_context_descriptor_lo;
    107 	uint32_t execlist_context_descriptor_hi;
    108 
    109 	uint32_t  rsv7[0x200 - 24];    /* pad to one page */
    110 } __packed;
    111 
    112 #define vgtif_reg(x) \
    113 	(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
    114 
    115 /* vGPU display status to be used by the host side */
    116 #define VGT_DRV_DISPLAY_NOT_READY 0
    117 #define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
    118 
    119 extern void i915_check_vgpu(struct drm_device *dev);
    120 extern int intel_vgt_balloon(struct drm_device *dev);
    121 extern void intel_vgt_deballoon(void);
    122 
    123 #endif /* _I915_VGPU_H_ */
    124