intel_pm.c revision 1.1.1.1.2.3
1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 25 * 26 */ 27 28 #include <linux/cpufreq.h> 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 #ifndef __NetBSD__ 32 #include "../../../platform/x86/intel_ips.h" 33 #endif 34 #include <linux/module.h> 35 36 #define FORCEWAKE_ACK_TIMEOUT_MS 2 37 38 /* FBC, or Frame Buffer Compression, is a technique employed to compress the 39 * framebuffer contents in-memory, aiming at reducing the required bandwidth 40 * during in-memory transfers and, therefore, reduce the power packet. 41 * 42 * The benefits of FBC are mostly visible with solid backgrounds and 43 * variation-less patterns. 44 * 45 * FBC-related functionality can be enabled by the means of the 46 * i915.i915_enable_fbc parameter 47 */ 48 49 static bool intel_crtc_active(struct drm_crtc *crtc) 50 { 51 /* Be paranoid as we can arrive here with only partial 52 * state retrieved from the hardware during setup. 53 */ 54 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; 55 } 56 57 static void i8xx_disable_fbc(struct drm_device *dev) 58 { 59 struct drm_i915_private *dev_priv = dev->dev_private; 60 u32 fbc_ctl; 61 62 /* Disable compression */ 63 fbc_ctl = I915_READ(FBC_CONTROL); 64 if ((fbc_ctl & FBC_CTL_EN) == 0) 65 return; 66 67 fbc_ctl &= ~FBC_CTL_EN; 68 I915_WRITE(FBC_CONTROL, fbc_ctl); 69 70 /* Wait for compressing bit to clear */ 71 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 72 DRM_DEBUG_KMS("FBC idle timed out\n"); 73 return; 74 } 75 76 DRM_DEBUG_KMS("disabled FBC\n"); 77 } 78 79 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 80 { 81 struct drm_device *dev = crtc->dev; 82 struct drm_i915_private *dev_priv = dev->dev_private; 83 struct drm_framebuffer *fb = crtc->fb; 84 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 85 struct drm_i915_gem_object *obj = intel_fb->obj; 86 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 87 int cfb_pitch; 88 int plane, i; 89 u32 fbc_ctl, fbc_ctl2; 90 91 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; 92 if (fb->pitches[0] < cfb_pitch) 93 cfb_pitch = fb->pitches[0]; 94 95 /* FBC_CTL wants 64B units */ 96 cfb_pitch = (cfb_pitch / 64) - 1; 97 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; 98 99 /* Clear old tags */ 100 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 101 I915_WRITE(FBC_TAG + (i * 4), 0); 102 103 /* Set it up... */ 104 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 105 fbc_ctl2 |= plane; 106 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 107 I915_WRITE(FBC_FENCE_OFF, crtc->y); 108 109 /* enable it... */ 110 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 111 if (IS_I945GM(dev)) 112 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 113 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 114 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 115 fbc_ctl |= obj->fence_reg; 116 I915_WRITE(FBC_CONTROL, fbc_ctl); 117 118 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 119 cfb_pitch, crtc->y, intel_crtc->plane); 120 } 121 122 static bool i8xx_fbc_enabled(struct drm_device *dev) 123 { 124 struct drm_i915_private *dev_priv = dev->dev_private; 125 126 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 127 } 128 129 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 130 { 131 struct drm_device *dev = crtc->dev; 132 struct drm_i915_private *dev_priv = dev->dev_private; 133 struct drm_framebuffer *fb = crtc->fb; 134 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 135 struct drm_i915_gem_object *obj = intel_fb->obj; 136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 137 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 138 unsigned long stall_watermark = 200; 139 u32 dpfc_ctl; 140 141 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 142 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 143 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); 144 145 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 146 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 147 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 148 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 149 150 /* enable it... */ 151 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 152 153 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 154 } 155 156 static void g4x_disable_fbc(struct drm_device *dev) 157 { 158 struct drm_i915_private *dev_priv = dev->dev_private; 159 u32 dpfc_ctl; 160 161 /* Disable compression */ 162 dpfc_ctl = I915_READ(DPFC_CONTROL); 163 if (dpfc_ctl & DPFC_CTL_EN) { 164 dpfc_ctl &= ~DPFC_CTL_EN; 165 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 166 167 DRM_DEBUG_KMS("disabled FBC\n"); 168 } 169 } 170 171 static bool g4x_fbc_enabled(struct drm_device *dev) 172 { 173 struct drm_i915_private *dev_priv = dev->dev_private; 174 175 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 176 } 177 178 static void sandybridge_blit_fbc_update(struct drm_device *dev) 179 { 180 struct drm_i915_private *dev_priv = dev->dev_private; 181 u32 blt_ecoskpd; 182 183 /* Make sure blitter notifies FBC of writes */ 184 gen6_gt_force_wake_get(dev_priv); 185 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 187 GEN6_BLITTER_LOCK_SHIFT; 188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 189 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 191 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 192 GEN6_BLITTER_LOCK_SHIFT); 193 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 194 POSTING_READ(GEN6_BLITTER_ECOSKPD); 195 gen6_gt_force_wake_put(dev_priv); 196 } 197 198 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 199 { 200 struct drm_device *dev = crtc->dev; 201 struct drm_i915_private *dev_priv = dev->dev_private; 202 struct drm_framebuffer *fb = crtc->fb; 203 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 204 struct drm_i915_gem_object *obj = intel_fb->obj; 205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 206 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 207 unsigned long stall_watermark = 200; 208 u32 dpfc_ctl; 209 210 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 211 dpfc_ctl &= DPFC_RESERVED; 212 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 213 /* Set persistent mode for front-buffer rendering, ala X. */ 214 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 215 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 216 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 217 218 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 219 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 220 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 221 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 222 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 223 /* enable it... */ 224 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 225 226 if (IS_GEN6(dev)) { 227 I915_WRITE(SNB_DPFC_CTL_SA, 228 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 229 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 230 sandybridge_blit_fbc_update(dev); 231 } 232 233 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 234 } 235 236 static void ironlake_disable_fbc(struct drm_device *dev) 237 { 238 struct drm_i915_private *dev_priv = dev->dev_private; 239 u32 dpfc_ctl; 240 241 /* Disable compression */ 242 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 243 if (dpfc_ctl & DPFC_CTL_EN) { 244 dpfc_ctl &= ~DPFC_CTL_EN; 245 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 246 247 DRM_DEBUG_KMS("disabled FBC\n"); 248 } 249 } 250 251 static bool ironlake_fbc_enabled(struct drm_device *dev) 252 { 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 255 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 256 } 257 258 bool intel_fbc_enabled(struct drm_device *dev) 259 { 260 struct drm_i915_private *dev_priv = dev->dev_private; 261 262 if (!dev_priv->display.fbc_enabled) 263 return false; 264 265 return dev_priv->display.fbc_enabled(dev); 266 } 267 268 static void intel_fbc_work_fn(struct work_struct *__work) 269 { 270 struct intel_fbc_work *work = 271 container_of(to_delayed_work(__work), 272 struct intel_fbc_work, work); 273 struct drm_device *dev = work->crtc->dev; 274 struct drm_i915_private *dev_priv = dev->dev_private; 275 276 mutex_lock(&dev->struct_mutex); 277 if (work == dev_priv->fbc_work) { 278 /* Double check that we haven't switched fb without cancelling 279 * the prior work. 280 */ 281 if (work->crtc->fb == work->fb) { 282 dev_priv->display.enable_fbc(work->crtc, 283 work->interval); 284 285 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; 286 dev_priv->cfb_fb = work->crtc->fb->base.id; 287 dev_priv->cfb_y = work->crtc->y; 288 } 289 290 dev_priv->fbc_work = NULL; 291 } 292 mutex_unlock(&dev->struct_mutex); 293 294 kfree(work); 295 } 296 297 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 298 { 299 if (dev_priv->fbc_work == NULL) 300 return; 301 302 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 303 304 /* Synchronisation is provided by struct_mutex and checking of 305 * dev_priv->fbc_work, so we can perform the cancellation 306 * entirely asynchronously. 307 */ 308 if (cancel_delayed_work(&dev_priv->fbc_work->work)) 309 /* tasklet was killed before being run, clean up */ 310 kfree(dev_priv->fbc_work); 311 312 /* Mark the work as no longer wanted so that if it does 313 * wake-up (because the work was already running and waiting 314 * for our mutex), it will discover that is no longer 315 * necessary to run. 316 */ 317 dev_priv->fbc_work = NULL; 318 } 319 320 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 321 { 322 struct intel_fbc_work *work; 323 struct drm_device *dev = crtc->dev; 324 struct drm_i915_private *dev_priv = dev->dev_private; 325 326 if (!dev_priv->display.enable_fbc) 327 return; 328 329 intel_cancel_fbc_work(dev_priv); 330 331 work = kzalloc(sizeof *work, GFP_KERNEL); 332 if (work == NULL) { 333 dev_priv->display.enable_fbc(crtc, interval); 334 return; 335 } 336 337 work->crtc = crtc; 338 work->fb = crtc->fb; 339 work->interval = interval; 340 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 341 342 dev_priv->fbc_work = work; 343 344 DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); 345 346 /* Delay the actual enabling to let pageflipping cease and the 347 * display to settle before starting the compression. Note that 348 * this delay also serves a second purpose: it allows for a 349 * vblank to pass after disabling the FBC before we attempt 350 * to modify the control registers. 351 * 352 * A more complicated solution would involve tracking vblanks 353 * following the termination of the page-flipping sequence 354 * and indeed performing the enable as a co-routine and not 355 * waiting synchronously upon the vblank. 356 */ 357 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 358 } 359 360 void intel_disable_fbc(struct drm_device *dev) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 364 intel_cancel_fbc_work(dev_priv); 365 366 if (!dev_priv->display.disable_fbc) 367 return; 368 369 dev_priv->display.disable_fbc(dev); 370 dev_priv->cfb_plane = -1; 371 } 372 373 /** 374 * intel_update_fbc - enable/disable FBC as needed 375 * @dev: the drm_device 376 * 377 * Set up the framebuffer compression hardware at mode set time. We 378 * enable it if possible: 379 * - plane A only (on pre-965) 380 * - no pixel mulitply/line duplication 381 * - no alpha buffer discard 382 * - no dual wide 383 * - framebuffer <= 2048 in width, 1536 in height 384 * 385 * We can't assume that any compression will take place (worst case), 386 * so the compressed buffer has to be the same size as the uncompressed 387 * one. It also must reside (along with the line length buffer) in 388 * stolen memory. 389 * 390 * We need to enable/disable FBC on a global basis. 391 */ 392 void intel_update_fbc(struct drm_device *dev) 393 { 394 struct drm_i915_private *dev_priv = dev->dev_private; 395 struct drm_crtc *crtc = NULL, *tmp_crtc; 396 struct intel_crtc *intel_crtc; 397 struct drm_framebuffer *fb; 398 struct intel_framebuffer *intel_fb; 399 struct drm_i915_gem_object *obj; 400 int enable_fbc; 401 402 if (!i915_powersave) 403 return; 404 405 if (!I915_HAS_FBC(dev)) 406 return; 407 408 /* 409 * If FBC is already on, we just have to verify that we can 410 * keep it that way... 411 * Need to disable if: 412 * - more than one pipe is active 413 * - changing FBC params (stride, fence, mode) 414 * - new fb is too large to fit in compressed buffer 415 * - going to an unsupported config (interlace, pixel multiply, etc.) 416 */ 417 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 418 if (intel_crtc_active(tmp_crtc) && 419 !to_intel_crtc(tmp_crtc)->primary_disabled) { 420 if (crtc) { 421 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 422 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 423 goto out_disable; 424 } 425 crtc = tmp_crtc; 426 } 427 } 428 429 if (!crtc || crtc->fb == NULL) { 430 DRM_DEBUG_KMS("no output, disabling\n"); 431 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; 432 goto out_disable; 433 } 434 435 intel_crtc = to_intel_crtc(crtc); 436 fb = crtc->fb; 437 intel_fb = to_intel_framebuffer(fb); 438 obj = intel_fb->obj; 439 440 enable_fbc = i915_enable_fbc; 441 if (enable_fbc < 0) { 442 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 443 enable_fbc = 1; 444 if (INTEL_INFO(dev)->gen <= 6) 445 enable_fbc = 0; 446 } 447 if (!enable_fbc) { 448 DRM_DEBUG_KMS("fbc disabled per module param\n"); 449 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; 450 goto out_disable; 451 } 452 if (intel_fb->obj->base.size > dev_priv->cfb_size) { 453 DRM_DEBUG_KMS("framebuffer too large, disabling " 454 "compression\n"); 455 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 456 goto out_disable; 457 } 458 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || 459 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { 460 DRM_DEBUG_KMS("mode incompatible with compression, " 461 "disabling\n"); 462 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 463 goto out_disable; 464 } 465 if ((crtc->mode.hdisplay > 2048) || 466 (crtc->mode.vdisplay > 1536)) { 467 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 468 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 469 goto out_disable; 470 } 471 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { 472 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 473 dev_priv->no_fbc_reason = FBC_BAD_PLANE; 474 goto out_disable; 475 } 476 477 /* The use of a CPU fence is mandatory in order to detect writes 478 * by the CPU to the scanout and trigger updates to the FBC. 479 */ 480 if (obj->tiling_mode != I915_TILING_X || 481 obj->fence_reg == I915_FENCE_REG_NONE) { 482 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 483 dev_priv->no_fbc_reason = FBC_NOT_TILED; 484 goto out_disable; 485 } 486 487 /* If the kernel debugger is active, always disable compression */ 488 if (in_dbg_master()) 489 goto out_disable; 490 491 /* If the scanout has not changed, don't modify the FBC settings. 492 * Note that we make the fundamental assumption that the fb->obj 493 * cannot be unpinned (and have its GTT offset and fence revoked) 494 * without first being decoupled from the scanout and FBC disabled. 495 */ 496 if (dev_priv->cfb_plane == intel_crtc->plane && 497 dev_priv->cfb_fb == fb->base.id && 498 dev_priv->cfb_y == crtc->y) 499 return; 500 501 if (intel_fbc_enabled(dev)) { 502 /* We update FBC along two paths, after changing fb/crtc 503 * configuration (modeswitching) and after page-flipping 504 * finishes. For the latter, we know that not only did 505 * we disable the FBC at the start of the page-flip 506 * sequence, but also more than one vblank has passed. 507 * 508 * For the former case of modeswitching, it is possible 509 * to switch between two FBC valid configurations 510 * instantaneously so we do need to disable the FBC 511 * before we can modify its control registers. We also 512 * have to wait for the next vblank for that to take 513 * effect. However, since we delay enabling FBC we can 514 * assume that a vblank has passed since disabling and 515 * that we can safely alter the registers in the deferred 516 * callback. 517 * 518 * In the scenario that we go from a valid to invalid 519 * and then back to valid FBC configuration we have 520 * no strict enforcement that a vblank occurred since 521 * disabling the FBC. However, along all current pipe 522 * disabling paths we do need to wait for a vblank at 523 * some point. And we wait before enabling FBC anyway. 524 */ 525 DRM_DEBUG_KMS("disabling active FBC for update\n"); 526 intel_disable_fbc(dev); 527 } 528 529 intel_enable_fbc(crtc, 500); 530 return; 531 532 out_disable: 533 /* Multiple disables should be harmless */ 534 if (intel_fbc_enabled(dev)) { 535 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 536 intel_disable_fbc(dev); 537 } 538 } 539 540 static void i915_pineview_get_mem_freq(struct drm_device *dev) 541 { 542 drm_i915_private_t *dev_priv = dev->dev_private; 543 u32 tmp; 544 545 tmp = I915_READ(CLKCFG); 546 547 switch (tmp & CLKCFG_FSB_MASK) { 548 case CLKCFG_FSB_533: 549 dev_priv->fsb_freq = 533; /* 133*4 */ 550 break; 551 case CLKCFG_FSB_800: 552 dev_priv->fsb_freq = 800; /* 200*4 */ 553 break; 554 case CLKCFG_FSB_667: 555 dev_priv->fsb_freq = 667; /* 167*4 */ 556 break; 557 case CLKCFG_FSB_400: 558 dev_priv->fsb_freq = 400; /* 100*4 */ 559 break; 560 } 561 562 switch (tmp & CLKCFG_MEM_MASK) { 563 case CLKCFG_MEM_533: 564 dev_priv->mem_freq = 533; 565 break; 566 case CLKCFG_MEM_667: 567 dev_priv->mem_freq = 667; 568 break; 569 case CLKCFG_MEM_800: 570 dev_priv->mem_freq = 800; 571 break; 572 } 573 574 /* detect pineview DDR3 setting */ 575 tmp = I915_READ(CSHRDDR3CTL); 576 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 577 } 578 579 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 580 { 581 drm_i915_private_t *dev_priv = dev->dev_private; 582 u16 ddrpll, csipll; 583 584 ddrpll = I915_READ16(DDRMPLL1); 585 csipll = I915_READ16(CSIPLL0); 586 587 switch (ddrpll & 0xff) { 588 case 0xc: 589 dev_priv->mem_freq = 800; 590 break; 591 case 0x10: 592 dev_priv->mem_freq = 1066; 593 break; 594 case 0x14: 595 dev_priv->mem_freq = 1333; 596 break; 597 case 0x18: 598 dev_priv->mem_freq = 1600; 599 break; 600 default: 601 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 602 ddrpll & 0xff); 603 dev_priv->mem_freq = 0; 604 break; 605 } 606 607 dev_priv->ips.r_t = dev_priv->mem_freq; 608 609 switch (csipll & 0x3ff) { 610 case 0x00c: 611 dev_priv->fsb_freq = 3200; 612 break; 613 case 0x00e: 614 dev_priv->fsb_freq = 3733; 615 break; 616 case 0x010: 617 dev_priv->fsb_freq = 4266; 618 break; 619 case 0x012: 620 dev_priv->fsb_freq = 4800; 621 break; 622 case 0x014: 623 dev_priv->fsb_freq = 5333; 624 break; 625 case 0x016: 626 dev_priv->fsb_freq = 5866; 627 break; 628 case 0x018: 629 dev_priv->fsb_freq = 6400; 630 break; 631 default: 632 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 633 csipll & 0x3ff); 634 dev_priv->fsb_freq = 0; 635 break; 636 } 637 638 if (dev_priv->fsb_freq == 3200) { 639 dev_priv->ips.c_m = 0; 640 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 641 dev_priv->ips.c_m = 1; 642 } else { 643 dev_priv->ips.c_m = 2; 644 } 645 } 646 647 static const struct cxsr_latency cxsr_latency_table[] = { 648 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 649 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 650 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 651 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 652 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 653 654 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 655 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 656 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 657 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 658 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 659 660 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 661 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 662 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 663 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 664 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 665 666 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 667 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 668 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 669 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 670 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 671 672 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 673 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 674 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 675 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 676 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 677 678 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 679 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 680 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 681 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 682 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 683 }; 684 685 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 686 int is_ddr3, 687 int fsb, 688 int mem) 689 { 690 const struct cxsr_latency *latency; 691 int i; 692 693 if (fsb == 0 || mem == 0) 694 return NULL; 695 696 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 697 latency = &cxsr_latency_table[i]; 698 if (is_desktop == latency->is_desktop && 699 is_ddr3 == latency->is_ddr3 && 700 fsb == latency->fsb_freq && mem == latency->mem_freq) 701 return latency; 702 } 703 704 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 705 706 return NULL; 707 } 708 709 static void pineview_disable_cxsr(struct drm_device *dev) 710 { 711 struct drm_i915_private *dev_priv = dev->dev_private; 712 713 /* deactivate cxsr */ 714 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 715 } 716 717 /* 718 * Latency for FIFO fetches is dependent on several factors: 719 * - memory configuration (speed, channels) 720 * - chipset 721 * - current MCH state 722 * It can be fairly high in some situations, so here we assume a fairly 723 * pessimal value. It's a tradeoff between extra memory fetches (if we 724 * set this value too high, the FIFO will fetch frequently to stay full) 725 * and power consumption (set it too low to save power and we might see 726 * FIFO underruns and display "flicker"). 727 * 728 * A value of 5us seems to be a good balance; safe for very low end 729 * platforms but not overly aggressive on lower latency configs. 730 */ 731 static const int latency_ns = 5000; 732 733 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 734 { 735 struct drm_i915_private *dev_priv = dev->dev_private; 736 uint32_t dsparb = I915_READ(DSPARB); 737 int size; 738 739 size = dsparb & 0x7f; 740 if (plane) 741 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 742 743 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 744 plane ? "B" : "A", size); 745 746 return size; 747 } 748 749 static int i85x_get_fifo_size(struct drm_device *dev, int plane) 750 { 751 struct drm_i915_private *dev_priv = dev->dev_private; 752 uint32_t dsparb = I915_READ(DSPARB); 753 int size; 754 755 size = dsparb & 0x1ff; 756 if (plane) 757 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 758 size >>= 1; /* Convert to cachelines */ 759 760 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 761 plane ? "B" : "A", size); 762 763 return size; 764 } 765 766 static int i845_get_fifo_size(struct drm_device *dev, int plane) 767 { 768 struct drm_i915_private *dev_priv = dev->dev_private; 769 uint32_t dsparb = I915_READ(DSPARB); 770 int size; 771 772 size = dsparb & 0x7f; 773 size >>= 2; /* Convert to cachelines */ 774 775 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 776 plane ? "B" : "A", 777 size); 778 779 return size; 780 } 781 782 static int i830_get_fifo_size(struct drm_device *dev, int plane) 783 { 784 struct drm_i915_private *dev_priv = dev->dev_private; 785 uint32_t dsparb = I915_READ(DSPARB); 786 int size; 787 788 size = dsparb & 0x7f; 789 size >>= 1; /* Convert to cachelines */ 790 791 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 792 plane ? "B" : "A", size); 793 794 return size; 795 } 796 797 /* Pineview has different values for various configs */ 798 static const struct intel_watermark_params pineview_display_wm = { 799 PINEVIEW_DISPLAY_FIFO, 800 PINEVIEW_MAX_WM, 801 PINEVIEW_DFT_WM, 802 PINEVIEW_GUARD_WM, 803 PINEVIEW_FIFO_LINE_SIZE 804 }; 805 static const struct intel_watermark_params pineview_display_hplloff_wm = { 806 PINEVIEW_DISPLAY_FIFO, 807 PINEVIEW_MAX_WM, 808 PINEVIEW_DFT_HPLLOFF_WM, 809 PINEVIEW_GUARD_WM, 810 PINEVIEW_FIFO_LINE_SIZE 811 }; 812 static const struct intel_watermark_params pineview_cursor_wm = { 813 PINEVIEW_CURSOR_FIFO, 814 PINEVIEW_CURSOR_MAX_WM, 815 PINEVIEW_CURSOR_DFT_WM, 816 PINEVIEW_CURSOR_GUARD_WM, 817 PINEVIEW_FIFO_LINE_SIZE, 818 }; 819 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 820 PINEVIEW_CURSOR_FIFO, 821 PINEVIEW_CURSOR_MAX_WM, 822 PINEVIEW_CURSOR_DFT_WM, 823 PINEVIEW_CURSOR_GUARD_WM, 824 PINEVIEW_FIFO_LINE_SIZE 825 }; 826 static const struct intel_watermark_params g4x_wm_info = { 827 G4X_FIFO_SIZE, 828 G4X_MAX_WM, 829 G4X_MAX_WM, 830 2, 831 G4X_FIFO_LINE_SIZE, 832 }; 833 static const struct intel_watermark_params g4x_cursor_wm_info = { 834 I965_CURSOR_FIFO, 835 I965_CURSOR_MAX_WM, 836 I965_CURSOR_DFT_WM, 837 2, 838 G4X_FIFO_LINE_SIZE, 839 }; 840 static const struct intel_watermark_params valleyview_wm_info = { 841 VALLEYVIEW_FIFO_SIZE, 842 VALLEYVIEW_MAX_WM, 843 VALLEYVIEW_MAX_WM, 844 2, 845 G4X_FIFO_LINE_SIZE, 846 }; 847 static const struct intel_watermark_params valleyview_cursor_wm_info = { 848 I965_CURSOR_FIFO, 849 VALLEYVIEW_CURSOR_MAX_WM, 850 I965_CURSOR_DFT_WM, 851 2, 852 G4X_FIFO_LINE_SIZE, 853 }; 854 static const struct intel_watermark_params i965_cursor_wm_info = { 855 I965_CURSOR_FIFO, 856 I965_CURSOR_MAX_WM, 857 I965_CURSOR_DFT_WM, 858 2, 859 I915_FIFO_LINE_SIZE, 860 }; 861 static const struct intel_watermark_params i945_wm_info = { 862 I945_FIFO_SIZE, 863 I915_MAX_WM, 864 1, 865 2, 866 I915_FIFO_LINE_SIZE 867 }; 868 static const struct intel_watermark_params i915_wm_info = { 869 I915_FIFO_SIZE, 870 I915_MAX_WM, 871 1, 872 2, 873 I915_FIFO_LINE_SIZE 874 }; 875 static const struct intel_watermark_params i855_wm_info = { 876 I855GM_FIFO_SIZE, 877 I915_MAX_WM, 878 1, 879 2, 880 I830_FIFO_LINE_SIZE 881 }; 882 static const struct intel_watermark_params i830_wm_info = { 883 I830_FIFO_SIZE, 884 I915_MAX_WM, 885 1, 886 2, 887 I830_FIFO_LINE_SIZE 888 }; 889 890 static const struct intel_watermark_params ironlake_display_wm_info = { 891 ILK_DISPLAY_FIFO, 892 ILK_DISPLAY_MAXWM, 893 ILK_DISPLAY_DFTWM, 894 2, 895 ILK_FIFO_LINE_SIZE 896 }; 897 static const struct intel_watermark_params ironlake_cursor_wm_info = { 898 ILK_CURSOR_FIFO, 899 ILK_CURSOR_MAXWM, 900 ILK_CURSOR_DFTWM, 901 2, 902 ILK_FIFO_LINE_SIZE 903 }; 904 static const struct intel_watermark_params ironlake_display_srwm_info = { 905 ILK_DISPLAY_SR_FIFO, 906 ILK_DISPLAY_MAX_SRWM, 907 ILK_DISPLAY_DFT_SRWM, 908 2, 909 ILK_FIFO_LINE_SIZE 910 }; 911 static const struct intel_watermark_params ironlake_cursor_srwm_info = { 912 ILK_CURSOR_SR_FIFO, 913 ILK_CURSOR_MAX_SRWM, 914 ILK_CURSOR_DFT_SRWM, 915 2, 916 ILK_FIFO_LINE_SIZE 917 }; 918 919 static const struct intel_watermark_params sandybridge_display_wm_info = { 920 SNB_DISPLAY_FIFO, 921 SNB_DISPLAY_MAXWM, 922 SNB_DISPLAY_DFTWM, 923 2, 924 SNB_FIFO_LINE_SIZE 925 }; 926 static const struct intel_watermark_params sandybridge_cursor_wm_info = { 927 SNB_CURSOR_FIFO, 928 SNB_CURSOR_MAXWM, 929 SNB_CURSOR_DFTWM, 930 2, 931 SNB_FIFO_LINE_SIZE 932 }; 933 static const struct intel_watermark_params sandybridge_display_srwm_info = { 934 SNB_DISPLAY_SR_FIFO, 935 SNB_DISPLAY_MAX_SRWM, 936 SNB_DISPLAY_DFT_SRWM, 937 2, 938 SNB_FIFO_LINE_SIZE 939 }; 940 static const struct intel_watermark_params sandybridge_cursor_srwm_info = { 941 SNB_CURSOR_SR_FIFO, 942 SNB_CURSOR_MAX_SRWM, 943 SNB_CURSOR_DFT_SRWM, 944 2, 945 SNB_FIFO_LINE_SIZE 946 }; 947 948 949 /** 950 * intel_calculate_wm - calculate watermark level 951 * @clock_in_khz: pixel clock 952 * @wm: chip FIFO params 953 * @pixel_size: display pixel size 954 * @latency_ns: memory latency for the platform 955 * 956 * Calculate the watermark level (the level at which the display plane will 957 * start fetching from memory again). Each chip has a different display 958 * FIFO size and allocation, so the caller needs to figure that out and pass 959 * in the correct intel_watermark_params structure. 960 * 961 * As the pixel clock runs, the FIFO will be drained at a rate that depends 962 * on the pixel size. When it reaches the watermark level, it'll start 963 * fetching FIFO line sized based chunks from memory until the FIFO fills 964 * past the watermark point. If the FIFO drains completely, a FIFO underrun 965 * will occur, and a display engine hang could result. 966 */ 967 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 968 const struct intel_watermark_params *wm, 969 int fifo_size, 970 int pixel_size, 971 unsigned long latency_ns) 972 { 973 long entries_required, wm_size; 974 975 /* 976 * Note: we need to make sure we don't overflow for various clock & 977 * latency values. 978 * clocks go from a few thousand to several hundred thousand. 979 * latency is usually a few thousand 980 */ 981 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 982 1000; 983 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 984 985 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 986 987 wm_size = fifo_size - (entries_required + wm->guard_size); 988 989 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 990 991 /* Don't promote wm_size to unsigned... */ 992 if (wm_size > (long)wm->max_wm) 993 wm_size = wm->max_wm; 994 if (wm_size <= 0) 995 wm_size = wm->default_wm; 996 return wm_size; 997 } 998 999 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 1000 { 1001 struct drm_crtc *crtc, *enabled = NULL; 1002 1003 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1004 if (intel_crtc_active(crtc)) { 1005 if (enabled) 1006 return NULL; 1007 enabled = crtc; 1008 } 1009 } 1010 1011 return enabled; 1012 } 1013 1014 static void pineview_update_wm(struct drm_device *dev) 1015 { 1016 struct drm_i915_private *dev_priv = dev->dev_private; 1017 struct drm_crtc *crtc; 1018 const struct cxsr_latency *latency; 1019 u32 reg; 1020 unsigned long wm; 1021 1022 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 1023 dev_priv->fsb_freq, dev_priv->mem_freq); 1024 if (!latency) { 1025 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 1026 pineview_disable_cxsr(dev); 1027 return; 1028 } 1029 1030 crtc = single_enabled_crtc(dev); 1031 if (crtc) { 1032 int clock = crtc->mode.clock; 1033 int pixel_size = crtc->fb->bits_per_pixel / 8; 1034 1035 /* Display SR */ 1036 wm = intel_calculate_wm(clock, &pineview_display_wm, 1037 pineview_display_wm.fifo_size, 1038 pixel_size, latency->display_sr); 1039 reg = I915_READ(DSPFW1); 1040 reg &= ~DSPFW_SR_MASK; 1041 reg |= wm << DSPFW_SR_SHIFT; 1042 I915_WRITE(DSPFW1, reg); 1043 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1044 1045 /* cursor SR */ 1046 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1047 pineview_display_wm.fifo_size, 1048 pixel_size, latency->cursor_sr); 1049 reg = I915_READ(DSPFW3); 1050 reg &= ~DSPFW_CURSOR_SR_MASK; 1051 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1052 I915_WRITE(DSPFW3, reg); 1053 1054 /* Display HPLL off SR */ 1055 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1056 pineview_display_hplloff_wm.fifo_size, 1057 pixel_size, latency->display_hpll_disable); 1058 reg = I915_READ(DSPFW3); 1059 reg &= ~DSPFW_HPLL_SR_MASK; 1060 reg |= wm & DSPFW_HPLL_SR_MASK; 1061 I915_WRITE(DSPFW3, reg); 1062 1063 /* cursor HPLL off SR */ 1064 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1065 pineview_display_hplloff_wm.fifo_size, 1066 pixel_size, latency->cursor_hpll_disable); 1067 reg = I915_READ(DSPFW3); 1068 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1069 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1070 I915_WRITE(DSPFW3, reg); 1071 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1072 1073 /* activate cxsr */ 1074 I915_WRITE(DSPFW3, 1075 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1076 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1077 } else { 1078 pineview_disable_cxsr(dev); 1079 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1080 } 1081 } 1082 1083 static bool g4x_compute_wm0(struct drm_device *dev, 1084 int plane, 1085 const struct intel_watermark_params *display, 1086 int display_latency_ns, 1087 const struct intel_watermark_params *cursor, 1088 int cursor_latency_ns, 1089 int *plane_wm, 1090 int *cursor_wm) 1091 { 1092 struct drm_crtc *crtc; 1093 int htotal, hdisplay, clock, pixel_size; 1094 int line_time_us, line_count; 1095 int entries, tlb_miss; 1096 1097 crtc = intel_get_crtc_for_plane(dev, plane); 1098 if (!intel_crtc_active(crtc)) { 1099 *cursor_wm = cursor->guard_size; 1100 *plane_wm = display->guard_size; 1101 return false; 1102 } 1103 1104 htotal = crtc->mode.htotal; 1105 hdisplay = crtc->mode.hdisplay; 1106 clock = crtc->mode.clock; 1107 pixel_size = crtc->fb->bits_per_pixel / 8; 1108 1109 /* Use the small buffer method to calculate plane watermark */ 1110 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1111 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1112 if (tlb_miss > 0) 1113 entries += tlb_miss; 1114 entries = DIV_ROUND_UP(entries, display->cacheline_size); 1115 *plane_wm = entries + display->guard_size; 1116 if (*plane_wm > (int)display->max_wm) 1117 *plane_wm = display->max_wm; 1118 1119 /* Use the large buffer method to calculate cursor watermark */ 1120 line_time_us = ((htotal * 1000) / clock); 1121 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1122 entries = line_count * 64 * pixel_size; 1123 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1124 if (tlb_miss > 0) 1125 entries += tlb_miss; 1126 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1127 *cursor_wm = entries + cursor->guard_size; 1128 if (*cursor_wm > (int)cursor->max_wm) 1129 *cursor_wm = (int)cursor->max_wm; 1130 1131 return true; 1132 } 1133 1134 /* 1135 * Check the wm result. 1136 * 1137 * If any calculated watermark values is larger than the maximum value that 1138 * can be programmed into the associated watermark register, that watermark 1139 * must be disabled. 1140 */ 1141 static bool g4x_check_srwm(struct drm_device *dev, 1142 int display_wm, int cursor_wm, 1143 const struct intel_watermark_params *display, 1144 const struct intel_watermark_params *cursor) 1145 { 1146 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1147 display_wm, cursor_wm); 1148 1149 if (display_wm > display->max_wm) { 1150 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1151 display_wm, display->max_wm); 1152 return false; 1153 } 1154 1155 if (cursor_wm > cursor->max_wm) { 1156 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1157 cursor_wm, cursor->max_wm); 1158 return false; 1159 } 1160 1161 if (!(display_wm || cursor_wm)) { 1162 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1163 return false; 1164 } 1165 1166 return true; 1167 } 1168 1169 static bool g4x_compute_srwm(struct drm_device *dev, 1170 int plane, 1171 int latency_ns, 1172 const struct intel_watermark_params *display, 1173 const struct intel_watermark_params *cursor, 1174 int *display_wm, int *cursor_wm) 1175 { 1176 struct drm_crtc *crtc; 1177 int hdisplay, htotal, pixel_size, clock; 1178 unsigned long line_time_us; 1179 int line_count, line_size; 1180 int small, large; 1181 int entries; 1182 1183 if (!latency_ns) { 1184 *display_wm = *cursor_wm = 0; 1185 return false; 1186 } 1187 1188 crtc = intel_get_crtc_for_plane(dev, plane); 1189 hdisplay = crtc->mode.hdisplay; 1190 htotal = crtc->mode.htotal; 1191 clock = crtc->mode.clock; 1192 pixel_size = crtc->fb->bits_per_pixel / 8; 1193 1194 line_time_us = (htotal * 1000) / clock; 1195 line_count = (latency_ns / line_time_us + 1000) / 1000; 1196 line_size = hdisplay * pixel_size; 1197 1198 /* Use the minimum of the small and large buffer method for primary */ 1199 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1200 large = line_count * line_size; 1201 1202 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1203 *display_wm = entries + display->guard_size; 1204 1205 /* calculate the self-refresh watermark for display cursor */ 1206 entries = line_count * pixel_size * 64; 1207 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1208 *cursor_wm = entries + cursor->guard_size; 1209 1210 return g4x_check_srwm(dev, 1211 *display_wm, *cursor_wm, 1212 display, cursor); 1213 } 1214 1215 static bool vlv_compute_drain_latency(struct drm_device *dev, 1216 int plane, 1217 int *plane_prec_mult, 1218 int *plane_dl, 1219 int *cursor_prec_mult, 1220 int *cursor_dl) 1221 { 1222 struct drm_crtc *crtc; 1223 int clock, pixel_size; 1224 int entries; 1225 1226 crtc = intel_get_crtc_for_plane(dev, plane); 1227 if (!intel_crtc_active(crtc)) 1228 return false; 1229 1230 clock = crtc->mode.clock; /* VESA DOT Clock */ 1231 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ 1232 1233 entries = (clock / 1000) * pixel_size; 1234 *plane_prec_mult = (entries > 256) ? 1235 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1236 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * 1237 pixel_size); 1238 1239 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1240 *cursor_prec_mult = (entries > 256) ? 1241 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1242 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); 1243 1244 return true; 1245 } 1246 1247 /* 1248 * Update drain latency registers of memory arbiter 1249 * 1250 * Valleyview SoC has a new memory arbiter and needs drain latency registers 1251 * to be programmed. Each plane has a drain latency multiplier and a drain 1252 * latency value. 1253 */ 1254 1255 static void vlv_update_drain_latency(struct drm_device *dev) 1256 { 1257 struct drm_i915_private *dev_priv = dev->dev_private; 1258 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1259 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1260 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1261 either 16 or 32 */ 1262 1263 /* For plane A, Cursor A */ 1264 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1265 &cursor_prec_mult, &cursora_dl)) { 1266 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1267 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; 1268 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1269 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; 1270 1271 I915_WRITE(VLV_DDL1, cursora_prec | 1272 (cursora_dl << DDL_CURSORA_SHIFT) | 1273 planea_prec | planea_dl); 1274 } 1275 1276 /* For plane B, Cursor B */ 1277 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1278 &cursor_prec_mult, &cursorb_dl)) { 1279 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1280 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; 1281 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1282 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; 1283 1284 I915_WRITE(VLV_DDL2, cursorb_prec | 1285 (cursorb_dl << DDL_CURSORB_SHIFT) | 1286 planeb_prec | planeb_dl); 1287 } 1288 } 1289 1290 #define single_plane_enabled(mask) is_power_of_2(mask) 1291 1292 static void valleyview_update_wm(struct drm_device *dev) 1293 { 1294 static const int sr_latency_ns = 12000; 1295 struct drm_i915_private *dev_priv = dev->dev_private; 1296 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1297 int plane_sr, cursor_sr; 1298 int ignore_plane_sr, ignore_cursor_sr; 1299 unsigned int enabled = 0; 1300 1301 vlv_update_drain_latency(dev); 1302 1303 if (g4x_compute_wm0(dev, 0, 1304 &valleyview_wm_info, latency_ns, 1305 &valleyview_cursor_wm_info, latency_ns, 1306 &planea_wm, &cursora_wm)) 1307 enabled |= 1; 1308 1309 if (g4x_compute_wm0(dev, 1, 1310 &valleyview_wm_info, latency_ns, 1311 &valleyview_cursor_wm_info, latency_ns, 1312 &planeb_wm, &cursorb_wm)) 1313 enabled |= 2; 1314 1315 if (single_plane_enabled(enabled) && 1316 g4x_compute_srwm(dev, ffs(enabled) - 1, 1317 sr_latency_ns, 1318 &valleyview_wm_info, 1319 &valleyview_cursor_wm_info, 1320 &plane_sr, &ignore_cursor_sr) && 1321 g4x_compute_srwm(dev, ffs(enabled) - 1, 1322 2*sr_latency_ns, 1323 &valleyview_wm_info, 1324 &valleyview_cursor_wm_info, 1325 &ignore_plane_sr, &cursor_sr)) { 1326 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1327 } else { 1328 I915_WRITE(FW_BLC_SELF_VLV, 1329 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1330 plane_sr = cursor_sr = 0; 1331 } 1332 1333 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1334 planea_wm, cursora_wm, 1335 planeb_wm, cursorb_wm, 1336 plane_sr, cursor_sr); 1337 1338 I915_WRITE(DSPFW1, 1339 (plane_sr << DSPFW_SR_SHIFT) | 1340 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1341 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1342 planea_wm); 1343 I915_WRITE(DSPFW2, 1344 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1345 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1346 I915_WRITE(DSPFW3, 1347 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | 1348 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1349 } 1350 1351 static void g4x_update_wm(struct drm_device *dev) 1352 { 1353 static const int sr_latency_ns = 12000; 1354 struct drm_i915_private *dev_priv = dev->dev_private; 1355 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1356 int plane_sr, cursor_sr; 1357 unsigned int enabled = 0; 1358 1359 if (g4x_compute_wm0(dev, 0, 1360 &g4x_wm_info, latency_ns, 1361 &g4x_cursor_wm_info, latency_ns, 1362 &planea_wm, &cursora_wm)) 1363 enabled |= 1; 1364 1365 if (g4x_compute_wm0(dev, 1, 1366 &g4x_wm_info, latency_ns, 1367 &g4x_cursor_wm_info, latency_ns, 1368 &planeb_wm, &cursorb_wm)) 1369 enabled |= 2; 1370 1371 if (single_plane_enabled(enabled) && 1372 g4x_compute_srwm(dev, ffs(enabled) - 1, 1373 sr_latency_ns, 1374 &g4x_wm_info, 1375 &g4x_cursor_wm_info, 1376 &plane_sr, &cursor_sr)) { 1377 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1378 } else { 1379 I915_WRITE(FW_BLC_SELF, 1380 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1381 plane_sr = cursor_sr = 0; 1382 } 1383 1384 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1385 planea_wm, cursora_wm, 1386 planeb_wm, cursorb_wm, 1387 plane_sr, cursor_sr); 1388 1389 I915_WRITE(DSPFW1, 1390 (plane_sr << DSPFW_SR_SHIFT) | 1391 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1392 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1393 planea_wm); 1394 I915_WRITE(DSPFW2, 1395 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1396 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1397 /* HPLL off in SR has some issues on G4x... disable it */ 1398 I915_WRITE(DSPFW3, 1399 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1400 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1401 } 1402 1403 static void i965_update_wm(struct drm_device *dev) 1404 { 1405 struct drm_i915_private *dev_priv = dev->dev_private; 1406 struct drm_crtc *crtc; 1407 int srwm = 1; 1408 int cursor_sr = 16; 1409 1410 /* Calc sr entries for one plane configs */ 1411 crtc = single_enabled_crtc(dev); 1412 if (crtc) { 1413 /* self-refresh has much higher latency */ 1414 static const int sr_latency_ns = 12000; 1415 int clock = crtc->mode.clock; 1416 int htotal = crtc->mode.htotal; 1417 int hdisplay = crtc->mode.hdisplay; 1418 int pixel_size = crtc->fb->bits_per_pixel / 8; 1419 unsigned long line_time_us; 1420 int entries; 1421 1422 line_time_us = ((htotal * 1000) / clock); 1423 1424 /* Use ns/us then divide to preserve precision */ 1425 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1426 pixel_size * hdisplay; 1427 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1428 srwm = I965_FIFO_SIZE - entries; 1429 if (srwm < 0) 1430 srwm = 1; 1431 srwm &= 0x1ff; 1432 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1433 entries, srwm); 1434 1435 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1436 pixel_size * 64; 1437 entries = DIV_ROUND_UP(entries, 1438 i965_cursor_wm_info.cacheline_size); 1439 cursor_sr = i965_cursor_wm_info.fifo_size - 1440 (entries + i965_cursor_wm_info.guard_size); 1441 1442 if (cursor_sr > i965_cursor_wm_info.max_wm) 1443 cursor_sr = i965_cursor_wm_info.max_wm; 1444 1445 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1446 "cursor %d\n", srwm, cursor_sr); 1447 1448 if (IS_CRESTLINE(dev)) 1449 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1450 } else { 1451 /* Turn off self refresh if both pipes are enabled */ 1452 if (IS_CRESTLINE(dev)) 1453 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1454 & ~FW_BLC_SELF_EN); 1455 } 1456 1457 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1458 srwm); 1459 1460 /* 965 has limitations... */ 1461 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1462 (8 << 16) | (8 << 8) | (8 << 0)); 1463 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1464 /* update cursor SR watermark */ 1465 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1466 } 1467 1468 static void i9xx_update_wm(struct drm_device *dev) 1469 { 1470 struct drm_i915_private *dev_priv = dev->dev_private; 1471 const struct intel_watermark_params *wm_info; 1472 uint32_t fwater_lo; 1473 uint32_t fwater_hi; 1474 int cwm, srwm = 1; 1475 int fifo_size; 1476 int planea_wm, planeb_wm; 1477 struct drm_crtc *crtc, *enabled = NULL; 1478 1479 if (IS_I945GM(dev)) 1480 wm_info = &i945_wm_info; 1481 else if (!IS_GEN2(dev)) 1482 wm_info = &i915_wm_info; 1483 else 1484 wm_info = &i855_wm_info; 1485 1486 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1487 crtc = intel_get_crtc_for_plane(dev, 0); 1488 if (intel_crtc_active(crtc)) { 1489 int cpp = crtc->fb->bits_per_pixel / 8; 1490 if (IS_GEN2(dev)) 1491 cpp = 4; 1492 1493 planea_wm = intel_calculate_wm(crtc->mode.clock, 1494 wm_info, fifo_size, cpp, 1495 latency_ns); 1496 enabled = crtc; 1497 } else 1498 planea_wm = fifo_size - wm_info->guard_size; 1499 1500 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1501 crtc = intel_get_crtc_for_plane(dev, 1); 1502 if (intel_crtc_active(crtc)) { 1503 int cpp = crtc->fb->bits_per_pixel / 8; 1504 if (IS_GEN2(dev)) 1505 cpp = 4; 1506 1507 planeb_wm = intel_calculate_wm(crtc->mode.clock, 1508 wm_info, fifo_size, cpp, 1509 latency_ns); 1510 if (enabled == NULL) 1511 enabled = crtc; 1512 else 1513 enabled = NULL; 1514 } else 1515 planeb_wm = fifo_size - wm_info->guard_size; 1516 1517 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1518 1519 /* 1520 * Overlay gets an aggressive default since video jitter is bad. 1521 */ 1522 cwm = 2; 1523 1524 /* Play safe and disable self-refresh before adjusting watermarks. */ 1525 if (IS_I945G(dev) || IS_I945GM(dev)) 1526 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1527 else if (IS_I915GM(dev)) 1528 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); 1529 1530 /* Calc sr entries for one plane configs */ 1531 if (HAS_FW_BLC(dev) && enabled) { 1532 /* self-refresh has much higher latency */ 1533 static const int sr_latency_ns = 6000; 1534 int clock = enabled->mode.clock; 1535 int htotal = enabled->mode.htotal; 1536 int hdisplay = enabled->mode.hdisplay; 1537 int pixel_size = enabled->fb->bits_per_pixel / 8; 1538 unsigned long line_time_us; 1539 int entries; 1540 1541 line_time_us = (htotal * 1000) / clock; 1542 1543 /* Use ns/us then divide to preserve precision */ 1544 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1545 pixel_size * hdisplay; 1546 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1547 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1548 srwm = wm_info->fifo_size - entries; 1549 if (srwm < 0) 1550 srwm = 1; 1551 1552 if (IS_I945G(dev) || IS_I945GM(dev)) 1553 I915_WRITE(FW_BLC_SELF, 1554 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1555 else if (IS_I915GM(dev)) 1556 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1557 } 1558 1559 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1560 planea_wm, planeb_wm, cwm, srwm); 1561 1562 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1563 fwater_hi = (cwm & 0x1f); 1564 1565 /* Set request length to 8 cachelines per fetch */ 1566 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1567 fwater_hi = fwater_hi | (1 << 8); 1568 1569 I915_WRITE(FW_BLC, fwater_lo); 1570 I915_WRITE(FW_BLC2, fwater_hi); 1571 1572 if (HAS_FW_BLC(dev)) { 1573 if (enabled) { 1574 if (IS_I945G(dev) || IS_I945GM(dev)) 1575 I915_WRITE(FW_BLC_SELF, 1576 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1577 else if (IS_I915GM(dev)) 1578 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); 1579 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1580 } else 1581 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1582 } 1583 } 1584 1585 static void i830_update_wm(struct drm_device *dev) 1586 { 1587 struct drm_i915_private *dev_priv = dev->dev_private; 1588 struct drm_crtc *crtc; 1589 uint32_t fwater_lo; 1590 int planea_wm; 1591 1592 crtc = single_enabled_crtc(dev); 1593 if (crtc == NULL) 1594 return; 1595 1596 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, 1597 dev_priv->display.get_fifo_size(dev, 0), 1598 4, latency_ns); 1599 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1600 fwater_lo |= (3<<8) | planea_wm; 1601 1602 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1603 1604 I915_WRITE(FW_BLC, fwater_lo); 1605 } 1606 1607 #define ILK_LP0_PLANE_LATENCY 700 1608 #define ILK_LP0_CURSOR_LATENCY 1300 1609 1610 /* 1611 * Check the wm result. 1612 * 1613 * If any calculated watermark values is larger than the maximum value that 1614 * can be programmed into the associated watermark register, that watermark 1615 * must be disabled. 1616 */ 1617 static bool ironlake_check_srwm(struct drm_device *dev, int level, 1618 int fbc_wm, int display_wm, int cursor_wm, 1619 const struct intel_watermark_params *display, 1620 const struct intel_watermark_params *cursor) 1621 { 1622 struct drm_i915_private *dev_priv = dev->dev_private; 1623 1624 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," 1625 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); 1626 1627 if (fbc_wm > SNB_FBC_MAX_SRWM) { 1628 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", 1629 fbc_wm, SNB_FBC_MAX_SRWM, level); 1630 1631 /* fbc has it's own way to disable FBC WM */ 1632 I915_WRITE(DISP_ARB_CTL, 1633 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); 1634 return false; 1635 } 1636 1637 if (display_wm > display->max_wm) { 1638 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", 1639 display_wm, SNB_DISPLAY_MAX_SRWM, level); 1640 return false; 1641 } 1642 1643 if (cursor_wm > cursor->max_wm) { 1644 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", 1645 cursor_wm, SNB_CURSOR_MAX_SRWM, level); 1646 return false; 1647 } 1648 1649 if (!(fbc_wm || display_wm || cursor_wm)) { 1650 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); 1651 return false; 1652 } 1653 1654 return true; 1655 } 1656 1657 /* 1658 * Compute watermark values of WM[1-3], 1659 */ 1660 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, 1661 int latency_ns, 1662 const struct intel_watermark_params *display, 1663 const struct intel_watermark_params *cursor, 1664 int *fbc_wm, int *display_wm, int *cursor_wm) 1665 { 1666 struct drm_crtc *crtc; 1667 unsigned long line_time_us; 1668 int hdisplay, htotal, pixel_size, clock; 1669 int line_count, line_size; 1670 int small, large; 1671 int entries; 1672 1673 if (!latency_ns) { 1674 *fbc_wm = *display_wm = *cursor_wm = 0; 1675 return false; 1676 } 1677 1678 crtc = intel_get_crtc_for_plane(dev, plane); 1679 hdisplay = crtc->mode.hdisplay; 1680 htotal = crtc->mode.htotal; 1681 clock = crtc->mode.clock; 1682 pixel_size = crtc->fb->bits_per_pixel / 8; 1683 1684 line_time_us = (htotal * 1000) / clock; 1685 line_count = (latency_ns / line_time_us + 1000) / 1000; 1686 line_size = hdisplay * pixel_size; 1687 1688 /* Use the minimum of the small and large buffer method for primary */ 1689 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1690 large = line_count * line_size; 1691 1692 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1693 *display_wm = entries + display->guard_size; 1694 1695 /* 1696 * Spec says: 1697 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 1698 */ 1699 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; 1700 1701 /* calculate the self-refresh watermark for display cursor */ 1702 entries = line_count * pixel_size * 64; 1703 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1704 *cursor_wm = entries + cursor->guard_size; 1705 1706 return ironlake_check_srwm(dev, level, 1707 *fbc_wm, *display_wm, *cursor_wm, 1708 display, cursor); 1709 } 1710 1711 static void ironlake_update_wm(struct drm_device *dev) 1712 { 1713 struct drm_i915_private *dev_priv = dev->dev_private; 1714 int fbc_wm, plane_wm, cursor_wm; 1715 unsigned int enabled; 1716 1717 enabled = 0; 1718 if (g4x_compute_wm0(dev, 0, 1719 &ironlake_display_wm_info, 1720 ILK_LP0_PLANE_LATENCY, 1721 &ironlake_cursor_wm_info, 1722 ILK_LP0_CURSOR_LATENCY, 1723 &plane_wm, &cursor_wm)) { 1724 I915_WRITE(WM0_PIPEA_ILK, 1725 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1726 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1727 " plane %d, " "cursor: %d\n", 1728 plane_wm, cursor_wm); 1729 enabled |= 1; 1730 } 1731 1732 if (g4x_compute_wm0(dev, 1, 1733 &ironlake_display_wm_info, 1734 ILK_LP0_PLANE_LATENCY, 1735 &ironlake_cursor_wm_info, 1736 ILK_LP0_CURSOR_LATENCY, 1737 &plane_wm, &cursor_wm)) { 1738 I915_WRITE(WM0_PIPEB_ILK, 1739 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1740 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1741 " plane %d, cursor: %d\n", 1742 plane_wm, cursor_wm); 1743 enabled |= 2; 1744 } 1745 1746 /* 1747 * Calculate and update the self-refresh watermark only when one 1748 * display plane is used. 1749 */ 1750 I915_WRITE(WM3_LP_ILK, 0); 1751 I915_WRITE(WM2_LP_ILK, 0); 1752 I915_WRITE(WM1_LP_ILK, 0); 1753 1754 if (!single_plane_enabled(enabled)) 1755 return; 1756 enabled = ffs(enabled) - 1; 1757 1758 /* WM1 */ 1759 if (!ironlake_compute_srwm(dev, 1, enabled, 1760 ILK_READ_WM1_LATENCY() * 500, 1761 &ironlake_display_srwm_info, 1762 &ironlake_cursor_srwm_info, 1763 &fbc_wm, &plane_wm, &cursor_wm)) 1764 return; 1765 1766 I915_WRITE(WM1_LP_ILK, 1767 WM1_LP_SR_EN | 1768 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1769 (fbc_wm << WM1_LP_FBC_SHIFT) | 1770 (plane_wm << WM1_LP_SR_SHIFT) | 1771 cursor_wm); 1772 1773 /* WM2 */ 1774 if (!ironlake_compute_srwm(dev, 2, enabled, 1775 ILK_READ_WM2_LATENCY() * 500, 1776 &ironlake_display_srwm_info, 1777 &ironlake_cursor_srwm_info, 1778 &fbc_wm, &plane_wm, &cursor_wm)) 1779 return; 1780 1781 I915_WRITE(WM2_LP_ILK, 1782 WM2_LP_EN | 1783 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1784 (fbc_wm << WM1_LP_FBC_SHIFT) | 1785 (plane_wm << WM1_LP_SR_SHIFT) | 1786 cursor_wm); 1787 1788 /* 1789 * WM3 is unsupported on ILK, probably because we don't have latency 1790 * data for that power state 1791 */ 1792 } 1793 1794 static void sandybridge_update_wm(struct drm_device *dev) 1795 { 1796 struct drm_i915_private *dev_priv = dev->dev_private; 1797 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1798 u32 val; 1799 int fbc_wm, plane_wm, cursor_wm; 1800 unsigned int enabled; 1801 1802 enabled = 0; 1803 if (g4x_compute_wm0(dev, 0, 1804 &sandybridge_display_wm_info, latency, 1805 &sandybridge_cursor_wm_info, latency, 1806 &plane_wm, &cursor_wm)) { 1807 val = I915_READ(WM0_PIPEA_ILK); 1808 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1809 I915_WRITE(WM0_PIPEA_ILK, val | 1810 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1811 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1812 " plane %d, " "cursor: %d\n", 1813 plane_wm, cursor_wm); 1814 enabled |= 1; 1815 } 1816 1817 if (g4x_compute_wm0(dev, 1, 1818 &sandybridge_display_wm_info, latency, 1819 &sandybridge_cursor_wm_info, latency, 1820 &plane_wm, &cursor_wm)) { 1821 val = I915_READ(WM0_PIPEB_ILK); 1822 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1823 I915_WRITE(WM0_PIPEB_ILK, val | 1824 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1825 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1826 " plane %d, cursor: %d\n", 1827 plane_wm, cursor_wm); 1828 enabled |= 2; 1829 } 1830 1831 /* 1832 * Calculate and update the self-refresh watermark only when one 1833 * display plane is used. 1834 * 1835 * SNB support 3 levels of watermark. 1836 * 1837 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1838 * and disabled in the descending order 1839 * 1840 */ 1841 I915_WRITE(WM3_LP_ILK, 0); 1842 I915_WRITE(WM2_LP_ILK, 0); 1843 I915_WRITE(WM1_LP_ILK, 0); 1844 1845 if (!single_plane_enabled(enabled) || 1846 dev_priv->sprite_scaling_enabled) 1847 return; 1848 enabled = ffs(enabled) - 1; 1849 1850 /* WM1 */ 1851 if (!ironlake_compute_srwm(dev, 1, enabled, 1852 SNB_READ_WM1_LATENCY() * 500, 1853 &sandybridge_display_srwm_info, 1854 &sandybridge_cursor_srwm_info, 1855 &fbc_wm, &plane_wm, &cursor_wm)) 1856 return; 1857 1858 I915_WRITE(WM1_LP_ILK, 1859 WM1_LP_SR_EN | 1860 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1861 (fbc_wm << WM1_LP_FBC_SHIFT) | 1862 (plane_wm << WM1_LP_SR_SHIFT) | 1863 cursor_wm); 1864 1865 /* WM2 */ 1866 if (!ironlake_compute_srwm(dev, 2, enabled, 1867 SNB_READ_WM2_LATENCY() * 500, 1868 &sandybridge_display_srwm_info, 1869 &sandybridge_cursor_srwm_info, 1870 &fbc_wm, &plane_wm, &cursor_wm)) 1871 return; 1872 1873 I915_WRITE(WM2_LP_ILK, 1874 WM2_LP_EN | 1875 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1876 (fbc_wm << WM1_LP_FBC_SHIFT) | 1877 (plane_wm << WM1_LP_SR_SHIFT) | 1878 cursor_wm); 1879 1880 /* WM3 */ 1881 if (!ironlake_compute_srwm(dev, 3, enabled, 1882 SNB_READ_WM3_LATENCY() * 500, 1883 &sandybridge_display_srwm_info, 1884 &sandybridge_cursor_srwm_info, 1885 &fbc_wm, &plane_wm, &cursor_wm)) 1886 return; 1887 1888 I915_WRITE(WM3_LP_ILK, 1889 WM3_LP_EN | 1890 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1891 (fbc_wm << WM1_LP_FBC_SHIFT) | 1892 (plane_wm << WM1_LP_SR_SHIFT) | 1893 cursor_wm); 1894 } 1895 1896 static void ivybridge_update_wm(struct drm_device *dev) 1897 { 1898 struct drm_i915_private *dev_priv = dev->dev_private; 1899 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1900 u32 val; 1901 int fbc_wm, plane_wm, cursor_wm; 1902 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; 1903 unsigned int enabled; 1904 1905 enabled = 0; 1906 if (g4x_compute_wm0(dev, 0, 1907 &sandybridge_display_wm_info, latency, 1908 &sandybridge_cursor_wm_info, latency, 1909 &plane_wm, &cursor_wm)) { 1910 val = I915_READ(WM0_PIPEA_ILK); 1911 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1912 I915_WRITE(WM0_PIPEA_ILK, val | 1913 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1914 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1915 " plane %d, " "cursor: %d\n", 1916 plane_wm, cursor_wm); 1917 enabled |= 1; 1918 } 1919 1920 if (g4x_compute_wm0(dev, 1, 1921 &sandybridge_display_wm_info, latency, 1922 &sandybridge_cursor_wm_info, latency, 1923 &plane_wm, &cursor_wm)) { 1924 val = I915_READ(WM0_PIPEB_ILK); 1925 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1926 I915_WRITE(WM0_PIPEB_ILK, val | 1927 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1928 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1929 " plane %d, cursor: %d\n", 1930 plane_wm, cursor_wm); 1931 enabled |= 2; 1932 } 1933 1934 if (g4x_compute_wm0(dev, 2, 1935 &sandybridge_display_wm_info, latency, 1936 &sandybridge_cursor_wm_info, latency, 1937 &plane_wm, &cursor_wm)) { 1938 val = I915_READ(WM0_PIPEC_IVB); 1939 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1940 I915_WRITE(WM0_PIPEC_IVB, val | 1941 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1942 DRM_DEBUG_KMS("FIFO watermarks For pipe C -" 1943 " plane %d, cursor: %d\n", 1944 plane_wm, cursor_wm); 1945 enabled |= 3; 1946 } 1947 1948 /* 1949 * Calculate and update the self-refresh watermark only when one 1950 * display plane is used. 1951 * 1952 * SNB support 3 levels of watermark. 1953 * 1954 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1955 * and disabled in the descending order 1956 * 1957 */ 1958 I915_WRITE(WM3_LP_ILK, 0); 1959 I915_WRITE(WM2_LP_ILK, 0); 1960 I915_WRITE(WM1_LP_ILK, 0); 1961 1962 if (!single_plane_enabled(enabled) || 1963 dev_priv->sprite_scaling_enabled) 1964 return; 1965 enabled = ffs(enabled) - 1; 1966 1967 /* WM1 */ 1968 if (!ironlake_compute_srwm(dev, 1, enabled, 1969 SNB_READ_WM1_LATENCY() * 500, 1970 &sandybridge_display_srwm_info, 1971 &sandybridge_cursor_srwm_info, 1972 &fbc_wm, &plane_wm, &cursor_wm)) 1973 return; 1974 1975 I915_WRITE(WM1_LP_ILK, 1976 WM1_LP_SR_EN | 1977 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1978 (fbc_wm << WM1_LP_FBC_SHIFT) | 1979 (plane_wm << WM1_LP_SR_SHIFT) | 1980 cursor_wm); 1981 1982 /* WM2 */ 1983 if (!ironlake_compute_srwm(dev, 2, enabled, 1984 SNB_READ_WM2_LATENCY() * 500, 1985 &sandybridge_display_srwm_info, 1986 &sandybridge_cursor_srwm_info, 1987 &fbc_wm, &plane_wm, &cursor_wm)) 1988 return; 1989 1990 I915_WRITE(WM2_LP_ILK, 1991 WM2_LP_EN | 1992 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1993 (fbc_wm << WM1_LP_FBC_SHIFT) | 1994 (plane_wm << WM1_LP_SR_SHIFT) | 1995 cursor_wm); 1996 1997 /* WM3, note we have to correct the cursor latency */ 1998 if (!ironlake_compute_srwm(dev, 3, enabled, 1999 SNB_READ_WM3_LATENCY() * 500, 2000 &sandybridge_display_srwm_info, 2001 &sandybridge_cursor_srwm_info, 2002 &fbc_wm, &plane_wm, &ignore_cursor_wm) || 2003 !ironlake_compute_srwm(dev, 3, enabled, 2004 2 * SNB_READ_WM3_LATENCY() * 500, 2005 &sandybridge_display_srwm_info, 2006 &sandybridge_cursor_srwm_info, 2007 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) 2008 return; 2009 2010 I915_WRITE(WM3_LP_ILK, 2011 WM3_LP_EN | 2012 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 2013 (fbc_wm << WM1_LP_FBC_SHIFT) | 2014 (plane_wm << WM1_LP_SR_SHIFT) | 2015 cursor_wm); 2016 } 2017 2018 static void 2019 haswell_update_linetime_wm(struct drm_device *dev, int pipe, 2020 struct drm_display_mode *mode) 2021 { 2022 struct drm_i915_private *dev_priv = dev->dev_private; 2023 u32 temp; 2024 2025 temp = I915_READ(PIPE_WM_LINETIME(pipe)); 2026 temp &= ~PIPE_WM_LINETIME_MASK; 2027 2028 /* The WM are computed with base on how long it takes to fill a single 2029 * row at the given clock rate, multiplied by 8. 2030 * */ 2031 temp |= PIPE_WM_LINETIME_TIME( 2032 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); 2033 2034 /* IPS watermarks are only used by pipe A, and are ignored by 2035 * pipes B and C. They are calculated similarly to the common 2036 * linetime values, except that we are using CD clock frequency 2037 * in MHz instead of pixel rate for the division. 2038 * 2039 * This is a placeholder for the IPS watermark calculation code. 2040 */ 2041 2042 I915_WRITE(PIPE_WM_LINETIME(pipe), temp); 2043 } 2044 2045 static bool 2046 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, 2047 uint32_t sprite_width, int pixel_size, 2048 const struct intel_watermark_params *display, 2049 int display_latency_ns, int *sprite_wm) 2050 { 2051 struct drm_crtc *crtc; 2052 int clock; 2053 int entries, tlb_miss; 2054 2055 crtc = intel_get_crtc_for_plane(dev, plane); 2056 if (!intel_crtc_active(crtc)) { 2057 *sprite_wm = display->guard_size; 2058 return false; 2059 } 2060 2061 clock = crtc->mode.clock; 2062 2063 /* Use the small buffer method to calculate the sprite watermark */ 2064 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 2065 tlb_miss = display->fifo_size*display->cacheline_size - 2066 sprite_width * 8; 2067 if (tlb_miss > 0) 2068 entries += tlb_miss; 2069 entries = DIV_ROUND_UP(entries, display->cacheline_size); 2070 *sprite_wm = entries + display->guard_size; 2071 if (*sprite_wm > (int)display->max_wm) 2072 *sprite_wm = display->max_wm; 2073 2074 return true; 2075 } 2076 2077 static bool 2078 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 2079 uint32_t sprite_width, int pixel_size, 2080 const struct intel_watermark_params *display, 2081 int latency_ns, int *sprite_wm) 2082 { 2083 struct drm_crtc *crtc; 2084 unsigned long line_time_us; 2085 int clock; 2086 int line_count, line_size; 2087 int small, large; 2088 int entries; 2089 2090 if (!latency_ns) { 2091 *sprite_wm = 0; 2092 return false; 2093 } 2094 2095 crtc = intel_get_crtc_for_plane(dev, plane); 2096 clock = crtc->mode.clock; 2097 if (!clock) { 2098 *sprite_wm = 0; 2099 return false; 2100 } 2101 2102 line_time_us = (sprite_width * 1000) / clock; 2103 if (!line_time_us) { 2104 *sprite_wm = 0; 2105 return false; 2106 } 2107 2108 line_count = (latency_ns / line_time_us + 1000) / 1000; 2109 line_size = sprite_width * pixel_size; 2110 2111 /* Use the minimum of the small and large buffer method for primary */ 2112 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 2113 large = line_count * line_size; 2114 2115 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 2116 *sprite_wm = entries + display->guard_size; 2117 2118 return *sprite_wm > 0x3ff ? false : true; 2119 } 2120 2121 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 2122 uint32_t sprite_width, int pixel_size) 2123 { 2124 struct drm_i915_private *dev_priv = dev->dev_private; 2125 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 2126 u32 val; 2127 int sprite_wm, reg; 2128 int ret; 2129 2130 switch (pipe) { 2131 case 0: 2132 reg = WM0_PIPEA_ILK; 2133 break; 2134 case 1: 2135 reg = WM0_PIPEB_ILK; 2136 break; 2137 case 2: 2138 reg = WM0_PIPEC_IVB; 2139 break; 2140 default: 2141 return; /* bad pipe */ 2142 } 2143 2144 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, 2145 &sandybridge_display_wm_info, 2146 latency, &sprite_wm); 2147 if (!ret) { 2148 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 2149 pipe); 2150 return; 2151 } 2152 2153 val = I915_READ(reg); 2154 val &= ~WM0_PIPE_SPRITE_MASK; 2155 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 2156 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 2157 2158 2159 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2160 pixel_size, 2161 &sandybridge_display_srwm_info, 2162 SNB_READ_WM1_LATENCY() * 500, 2163 &sprite_wm); 2164 if (!ret) { 2165 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 2166 pipe); 2167 return; 2168 } 2169 I915_WRITE(WM1S_LP_ILK, sprite_wm); 2170 2171 /* Only IVB has two more LP watermarks for sprite */ 2172 if (!IS_IVYBRIDGE(dev)) 2173 return; 2174 2175 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2176 pixel_size, 2177 &sandybridge_display_srwm_info, 2178 SNB_READ_WM2_LATENCY() * 500, 2179 &sprite_wm); 2180 if (!ret) { 2181 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 2182 pipe); 2183 return; 2184 } 2185 I915_WRITE(WM2S_LP_IVB, sprite_wm); 2186 2187 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2188 pixel_size, 2189 &sandybridge_display_srwm_info, 2190 SNB_READ_WM3_LATENCY() * 500, 2191 &sprite_wm); 2192 if (!ret) { 2193 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 2194 pipe); 2195 return; 2196 } 2197 I915_WRITE(WM3S_LP_IVB, sprite_wm); 2198 } 2199 2200 /** 2201 * intel_update_watermarks - update FIFO watermark values based on current modes 2202 * 2203 * Calculate watermark values for the various WM regs based on current mode 2204 * and plane configuration. 2205 * 2206 * There are several cases to deal with here: 2207 * - normal (i.e. non-self-refresh) 2208 * - self-refresh (SR) mode 2209 * - lines are large relative to FIFO size (buffer can hold up to 2) 2210 * - lines are small relative to FIFO size (buffer can hold more than 2 2211 * lines), so need to account for TLB latency 2212 * 2213 * The normal calculation is: 2214 * watermark = dotclock * bytes per pixel * latency 2215 * where latency is platform & configuration dependent (we assume pessimal 2216 * values here). 2217 * 2218 * The SR calculation is: 2219 * watermark = (trunc(latency/line time)+1) * surface width * 2220 * bytes per pixel 2221 * where 2222 * line time = htotal / dotclock 2223 * surface width = hdisplay for normal plane and 64 for cursor 2224 * and latency is assumed to be high, as above. 2225 * 2226 * The final value programmed to the register should always be rounded up, 2227 * and include an extra 2 entries to account for clock crossings. 2228 * 2229 * We don't use the sprite, so we can ignore that. And on Crestline we have 2230 * to set the non-SR watermarks to 8. 2231 */ 2232 void intel_update_watermarks(struct drm_device *dev) 2233 { 2234 struct drm_i915_private *dev_priv = dev->dev_private; 2235 2236 if (dev_priv->display.update_wm) 2237 dev_priv->display.update_wm(dev); 2238 } 2239 2240 void intel_update_linetime_watermarks(struct drm_device *dev, 2241 int pipe, struct drm_display_mode *mode) 2242 { 2243 struct drm_i915_private *dev_priv = dev->dev_private; 2244 2245 if (dev_priv->display.update_linetime_wm) 2246 dev_priv->display.update_linetime_wm(dev, pipe, mode); 2247 } 2248 2249 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 2250 uint32_t sprite_width, int pixel_size) 2251 { 2252 struct drm_i915_private *dev_priv = dev->dev_private; 2253 2254 if (dev_priv->display.update_sprite_wm) 2255 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, 2256 pixel_size); 2257 } 2258 2259 static struct drm_i915_gem_object * 2260 intel_alloc_context_page(struct drm_device *dev) 2261 { 2262 struct drm_i915_gem_object *ctx; 2263 int ret; 2264 2265 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2266 2267 ctx = i915_gem_alloc_object(dev, 4096); 2268 if (!ctx) { 2269 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 2270 return NULL; 2271 } 2272 2273 ret = i915_gem_object_pin(ctx, 4096, true, false); 2274 if (ret) { 2275 DRM_ERROR("failed to pin power context: %d\n", ret); 2276 goto err_unref; 2277 } 2278 2279 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 2280 if (ret) { 2281 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 2282 goto err_unpin; 2283 } 2284 2285 return ctx; 2286 2287 err_unpin: 2288 i915_gem_object_unpin(ctx); 2289 err_unref: 2290 drm_gem_object_unreference(&ctx->base); 2291 mutex_unlock(&dev->struct_mutex); 2292 return NULL; 2293 } 2294 2295 /** 2296 * Lock protecting IPS related data structures 2297 */ 2298 DEFINE_SPINLOCK(mchdev_lock); 2299 2300 /* Global for IPS driver to get at the current i915 device. Protected by 2301 * mchdev_lock. */ 2302 static struct drm_i915_private *i915_mch_dev; 2303 2304 bool ironlake_set_drps(struct drm_device *dev, u8 val) 2305 { 2306 struct drm_i915_private *dev_priv = dev->dev_private; 2307 u16 rgvswctl; 2308 2309 assert_spin_locked(&mchdev_lock); 2310 2311 rgvswctl = I915_READ16(MEMSWCTL); 2312 if (rgvswctl & MEMCTL_CMD_STS) { 2313 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2314 return false; /* still busy with another command */ 2315 } 2316 2317 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2318 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2319 I915_WRITE16(MEMSWCTL, rgvswctl); 2320 POSTING_READ16(MEMSWCTL); 2321 2322 rgvswctl |= MEMCTL_CMD_STS; 2323 I915_WRITE16(MEMSWCTL, rgvswctl); 2324 2325 return true; 2326 } 2327 2328 static void ironlake_enable_drps(struct drm_device *dev) 2329 { 2330 struct drm_i915_private *dev_priv = dev->dev_private; 2331 u32 rgvmodectl = I915_READ(MEMMODECTL); 2332 u8 fmax, fmin, fstart, vstart; 2333 2334 spin_lock_irq(&mchdev_lock); 2335 2336 /* Enable temp reporting */ 2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2339 2340 /* 100ms RC evaluation intervals */ 2341 I915_WRITE(RCUPEI, 100000); 2342 I915_WRITE(RCDNEI, 100000); 2343 2344 /* Set max/min thresholds to 90ms and 80ms respectively */ 2345 I915_WRITE(RCBMAXAVG, 90000); 2346 I915_WRITE(RCBMINAVG, 80000); 2347 2348 I915_WRITE(MEMIHYST, 1); 2349 2350 /* Set up min, max, and cur for interrupt handling */ 2351 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2352 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2353 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2354 MEMMODE_FSTART_SHIFT; 2355 2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2357 PXVFREQ_PX_SHIFT; 2358 2359 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 2360 dev_priv->ips.fstart = fstart; 2361 2362 dev_priv->ips.max_delay = fstart; 2363 dev_priv->ips.min_delay = fmin; 2364 dev_priv->ips.cur_delay = fstart; 2365 2366 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 2367 fmax, fmin, fstart); 2368 2369 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2370 2371 /* 2372 * Interrupts will be enabled in ironlake_irq_postinstall 2373 */ 2374 2375 I915_WRITE(VIDSTART, vstart); 2376 POSTING_READ(VIDSTART); 2377 2378 rgvmodectl |= MEMMODE_SWMODE_EN; 2379 I915_WRITE(MEMMODECTL, rgvmodectl); 2380 2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 2382 DRM_ERROR("stuck trying to change perf mode\n"); 2383 mdelay(1); 2384 2385 ironlake_set_drps(dev, fstart); 2386 2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2388 I915_READ(0x112e0); 2389 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 2390 dev_priv->ips.last_count2 = I915_READ(0x112f4); 2391 getrawmonotonic(&dev_priv->ips.last_time2); 2392 2393 spin_unlock_irq(&mchdev_lock); 2394 } 2395 2396 static void ironlake_disable_drps(struct drm_device *dev) 2397 { 2398 struct drm_i915_private *dev_priv = dev->dev_private; 2399 u16 rgvswctl; 2400 2401 spin_lock_irq(&mchdev_lock); 2402 2403 rgvswctl = I915_READ16(MEMSWCTL); 2404 2405 /* Ack interrupts, disable EFC interrupt */ 2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2407 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2409 I915_WRITE(DEIIR, DE_PCU_EVENT); 2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2411 2412 /* Go back to the starting frequency */ 2413 ironlake_set_drps(dev, dev_priv->ips.fstart); 2414 mdelay(1); 2415 rgvswctl |= MEMCTL_CMD_STS; 2416 I915_WRITE(MEMSWCTL, rgvswctl); 2417 mdelay(1); 2418 2419 spin_unlock_irq(&mchdev_lock); 2420 } 2421 2422 /* There's a funny hw issue where the hw returns all 0 when reading from 2423 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 2424 * ourselves, instead of doing a rmw cycle (which might result in us clearing 2425 * all limits and the gpu stuck at whatever frequency it is at atm). 2426 */ 2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) 2428 { 2429 u32 limits; 2430 2431 limits = 0; 2432 2433 if (*val >= dev_priv->rps.max_delay) 2434 *val = dev_priv->rps.max_delay; 2435 limits |= dev_priv->rps.max_delay << 24; 2436 2437 /* Only set the down limit when we've reached the lowest level to avoid 2438 * getting more interrupts, otherwise leave this clear. This prevents a 2439 * race in the hw when coming out of rc6: There's a tiny window where 2440 * the hw runs at the minimal clock before selecting the desired 2441 * frequency, if the down threshold expires in that window we will not 2442 * receive a down interrupt. */ 2443 if (*val <= dev_priv->rps.min_delay) { 2444 *val = dev_priv->rps.min_delay; 2445 limits |= dev_priv->rps.min_delay << 16; 2446 } 2447 2448 return limits; 2449 } 2450 2451 void gen6_set_rps(struct drm_device *dev, u8 val) 2452 { 2453 struct drm_i915_private *dev_priv = dev->dev_private; 2454 u32 limits = gen6_rps_limits(dev_priv, &val); 2455 2456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2457 WARN_ON(val > dev_priv->rps.max_delay); 2458 WARN_ON(val < dev_priv->rps.min_delay); 2459 2460 if (val == dev_priv->rps.cur_delay) 2461 return; 2462 2463 I915_WRITE(GEN6_RPNSWREQ, 2464 GEN6_FREQUENCY(val) | 2465 GEN6_OFFSET(0) | 2466 GEN6_AGGRESSIVE_TURBO); 2467 2468 /* Make sure we continue to get interrupts 2469 * until we hit the minimum or maximum frequencies. 2470 */ 2471 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); 2472 2473 POSTING_READ(GEN6_RPNSWREQ); 2474 2475 dev_priv->rps.cur_delay = val; 2476 2477 trace_intel_gpu_freq_change(val * 50); 2478 } 2479 2480 static void gen6_disable_rps(struct drm_device *dev) 2481 { 2482 struct drm_i915_private *dev_priv = dev->dev_private; 2483 2484 I915_WRITE(GEN6_RC_CONTROL, 0); 2485 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 2486 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 2487 I915_WRITE(GEN6_PMIER, 0); 2488 /* Complete PM interrupt masking here doesn't race with the rps work 2489 * item again unmasking PM interrupts because that is using a different 2490 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 2491 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 2492 2493 spin_lock_irq(&dev_priv->rps.lock); 2494 dev_priv->rps.pm_iir = 0; 2495 spin_unlock_irq(&dev_priv->rps.lock); 2496 2497 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2498 } 2499 2500 int intel_enable_rc6(const struct drm_device *dev) 2501 { 2502 /* Respect the kernel parameter if it is set */ 2503 if (i915_enable_rc6 >= 0) 2504 return i915_enable_rc6; 2505 2506 /* Disable RC6 on Ironlake */ 2507 if (INTEL_INFO(dev)->gen == 5) 2508 return 0; 2509 2510 if (IS_HASWELL(dev)) { 2511 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); 2512 return INTEL_RC6_ENABLE; 2513 } 2514 2515 /* snb/ivb have more than one rc6 state. */ 2516 if (INTEL_INFO(dev)->gen == 6) { 2517 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); 2518 return INTEL_RC6_ENABLE; 2519 } 2520 2521 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); 2522 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 2523 } 2524 2525 static void gen6_enable_rps(struct drm_device *dev) 2526 { 2527 struct drm_i915_private *dev_priv = dev->dev_private; 2528 struct intel_ring_buffer *ring; 2529 u32 rp_state_cap; 2530 u32 gt_perf_status; 2531 u32 rc6vids, pcu_mbox, rc6_mask = 0; 2532 u32 gtfifodbg; 2533 int rc6_mode; 2534 int i, ret; 2535 2536 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2537 2538 /* Here begins a magic sequence of register writes to enable 2539 * auto-downclocking. 2540 * 2541 * Perhaps there might be some value in exposing these to 2542 * userspace... 2543 */ 2544 I915_WRITE(GEN6_RC_STATE, 0); 2545 2546 /* Clear the DBG now so we don't confuse earlier errors */ 2547 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 2548 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 2549 I915_WRITE(GTFIFODBG, gtfifodbg); 2550 } 2551 2552 gen6_gt_force_wake_get(dev_priv); 2553 2554 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 2555 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 2556 2557 /* In units of 100MHz */ 2558 dev_priv->rps.max_delay = rp_state_cap & 0xff; 2559 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; 2560 dev_priv->rps.cur_delay = 0; 2561 2562 /* disable the counters and set deterministic thresholds */ 2563 I915_WRITE(GEN6_RC_CONTROL, 0); 2564 2565 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 2566 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 2567 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 2568 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 2569 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 2570 2571 for_each_ring(ring, dev_priv, i) 2572 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 2573 2574 I915_WRITE(GEN6_RC_SLEEP, 0); 2575 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2576 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2577 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 2578 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2579 2580 /* Check if we are enabling RC6 */ 2581 rc6_mode = intel_enable_rc6(dev_priv->dev); 2582 if (rc6_mode & INTEL_RC6_ENABLE) 2583 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 2584 2585 /* We don't use those on Haswell */ 2586 if (!IS_HASWELL(dev)) { 2587 if (rc6_mode & INTEL_RC6p_ENABLE) 2588 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 2589 2590 if (rc6_mode & INTEL_RC6pp_ENABLE) 2591 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 2592 } 2593 2594 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 2595 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 2596 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 2597 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 2598 2599 I915_WRITE(GEN6_RC_CONTROL, 2600 rc6_mask | 2601 GEN6_RC_CTL_EI_MODE(1) | 2602 GEN6_RC_CTL_HW_ENABLE); 2603 2604 I915_WRITE(GEN6_RPNSWREQ, 2605 GEN6_FREQUENCY(10) | 2606 GEN6_OFFSET(0) | 2607 GEN6_AGGRESSIVE_TURBO); 2608 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2609 GEN6_FREQUENCY(12)); 2610 2611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2612 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2613 dev_priv->rps.max_delay << 24 | 2614 dev_priv->rps.min_delay << 16); 2615 2616 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 2617 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 2618 I915_WRITE(GEN6_RP_UP_EI, 66000); 2619 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 2620 2621 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2622 I915_WRITE(GEN6_RP_CONTROL, 2623 GEN6_RP_MEDIA_TURBO | 2624 GEN6_RP_MEDIA_HW_NORMAL_MODE | 2625 GEN6_RP_MEDIA_IS_GFX | 2626 GEN6_RP_ENABLE | 2627 GEN6_RP_UP_BUSY_AVG | 2628 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); 2629 2630 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 2631 if (!ret) { 2632 pcu_mbox = 0; 2633 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 2634 if (ret && pcu_mbox & (1<<31)) { /* OC supported */ 2635 dev_priv->rps.max_delay = pcu_mbox & 0xff; 2636 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); 2637 } 2638 } else { 2639 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 2640 } 2641 2642 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); 2643 2644 /* requires MSI enabled */ 2645 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); 2646 spin_lock_irq(&dev_priv->rps.lock); 2647 WARN_ON(dev_priv->rps.pm_iir != 0); 2648 I915_WRITE(GEN6_PMIMR, 0); 2649 spin_unlock_irq(&dev_priv->rps.lock); 2650 /* enable all PM interrupts */ 2651 I915_WRITE(GEN6_PMINTRMSK, 0); 2652 2653 rc6vids = 0; 2654 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 2655 if (IS_GEN6(dev) && ret) { 2656 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 2657 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 2658 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 2659 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 2660 rc6vids &= 0xffff00; 2661 rc6vids |= GEN6_ENCODE_RC6_VID(450); 2662 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 2663 if (ret) 2664 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 2665 } 2666 2667 gen6_gt_force_wake_put(dev_priv); 2668 } 2669 2670 static void gen6_update_ring_freq(struct drm_device *dev) 2671 { 2672 struct drm_i915_private *dev_priv = dev->dev_private; 2673 int min_freq = 15; 2674 int gpu_freq; 2675 unsigned int ia_freq, max_ia_freq; 2676 int scaling_factor = 180; 2677 2678 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2679 2680 max_ia_freq = cpufreq_quick_get_max(0); 2681 /* 2682 * Default to measured freq if none found, PCU will ensure we don't go 2683 * over 2684 */ 2685 if (!max_ia_freq) 2686 max_ia_freq = tsc_khz; 2687 2688 /* Convert from kHz to MHz */ 2689 max_ia_freq /= 1000; 2690 2691 /* 2692 * For each potential GPU frequency, load a ring frequency we'd like 2693 * to use for memory access. We do this by specifying the IA frequency 2694 * the PCU should use as a reference to determine the ring frequency. 2695 */ 2696 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 2697 gpu_freq--) { 2698 int diff = dev_priv->rps.max_delay - gpu_freq; 2699 2700 /* 2701 * For GPU frequencies less than 750MHz, just use the lowest 2702 * ring freq. 2703 */ 2704 if (gpu_freq < min_freq) 2705 ia_freq = 800; 2706 else 2707 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 2708 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 2709 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; 2710 2711 sandybridge_pcode_write(dev_priv, 2712 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 2713 ia_freq | gpu_freq); 2714 } 2715 } 2716 2717 void ironlake_teardown_rc6(struct drm_device *dev) 2718 { 2719 struct drm_i915_private *dev_priv = dev->dev_private; 2720 2721 if (dev_priv->ips.renderctx) { 2722 i915_gem_object_unpin(dev_priv->ips.renderctx); 2723 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 2724 dev_priv->ips.renderctx = NULL; 2725 } 2726 2727 if (dev_priv->ips.pwrctx) { 2728 i915_gem_object_unpin(dev_priv->ips.pwrctx); 2729 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 2730 dev_priv->ips.pwrctx = NULL; 2731 } 2732 } 2733 2734 static void ironlake_disable_rc6(struct drm_device *dev) 2735 { 2736 struct drm_i915_private *dev_priv = dev->dev_private; 2737 2738 if (I915_READ(PWRCTXA)) { 2739 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 2740 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 2741 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 2742 50); 2743 2744 I915_WRITE(PWRCTXA, 0); 2745 POSTING_READ(PWRCTXA); 2746 2747 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2748 POSTING_READ(RSTDBYCTL); 2749 } 2750 } 2751 2752 static int ironlake_setup_rc6(struct drm_device *dev) 2753 { 2754 struct drm_i915_private *dev_priv = dev->dev_private; 2755 2756 if (dev_priv->ips.renderctx == NULL) 2757 dev_priv->ips.renderctx = intel_alloc_context_page(dev); 2758 if (!dev_priv->ips.renderctx) 2759 return -ENOMEM; 2760 2761 if (dev_priv->ips.pwrctx == NULL) 2762 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); 2763 if (!dev_priv->ips.pwrctx) { 2764 ironlake_teardown_rc6(dev); 2765 return -ENOMEM; 2766 } 2767 2768 return 0; 2769 } 2770 2771 static void ironlake_enable_rc6(struct drm_device *dev) 2772 { 2773 struct drm_i915_private *dev_priv = dev->dev_private; 2774 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 2775 bool was_interruptible; 2776 int ret; 2777 2778 /* rc6 disabled by default due to repeated reports of hanging during 2779 * boot and resume. 2780 */ 2781 if (!intel_enable_rc6(dev)) 2782 return; 2783 2784 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2785 2786 ret = ironlake_setup_rc6(dev); 2787 if (ret) 2788 return; 2789 2790 was_interruptible = dev_priv->mm.interruptible; 2791 dev_priv->mm.interruptible = false; 2792 2793 /* 2794 * GPU can automatically power down the render unit if given a page 2795 * to save state. 2796 */ 2797 ret = intel_ring_begin(ring, 6); 2798 if (ret) { 2799 ironlake_teardown_rc6(dev); 2800 dev_priv->mm.interruptible = was_interruptible; 2801 return; 2802 } 2803 2804 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 2805 intel_ring_emit(ring, MI_SET_CONTEXT); 2806 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | 2807 MI_MM_SPACE_GTT | 2808 MI_SAVE_EXT_STATE_EN | 2809 MI_RESTORE_EXT_STATE_EN | 2810 MI_RESTORE_INHIBIT); 2811 intel_ring_emit(ring, MI_SUSPEND_FLUSH); 2812 intel_ring_emit(ring, MI_NOOP); 2813 intel_ring_emit(ring, MI_FLUSH); 2814 intel_ring_advance(ring); 2815 2816 /* 2817 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 2818 * does an implicit flush, combined with MI_FLUSH above, it should be 2819 * safe to assume that renderctx is valid 2820 */ 2821 ret = intel_ring_idle(ring); 2822 dev_priv->mm.interruptible = was_interruptible; 2823 if (ret) { 2824 DRM_ERROR("failed to enable ironlake power power savings\n"); 2825 ironlake_teardown_rc6(dev); 2826 return; 2827 } 2828 2829 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); 2830 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2831 } 2832 2833 static unsigned long intel_pxfreq(u32 vidfreq) 2834 { 2835 unsigned long freq; 2836 int div = (vidfreq & 0x3f0000) >> 16; 2837 int post = (vidfreq & 0x3000) >> 12; 2838 int pre = (vidfreq & 0x7); 2839 2840 if (!pre) 2841 return 0; 2842 2843 freq = ((div * 133333) / ((1<<post) * pre)); 2844 2845 return freq; 2846 } 2847 2848 static const struct cparams { 2849 u16 i; 2850 u16 t; 2851 u16 m; 2852 u16 c; 2853 } cparams[] = { 2854 { 1, 1333, 301, 28664 }, 2855 { 1, 1066, 294, 24460 }, 2856 { 1, 800, 294, 25192 }, 2857 { 0, 1333, 276, 27605 }, 2858 { 0, 1066, 276, 27605 }, 2859 { 0, 800, 231, 23784 }, 2860 }; 2861 2862 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 2863 { 2864 u64 total_count, diff, ret; 2865 u32 count1, count2, count3, m = 0, c = 0; 2866 unsigned long now = jiffies_to_msecs(jiffies), diff1; 2867 int i; 2868 2869 assert_spin_locked(&mchdev_lock); 2870 2871 diff1 = now - dev_priv->ips.last_time1; 2872 2873 /* Prevent division-by-zero if we are asking too fast. 2874 * Also, we don't get interesting results if we are polling 2875 * faster than once in 10ms, so just return the saved value 2876 * in such cases. 2877 */ 2878 if (diff1 <= 10) 2879 return dev_priv->ips.chipset_power; 2880 2881 count1 = I915_READ(DMIEC); 2882 count2 = I915_READ(DDREC); 2883 count3 = I915_READ(CSIEC); 2884 2885 total_count = count1 + count2 + count3; 2886 2887 /* FIXME: handle per-counter overflow */ 2888 if (total_count < dev_priv->ips.last_count1) { 2889 diff = ~0UL - dev_priv->ips.last_count1; 2890 diff += total_count; 2891 } else { 2892 diff = total_count - dev_priv->ips.last_count1; 2893 } 2894 2895 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 2896 if (cparams[i].i == dev_priv->ips.c_m && 2897 cparams[i].t == dev_priv->ips.r_t) { 2898 m = cparams[i].m; 2899 c = cparams[i].c; 2900 break; 2901 } 2902 } 2903 2904 diff = div_u64(diff, diff1); 2905 ret = ((m * diff) + c); 2906 ret = div_u64(ret, 10); 2907 2908 dev_priv->ips.last_count1 = total_count; 2909 dev_priv->ips.last_time1 = now; 2910 2911 dev_priv->ips.chipset_power = ret; 2912 2913 return ret; 2914 } 2915 2916 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 2917 { 2918 unsigned long val; 2919 2920 if (dev_priv->info->gen != 5) 2921 return 0; 2922 2923 spin_lock_irq(&mchdev_lock); 2924 2925 val = __i915_chipset_val(dev_priv); 2926 2927 spin_unlock_irq(&mchdev_lock); 2928 2929 return val; 2930 } 2931 2932 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 2933 { 2934 unsigned long m, x, b; 2935 u32 tsfs; 2936 2937 tsfs = I915_READ(TSFS); 2938 2939 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 2940 x = I915_READ8(TR1); 2941 2942 b = tsfs & TSFS_INTR_MASK; 2943 2944 return ((m * x) / 127) - b; 2945 } 2946 2947 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 2948 { 2949 static const struct v_table { 2950 u16 vd; /* in .1 mil */ 2951 u16 vm; /* in .1 mil */ 2952 } v_table[] = { 2953 { 0, 0, }, 2954 { 375, 0, }, 2955 { 500, 0, }, 2956 { 625, 0, }, 2957 { 750, 0, }, 2958 { 875, 0, }, 2959 { 1000, 0, }, 2960 { 1125, 0, }, 2961 { 4125, 3000, }, 2962 { 4125, 3000, }, 2963 { 4125, 3000, }, 2964 { 4125, 3000, }, 2965 { 4125, 3000, }, 2966 { 4125, 3000, }, 2967 { 4125, 3000, }, 2968 { 4125, 3000, }, 2969 { 4125, 3000, }, 2970 { 4125, 3000, }, 2971 { 4125, 3000, }, 2972 { 4125, 3000, }, 2973 { 4125, 3000, }, 2974 { 4125, 3000, }, 2975 { 4125, 3000, }, 2976 { 4125, 3000, }, 2977 { 4125, 3000, }, 2978 { 4125, 3000, }, 2979 { 4125, 3000, }, 2980 { 4125, 3000, }, 2981 { 4125, 3000, }, 2982 { 4125, 3000, }, 2983 { 4125, 3000, }, 2984 { 4125, 3000, }, 2985 { 4250, 3125, }, 2986 { 4375, 3250, }, 2987 { 4500, 3375, }, 2988 { 4625, 3500, }, 2989 { 4750, 3625, }, 2990 { 4875, 3750, }, 2991 { 5000, 3875, }, 2992 { 5125, 4000, }, 2993 { 5250, 4125, }, 2994 { 5375, 4250, }, 2995 { 5500, 4375, }, 2996 { 5625, 4500, }, 2997 { 5750, 4625, }, 2998 { 5875, 4750, }, 2999 { 6000, 4875, }, 3000 { 6125, 5000, }, 3001 { 6250, 5125, }, 3002 { 6375, 5250, }, 3003 { 6500, 5375, }, 3004 { 6625, 5500, }, 3005 { 6750, 5625, }, 3006 { 6875, 5750, }, 3007 { 7000, 5875, }, 3008 { 7125, 6000, }, 3009 { 7250, 6125, }, 3010 { 7375, 6250, }, 3011 { 7500, 6375, }, 3012 { 7625, 6500, }, 3013 { 7750, 6625, }, 3014 { 7875, 6750, }, 3015 { 8000, 6875, }, 3016 { 8125, 7000, }, 3017 { 8250, 7125, }, 3018 { 8375, 7250, }, 3019 { 8500, 7375, }, 3020 { 8625, 7500, }, 3021 { 8750, 7625, }, 3022 { 8875, 7750, }, 3023 { 9000, 7875, }, 3024 { 9125, 8000, }, 3025 { 9250, 8125, }, 3026 { 9375, 8250, }, 3027 { 9500, 8375, }, 3028 { 9625, 8500, }, 3029 { 9750, 8625, }, 3030 { 9875, 8750, }, 3031 { 10000, 8875, }, 3032 { 10125, 9000, }, 3033 { 10250, 9125, }, 3034 { 10375, 9250, }, 3035 { 10500, 9375, }, 3036 { 10625, 9500, }, 3037 { 10750, 9625, }, 3038 { 10875, 9750, }, 3039 { 11000, 9875, }, 3040 { 11125, 10000, }, 3041 { 11250, 10125, }, 3042 { 11375, 10250, }, 3043 { 11500, 10375, }, 3044 { 11625, 10500, }, 3045 { 11750, 10625, }, 3046 { 11875, 10750, }, 3047 { 12000, 10875, }, 3048 { 12125, 11000, }, 3049 { 12250, 11125, }, 3050 { 12375, 11250, }, 3051 { 12500, 11375, }, 3052 { 12625, 11500, }, 3053 { 12750, 11625, }, 3054 { 12875, 11750, }, 3055 { 13000, 11875, }, 3056 { 13125, 12000, }, 3057 { 13250, 12125, }, 3058 { 13375, 12250, }, 3059 { 13500, 12375, }, 3060 { 13625, 12500, }, 3061 { 13750, 12625, }, 3062 { 13875, 12750, }, 3063 { 14000, 12875, }, 3064 { 14125, 13000, }, 3065 { 14250, 13125, }, 3066 { 14375, 13250, }, 3067 { 14500, 13375, }, 3068 { 14625, 13500, }, 3069 { 14750, 13625, }, 3070 { 14875, 13750, }, 3071 { 15000, 13875, }, 3072 { 15125, 14000, }, 3073 { 15250, 14125, }, 3074 { 15375, 14250, }, 3075 { 15500, 14375, }, 3076 { 15625, 14500, }, 3077 { 15750, 14625, }, 3078 { 15875, 14750, }, 3079 { 16000, 14875, }, 3080 { 16125, 15000, }, 3081 }; 3082 if (dev_priv->info->is_mobile) 3083 return v_table[pxvid].vm; 3084 else 3085 return v_table[pxvid].vd; 3086 } 3087 3088 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 3089 { 3090 struct timespec now, diff1; 3091 u64 diff; 3092 unsigned long diffms; 3093 u32 count; 3094 3095 assert_spin_locked(&mchdev_lock); 3096 3097 getrawmonotonic(&now); 3098 diff1 = timespec_sub(now, dev_priv->ips.last_time2); 3099 3100 /* Don't divide by 0 */ 3101 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 3102 if (!diffms) 3103 return; 3104 3105 count = I915_READ(GFXEC); 3106 3107 if (count < dev_priv->ips.last_count2) { 3108 diff = ~0UL - dev_priv->ips.last_count2; 3109 diff += count; 3110 } else { 3111 diff = count - dev_priv->ips.last_count2; 3112 } 3113 3114 dev_priv->ips.last_count2 = count; 3115 dev_priv->ips.last_time2 = now; 3116 3117 /* More magic constants... */ 3118 diff = diff * 1181; 3119 diff = div_u64(diff, diffms * 10); 3120 dev_priv->ips.gfx_power = diff; 3121 } 3122 3123 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 3124 { 3125 if (dev_priv->info->gen != 5) 3126 return; 3127 3128 spin_lock_irq(&mchdev_lock); 3129 3130 __i915_update_gfx_val(dev_priv); 3131 3132 spin_unlock_irq(&mchdev_lock); 3133 } 3134 3135 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 3136 { 3137 unsigned long t, corr, state1, corr2, state2; 3138 u32 pxvid, ext_v; 3139 3140 assert_spin_locked(&mchdev_lock); 3141 3142 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 3143 pxvid = (pxvid >> 24) & 0x7f; 3144 ext_v = pvid_to_extvid(dev_priv, pxvid); 3145 3146 state1 = ext_v; 3147 3148 t = i915_mch_val(dev_priv); 3149 3150 /* Revel in the empirically derived constants */ 3151 3152 /* Correction factor in 1/100000 units */ 3153 if (t > 80) 3154 corr = ((t * 2349) + 135940); 3155 else if (t >= 50) 3156 corr = ((t * 964) + 29317); 3157 else /* < 50 */ 3158 corr = ((t * 301) + 1004); 3159 3160 corr = corr * ((150142 * state1) / 10000 - 78642); 3161 corr /= 100000; 3162 corr2 = (corr * dev_priv->ips.corr); 3163 3164 state2 = (corr2 * state1) / 10000; 3165 state2 /= 100; /* convert to mW */ 3166 3167 __i915_update_gfx_val(dev_priv); 3168 3169 return dev_priv->ips.gfx_power + state2; 3170 } 3171 3172 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 3173 { 3174 unsigned long val; 3175 3176 if (dev_priv->info->gen != 5) 3177 return 0; 3178 3179 spin_lock_irq(&mchdev_lock); 3180 3181 val = __i915_gfx_val(dev_priv); 3182 3183 spin_unlock_irq(&mchdev_lock); 3184 3185 return val; 3186 } 3187 3188 /** 3189 * i915_read_mch_val - return value for IPS use 3190 * 3191 * Calculate and return a value for the IPS driver to use when deciding whether 3192 * we have thermal and power headroom to increase CPU or GPU power budget. 3193 */ 3194 unsigned long i915_read_mch_val(void) 3195 { 3196 struct drm_i915_private *dev_priv; 3197 unsigned long chipset_val, graphics_val, ret = 0; 3198 3199 spin_lock_irq(&mchdev_lock); 3200 if (!i915_mch_dev) 3201 goto out_unlock; 3202 dev_priv = i915_mch_dev; 3203 3204 chipset_val = __i915_chipset_val(dev_priv); 3205 graphics_val = __i915_gfx_val(dev_priv); 3206 3207 ret = chipset_val + graphics_val; 3208 3209 out_unlock: 3210 spin_unlock_irq(&mchdev_lock); 3211 3212 return ret; 3213 } 3214 EXPORT_SYMBOL_GPL(i915_read_mch_val); 3215 3216 /** 3217 * i915_gpu_raise - raise GPU frequency limit 3218 * 3219 * Raise the limit; IPS indicates we have thermal headroom. 3220 */ 3221 bool i915_gpu_raise(void) 3222 { 3223 struct drm_i915_private *dev_priv; 3224 bool ret = true; 3225 3226 spin_lock_irq(&mchdev_lock); 3227 if (!i915_mch_dev) { 3228 ret = false; 3229 goto out_unlock; 3230 } 3231 dev_priv = i915_mch_dev; 3232 3233 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 3234 dev_priv->ips.max_delay--; 3235 3236 out_unlock: 3237 spin_unlock_irq(&mchdev_lock); 3238 3239 return ret; 3240 } 3241 EXPORT_SYMBOL_GPL(i915_gpu_raise); 3242 3243 /** 3244 * i915_gpu_lower - lower GPU frequency limit 3245 * 3246 * IPS indicates we're close to a thermal limit, so throttle back the GPU 3247 * frequency maximum. 3248 */ 3249 bool i915_gpu_lower(void) 3250 { 3251 struct drm_i915_private *dev_priv; 3252 bool ret = true; 3253 3254 spin_lock_irq(&mchdev_lock); 3255 if (!i915_mch_dev) { 3256 ret = false; 3257 goto out_unlock; 3258 } 3259 dev_priv = i915_mch_dev; 3260 3261 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 3262 dev_priv->ips.max_delay++; 3263 3264 out_unlock: 3265 spin_unlock_irq(&mchdev_lock); 3266 3267 return ret; 3268 } 3269 EXPORT_SYMBOL_GPL(i915_gpu_lower); 3270 3271 /** 3272 * i915_gpu_busy - indicate GPU business to IPS 3273 * 3274 * Tell the IPS driver whether or not the GPU is busy. 3275 */ 3276 bool i915_gpu_busy(void) 3277 { 3278 struct drm_i915_private *dev_priv; 3279 struct intel_ring_buffer *ring; 3280 bool ret = false; 3281 int i; 3282 3283 spin_lock_irq(&mchdev_lock); 3284 if (!i915_mch_dev) 3285 goto out_unlock; 3286 dev_priv = i915_mch_dev; 3287 3288 for_each_ring(ring, dev_priv, i) 3289 ret |= !list_empty(&ring->request_list); 3290 3291 out_unlock: 3292 spin_unlock_irq(&mchdev_lock); 3293 3294 return ret; 3295 } 3296 EXPORT_SYMBOL_GPL(i915_gpu_busy); 3297 3298 /** 3299 * i915_gpu_turbo_disable - disable graphics turbo 3300 * 3301 * Disable graphics turbo by resetting the max frequency and setting the 3302 * current frequency to the default. 3303 */ 3304 bool i915_gpu_turbo_disable(void) 3305 { 3306 struct drm_i915_private *dev_priv; 3307 bool ret = true; 3308 3309 spin_lock_irq(&mchdev_lock); 3310 if (!i915_mch_dev) { 3311 ret = false; 3312 goto out_unlock; 3313 } 3314 dev_priv = i915_mch_dev; 3315 3316 dev_priv->ips.max_delay = dev_priv->ips.fstart; 3317 3318 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 3319 ret = false; 3320 3321 out_unlock: 3322 spin_unlock_irq(&mchdev_lock); 3323 3324 return ret; 3325 } 3326 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 3327 3328 /** 3329 * Tells the intel_ips driver that the i915 driver is now loaded, if 3330 * IPS got loaded first. 3331 * 3332 * This awkward dance is so that neither module has to depend on the 3333 * other in order for IPS to do the appropriate communication of 3334 * GPU turbo limits to i915. 3335 */ 3336 static void 3337 ips_ping_for_i915_load(void) 3338 { 3339 #ifndef __NetBSD__ /* XXX whattakludge for Linux module mania */ 3340 void (*link)(void); 3341 3342 link = symbol_get(ips_link_to_i915_driver); 3343 if (link) { 3344 link(); 3345 symbol_put(ips_link_to_i915_driver); 3346 } 3347 #endif 3348 } 3349 3350 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 3351 { 3352 /* We only register the i915 ips part with intel-ips once everything is 3353 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 3354 spin_lock_irq(&mchdev_lock); 3355 i915_mch_dev = dev_priv; 3356 spin_unlock_irq(&mchdev_lock); 3357 3358 ips_ping_for_i915_load(); 3359 } 3360 3361 void intel_gpu_ips_teardown(void) 3362 { 3363 spin_lock_irq(&mchdev_lock); 3364 i915_mch_dev = NULL; 3365 spin_unlock_irq(&mchdev_lock); 3366 } 3367 static void intel_init_emon(struct drm_device *dev) 3368 { 3369 struct drm_i915_private *dev_priv = dev->dev_private; 3370 u32 lcfuse; 3371 u8 pxw[16]; 3372 int i; 3373 3374 /* Disable to program */ 3375 I915_WRITE(ECR, 0); 3376 POSTING_READ(ECR); 3377 3378 /* Program energy weights for various events */ 3379 I915_WRITE(SDEW, 0x15040d00); 3380 I915_WRITE(CSIEW0, 0x007f0000); 3381 I915_WRITE(CSIEW1, 0x1e220004); 3382 I915_WRITE(CSIEW2, 0x04000004); 3383 3384 for (i = 0; i < 5; i++) 3385 I915_WRITE(PEW + (i * 4), 0); 3386 for (i = 0; i < 3; i++) 3387 I915_WRITE(DEW + (i * 4), 0); 3388 3389 /* Program P-state weights to account for frequency power adjustment */ 3390 for (i = 0; i < 16; i++) { 3391 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 3392 unsigned long freq = intel_pxfreq(pxvidfreq); 3393 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 3394 PXVFREQ_PX_SHIFT; 3395 unsigned long val; 3396 3397 val = vid * vid; 3398 val *= (freq / 1000); 3399 val *= 255; 3400 val /= (127*127*900); 3401 if (val > 0xff) 3402 DRM_ERROR("bad pxval: %ld\n", val); 3403 pxw[i] = val; 3404 } 3405 /* Render standby states get 0 weight */ 3406 pxw[14] = 0; 3407 pxw[15] = 0; 3408 3409 for (i = 0; i < 4; i++) { 3410 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 3411 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 3412 I915_WRITE(PXW + (i * 4), val); 3413 } 3414 3415 /* Adjust magic regs to magic values (more experimental results) */ 3416 I915_WRITE(OGW0, 0); 3417 I915_WRITE(OGW1, 0); 3418 I915_WRITE(EG0, 0x00007f00); 3419 I915_WRITE(EG1, 0x0000000e); 3420 I915_WRITE(EG2, 0x000e0000); 3421 I915_WRITE(EG3, 0x68000300); 3422 I915_WRITE(EG4, 0x42000000); 3423 I915_WRITE(EG5, 0x00140031); 3424 I915_WRITE(EG6, 0); 3425 I915_WRITE(EG7, 0); 3426 3427 for (i = 0; i < 8; i++) 3428 I915_WRITE(PXWL + (i * 4), 0); 3429 3430 /* Enable PMON + select events */ 3431 I915_WRITE(ECR, 0x80000019); 3432 3433 lcfuse = I915_READ(LCFUSE02); 3434 3435 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 3436 } 3437 3438 void intel_disable_gt_powersave(struct drm_device *dev) 3439 { 3440 struct drm_i915_private *dev_priv = dev->dev_private; 3441 3442 if (IS_IRONLAKE_M(dev)) { 3443 ironlake_disable_drps(dev); 3444 ironlake_disable_rc6(dev); 3445 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { 3446 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 3447 mutex_lock(&dev_priv->rps.hw_lock); 3448 gen6_disable_rps(dev); 3449 mutex_unlock(&dev_priv->rps.hw_lock); 3450 } 3451 } 3452 3453 static void intel_gen6_powersave_work(struct work_struct *work) 3454 { 3455 struct drm_i915_private *dev_priv = 3456 container_of(work, struct drm_i915_private, 3457 rps.delayed_resume_work.work); 3458 struct drm_device *dev = dev_priv->dev; 3459 3460 mutex_lock(&dev_priv->rps.hw_lock); 3461 gen6_enable_rps(dev); 3462 gen6_update_ring_freq(dev); 3463 mutex_unlock(&dev_priv->rps.hw_lock); 3464 } 3465 3466 void intel_enable_gt_powersave(struct drm_device *dev) 3467 { 3468 struct drm_i915_private *dev_priv = dev->dev_private; 3469 3470 if (IS_IRONLAKE_M(dev)) { 3471 ironlake_enable_drps(dev); 3472 ironlake_enable_rc6(dev); 3473 intel_init_emon(dev); 3474 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { 3475 /* 3476 * PCU communication is slow and this doesn't need to be 3477 * done at any specific time, so do this out of our fast path 3478 * to make resume and init faster. 3479 */ 3480 schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 3481 round_jiffies_up_relative(HZ)); 3482 } 3483 } 3484 3485 static void ibx_init_clock_gating(struct drm_device *dev) 3486 { 3487 struct drm_i915_private *dev_priv = dev->dev_private; 3488 3489 /* 3490 * On Ibex Peak and Cougar Point, we need to disable clock 3491 * gating for the panel power sequencer or it will fail to 3492 * start up when no ports are active. 3493 */ 3494 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3495 } 3496 3497 static void ironlake_init_clock_gating(struct drm_device *dev) 3498 { 3499 struct drm_i915_private *dev_priv = dev->dev_private; 3500 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3501 3502 /* Required for FBC */ 3503 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 3504 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 3505 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 3506 3507 I915_WRITE(PCH_3DCGDIS0, 3508 MARIUNIT_CLOCK_GATE_DISABLE | 3509 SVSMUNIT_CLOCK_GATE_DISABLE); 3510 I915_WRITE(PCH_3DCGDIS1, 3511 VFMUNIT_CLOCK_GATE_DISABLE); 3512 3513 /* 3514 * According to the spec the following bits should be set in 3515 * order to enable memory self-refresh 3516 * The bit 22/21 of 0x42004 3517 * The bit 5 of 0x42020 3518 * The bit 15 of 0x45000 3519 */ 3520 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3521 (I915_READ(ILK_DISPLAY_CHICKEN2) | 3522 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 3523 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 3524 I915_WRITE(DISP_ARB_CTL, 3525 (I915_READ(DISP_ARB_CTL) | 3526 DISP_FBC_WM_DIS)); 3527 I915_WRITE(WM3_LP_ILK, 0); 3528 I915_WRITE(WM2_LP_ILK, 0); 3529 I915_WRITE(WM1_LP_ILK, 0); 3530 3531 /* 3532 * Based on the document from hardware guys the following bits 3533 * should be set unconditionally in order to enable FBC. 3534 * The bit 22 of 0x42000 3535 * The bit 22 of 0x42004 3536 * The bit 7,8,9 of 0x42020. 3537 */ 3538 if (IS_IRONLAKE_M(dev)) { 3539 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3540 I915_READ(ILK_DISPLAY_CHICKEN1) | 3541 ILK_FBCQ_DIS); 3542 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3543 I915_READ(ILK_DISPLAY_CHICKEN2) | 3544 ILK_DPARB_GATE); 3545 } 3546 3547 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3548 3549 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3550 I915_READ(ILK_DISPLAY_CHICKEN2) | 3551 ILK_ELPIN_409_SELECT); 3552 I915_WRITE(_3D_CHICKEN2, 3553 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 3554 _3D_CHICKEN2_WM_READ_PIPELINED); 3555 3556 /* WaDisableRenderCachePipelinedFlush */ 3557 I915_WRITE(CACHE_MODE_0, 3558 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 3559 3560 ibx_init_clock_gating(dev); 3561 } 3562 3563 static void cpt_init_clock_gating(struct drm_device *dev) 3564 { 3565 struct drm_i915_private *dev_priv = dev->dev_private; 3566 int pipe; 3567 3568 /* 3569 * On Ibex Peak and Cougar Point, we need to disable clock 3570 * gating for the panel power sequencer or it will fail to 3571 * start up when no ports are active. 3572 */ 3573 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3574 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 3575 DPLS_EDP_PPS_FIX_DIS); 3576 /* The below fixes the weird display corruption, a few pixels shifted 3577 * downward, on (only) LVDS of some HP laptops with IVY. 3578 */ 3579 for_each_pipe(pipe) 3580 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); 3581 /* WADP0ClockGatingDisable */ 3582 for_each_pipe(pipe) { 3583 I915_WRITE(TRANS_CHICKEN1(pipe), 3584 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 3585 } 3586 } 3587 3588 static void gen6_init_clock_gating(struct drm_device *dev) 3589 { 3590 struct drm_i915_private *dev_priv = dev->dev_private; 3591 int pipe; 3592 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3593 3594 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3595 3596 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3597 I915_READ(ILK_DISPLAY_CHICKEN2) | 3598 ILK_ELPIN_409_SELECT); 3599 3600 /* WaDisableHiZPlanesWhenMSAAEnabled */ 3601 I915_WRITE(_3D_CHICKEN, 3602 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 3603 3604 /* WaSetupGtModeTdRowDispatch */ 3605 if (IS_SNB_GT1(dev)) 3606 I915_WRITE(GEN6_GT_MODE, 3607 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 3608 3609 I915_WRITE(WM3_LP_ILK, 0); 3610 I915_WRITE(WM2_LP_ILK, 0); 3611 I915_WRITE(WM1_LP_ILK, 0); 3612 3613 I915_WRITE(CACHE_MODE_0, 3614 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 3615 3616 I915_WRITE(GEN6_UCGCTL1, 3617 I915_READ(GEN6_UCGCTL1) | 3618 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 3619 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 3620 3621 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3622 * gating disable must be set. Failure to set it results in 3623 * flickering pixels due to Z write ordering failures after 3624 * some amount of runtime in the Mesa "fire" demo, and Unigine 3625 * Sanctuary and Tropics, and apparently anything else with 3626 * alpha test or pixel discard. 3627 * 3628 * According to the spec, bit 11 (RCCUNIT) must also be set, 3629 * but we didn't debug actual testcases to find it out. 3630 * 3631 * Also apply WaDisableVDSUnitClockGating and 3632 * WaDisableRCPBUnitClockGating. 3633 */ 3634 I915_WRITE(GEN6_UCGCTL2, 3635 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3636 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3637 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3638 3639 /* Bspec says we need to always set all mask bits. */ 3640 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 3641 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 3642 3643 /* 3644 * According to the spec the following bits should be 3645 * set in order to enable memory self-refresh and fbc: 3646 * The bit21 and bit22 of 0x42000 3647 * The bit21 and bit22 of 0x42004 3648 * The bit5 and bit7 of 0x42020 3649 * The bit14 of 0x70180 3650 * The bit14 of 0x71180 3651 */ 3652 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3653 I915_READ(ILK_DISPLAY_CHICKEN1) | 3654 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 3655 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3656 I915_READ(ILK_DISPLAY_CHICKEN2) | 3657 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 3658 I915_WRITE(ILK_DSPCLK_GATE_D, 3659 I915_READ(ILK_DSPCLK_GATE_D) | 3660 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 3661 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 3662 3663 /* WaMbcDriverBootEnable */ 3664 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3665 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3666 3667 for_each_pipe(pipe) { 3668 I915_WRITE(DSPCNTR(pipe), 3669 I915_READ(DSPCNTR(pipe)) | 3670 DISPPLANE_TRICKLE_FEED_DISABLE); 3671 intel_flush_display_plane(dev_priv, pipe); 3672 } 3673 3674 /* The default value should be 0x200 according to docs, but the two 3675 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 3676 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); 3677 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); 3678 3679 cpt_init_clock_gating(dev); 3680 } 3681 3682 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 3683 { 3684 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 3685 3686 reg &= ~GEN7_FF_SCHED_MASK; 3687 reg |= GEN7_FF_TS_SCHED_HW; 3688 reg |= GEN7_FF_VS_SCHED_HW; 3689 reg |= GEN7_FF_DS_SCHED_HW; 3690 3691 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 3692 } 3693 3694 static void lpt_init_clock_gating(struct drm_device *dev) 3695 { 3696 struct drm_i915_private *dev_priv = dev->dev_private; 3697 3698 /* 3699 * TODO: this bit should only be enabled when really needed, then 3700 * disabled when not needed anymore in order to save power. 3701 */ 3702 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 3703 I915_WRITE(SOUTH_DSPCLK_GATE_D, 3704 I915_READ(SOUTH_DSPCLK_GATE_D) | 3705 PCH_LP_PARTITION_LEVEL_DISABLE); 3706 } 3707 3708 static void haswell_init_clock_gating(struct drm_device *dev) 3709 { 3710 struct drm_i915_private *dev_priv = dev->dev_private; 3711 int pipe; 3712 3713 I915_WRITE(WM3_LP_ILK, 0); 3714 I915_WRITE(WM2_LP_ILK, 0); 3715 I915_WRITE(WM1_LP_ILK, 0); 3716 3717 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3718 * This implements the WaDisableRCZUnitClockGating workaround. 3719 */ 3720 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 3721 3722 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3723 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3724 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3725 3726 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3727 I915_WRITE(GEN7_L3CNTLREG1, 3728 GEN7_WA_FOR_GEN7_L3_CONTROL); 3729 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3730 GEN7_WA_L3_CHICKEN_MODE); 3731 3732 /* This is required by WaCatErrorRejectionIssue */ 3733 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3734 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3735 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3736 3737 for_each_pipe(pipe) { 3738 I915_WRITE(DSPCNTR(pipe), 3739 I915_READ(DSPCNTR(pipe)) | 3740 DISPPLANE_TRICKLE_FEED_DISABLE); 3741 intel_flush_display_plane(dev_priv, pipe); 3742 } 3743 3744 gen7_setup_fixed_func_scheduler(dev_priv); 3745 3746 /* WaDisable4x2SubspanOptimization */ 3747 I915_WRITE(CACHE_MODE_1, 3748 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3749 3750 /* WaMbcDriverBootEnable */ 3751 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3752 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3753 3754 /* XXX: This is a workaround for early silicon revisions and should be 3755 * removed later. 3756 */ 3757 I915_WRITE(WM_DBG, 3758 I915_READ(WM_DBG) | 3759 WM_DBG_DISALLOW_MULTIPLE_LP | 3760 WM_DBG_DISALLOW_SPRITE | 3761 WM_DBG_DISALLOW_MAXFIFO); 3762 3763 lpt_init_clock_gating(dev); 3764 } 3765 3766 static void ivybridge_init_clock_gating(struct drm_device *dev) 3767 { 3768 struct drm_i915_private *dev_priv = dev->dev_private; 3769 int pipe; 3770 uint32_t snpcr; 3771 3772 I915_WRITE(WM3_LP_ILK, 0); 3773 I915_WRITE(WM2_LP_ILK, 0); 3774 I915_WRITE(WM1_LP_ILK, 0); 3775 3776 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3777 3778 /* WaDisableEarlyCull */ 3779 I915_WRITE(_3D_CHICKEN3, 3780 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3781 3782 /* WaDisableBackToBackFlipFix */ 3783 I915_WRITE(IVB_CHICKEN3, 3784 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3785 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3786 3787 /* WaDisablePSDDualDispatchEnable */ 3788 if (IS_IVB_GT1(dev)) 3789 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3790 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3791 else 3792 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, 3793 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3794 3795 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3796 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3797 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3798 3799 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3800 I915_WRITE(GEN7_L3CNTLREG1, 3801 GEN7_WA_FOR_GEN7_L3_CONTROL); 3802 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3803 GEN7_WA_L3_CHICKEN_MODE); 3804 if (IS_IVB_GT1(dev)) 3805 I915_WRITE(GEN7_ROW_CHICKEN2, 3806 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3807 else 3808 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 3809 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3810 3811 3812 /* WaForceL3Serialization */ 3813 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3814 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3815 3816 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3817 * gating disable must be set. Failure to set it results in 3818 * flickering pixels due to Z write ordering failures after 3819 * some amount of runtime in the Mesa "fire" demo, and Unigine 3820 * Sanctuary and Tropics, and apparently anything else with 3821 * alpha test or pixel discard. 3822 * 3823 * According to the spec, bit 11 (RCCUNIT) must also be set, 3824 * but we didn't debug actual testcases to find it out. 3825 * 3826 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3827 * This implements the WaDisableRCZUnitClockGating workaround. 3828 */ 3829 I915_WRITE(GEN6_UCGCTL2, 3830 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3831 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3832 3833 /* This is required by WaCatErrorRejectionIssue */ 3834 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3835 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3836 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3837 3838 for_each_pipe(pipe) { 3839 I915_WRITE(DSPCNTR(pipe), 3840 I915_READ(DSPCNTR(pipe)) | 3841 DISPPLANE_TRICKLE_FEED_DISABLE); 3842 intel_flush_display_plane(dev_priv, pipe); 3843 } 3844 3845 /* WaMbcDriverBootEnable */ 3846 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3847 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3848 3849 gen7_setup_fixed_func_scheduler(dev_priv); 3850 3851 /* WaDisable4x2SubspanOptimization */ 3852 I915_WRITE(CACHE_MODE_1, 3853 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3854 3855 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 3856 snpcr &= ~GEN6_MBC_SNPCR_MASK; 3857 snpcr |= GEN6_MBC_SNPCR_MED; 3858 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 3859 3860 cpt_init_clock_gating(dev); 3861 } 3862 3863 static void valleyview_init_clock_gating(struct drm_device *dev) 3864 { 3865 struct drm_i915_private *dev_priv = dev->dev_private; 3866 int pipe; 3867 3868 I915_WRITE(WM3_LP_ILK, 0); 3869 I915_WRITE(WM2_LP_ILK, 0); 3870 I915_WRITE(WM1_LP_ILK, 0); 3871 3872 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3873 3874 /* WaDisableEarlyCull */ 3875 I915_WRITE(_3D_CHICKEN3, 3876 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3877 3878 /* WaDisableBackToBackFlipFix */ 3879 I915_WRITE(IVB_CHICKEN3, 3880 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3881 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3882 3883 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3884 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3885 3886 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3887 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3888 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3889 3890 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3891 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); 3892 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 3893 3894 /* WaForceL3Serialization */ 3895 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3896 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3897 3898 /* WaDisableDopClockGating */ 3899 I915_WRITE(GEN7_ROW_CHICKEN2, 3900 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3901 3902 /* WaForceL3Serialization */ 3903 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3904 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3905 3906 /* This is required by WaCatErrorRejectionIssue */ 3907 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3908 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3909 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3910 3911 /* WaMbcDriverBootEnable */ 3912 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3913 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3914 3915 3916 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3917 * gating disable must be set. Failure to set it results in 3918 * flickering pixels due to Z write ordering failures after 3919 * some amount of runtime in the Mesa "fire" demo, and Unigine 3920 * Sanctuary and Tropics, and apparently anything else with 3921 * alpha test or pixel discard. 3922 * 3923 * According to the spec, bit 11 (RCCUNIT) must also be set, 3924 * but we didn't debug actual testcases to find it out. 3925 * 3926 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3927 * This implements the WaDisableRCZUnitClockGating workaround. 3928 * 3929 * Also apply WaDisableVDSUnitClockGating and 3930 * WaDisableRCPBUnitClockGating. 3931 */ 3932 I915_WRITE(GEN6_UCGCTL2, 3933 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3934 GEN7_TDLUNIT_CLOCK_GATE_DISABLE | 3935 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3936 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3937 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3938 3939 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 3940 3941 for_each_pipe(pipe) { 3942 I915_WRITE(DSPCNTR(pipe), 3943 I915_READ(DSPCNTR(pipe)) | 3944 DISPPLANE_TRICKLE_FEED_DISABLE); 3945 intel_flush_display_plane(dev_priv, pipe); 3946 } 3947 3948 I915_WRITE(CACHE_MODE_1, 3949 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3950 3951 /* 3952 * On ValleyView, the GUnit needs to signal the GT 3953 * when flip and other events complete. So enable 3954 * all the GUnit->GT interrupts here 3955 */ 3956 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | 3957 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | 3958 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | 3959 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | 3960 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | 3961 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | 3962 PLANEA_FLIPDONE_INT_EN); 3963 3964 /* 3965 * WaDisableVLVClockGating_VBIIssue 3966 * Disable clock gating on th GCFG unit to prevent a delay 3967 * in the reporting of vblank events. 3968 */ 3969 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 3970 } 3971 3972 static void g4x_init_clock_gating(struct drm_device *dev) 3973 { 3974 struct drm_i915_private *dev_priv = dev->dev_private; 3975 uint32_t dspclk_gate; 3976 3977 I915_WRITE(RENCLK_GATE_D1, 0); 3978 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 3979 GS_UNIT_CLOCK_GATE_DISABLE | 3980 CL_UNIT_CLOCK_GATE_DISABLE); 3981 I915_WRITE(RAMCLK_GATE_D, 0); 3982 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 3983 OVRUNIT_CLOCK_GATE_DISABLE | 3984 OVCUNIT_CLOCK_GATE_DISABLE; 3985 if (IS_GM45(dev)) 3986 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 3987 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 3988 3989 /* WaDisableRenderCachePipelinedFlush */ 3990 I915_WRITE(CACHE_MODE_0, 3991 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 3992 } 3993 3994 static void crestline_init_clock_gating(struct drm_device *dev) 3995 { 3996 struct drm_i915_private *dev_priv = dev->dev_private; 3997 3998 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 3999 I915_WRITE(RENCLK_GATE_D2, 0); 4000 I915_WRITE(DSPCLK_GATE_D, 0); 4001 I915_WRITE(RAMCLK_GATE_D, 0); 4002 I915_WRITE16(DEUC, 0); 4003 } 4004 4005 static void broadwater_init_clock_gating(struct drm_device *dev) 4006 { 4007 struct drm_i915_private *dev_priv = dev->dev_private; 4008 4009 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 4010 I965_RCC_CLOCK_GATE_DISABLE | 4011 I965_RCPB_CLOCK_GATE_DISABLE | 4012 I965_ISC_CLOCK_GATE_DISABLE | 4013 I965_FBC_CLOCK_GATE_DISABLE); 4014 I915_WRITE(RENCLK_GATE_D2, 0); 4015 } 4016 4017 static void gen3_init_clock_gating(struct drm_device *dev) 4018 { 4019 struct drm_i915_private *dev_priv = dev->dev_private; 4020 u32 dstate = I915_READ(D_STATE); 4021 4022 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4023 DSTATE_DOT_CLOCK_GATING; 4024 I915_WRITE(D_STATE, dstate); 4025 4026 if (IS_PINEVIEW(dev)) 4027 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 4028 4029 /* IIR "flip pending" means done if this bit is set */ 4030 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 4031 } 4032 4033 static void i85x_init_clock_gating(struct drm_device *dev) 4034 { 4035 struct drm_i915_private *dev_priv = dev->dev_private; 4036 4037 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4038 } 4039 4040 static void i830_init_clock_gating(struct drm_device *dev) 4041 { 4042 struct drm_i915_private *dev_priv = dev->dev_private; 4043 4044 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4045 } 4046 4047 void intel_init_clock_gating(struct drm_device *dev) 4048 { 4049 struct drm_i915_private *dev_priv = dev->dev_private; 4050 4051 dev_priv->display.init_clock_gating(dev); 4052 } 4053 4054 /* Starting with Haswell, we have different power wells for 4055 * different parts of the GPU. This attempts to enable them all. 4056 */ 4057 void intel_init_power_wells(struct drm_device *dev) 4058 { 4059 struct drm_i915_private *dev_priv = dev->dev_private; 4060 unsigned long power_wells[] = { 4061 HSW_PWR_WELL_CTL1, 4062 HSW_PWR_WELL_CTL2, 4063 HSW_PWR_WELL_CTL4 4064 }; 4065 int i; 4066 4067 if (!IS_HASWELL(dev)) 4068 return; 4069 4070 mutex_lock(&dev->struct_mutex); 4071 4072 for (i = 0; i < ARRAY_SIZE(power_wells); i++) { 4073 int well = I915_READ(power_wells[i]); 4074 4075 if ((well & HSW_PWR_WELL_STATE) == 0) { 4076 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); 4077 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) 4078 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); 4079 } 4080 } 4081 4082 mutex_unlock(&dev->struct_mutex); 4083 } 4084 4085 /* Set up chip specific power management-related functions */ 4086 void intel_init_pm(struct drm_device *dev) 4087 { 4088 struct drm_i915_private *dev_priv = dev->dev_private; 4089 4090 if (I915_HAS_FBC(dev)) { 4091 if (HAS_PCH_SPLIT(dev)) { 4092 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 4093 dev_priv->display.enable_fbc = ironlake_enable_fbc; 4094 dev_priv->display.disable_fbc = ironlake_disable_fbc; 4095 } else if (IS_GM45(dev)) { 4096 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4097 dev_priv->display.enable_fbc = g4x_enable_fbc; 4098 dev_priv->display.disable_fbc = g4x_disable_fbc; 4099 } else if (IS_CRESTLINE(dev)) { 4100 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4101 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4102 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4103 } 4104 /* 855GM needs testing */ 4105 } 4106 4107 /* For cxsr */ 4108 if (IS_PINEVIEW(dev)) 4109 i915_pineview_get_mem_freq(dev); 4110 else if (IS_GEN5(dev)) 4111 i915_ironlake_get_mem_freq(dev); 4112 4113 /* For FIFO watermark updates */ 4114 if (HAS_PCH_SPLIT(dev)) { 4115 if (IS_GEN5(dev)) { 4116 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) 4117 dev_priv->display.update_wm = ironlake_update_wm; 4118 else { 4119 DRM_DEBUG_KMS("Failed to get proper latency. " 4120 "Disable CxSR\n"); 4121 dev_priv->display.update_wm = NULL; 4122 } 4123 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 4124 } else if (IS_GEN6(dev)) { 4125 if (SNB_READ_WM0_LATENCY()) { 4126 dev_priv->display.update_wm = sandybridge_update_wm; 4127 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4128 } else { 4129 DRM_DEBUG_KMS("Failed to read display plane latency. " 4130 "Disable CxSR\n"); 4131 dev_priv->display.update_wm = NULL; 4132 } 4133 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 4134 } else if (IS_IVYBRIDGE(dev)) { 4135 /* FIXME: detect B0+ stepping and use auto training */ 4136 if (SNB_READ_WM0_LATENCY()) { 4137 dev_priv->display.update_wm = ivybridge_update_wm; 4138 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4139 } else { 4140 DRM_DEBUG_KMS("Failed to read display plane latency. " 4141 "Disable CxSR\n"); 4142 dev_priv->display.update_wm = NULL; 4143 } 4144 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 4145 } else if (IS_HASWELL(dev)) { 4146 if (SNB_READ_WM0_LATENCY()) { 4147 dev_priv->display.update_wm = sandybridge_update_wm; 4148 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4149 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; 4150 } else { 4151 DRM_DEBUG_KMS("Failed to read display plane latency. " 4152 "Disable CxSR\n"); 4153 dev_priv->display.update_wm = NULL; 4154 } 4155 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 4156 } else 4157 dev_priv->display.update_wm = NULL; 4158 } else if (IS_VALLEYVIEW(dev)) { 4159 dev_priv->display.update_wm = valleyview_update_wm; 4160 dev_priv->display.init_clock_gating = 4161 valleyview_init_clock_gating; 4162 } else if (IS_PINEVIEW(dev)) { 4163 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 4164 dev_priv->is_ddr3, 4165 dev_priv->fsb_freq, 4166 dev_priv->mem_freq)) { 4167 DRM_INFO("failed to find known CxSR latency " 4168 "(found ddr%s fsb freq %d, mem freq %d), " 4169 "disabling CxSR\n", 4170 (dev_priv->is_ddr3 == 1) ? "3" : "2", 4171 dev_priv->fsb_freq, dev_priv->mem_freq); 4172 /* Disable CxSR and never update its watermark again */ 4173 pineview_disable_cxsr(dev); 4174 dev_priv->display.update_wm = NULL; 4175 } else 4176 dev_priv->display.update_wm = pineview_update_wm; 4177 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4178 } else if (IS_G4X(dev)) { 4179 dev_priv->display.update_wm = g4x_update_wm; 4180 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 4181 } else if (IS_GEN4(dev)) { 4182 dev_priv->display.update_wm = i965_update_wm; 4183 if (IS_CRESTLINE(dev)) 4184 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 4185 else if (IS_BROADWATER(dev)) 4186 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 4187 } else if (IS_GEN3(dev)) { 4188 dev_priv->display.update_wm = i9xx_update_wm; 4189 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4190 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4191 } else if (IS_I865G(dev)) { 4192 dev_priv->display.update_wm = i830_update_wm; 4193 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4194 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4195 } else if (IS_I85X(dev)) { 4196 dev_priv->display.update_wm = i9xx_update_wm; 4197 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4198 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4199 } else { 4200 dev_priv->display.update_wm = i830_update_wm; 4201 dev_priv->display.init_clock_gating = i830_init_clock_gating; 4202 if (IS_845G(dev)) 4203 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4204 else 4205 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4206 } 4207 } 4208 4209 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 4210 { 4211 u32 gt_thread_status_mask; 4212 4213 if (IS_HASWELL(dev_priv->dev)) 4214 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 4215 else 4216 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 4217 4218 /* w/a for a sporadic read returning 0 by waiting for the GT 4219 * thread to wake up. 4220 */ 4221 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 4222 DRM_ERROR("GT thread status wait timed out\n"); 4223 } 4224 4225 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 4226 { 4227 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4228 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4229 } 4230 4231 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4232 { 4233 u32 forcewake_ack; 4234 4235 if (IS_HASWELL(dev_priv->dev)) 4236 forcewake_ack = FORCEWAKE_ACK_HSW; 4237 else 4238 forcewake_ack = FORCEWAKE_ACK; 4239 4240 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4241 FORCEWAKE_ACK_TIMEOUT_MS)) 4242 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4243 4244 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); 4245 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4246 4247 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4248 FORCEWAKE_ACK_TIMEOUT_MS)) 4249 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4250 4251 __gen6_gt_wait_for_thread_c0(dev_priv); 4252 } 4253 4254 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 4255 { 4256 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 4257 /* something from same cacheline, but !FORCEWAKE_MT */ 4258 POSTING_READ(ECOBUS); 4259 } 4260 4261 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 4262 { 4263 u32 forcewake_ack; 4264 4265 if (IS_HASWELL(dev_priv->dev)) 4266 forcewake_ack = FORCEWAKE_ACK_HSW; 4267 else 4268 forcewake_ack = FORCEWAKE_MT_ACK; 4269 4270 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4271 FORCEWAKE_ACK_TIMEOUT_MS)) 4272 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4273 4274 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4275 /* something from same cacheline, but !FORCEWAKE_MT */ 4276 POSTING_READ(ECOBUS); 4277 4278 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4279 FORCEWAKE_ACK_TIMEOUT_MS)) 4280 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4281 4282 __gen6_gt_wait_for_thread_c0(dev_priv); 4283 } 4284 4285 /* 4286 * Generally this is called implicitly by the register read function. However, 4287 * if some sequence requires the GT to not power down then this function should 4288 * be called at the beginning of the sequence followed by a call to 4289 * gen6_gt_force_wake_put() at the end of the sequence. 4290 */ 4291 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4292 { 4293 unsigned long irqflags; 4294 4295 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); 4296 if (dev_priv->forcewake_count++ == 0) 4297 dev_priv->gt.force_wake_get(dev_priv); 4298 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); 4299 } 4300 4301 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 4302 { 4303 u32 gtfifodbg; 4304 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 4305 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 4306 "MMIO read or write has been dropped %x\n", gtfifodbg)) 4307 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 4308 } 4309 4310 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4311 { 4312 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4313 /* something from same cacheline, but !FORCEWAKE */ 4314 POSTING_READ(ECOBUS); 4315 gen6_gt_check_fifodbg(dev_priv); 4316 } 4317 4318 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4319 { 4320 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4321 /* something from same cacheline, but !FORCEWAKE_MT */ 4322 POSTING_READ(ECOBUS); 4323 gen6_gt_check_fifodbg(dev_priv); 4324 } 4325 4326 /* 4327 * see gen6_gt_force_wake_get() 4328 */ 4329 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4330 { 4331 unsigned long irqflags; 4332 4333 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); 4334 if (--dev_priv->forcewake_count == 0) 4335 dev_priv->gt.force_wake_put(dev_priv); 4336 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); 4337 } 4338 4339 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 4340 { 4341 int ret = 0; 4342 4343 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 4344 int loop = 500; 4345 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4346 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 4347 udelay(10); 4348 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4349 } 4350 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 4351 ++ret; 4352 dev_priv->gt_fifo_count = fifo; 4353 } 4354 dev_priv->gt_fifo_count--; 4355 4356 return ret; 4357 } 4358 4359 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 4360 { 4361 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); 4362 /* something from same cacheline, but !FORCEWAKE_VLV */ 4363 POSTING_READ(FORCEWAKE_ACK_VLV); 4364 } 4365 4366 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 4367 { 4368 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, 4369 FORCEWAKE_ACK_TIMEOUT_MS)) 4370 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4371 4372 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4373 4374 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 4375 FORCEWAKE_ACK_TIMEOUT_MS)) 4376 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4377 4378 __gen6_gt_wait_for_thread_c0(dev_priv); 4379 } 4380 4381 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 4382 { 4383 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4384 /* something from same cacheline, but !FORCEWAKE_VLV */ 4385 POSTING_READ(FORCEWAKE_ACK_VLV); 4386 gen6_gt_check_fifodbg(dev_priv); 4387 } 4388 4389 void intel_gt_reset(struct drm_device *dev) 4390 { 4391 struct drm_i915_private *dev_priv = dev->dev_private; 4392 4393 if (IS_VALLEYVIEW(dev)) { 4394 vlv_force_wake_reset(dev_priv); 4395 } else if (INTEL_INFO(dev)->gen >= 6) { 4396 __gen6_gt_force_wake_reset(dev_priv); 4397 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 4398 __gen6_gt_force_wake_mt_reset(dev_priv); 4399 } 4400 } 4401 4402 void intel_gt_init(struct drm_device *dev) 4403 { 4404 struct drm_i915_private *dev_priv = dev->dev_private; 4405 4406 spin_lock_init(&dev_priv->gt_lock); 4407 4408 intel_gt_reset(dev); 4409 4410 if (IS_VALLEYVIEW(dev)) { 4411 dev_priv->gt.force_wake_get = vlv_force_wake_get; 4412 dev_priv->gt.force_wake_put = vlv_force_wake_put; 4413 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 4414 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; 4415 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; 4416 } else if (IS_GEN6(dev)) { 4417 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; 4418 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; 4419 } 4420 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 4421 intel_gen6_powersave_work); 4422 } 4423 4424 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 4425 { 4426 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4427 4428 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4429 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 4430 return -EAGAIN; 4431 } 4432 4433 I915_WRITE(GEN6_PCODE_DATA, *val); 4434 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4435 4436 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4437 500)) { 4438 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 4439 return -ETIMEDOUT; 4440 } 4441 4442 *val = I915_READ(GEN6_PCODE_DATA); 4443 I915_WRITE(GEN6_PCODE_DATA, 0); 4444 4445 return 0; 4446 } 4447 4448 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 4449 { 4450 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4451 4452 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4453 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 4454 return -EAGAIN; 4455 } 4456 4457 I915_WRITE(GEN6_PCODE_DATA, val); 4458 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4459 4460 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4461 500)) { 4462 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 4463 return -ETIMEDOUT; 4464 } 4465 4466 I915_WRITE(GEN6_PCODE_DATA, 0); 4467 4468 return 0; 4469 } 4470
Indexes created Sat Oct 11 19:10:01 GMT 2025