intel_pm.c revision 1.12
1 /* $NetBSD: intel_pm.c,v 1.12 2018/08/27 07:26:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.12 2018/08/27 07:26:59 riastradh Exp $"); 32 33 #include <linux/bitops.h> 34 #include <linux/cpufreq.h> 35 #include <linux/export.h> 36 #include "i915_drv.h" 37 #include "intel_drv.h" 38 #ifndef __NetBSD__ 39 #include "../../../platform/x86/intel_ips.h" 40 #endif 41 #include <linux/module.h> 42 #include <linux/log2.h> 43 #include <linux/math64.h> 44 #include <linux/time.h> 45 46 /** 47 * RC6 is a special power stage which allows the GPU to enter an very 48 * low-voltage mode when idle, using down to 0V while at this stage. This 49 * stage is entered automatically when the GPU is idle when RC6 support is 50 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 51 * 52 * There are different RC6 modes available in Intel GPU, which differentiate 53 * among each other with the latency required to enter and leave RC6 and 54 * voltage consumed by the GPU in different states. 55 * 56 * The combination of the following flags define which states GPU is allowed 57 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 58 * RC6pp is deepest RC6. Their support by hardware varies according to the 59 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 60 * which brings the most power savings; deeper states save more power, but 61 * require higher latency to switch to and wake up. 62 */ 63 #define INTEL_RC6_ENABLE (1<<0) 64 #define INTEL_RC6p_ENABLE (1<<1) 65 #define INTEL_RC6pp_ENABLE (1<<2) 66 67 static void bxt_init_clock_gating(struct drm_device *dev) 68 { 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 71 /* WaDisableSDEUnitClockGating:bxt */ 72 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 73 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 74 75 /* 76 * FIXME: 77 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 78 */ 79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 80 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 81 } 82 83 static void i915_pineview_get_mem_freq(struct drm_device *dev) 84 { 85 struct drm_i915_private *dev_priv = dev->dev_private; 86 u32 tmp; 87 88 tmp = I915_READ(CLKCFG); 89 90 switch (tmp & CLKCFG_FSB_MASK) { 91 case CLKCFG_FSB_533: 92 dev_priv->fsb_freq = 533; /* 133*4 */ 93 break; 94 case CLKCFG_FSB_800: 95 dev_priv->fsb_freq = 800; /* 200*4 */ 96 break; 97 case CLKCFG_FSB_667: 98 dev_priv->fsb_freq = 667; /* 167*4 */ 99 break; 100 case CLKCFG_FSB_400: 101 dev_priv->fsb_freq = 400; /* 100*4 */ 102 break; 103 } 104 105 switch (tmp & CLKCFG_MEM_MASK) { 106 case CLKCFG_MEM_533: 107 dev_priv->mem_freq = 533; 108 break; 109 case CLKCFG_MEM_667: 110 dev_priv->mem_freq = 667; 111 break; 112 case CLKCFG_MEM_800: 113 dev_priv->mem_freq = 800; 114 break; 115 } 116 117 /* detect pineview DDR3 setting */ 118 tmp = I915_READ(CSHRDDR3CTL); 119 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 120 } 121 122 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 123 { 124 struct drm_i915_private *dev_priv = dev->dev_private; 125 u16 ddrpll, csipll; 126 127 ddrpll = I915_READ16(DDRMPLL1); 128 csipll = I915_READ16(CSIPLL0); 129 130 switch (ddrpll & 0xff) { 131 case 0xc: 132 dev_priv->mem_freq = 800; 133 break; 134 case 0x10: 135 dev_priv->mem_freq = 1066; 136 break; 137 case 0x14: 138 dev_priv->mem_freq = 1333; 139 break; 140 case 0x18: 141 dev_priv->mem_freq = 1600; 142 break; 143 default: 144 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 145 ddrpll & 0xff); 146 dev_priv->mem_freq = 0; 147 break; 148 } 149 150 dev_priv->ips.r_t = dev_priv->mem_freq; 151 152 switch (csipll & 0x3ff) { 153 case 0x00c: 154 dev_priv->fsb_freq = 3200; 155 break; 156 case 0x00e: 157 dev_priv->fsb_freq = 3733; 158 break; 159 case 0x010: 160 dev_priv->fsb_freq = 4266; 161 break; 162 case 0x012: 163 dev_priv->fsb_freq = 4800; 164 break; 165 case 0x014: 166 dev_priv->fsb_freq = 5333; 167 break; 168 case 0x016: 169 dev_priv->fsb_freq = 5866; 170 break; 171 case 0x018: 172 dev_priv->fsb_freq = 6400; 173 break; 174 default: 175 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 176 csipll & 0x3ff); 177 dev_priv->fsb_freq = 0; 178 break; 179 } 180 181 if (dev_priv->fsb_freq == 3200) { 182 dev_priv->ips.c_m = 0; 183 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 184 dev_priv->ips.c_m = 1; 185 } else { 186 dev_priv->ips.c_m = 2; 187 } 188 } 189 190 static const struct cxsr_latency cxsr_latency_table[] = { 191 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 192 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 193 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 194 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 195 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 196 197 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 198 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 199 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 200 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 201 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 202 203 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 204 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 205 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 206 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 207 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 208 209 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 210 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 211 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 212 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 213 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 214 215 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 216 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 217 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 218 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 219 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 220 221 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 222 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 223 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 224 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 225 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 226 }; 227 228 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 229 int is_ddr3, 230 int fsb, 231 int mem) 232 { 233 const struct cxsr_latency *latency; 234 int i; 235 236 if (fsb == 0 || mem == 0) 237 return NULL; 238 239 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 240 latency = &cxsr_latency_table[i]; 241 if (is_desktop == latency->is_desktop && 242 is_ddr3 == latency->is_ddr3 && 243 fsb == latency->fsb_freq && mem == latency->mem_freq) 244 return latency; 245 } 246 247 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 248 249 return NULL; 250 } 251 252 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 253 { 254 u32 val; 255 256 mutex_lock(&dev_priv->rps.hw_lock); 257 258 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 259 if (enable) 260 val &= ~FORCE_DDR_HIGH_FREQ; 261 else 262 val |= FORCE_DDR_HIGH_FREQ; 263 val &= ~FORCE_DDR_LOW_FREQ; 264 val |= FORCE_DDR_FREQ_REQ_ACK; 265 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 266 267 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 268 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 269 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 270 271 mutex_unlock(&dev_priv->rps.hw_lock); 272 } 273 274 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 275 { 276 u32 val; 277 278 mutex_lock(&dev_priv->rps.hw_lock); 279 280 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 281 if (enable) 282 val |= DSP_MAXFIFO_PM5_ENABLE; 283 else 284 val &= ~DSP_MAXFIFO_PM5_ENABLE; 285 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 286 287 mutex_unlock(&dev_priv->rps.hw_lock); 288 } 289 290 #define FW_WM(value, plane) \ 291 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 292 293 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 294 { 295 struct drm_device *dev = dev_priv->dev; 296 u32 val; 297 298 if (IS_VALLEYVIEW(dev)) { 299 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 300 POSTING_READ(FW_BLC_SELF_VLV); 301 dev_priv->wm.vlv.cxsr = enable; 302 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 303 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 304 POSTING_READ(FW_BLC_SELF); 305 } else if (IS_PINEVIEW(dev)) { 306 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 307 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 308 I915_WRITE(DSPFW3, val); 309 POSTING_READ(DSPFW3); 310 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 311 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 312 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 313 I915_WRITE(FW_BLC_SELF, val); 314 POSTING_READ(FW_BLC_SELF); 315 } else if (IS_I915GM(dev)) { 316 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 317 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 318 I915_WRITE(INSTPM, val); 319 POSTING_READ(INSTPM); 320 } else { 321 return; 322 } 323 324 DRM_DEBUG_KMS("memory self-refresh is %s\n", 325 enable ? "enabled" : "disabled"); 326 } 327 328 329 /* 330 * Latency for FIFO fetches is dependent on several factors: 331 * - memory configuration (speed, channels) 332 * - chipset 333 * - current MCH state 334 * It can be fairly high in some situations, so here we assume a fairly 335 * pessimal value. It's a tradeoff between extra memory fetches (if we 336 * set this value too high, the FIFO will fetch frequently to stay full) 337 * and power consumption (set it too low to save power and we might see 338 * FIFO underruns and display "flicker"). 339 * 340 * A value of 5us seems to be a good balance; safe for very low end 341 * platforms but not overly aggressive on lower latency configs. 342 */ 343 static const int pessimal_latency_ns = 5000; 344 345 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 346 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 347 348 static int vlv_get_fifo_size(struct drm_device *dev, 349 enum i915_pipe pipe, int plane) 350 { 351 struct drm_i915_private *dev_priv = dev->dev_private; 352 int sprite0_start, sprite1_start, size; 353 354 switch (pipe) { 355 uint32_t dsparb, dsparb2, dsparb3; 356 case PIPE_A: 357 dsparb = I915_READ(DSPARB); 358 dsparb2 = I915_READ(DSPARB2); 359 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 360 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 361 break; 362 case PIPE_B: 363 dsparb = I915_READ(DSPARB); 364 dsparb2 = I915_READ(DSPARB2); 365 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 366 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 367 break; 368 case PIPE_C: 369 dsparb2 = I915_READ(DSPARB2); 370 dsparb3 = I915_READ(DSPARB3); 371 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 372 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 373 break; 374 default: 375 return 0; 376 } 377 378 switch (plane) { 379 case 0: 380 size = sprite0_start; 381 break; 382 case 1: 383 size = sprite1_start - sprite0_start; 384 break; 385 case 2: 386 size = 512 - 1 - sprite1_start; 387 break; 388 default: 389 return 0; 390 } 391 392 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 393 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 394 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 395 size); 396 397 return size; 398 } 399 400 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 401 { 402 struct drm_i915_private *dev_priv = dev->dev_private; 403 uint32_t dsparb = I915_READ(DSPARB); 404 int size; 405 406 size = dsparb & 0x7f; 407 if (plane) 408 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 409 410 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 411 plane ? "B" : "A", size); 412 413 return size; 414 } 415 416 static int i830_get_fifo_size(struct drm_device *dev, int plane) 417 { 418 struct drm_i915_private *dev_priv = dev->dev_private; 419 uint32_t dsparb = I915_READ(DSPARB); 420 int size; 421 422 size = dsparb & 0x1ff; 423 if (plane) 424 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 425 size >>= 1; /* Convert to cachelines */ 426 427 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 428 plane ? "B" : "A", size); 429 430 return size; 431 } 432 433 static int i845_get_fifo_size(struct drm_device *dev, int plane) 434 { 435 struct drm_i915_private *dev_priv = dev->dev_private; 436 uint32_t dsparb = I915_READ(DSPARB); 437 int size; 438 439 size = dsparb & 0x7f; 440 size >>= 2; /* Convert to cachelines */ 441 442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 443 plane ? "B" : "A", 444 size); 445 446 return size; 447 } 448 449 /* Pineview has different values for various configs */ 450 static const struct intel_watermark_params pineview_display_wm = { 451 .fifo_size = PINEVIEW_DISPLAY_FIFO, 452 .max_wm = PINEVIEW_MAX_WM, 453 .default_wm = PINEVIEW_DFT_WM, 454 .guard_size = PINEVIEW_GUARD_WM, 455 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 456 }; 457 static const struct intel_watermark_params pineview_display_hplloff_wm = { 458 .fifo_size = PINEVIEW_DISPLAY_FIFO, 459 .max_wm = PINEVIEW_MAX_WM, 460 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 461 .guard_size = PINEVIEW_GUARD_WM, 462 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 463 }; 464 static const struct intel_watermark_params pineview_cursor_wm = { 465 .fifo_size = PINEVIEW_CURSOR_FIFO, 466 .max_wm = PINEVIEW_CURSOR_MAX_WM, 467 .default_wm = PINEVIEW_CURSOR_DFT_WM, 468 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 469 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 470 }; 471 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 472 .fifo_size = PINEVIEW_CURSOR_FIFO, 473 .max_wm = PINEVIEW_CURSOR_MAX_WM, 474 .default_wm = PINEVIEW_CURSOR_DFT_WM, 475 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 477 }; 478 static const struct intel_watermark_params g4x_wm_info = { 479 .fifo_size = G4X_FIFO_SIZE, 480 .max_wm = G4X_MAX_WM, 481 .default_wm = G4X_MAX_WM, 482 .guard_size = 2, 483 .cacheline_size = G4X_FIFO_LINE_SIZE, 484 }; 485 static const struct intel_watermark_params g4x_cursor_wm_info = { 486 .fifo_size = I965_CURSOR_FIFO, 487 .max_wm = I965_CURSOR_MAX_WM, 488 .default_wm = I965_CURSOR_DFT_WM, 489 .guard_size = 2, 490 .cacheline_size = G4X_FIFO_LINE_SIZE, 491 }; 492 static const struct intel_watermark_params valleyview_wm_info = { 493 .fifo_size = VALLEYVIEW_FIFO_SIZE, 494 .max_wm = VALLEYVIEW_MAX_WM, 495 .default_wm = VALLEYVIEW_MAX_WM, 496 .guard_size = 2, 497 .cacheline_size = G4X_FIFO_LINE_SIZE, 498 }; 499 static const struct intel_watermark_params valleyview_cursor_wm_info = { 500 .fifo_size = I965_CURSOR_FIFO, 501 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 502 .default_wm = I965_CURSOR_DFT_WM, 503 .guard_size = 2, 504 .cacheline_size = G4X_FIFO_LINE_SIZE, 505 }; 506 static const struct intel_watermark_params i965_cursor_wm_info = { 507 .fifo_size = I965_CURSOR_FIFO, 508 .max_wm = I965_CURSOR_MAX_WM, 509 .default_wm = I965_CURSOR_DFT_WM, 510 .guard_size = 2, 511 .cacheline_size = I915_FIFO_LINE_SIZE, 512 }; 513 static const struct intel_watermark_params i945_wm_info = { 514 .fifo_size = I945_FIFO_SIZE, 515 .max_wm = I915_MAX_WM, 516 .default_wm = 1, 517 .guard_size = 2, 518 .cacheline_size = I915_FIFO_LINE_SIZE, 519 }; 520 static const struct intel_watermark_params i915_wm_info = { 521 .fifo_size = I915_FIFO_SIZE, 522 .max_wm = I915_MAX_WM, 523 .default_wm = 1, 524 .guard_size = 2, 525 .cacheline_size = I915_FIFO_LINE_SIZE, 526 }; 527 static const struct intel_watermark_params i830_a_wm_info = { 528 .fifo_size = I855GM_FIFO_SIZE, 529 .max_wm = I915_MAX_WM, 530 .default_wm = 1, 531 .guard_size = 2, 532 .cacheline_size = I830_FIFO_LINE_SIZE, 533 }; 534 static const struct intel_watermark_params i830_bc_wm_info = { 535 .fifo_size = I855GM_FIFO_SIZE, 536 .max_wm = I915_MAX_WM/2, 537 .default_wm = 1, 538 .guard_size = 2, 539 .cacheline_size = I830_FIFO_LINE_SIZE, 540 }; 541 static const struct intel_watermark_params i845_wm_info = { 542 .fifo_size = I830_FIFO_SIZE, 543 .max_wm = I915_MAX_WM, 544 .default_wm = 1, 545 .guard_size = 2, 546 .cacheline_size = I830_FIFO_LINE_SIZE, 547 }; 548 549 /** 550 * intel_calculate_wm - calculate watermark level 551 * @clock_in_khz: pixel clock 552 * @wm: chip FIFO params 553 * @pixel_size: display pixel size 554 * @latency_ns: memory latency for the platform 555 * 556 * Calculate the watermark level (the level at which the display plane will 557 * start fetching from memory again). Each chip has a different display 558 * FIFO size and allocation, so the caller needs to figure that out and pass 559 * in the correct intel_watermark_params structure. 560 * 561 * As the pixel clock runs, the FIFO will be drained at a rate that depends 562 * on the pixel size. When it reaches the watermark level, it'll start 563 * fetching FIFO line sized based chunks from memory until the FIFO fills 564 * past the watermark point. If the FIFO drains completely, a FIFO underrun 565 * will occur, and a display engine hang could result. 566 */ 567 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 568 const struct intel_watermark_params *wm, 569 int fifo_size, 570 int pixel_size, 571 unsigned long latency_ns) 572 { 573 long entries_required, wm_size; 574 575 /* 576 * Note: we need to make sure we don't overflow for various clock & 577 * latency values. 578 * clocks go from a few thousand to several hundred thousand. 579 * latency is usually a few thousand 580 */ 581 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 582 1000; 583 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 584 585 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 586 587 wm_size = fifo_size - (entries_required + wm->guard_size); 588 589 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 590 591 /* Don't promote wm_size to unsigned... */ 592 if (wm_size > (long)wm->max_wm) 593 wm_size = wm->max_wm; 594 if (wm_size <= 0) 595 wm_size = wm->default_wm; 596 597 /* 598 * Bspec seems to indicate that the value shouldn't be lower than 599 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 600 * Lets go for 8 which is the burst size since certain platforms 601 * already use a hardcoded 8 (which is what the spec says should be 602 * done). 603 */ 604 if (wm_size <= 8) 605 wm_size = 8; 606 607 return wm_size; 608 } 609 610 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 611 { 612 struct drm_crtc *crtc, *enabled = NULL; 613 614 for_each_crtc(dev, crtc) { 615 if (intel_crtc_active(crtc)) { 616 if (enabled) 617 return NULL; 618 enabled = crtc; 619 } 620 } 621 622 return enabled; 623 } 624 625 static void pineview_update_wm(struct drm_crtc *unused_crtc) 626 { 627 struct drm_device *dev = unused_crtc->dev; 628 struct drm_i915_private *dev_priv = dev->dev_private; 629 struct drm_crtc *crtc; 630 const struct cxsr_latency *latency; 631 u32 reg; 632 unsigned long wm; 633 634 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 635 dev_priv->fsb_freq, dev_priv->mem_freq); 636 if (!latency) { 637 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 638 intel_set_memory_cxsr(dev_priv, false); 639 return; 640 } 641 642 crtc = single_enabled_crtc(dev); 643 if (crtc) { 644 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 645 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 646 int clock = adjusted_mode->crtc_clock; 647 648 /* Display SR */ 649 wm = intel_calculate_wm(clock, &pineview_display_wm, 650 pineview_display_wm.fifo_size, 651 pixel_size, latency->display_sr); 652 reg = I915_READ(DSPFW1); 653 reg &= ~DSPFW_SR_MASK; 654 reg |= FW_WM(wm, SR); 655 I915_WRITE(DSPFW1, reg); 656 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 657 658 /* cursor SR */ 659 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 660 pineview_display_wm.fifo_size, 661 pixel_size, latency->cursor_sr); 662 reg = I915_READ(DSPFW3); 663 reg &= ~DSPFW_CURSOR_SR_MASK; 664 reg |= FW_WM(wm, CURSOR_SR); 665 I915_WRITE(DSPFW3, reg); 666 667 /* Display HPLL off SR */ 668 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 669 pineview_display_hplloff_wm.fifo_size, 670 pixel_size, latency->display_hpll_disable); 671 reg = I915_READ(DSPFW3); 672 reg &= ~DSPFW_HPLL_SR_MASK; 673 reg |= FW_WM(wm, HPLL_SR); 674 I915_WRITE(DSPFW3, reg); 675 676 /* cursor HPLL off SR */ 677 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 678 pineview_display_hplloff_wm.fifo_size, 679 pixel_size, latency->cursor_hpll_disable); 680 reg = I915_READ(DSPFW3); 681 reg &= ~DSPFW_HPLL_CURSOR_MASK; 682 reg |= FW_WM(wm, HPLL_CURSOR); 683 I915_WRITE(DSPFW3, reg); 684 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 685 686 intel_set_memory_cxsr(dev_priv, true); 687 } else { 688 intel_set_memory_cxsr(dev_priv, false); 689 } 690 } 691 692 static bool g4x_compute_wm0(struct drm_device *dev, 693 int plane, 694 const struct intel_watermark_params *display, 695 int display_latency_ns, 696 const struct intel_watermark_params *cursor, 697 int cursor_latency_ns, 698 int *plane_wm, 699 int *cursor_wm) 700 { 701 struct drm_crtc *crtc; 702 const struct drm_display_mode *adjusted_mode; 703 int htotal, hdisplay, clock, pixel_size; 704 int line_time_us, line_count; 705 int entries, tlb_miss; 706 707 crtc = intel_get_crtc_for_plane(dev, plane); 708 if (!intel_crtc_active(crtc)) { 709 *cursor_wm = cursor->guard_size; 710 *plane_wm = display->guard_size; 711 return false; 712 } 713 714 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 715 clock = adjusted_mode->crtc_clock; 716 htotal = adjusted_mode->crtc_htotal; 717 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 718 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 719 720 /* Use the small buffer method to calculate plane watermark */ 721 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 722 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 723 if (tlb_miss > 0) 724 entries += tlb_miss; 725 entries = DIV_ROUND_UP(entries, display->cacheline_size); 726 *plane_wm = entries + display->guard_size; 727 if (*plane_wm > (int)display->max_wm) 728 *plane_wm = display->max_wm; 729 730 /* Use the large buffer method to calculate cursor watermark */ 731 line_time_us = max(htotal * 1000 / clock, 1); 732 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 733 entries = line_count * crtc->cursor->state->crtc_w * pixel_size; 734 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 735 if (tlb_miss > 0) 736 entries += tlb_miss; 737 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 738 *cursor_wm = entries + cursor->guard_size; 739 if (*cursor_wm > (int)cursor->max_wm) 740 *cursor_wm = (int)cursor->max_wm; 741 742 return true; 743 } 744 745 /* 746 * Check the wm result. 747 * 748 * If any calculated watermark values is larger than the maximum value that 749 * can be programmed into the associated watermark register, that watermark 750 * must be disabled. 751 */ 752 static bool g4x_check_srwm(struct drm_device *dev, 753 int display_wm, int cursor_wm, 754 const struct intel_watermark_params *display, 755 const struct intel_watermark_params *cursor) 756 { 757 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 758 display_wm, cursor_wm); 759 760 if (display_wm > display->max_wm) { 761 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 762 display_wm, display->max_wm); 763 return false; 764 } 765 766 if (cursor_wm > cursor->max_wm) { 767 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 768 cursor_wm, cursor->max_wm); 769 return false; 770 } 771 772 if (!(display_wm || cursor_wm)) { 773 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 774 return false; 775 } 776 777 return true; 778 } 779 780 static bool g4x_compute_srwm(struct drm_device *dev, 781 int plane, 782 int latency_ns, 783 const struct intel_watermark_params *display, 784 const struct intel_watermark_params *cursor, 785 int *display_wm, int *cursor_wm) 786 { 787 struct drm_crtc *crtc; 788 const struct drm_display_mode *adjusted_mode; 789 int hdisplay, htotal, pixel_size, clock; 790 unsigned long line_time_us; 791 int line_count, line_size; 792 int small, large; 793 int entries; 794 795 if (!latency_ns) { 796 *display_wm = *cursor_wm = 0; 797 return false; 798 } 799 800 crtc = intel_get_crtc_for_plane(dev, plane); 801 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 802 clock = adjusted_mode->crtc_clock; 803 htotal = adjusted_mode->crtc_htotal; 804 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 805 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 806 807 line_time_us = max(htotal * 1000 / clock, 1); 808 line_count = (latency_ns / line_time_us + 1000) / 1000; 809 line_size = hdisplay * pixel_size; 810 811 /* Use the minimum of the small and large buffer method for primary */ 812 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 813 large = line_count * line_size; 814 815 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 816 *display_wm = entries + display->guard_size; 817 818 /* calculate the self-refresh watermark for display cursor */ 819 entries = line_count * pixel_size * crtc->cursor->state->crtc_w; 820 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 821 *cursor_wm = entries + cursor->guard_size; 822 823 return g4x_check_srwm(dev, 824 *display_wm, *cursor_wm, 825 display, cursor); 826 } 827 828 #define FW_WM_VLV(value, plane) \ 829 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 830 831 static void vlv_write_wm_values(struct intel_crtc *crtc, 832 const struct vlv_wm_values *wm) 833 { 834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 835 enum i915_pipe pipe = crtc->pipe; 836 837 I915_WRITE(VLV_DDL(pipe), 838 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 839 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 840 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 841 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 842 843 I915_WRITE(DSPFW1, 844 FW_WM(wm->sr.plane, SR) | 845 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 846 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 847 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 848 I915_WRITE(DSPFW2, 849 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 850 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 851 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 852 I915_WRITE(DSPFW3, 853 FW_WM(wm->sr.cursor, CURSOR_SR)); 854 855 if (IS_CHERRYVIEW(dev_priv)) { 856 I915_WRITE(DSPFW7_CHV, 857 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 858 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 859 I915_WRITE(DSPFW8_CHV, 860 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 861 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 862 I915_WRITE(DSPFW9_CHV, 863 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 864 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 865 I915_WRITE(DSPHOWM, 866 FW_WM(wm->sr.plane >> 9, SR_HI) | 867 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 868 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 869 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 876 } else { 877 I915_WRITE(DSPFW7, 878 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 879 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 880 I915_WRITE(DSPHOWM, 881 FW_WM(wm->sr.plane >> 9, SR_HI) | 882 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 883 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 884 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 885 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 886 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 887 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 888 } 889 890 /* zero (unused) WM1 watermarks */ 891 I915_WRITE(DSPFW4, 0); 892 I915_WRITE(DSPFW5, 0); 893 I915_WRITE(DSPFW6, 0); 894 I915_WRITE(DSPHOWM1, 0); 895 896 POSTING_READ(DSPFW1); 897 } 898 899 #undef FW_WM_VLV 900 901 enum vlv_wm_level { 902 VLV_WM_LEVEL_PM2, 903 VLV_WM_LEVEL_PM5, 904 VLV_WM_LEVEL_DDR_DVFS, 905 }; 906 907 /* latency must be in 0.1us units. */ 908 static unsigned int vlv_wm_method2(unsigned int pixel_rate, 909 unsigned int pipe_htotal, 910 unsigned int horiz_pixels, 911 unsigned int bytes_per_pixel, 912 unsigned int latency) 913 { 914 unsigned int ret; 915 916 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 917 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 918 ret = DIV_ROUND_UP(ret, 64); 919 920 return ret; 921 } 922 923 static void vlv_setup_wm_latency(struct drm_device *dev) 924 { 925 struct drm_i915_private *dev_priv = dev->dev_private; 926 927 /* all latencies in usec */ 928 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 929 930 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 931 932 if (IS_CHERRYVIEW(dev_priv)) { 933 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 934 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 935 936 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 937 } 938 } 939 940 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 941 struct intel_crtc *crtc, 942 const struct intel_plane_state *state, 943 int level) 944 { 945 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 946 int clock, htotal, pixel_size, width, wm; 947 948 if (dev_priv->wm.pri_latency[level] == 0) 949 return USHRT_MAX; 950 951 if (!state->visible) 952 return 0; 953 954 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 955 clock = crtc->config->base.adjusted_mode.crtc_clock; 956 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 957 width = crtc->config->pipe_src_w; 958 if (WARN_ON(htotal == 0)) 959 htotal = 1; 960 961 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 962 /* 963 * FIXME the formula gives values that are 964 * too big for the cursor FIFO, and hence we 965 * would never be able to use cursors. For 966 * now just hardcode the watermark. 967 */ 968 wm = 63; 969 } else { 970 wm = vlv_wm_method2(clock, htotal, width, pixel_size, 971 dev_priv->wm.pri_latency[level] * 10); 972 } 973 974 return min_t(int, wm, USHRT_MAX); 975 } 976 977 static void vlv_compute_fifo(struct intel_crtc *crtc) 978 { 979 struct drm_device *dev = crtc->base.dev; 980 struct vlv_wm_state *wm_state = &crtc->wm_state; 981 struct intel_plane *plane; 982 unsigned int total_rate = 0; 983 const int fifo_size = 512 - 1; 984 int fifo_extra, fifo_left = fifo_size; 985 986 for_each_intel_plane_on_crtc(dev, crtc, plane) { 987 struct intel_plane_state *state = 988 to_intel_plane_state(plane->base.state); 989 990 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 991 continue; 992 993 if (state->visible) { 994 wm_state->num_active_planes++; 995 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 996 } 997 } 998 999 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1000 struct intel_plane_state *state = 1001 to_intel_plane_state(plane->base.state); 1002 unsigned int rate; 1003 1004 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1005 plane->wm.fifo_size = 63; 1006 continue; 1007 } 1008 1009 if (!state->visible) { 1010 plane->wm.fifo_size = 0; 1011 continue; 1012 } 1013 1014 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1015 plane->wm.fifo_size = fifo_size * rate / total_rate; 1016 fifo_left -= plane->wm.fifo_size; 1017 } 1018 1019 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1020 1021 /* spread the remainder evenly */ 1022 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1023 int plane_extra; 1024 1025 if (fifo_left == 0) 1026 break; 1027 1028 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1029 continue; 1030 1031 /* give it all to the first plane if none are active */ 1032 if (plane->wm.fifo_size == 0 && 1033 wm_state->num_active_planes) 1034 continue; 1035 1036 plane_extra = min(fifo_extra, fifo_left); 1037 plane->wm.fifo_size += plane_extra; 1038 fifo_left -= plane_extra; 1039 } 1040 1041 WARN_ON(fifo_left != 0); 1042 } 1043 1044 static void vlv_invert_wms(struct intel_crtc *crtc) 1045 { 1046 struct vlv_wm_state *wm_state = &crtc->wm_state; 1047 int level; 1048 1049 for (level = 0; level < wm_state->num_levels; level++) { 1050 struct drm_device *dev = crtc->base.dev; 1051 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1052 struct intel_plane *plane; 1053 1054 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1055 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1056 1057 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1058 switch (plane->base.type) { 1059 int sprite; 1060 case DRM_PLANE_TYPE_CURSOR: 1061 wm_state->wm[level].cursor = plane->wm.fifo_size - 1062 wm_state->wm[level].cursor; 1063 break; 1064 case DRM_PLANE_TYPE_PRIMARY: 1065 wm_state->wm[level].primary = plane->wm.fifo_size - 1066 wm_state->wm[level].primary; 1067 break; 1068 case DRM_PLANE_TYPE_OVERLAY: 1069 sprite = plane->plane; 1070 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1071 wm_state->wm[level].sprite[sprite]; 1072 break; 1073 } 1074 } 1075 } 1076 } 1077 1078 static void vlv_compute_wm(struct intel_crtc *crtc) 1079 { 1080 struct drm_device *dev = crtc->base.dev; 1081 struct vlv_wm_state *wm_state = &crtc->wm_state; 1082 struct intel_plane *plane; 1083 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1084 int level; 1085 1086 memset(wm_state, 0, sizeof(*wm_state)); 1087 1088 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1089 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1090 1091 wm_state->num_active_planes = 0; 1092 1093 vlv_compute_fifo(crtc); 1094 1095 if (wm_state->num_active_planes != 1) 1096 wm_state->cxsr = false; 1097 1098 if (wm_state->cxsr) { 1099 for (level = 0; level < wm_state->num_levels; level++) { 1100 wm_state->sr[level].plane = sr_fifo_size; 1101 wm_state->sr[level].cursor = 63; 1102 } 1103 } 1104 1105 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1106 struct intel_plane_state *state = 1107 to_intel_plane_state(plane->base.state); 1108 1109 if (!state->visible) 1110 continue; 1111 1112 /* normal watermarks */ 1113 for (level = 0; level < wm_state->num_levels; level++) { 1114 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1115 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1116 1117 /* hack */ 1118 if (WARN_ON(level == 0 && wm > max_wm)) 1119 wm = max_wm; 1120 1121 if (wm > plane->wm.fifo_size) 1122 break; 1123 1124 switch (plane->base.type) { 1125 int sprite; 1126 case DRM_PLANE_TYPE_CURSOR: 1127 wm_state->wm[level].cursor = wm; 1128 break; 1129 case DRM_PLANE_TYPE_PRIMARY: 1130 wm_state->wm[level].primary = wm; 1131 break; 1132 case DRM_PLANE_TYPE_OVERLAY: 1133 sprite = plane->plane; 1134 wm_state->wm[level].sprite[sprite] = wm; 1135 break; 1136 } 1137 } 1138 1139 wm_state->num_levels = level; 1140 1141 if (!wm_state->cxsr) 1142 continue; 1143 1144 /* maxfifo watermarks */ 1145 switch (plane->base.type) { 1146 int sprite, level; 1147 case DRM_PLANE_TYPE_CURSOR: 1148 for (level = 0; level < wm_state->num_levels; level++) 1149 wm_state->sr[level].cursor = 1150 wm_state->wm[level].cursor; 1151 break; 1152 case DRM_PLANE_TYPE_PRIMARY: 1153 for (level = 0; level < wm_state->num_levels; level++) 1154 wm_state->sr[level].plane = 1155 min(wm_state->sr[level].plane, 1156 wm_state->wm[level].primary); 1157 break; 1158 case DRM_PLANE_TYPE_OVERLAY: 1159 sprite = plane->plane; 1160 for (level = 0; level < wm_state->num_levels; level++) 1161 wm_state->sr[level].plane = 1162 min(wm_state->sr[level].plane, 1163 wm_state->wm[level].sprite[sprite]); 1164 break; 1165 } 1166 } 1167 1168 /* clear any (partially) filled invalid levels */ 1169 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1170 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1171 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1172 } 1173 1174 vlv_invert_wms(crtc); 1175 } 1176 1177 #define VLV_FIFO(plane, value) \ 1178 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1179 1180 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1181 { 1182 struct drm_device *dev = crtc->base.dev; 1183 struct drm_i915_private *dev_priv = to_i915(dev); 1184 struct intel_plane *plane; 1185 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1186 1187 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1188 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1189 WARN_ON(plane->wm.fifo_size != 63); 1190 continue; 1191 } 1192 1193 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1194 sprite0_start = plane->wm.fifo_size; 1195 else if (plane->plane == 0) 1196 sprite1_start = sprite0_start + plane->wm.fifo_size; 1197 else 1198 fifo_size = sprite1_start + plane->wm.fifo_size; 1199 } 1200 1201 WARN_ON(fifo_size != 512 - 1); 1202 1203 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1204 pipe_name(crtc->pipe), sprite0_start, 1205 sprite1_start, fifo_size); 1206 1207 switch (crtc->pipe) { 1208 uint32_t dsparb, dsparb2, dsparb3; 1209 case PIPE_A: 1210 dsparb = I915_READ(DSPARB); 1211 dsparb2 = I915_READ(DSPARB2); 1212 1213 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1214 VLV_FIFO(SPRITEB, 0xff)); 1215 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1216 VLV_FIFO(SPRITEB, sprite1_start)); 1217 1218 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1219 VLV_FIFO(SPRITEB_HI, 0x1)); 1220 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1221 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1222 1223 I915_WRITE(DSPARB, dsparb); 1224 I915_WRITE(DSPARB2, dsparb2); 1225 break; 1226 case PIPE_B: 1227 dsparb = I915_READ(DSPARB); 1228 dsparb2 = I915_READ(DSPARB2); 1229 1230 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1231 VLV_FIFO(SPRITED, 0xff)); 1232 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1233 VLV_FIFO(SPRITED, sprite1_start)); 1234 1235 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1236 VLV_FIFO(SPRITED_HI, 0xff)); 1237 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1238 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1239 1240 I915_WRITE(DSPARB, dsparb); 1241 I915_WRITE(DSPARB2, dsparb2); 1242 break; 1243 case PIPE_C: 1244 dsparb3 = I915_READ(DSPARB3); 1245 dsparb2 = I915_READ(DSPARB2); 1246 1247 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1248 VLV_FIFO(SPRITEF, 0xff)); 1249 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1250 VLV_FIFO(SPRITEF, sprite1_start)); 1251 1252 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1253 VLV_FIFO(SPRITEF_HI, 0xff)); 1254 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1255 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1256 1257 I915_WRITE(DSPARB3, dsparb3); 1258 I915_WRITE(DSPARB2, dsparb2); 1259 break; 1260 default: 1261 break; 1262 } 1263 } 1264 1265 #undef VLV_FIFO 1266 1267 static void vlv_merge_wm(struct drm_device *dev, 1268 struct vlv_wm_values *wm) 1269 { 1270 struct intel_crtc *crtc; 1271 int num_active_crtcs = 0; 1272 1273 wm->level = to_i915(dev)->wm.max_level; 1274 wm->cxsr = true; 1275 1276 for_each_intel_crtc(dev, crtc) { 1277 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1278 1279 if (!crtc->active) 1280 continue; 1281 1282 if (!wm_state->cxsr) 1283 wm->cxsr = false; 1284 1285 num_active_crtcs++; 1286 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1287 } 1288 1289 if (num_active_crtcs != 1) 1290 wm->cxsr = false; 1291 1292 if (num_active_crtcs > 1) 1293 wm->level = VLV_WM_LEVEL_PM2; 1294 1295 for_each_intel_crtc(dev, crtc) { 1296 struct vlv_wm_state *wm_state = &crtc->wm_state; 1297 enum i915_pipe pipe = crtc->pipe; 1298 1299 if (!crtc->active) 1300 continue; 1301 1302 wm->pipe[pipe] = wm_state->wm[wm->level]; 1303 if (wm->cxsr) 1304 wm->sr = wm_state->sr[wm->level]; 1305 1306 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1307 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1308 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1309 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1310 } 1311 } 1312 1313 static void vlv_update_wm(struct drm_crtc *crtc) 1314 { 1315 struct drm_device *dev = crtc->dev; 1316 struct drm_i915_private *dev_priv = dev->dev_private; 1317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1318 enum i915_pipe pipe = intel_crtc->pipe; 1319 struct vlv_wm_values wm = {}; 1320 1321 vlv_compute_wm(intel_crtc); 1322 vlv_merge_wm(dev, &wm); 1323 1324 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1325 /* FIXME should be part of crtc atomic commit */ 1326 vlv_pipe_set_fifo_size(intel_crtc); 1327 return; 1328 } 1329 1330 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1332 chv_set_memory_dvfs(dev_priv, false); 1333 1334 if (wm.level < VLV_WM_LEVEL_PM5 && 1335 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1336 chv_set_memory_pm5(dev_priv, false); 1337 1338 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1339 intel_set_memory_cxsr(dev_priv, false); 1340 1341 /* FIXME should be part of crtc atomic commit */ 1342 vlv_pipe_set_fifo_size(intel_crtc); 1343 1344 vlv_write_wm_values(intel_crtc, &wm); 1345 1346 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1347 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1348 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1349 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1350 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1351 1352 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1353 intel_set_memory_cxsr(dev_priv, true); 1354 1355 if (wm.level >= VLV_WM_LEVEL_PM5 && 1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1357 chv_set_memory_pm5(dev_priv, true); 1358 1359 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1360 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1361 chv_set_memory_dvfs(dev_priv, true); 1362 1363 dev_priv->wm.vlv = wm; 1364 } 1365 1366 #define single_plane_enabled(mask) is_power_of_2(mask) 1367 1368 static void g4x_update_wm(struct drm_crtc *crtc) 1369 { 1370 struct drm_device *dev = crtc->dev; 1371 static const int sr_latency_ns = 12000; 1372 struct drm_i915_private *dev_priv = dev->dev_private; 1373 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1374 int plane_sr, cursor_sr; 1375 unsigned int enabled = 0; 1376 bool cxsr_enabled; 1377 1378 if (g4x_compute_wm0(dev, PIPE_A, 1379 &g4x_wm_info, pessimal_latency_ns, 1380 &g4x_cursor_wm_info, pessimal_latency_ns, 1381 &planea_wm, &cursora_wm)) 1382 enabled |= 1 << PIPE_A; 1383 1384 if (g4x_compute_wm0(dev, PIPE_B, 1385 &g4x_wm_info, pessimal_latency_ns, 1386 &g4x_cursor_wm_info, pessimal_latency_ns, 1387 &planeb_wm, &cursorb_wm)) 1388 enabled |= 1 << PIPE_B; 1389 1390 if (single_plane_enabled(enabled) && 1391 g4x_compute_srwm(dev, ffs(enabled) - 1, 1392 sr_latency_ns, 1393 &g4x_wm_info, 1394 &g4x_cursor_wm_info, 1395 &plane_sr, &cursor_sr)) { 1396 cxsr_enabled = true; 1397 } else { 1398 cxsr_enabled = false; 1399 intel_set_memory_cxsr(dev_priv, false); 1400 plane_sr = cursor_sr = 0; 1401 } 1402 1403 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1404 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1405 planea_wm, cursora_wm, 1406 planeb_wm, cursorb_wm, 1407 plane_sr, cursor_sr); 1408 1409 I915_WRITE(DSPFW1, 1410 FW_WM(plane_sr, SR) | 1411 FW_WM(cursorb_wm, CURSORB) | 1412 FW_WM(planeb_wm, PLANEB) | 1413 FW_WM(planea_wm, PLANEA)); 1414 I915_WRITE(DSPFW2, 1415 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1416 FW_WM(cursora_wm, CURSORA)); 1417 /* HPLL off in SR has some issues on G4x... disable it */ 1418 I915_WRITE(DSPFW3, 1419 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1420 FW_WM(cursor_sr, CURSOR_SR)); 1421 1422 if (cxsr_enabled) 1423 intel_set_memory_cxsr(dev_priv, true); 1424 } 1425 1426 static void i965_update_wm(struct drm_crtc *unused_crtc) 1427 { 1428 struct drm_device *dev = unused_crtc->dev; 1429 struct drm_i915_private *dev_priv = dev->dev_private; 1430 struct drm_crtc *crtc; 1431 int srwm = 1; 1432 int cursor_sr = 16; 1433 bool cxsr_enabled; 1434 1435 /* Calc sr entries for one plane configs */ 1436 crtc = single_enabled_crtc(dev); 1437 if (crtc) { 1438 /* self-refresh has much higher latency */ 1439 static const int sr_latency_ns = 12000; 1440 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1441 int clock = adjusted_mode->crtc_clock; 1442 int htotal = adjusted_mode->crtc_htotal; 1443 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1444 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 1445 unsigned long line_time_us; 1446 int entries; 1447 1448 line_time_us = max(htotal * 1000 / clock, 1); 1449 1450 /* Use ns/us then divide to preserve precision */ 1451 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1452 pixel_size * hdisplay; 1453 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1454 srwm = I965_FIFO_SIZE - entries; 1455 if (srwm < 0) 1456 srwm = 1; 1457 srwm &= 0x1ff; 1458 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1459 entries, srwm); 1460 1461 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1462 pixel_size * crtc->cursor->state->crtc_w; 1463 entries = DIV_ROUND_UP(entries, 1464 i965_cursor_wm_info.cacheline_size); 1465 cursor_sr = i965_cursor_wm_info.fifo_size - 1466 (entries + i965_cursor_wm_info.guard_size); 1467 1468 if (cursor_sr > i965_cursor_wm_info.max_wm) 1469 cursor_sr = i965_cursor_wm_info.max_wm; 1470 1471 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1472 "cursor %d\n", srwm, cursor_sr); 1473 1474 cxsr_enabled = true; 1475 } else { 1476 cxsr_enabled = false; 1477 /* Turn off self refresh if both pipes are enabled */ 1478 intel_set_memory_cxsr(dev_priv, false); 1479 } 1480 1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1482 srwm); 1483 1484 /* 965 has limitations... */ 1485 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1486 FW_WM(8, CURSORB) | 1487 FW_WM(8, PLANEB) | 1488 FW_WM(8, PLANEA)); 1489 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1490 FW_WM(8, PLANEC_OLD)); 1491 /* update cursor SR watermark */ 1492 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1493 1494 if (cxsr_enabled) 1495 intel_set_memory_cxsr(dev_priv, true); 1496 } 1497 1498 #undef FW_WM 1499 1500 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1501 { 1502 struct drm_device *dev = unused_crtc->dev; 1503 struct drm_i915_private *dev_priv = dev->dev_private; 1504 const struct intel_watermark_params *wm_info; 1505 uint32_t fwater_lo; 1506 uint32_t fwater_hi; 1507 int cwm, srwm = 1; 1508 int fifo_size; 1509 int planea_wm, planeb_wm; 1510 struct drm_crtc *crtc, *enabled = NULL; 1511 1512 if (IS_I945GM(dev)) 1513 wm_info = &i945_wm_info; 1514 else if (!IS_GEN2(dev)) 1515 wm_info = &i915_wm_info; 1516 else 1517 wm_info = &i830_a_wm_info; 1518 1519 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1520 crtc = intel_get_crtc_for_plane(dev, 0); 1521 if (intel_crtc_active(crtc)) { 1522 const struct drm_display_mode *adjusted_mode; 1523 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1524 if (IS_GEN2(dev)) 1525 cpp = 4; 1526 1527 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1528 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1529 wm_info, fifo_size, cpp, 1530 pessimal_latency_ns); 1531 enabled = crtc; 1532 } else { 1533 planea_wm = fifo_size - wm_info->guard_size; 1534 if (planea_wm > (long)wm_info->max_wm) 1535 planea_wm = wm_info->max_wm; 1536 } 1537 1538 if (IS_GEN2(dev)) 1539 wm_info = &i830_bc_wm_info; 1540 1541 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1542 crtc = intel_get_crtc_for_plane(dev, 1); 1543 if (intel_crtc_active(crtc)) { 1544 const struct drm_display_mode *adjusted_mode; 1545 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1546 if (IS_GEN2(dev)) 1547 cpp = 4; 1548 1549 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1550 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1551 wm_info, fifo_size, cpp, 1552 pessimal_latency_ns); 1553 if (enabled == NULL) 1554 enabled = crtc; 1555 else 1556 enabled = NULL; 1557 } else { 1558 planeb_wm = fifo_size - wm_info->guard_size; 1559 if (planeb_wm > (long)wm_info->max_wm) 1560 planeb_wm = wm_info->max_wm; 1561 } 1562 1563 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1564 1565 if (IS_I915GM(dev) && enabled) { 1566 struct drm_i915_gem_object *obj; 1567 1568 obj = intel_fb_obj(enabled->primary->state->fb); 1569 1570 /* self-refresh seems busted with untiled */ 1571 if (obj->tiling_mode == I915_TILING_NONE) 1572 enabled = NULL; 1573 } 1574 1575 /* 1576 * Overlay gets an aggressive default since video jitter is bad. 1577 */ 1578 cwm = 2; 1579 1580 /* Play safe and disable self-refresh before adjusting watermarks. */ 1581 intel_set_memory_cxsr(dev_priv, false); 1582 1583 /* Calc sr entries for one plane configs */ 1584 if (HAS_FW_BLC(dev) && enabled) { 1585 /* self-refresh has much higher latency */ 1586 static const int sr_latency_ns = 6000; 1587 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; 1588 int clock = adjusted_mode->crtc_clock; 1589 int htotal = adjusted_mode->crtc_htotal; 1590 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1591 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; 1592 unsigned long line_time_us; 1593 int entries; 1594 1595 line_time_us = max(htotal * 1000 / clock, 1); 1596 1597 /* Use ns/us then divide to preserve precision */ 1598 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1599 pixel_size * hdisplay; 1600 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1601 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1602 srwm = wm_info->fifo_size - entries; 1603 if (srwm < 0) 1604 srwm = 1; 1605 1606 if (IS_I945G(dev) || IS_I945GM(dev)) 1607 I915_WRITE(FW_BLC_SELF, 1608 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1609 else if (IS_I915GM(dev)) 1610 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1611 } 1612 1613 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1614 planea_wm, planeb_wm, cwm, srwm); 1615 1616 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1617 fwater_hi = (cwm & 0x1f); 1618 1619 /* Set request length to 8 cachelines per fetch */ 1620 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1621 fwater_hi = fwater_hi | (1 << 8); 1622 1623 I915_WRITE(FW_BLC, fwater_lo); 1624 I915_WRITE(FW_BLC2, fwater_hi); 1625 1626 if (enabled) 1627 intel_set_memory_cxsr(dev_priv, true); 1628 } 1629 1630 static void i845_update_wm(struct drm_crtc *unused_crtc) 1631 { 1632 struct drm_device *dev = unused_crtc->dev; 1633 struct drm_i915_private *dev_priv = dev->dev_private; 1634 struct drm_crtc *crtc; 1635 const struct drm_display_mode *adjusted_mode; 1636 uint32_t fwater_lo; 1637 int planea_wm; 1638 1639 crtc = single_enabled_crtc(dev); 1640 if (crtc == NULL) 1641 return; 1642 1643 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1644 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1645 &i845_wm_info, 1646 dev_priv->display.get_fifo_size(dev, 0), 1647 4, pessimal_latency_ns); 1648 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1649 fwater_lo |= (3<<8) | planea_wm; 1650 1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1652 1653 I915_WRITE(FW_BLC, fwater_lo); 1654 } 1655 1656 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1657 { 1658 uint32_t pixel_rate; 1659 1660 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1661 1662 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1663 * adjust the pixel_rate here. */ 1664 1665 if (pipe_config->pch_pfit.enabled) { 1666 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1667 uint32_t pfit_size = pipe_config->pch_pfit.size; 1668 1669 pipe_w = pipe_config->pipe_src_w; 1670 pipe_h = pipe_config->pipe_src_h; 1671 1672 pfit_w = (pfit_size >> 16) & 0xFFFF; 1673 pfit_h = pfit_size & 0xFFFF; 1674 if (pipe_w < pfit_w) 1675 pipe_w = pfit_w; 1676 if (pipe_h < pfit_h) 1677 pipe_h = pfit_h; 1678 1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1680 pfit_w * pfit_h); 1681 } 1682 1683 return pixel_rate; 1684 } 1685 1686 /* latency must be in 0.1us units. */ 1687 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1688 uint32_t latency) 1689 { 1690 uint64_t ret; 1691 1692 if (WARN(latency == 0, "Latency value missing\n")) 1693 return UINT_MAX; 1694 1695 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1696 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1697 1698 return ret; 1699 } 1700 1701 /* latency must be in 0.1us units. */ 1702 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1703 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1704 uint32_t latency) 1705 { 1706 uint32_t ret; 1707 1708 if (WARN(latency == 0, "Latency value missing\n")) 1709 return UINT_MAX; 1710 1711 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1712 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1713 ret = DIV_ROUND_UP(ret, 64) + 2; 1714 return ret; 1715 } 1716 1717 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1718 uint8_t bytes_per_pixel) 1719 { 1720 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1721 } 1722 1723 struct skl_pipe_wm_parameters { 1724 bool active; 1725 uint32_t pipe_htotal; 1726 uint32_t pixel_rate; /* in KHz */ 1727 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; 1728 }; 1729 1730 struct ilk_wm_maximums { 1731 uint16_t pri; 1732 uint16_t spr; 1733 uint16_t cur; 1734 uint16_t fbc; 1735 }; 1736 1737 /* used in computing the new watermarks state */ 1738 struct intel_wm_config { 1739 unsigned int num_pipes_active; 1740 bool sprites_enabled; 1741 bool sprites_scaled; 1742 }; 1743 1744 /* 1745 * For both WM_PIPE and WM_LP. 1746 * mem_value must be in 0.1us units. 1747 */ 1748 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 1749 const struct intel_plane_state *pstate, 1750 uint32_t mem_value, 1751 bool is_lp) 1752 { 1753 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1754 uint32_t method1, method2; 1755 1756 if (!cstate->base.active || !pstate->visible) 1757 return 0; 1758 1759 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1760 1761 if (!is_lp) 1762 return method1; 1763 1764 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1765 cstate->base.adjusted_mode.crtc_htotal, 1766 drm_rect_width(&pstate->dst), 1767 bpp, 1768 mem_value); 1769 1770 return min(method1, method2); 1771 } 1772 1773 /* 1774 * For both WM_PIPE and WM_LP. 1775 * mem_value must be in 0.1us units. 1776 */ 1777 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 1778 const struct intel_plane_state *pstate, 1779 uint32_t mem_value) 1780 { 1781 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1782 uint32_t method1, method2; 1783 1784 if (!cstate->base.active || !pstate->visible) 1785 return 0; 1786 1787 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1788 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1789 cstate->base.adjusted_mode.crtc_htotal, 1790 drm_rect_width(&pstate->dst), 1791 bpp, 1792 mem_value); 1793 return min(method1, method2); 1794 } 1795 1796 /* 1797 * For both WM_PIPE and WM_LP. 1798 * mem_value must be in 0.1us units. 1799 */ 1800 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 1801 const struct intel_plane_state *pstate, 1802 uint32_t mem_value) 1803 { 1804 /* 1805 * We treat the cursor plane as always-on for the purposes of watermark 1806 * calculation. Until we have two-stage watermark programming merged, 1807 * this is necessary to avoid flickering. 1808 */ 1809 int cpp = 4; 1810 int width = pstate->visible ? pstate->base.crtc_w : 64; 1811 1812 if (!cstate->base.active) 1813 return 0; 1814 1815 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1816 cstate->base.adjusted_mode.crtc_htotal, 1817 width, cpp, mem_value); 1818 } 1819 1820 /* Only for WM_LP. */ 1821 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 1822 const struct intel_plane_state *pstate, 1823 uint32_t pri_val) 1824 { 1825 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1826 1827 if (!cstate->base.active || !pstate->visible) 1828 return 0; 1829 1830 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); 1831 } 1832 1833 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1834 { 1835 if (INTEL_INFO(dev)->gen >= 8) 1836 return 3072; 1837 else if (INTEL_INFO(dev)->gen >= 7) 1838 return 768; 1839 else 1840 return 512; 1841 } 1842 1843 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1844 int level, bool is_sprite) 1845 { 1846 if (INTEL_INFO(dev)->gen >= 8) 1847 /* BDW primary/sprite plane watermarks */ 1848 return level == 0 ? 255 : 2047; 1849 else if (INTEL_INFO(dev)->gen >= 7) 1850 /* IVB/HSW primary/sprite plane watermarks */ 1851 return level == 0 ? 127 : 1023; 1852 else if (!is_sprite) 1853 /* ILK/SNB primary plane watermarks */ 1854 return level == 0 ? 127 : 511; 1855 else 1856 /* ILK/SNB sprite plane watermarks */ 1857 return level == 0 ? 63 : 255; 1858 } 1859 1860 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1861 int level) 1862 { 1863 if (INTEL_INFO(dev)->gen >= 7) 1864 return level == 0 ? 63 : 255; 1865 else 1866 return level == 0 ? 31 : 63; 1867 } 1868 1869 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1870 { 1871 if (INTEL_INFO(dev)->gen >= 8) 1872 return 31; 1873 else 1874 return 15; 1875 } 1876 1877 /* Calculate the maximum primary/sprite plane watermark */ 1878 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1879 int level, 1880 const struct intel_wm_config *config, 1881 enum intel_ddb_partitioning ddb_partitioning, 1882 bool is_sprite) 1883 { 1884 unsigned int fifo_size = ilk_display_fifo_size(dev); 1885 1886 /* if sprites aren't enabled, sprites get nothing */ 1887 if (is_sprite && !config->sprites_enabled) 1888 return 0; 1889 1890 /* HSW allows LP1+ watermarks even with multiple pipes */ 1891 if (level == 0 || config->num_pipes_active > 1) { 1892 fifo_size /= INTEL_INFO(dev)->num_pipes; 1893 1894 /* 1895 * For some reason the non self refresh 1896 * FIFO size is only half of the self 1897 * refresh FIFO size on ILK/SNB. 1898 */ 1899 if (INTEL_INFO(dev)->gen <= 6) 1900 fifo_size /= 2; 1901 } 1902 1903 if (config->sprites_enabled) { 1904 /* level 0 is always calculated with 1:1 split */ 1905 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1906 if (is_sprite) 1907 fifo_size *= 5; 1908 fifo_size /= 6; 1909 } else { 1910 fifo_size /= 2; 1911 } 1912 } 1913 1914 /* clamp to max that the registers can hold */ 1915 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1916 } 1917 1918 /* Calculate the maximum cursor plane watermark */ 1919 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1920 int level, 1921 const struct intel_wm_config *config) 1922 { 1923 /* HSW LP1+ watermarks w/ multiple pipes */ 1924 if (level > 0 && config->num_pipes_active > 1) 1925 return 64; 1926 1927 /* otherwise just report max that registers can hold */ 1928 return ilk_cursor_wm_reg_max(dev, level); 1929 } 1930 1931 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1932 int level, 1933 const struct intel_wm_config *config, 1934 enum intel_ddb_partitioning ddb_partitioning, 1935 struct ilk_wm_maximums *max) 1936 { 1937 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1938 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1939 max->cur = ilk_cursor_wm_max(dev, level, config); 1940 max->fbc = ilk_fbc_wm_reg_max(dev); 1941 } 1942 1943 static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 1944 int level, 1945 struct ilk_wm_maximums *max) 1946 { 1947 max->pri = ilk_plane_wm_reg_max(dev, level, false); 1948 max->spr = ilk_plane_wm_reg_max(dev, level, true); 1949 max->cur = ilk_cursor_wm_reg_max(dev, level); 1950 max->fbc = ilk_fbc_wm_reg_max(dev); 1951 } 1952 1953 static bool ilk_validate_wm_level(int level, 1954 const struct ilk_wm_maximums *max, 1955 struct intel_wm_level *result) 1956 { 1957 bool ret; 1958 1959 /* already determined to be invalid? */ 1960 if (!result->enable) 1961 return false; 1962 1963 result->enable = result->pri_val <= max->pri && 1964 result->spr_val <= max->spr && 1965 result->cur_val <= max->cur; 1966 1967 ret = result->enable; 1968 1969 /* 1970 * HACK until we can pre-compute everything, 1971 * and thus fail gracefully if LP0 watermarks 1972 * are exceeded... 1973 */ 1974 if (level == 0 && !result->enable) { 1975 if (result->pri_val > max->pri) 1976 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1977 level, result->pri_val, max->pri); 1978 if (result->spr_val > max->spr) 1979 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1980 level, result->spr_val, max->spr); 1981 if (result->cur_val > max->cur) 1982 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1983 level, result->cur_val, max->cur); 1984 1985 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1986 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1987 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1988 result->enable = true; 1989 } 1990 1991 return ret; 1992 } 1993 1994 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 1995 const struct intel_crtc *intel_crtc, 1996 int level, 1997 struct intel_crtc_state *cstate, 1998 struct intel_wm_level *result) 1999 { 2000 struct intel_plane *intel_plane; 2001 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 2002 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 2003 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 2004 2005 /* WM1+ latency values stored in 0.5us units */ 2006 if (level > 0) { 2007 pri_latency *= 5; 2008 spr_latency *= 5; 2009 cur_latency *= 5; 2010 } 2011 2012 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { 2013 struct intel_plane_state *pstate = 2014 to_intel_plane_state(intel_plane->base.state); 2015 2016 switch (intel_plane->base.type) { 2017 case DRM_PLANE_TYPE_PRIMARY: 2018 result->pri_val = ilk_compute_pri_wm(cstate, pstate, 2019 pri_latency, 2020 level); 2021 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, 2022 result->pri_val); 2023 break; 2024 case DRM_PLANE_TYPE_OVERLAY: 2025 result->spr_val = ilk_compute_spr_wm(cstate, pstate, 2026 spr_latency); 2027 break; 2028 case DRM_PLANE_TYPE_CURSOR: 2029 result->cur_val = ilk_compute_cur_wm(cstate, pstate, 2030 cur_latency); 2031 break; 2032 } 2033 } 2034 2035 result->enable = true; 2036 } 2037 2038 static uint32_t 2039 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 2040 { 2041 struct drm_i915_private *dev_priv = dev->dev_private; 2042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2043 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 2044 u32 linetime, ips_linetime; 2045 2046 if (!intel_crtc->active) 2047 return 0; 2048 2049 /* The WM are computed with base on how long it takes to fill a single 2050 * row at the given clock rate, multiplied by 8. 2051 * */ 2052 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2053 adjusted_mode->crtc_clock); 2054 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2055 dev_priv->cdclk_freq); 2056 2057 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2058 PIPE_WM_LINETIME_TIME(linetime); 2059 } 2060 2061 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2062 { 2063 struct drm_i915_private *dev_priv = dev->dev_private; 2064 2065 if (IS_GEN9(dev)) { 2066 uint32_t val; 2067 int ret, i; 2068 int level, max_level = ilk_wm_max_level(dev); 2069 2070 /* read the first set of memory latencies[0:3] */ 2071 val = 0; /* data0 to be programmed to 0 for first set */ 2072 mutex_lock(&dev_priv->rps.hw_lock); 2073 ret = sandybridge_pcode_read(dev_priv, 2074 GEN9_PCODE_READ_MEM_LATENCY, 2075 &val); 2076 mutex_unlock(&dev_priv->rps.hw_lock); 2077 2078 if (ret) { 2079 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2080 return; 2081 } 2082 2083 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2084 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2085 GEN9_MEM_LATENCY_LEVEL_MASK; 2086 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2087 GEN9_MEM_LATENCY_LEVEL_MASK; 2088 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2089 GEN9_MEM_LATENCY_LEVEL_MASK; 2090 2091 /* read the second set of memory latencies[4:7] */ 2092 val = 1; /* data0 to be programmed to 1 for second set */ 2093 mutex_lock(&dev_priv->rps.hw_lock); 2094 ret = sandybridge_pcode_read(dev_priv, 2095 GEN9_PCODE_READ_MEM_LATENCY, 2096 &val); 2097 mutex_unlock(&dev_priv->rps.hw_lock); 2098 if (ret) { 2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2100 return; 2101 } 2102 2103 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2104 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2105 GEN9_MEM_LATENCY_LEVEL_MASK; 2106 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2107 GEN9_MEM_LATENCY_LEVEL_MASK; 2108 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2109 GEN9_MEM_LATENCY_LEVEL_MASK; 2110 2111 /* 2112 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 2113 * need to be disabled. We make sure to sanitize the values out 2114 * of the punit to satisfy this requirement. 2115 */ 2116 for (level = 1; level <= max_level; level++) { 2117 if (wm[level] == 0) { 2118 for (i = level + 1; i <= max_level; i++) 2119 wm[i] = 0; 2120 break; 2121 } 2122 } 2123 2124 /* 2125 * WaWmMemoryReadLatency:skl 2126 * 2127 * punit doesn't take into account the read latency so we need 2128 * to add 2us to the various latency levels we retrieve from the 2129 * punit when level 0 response data us 0us. 2130 */ 2131 if (wm[0] == 0) { 2132 wm[0] += 2; 2133 for (level = 1; level <= max_level; level++) { 2134 if (wm[level] == 0) 2135 break; 2136 wm[level] += 2; 2137 } 2138 } 2139 2140 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2141 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2142 2143 wm[0] = (sskpd >> 56) & 0xFF; 2144 if (wm[0] == 0) 2145 wm[0] = sskpd & 0xF; 2146 wm[1] = (sskpd >> 4) & 0xFF; 2147 wm[2] = (sskpd >> 12) & 0xFF; 2148 wm[3] = (sskpd >> 20) & 0x1FF; 2149 wm[4] = (sskpd >> 32) & 0x1FF; 2150 } else if (INTEL_INFO(dev)->gen >= 6) { 2151 uint32_t sskpd = I915_READ(MCH_SSKPD); 2152 2153 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2154 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2155 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2156 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2157 } else if (INTEL_INFO(dev)->gen >= 5) { 2158 uint32_t mltr = I915_READ(MLTR_ILK); 2159 2160 /* ILK primary LP0 latency is 700 ns */ 2161 wm[0] = 7; 2162 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2163 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2164 } 2165 } 2166 2167 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2168 { 2169 /* ILK sprite LP0 latency is 1300 ns */ 2170 if (INTEL_INFO(dev)->gen == 5) 2171 wm[0] = 13; 2172 } 2173 2174 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2175 { 2176 /* ILK cursor LP0 latency is 1300 ns */ 2177 if (INTEL_INFO(dev)->gen == 5) 2178 wm[0] = 13; 2179 2180 /* WaDoubleCursorLP3Latency:ivb */ 2181 if (IS_IVYBRIDGE(dev)) 2182 wm[3] *= 2; 2183 } 2184 2185 int ilk_wm_max_level(const struct drm_device *dev) 2186 { 2187 /* how many WM levels are we expecting */ 2188 if (INTEL_INFO(dev)->gen >= 9) 2189 return 7; 2190 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2191 return 4; 2192 else if (INTEL_INFO(dev)->gen >= 6) 2193 return 3; 2194 else 2195 return 2; 2196 } 2197 2198 static void intel_print_wm_latency(struct drm_device *dev, 2199 const char *name, 2200 const uint16_t wm[8]) 2201 { 2202 int level, max_level = ilk_wm_max_level(dev); 2203 2204 for (level = 0; level <= max_level; level++) { 2205 unsigned int latency = wm[level]; 2206 2207 if (latency == 0) { 2208 DRM_ERROR("%s WM%d latency not provided\n", 2209 name, level); 2210 continue; 2211 } 2212 2213 /* 2214 * - latencies are in us on gen9. 2215 * - before then, WM1+ latency values are in 0.5us units 2216 */ 2217 if (IS_GEN9(dev)) 2218 latency *= 10; 2219 else if (level > 0) 2220 latency *= 5; 2221 2222 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2223 name, level, wm[level], 2224 latency / 10, latency % 10); 2225 } 2226 } 2227 2228 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2229 uint16_t wm[5], uint16_t min) 2230 { 2231 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2232 2233 if (wm[0] >= min) 2234 return false; 2235 2236 wm[0] = max(wm[0], min); 2237 for (level = 1; level <= max_level; level++) 2238 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2239 2240 return true; 2241 } 2242 2243 static void snb_wm_latency_quirk(struct drm_device *dev) 2244 { 2245 struct drm_i915_private *dev_priv = dev->dev_private; 2246 bool changed; 2247 2248 /* 2249 * The BIOS provided WM memory latency values are often 2250 * inadequate for high resolution displays. Adjust them. 2251 */ 2252 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2253 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2254 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2255 2256 if (!changed) 2257 return; 2258 2259 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2260 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2261 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2262 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2263 } 2264 2265 static void ilk_setup_wm_latency(struct drm_device *dev) 2266 { 2267 struct drm_i915_private *dev_priv = dev->dev_private; 2268 2269 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2270 2271 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2272 sizeof(dev_priv->wm.pri_latency)); 2273 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2274 sizeof(dev_priv->wm.pri_latency)); 2275 2276 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2277 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2278 2279 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2280 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2281 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2282 2283 if (IS_GEN6(dev)) 2284 snb_wm_latency_quirk(dev); 2285 } 2286 2287 static void skl_setup_wm_latency(struct drm_device *dev) 2288 { 2289 struct drm_i915_private *dev_priv = dev->dev_private; 2290 2291 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2292 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2293 } 2294 2295 static void ilk_compute_wm_config(struct drm_device *dev, 2296 struct intel_wm_config *config) 2297 { 2298 struct intel_crtc *intel_crtc; 2299 2300 /* Compute the currently _active_ config */ 2301 for_each_intel_crtc(dev, intel_crtc) { 2302 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; 2303 2304 if (!wm->pipe_enabled) 2305 continue; 2306 2307 config->sprites_enabled |= wm->sprites_enabled; 2308 config->sprites_scaled |= wm->sprites_scaled; 2309 config->num_pipes_active++; 2310 } 2311 } 2312 2313 /* Compute new watermarks for the pipe */ 2314 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, 2315 struct intel_pipe_wm *pipe_wm) 2316 { 2317 struct drm_crtc *crtc = cstate->base.crtc; 2318 struct drm_device *dev = crtc->dev; 2319 const struct drm_i915_private *dev_priv = dev->dev_private; 2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2321 struct intel_plane *intel_plane; 2322 struct intel_plane_state *sprstate = NULL; 2323 int level, max_level = ilk_wm_max_level(dev); 2324 /* LP0 watermark maximums depend on this pipe alone */ 2325 struct intel_wm_config config = { 2326 .num_pipes_active = 1, 2327 }; 2328 struct ilk_wm_maximums max; 2329 2330 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2331 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { 2332 sprstate = to_intel_plane_state(intel_plane->base.state); 2333 break; 2334 } 2335 } 2336 2337 config.sprites_enabled = sprstate->visible; 2338 config.sprites_scaled = sprstate->visible && 2339 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || 2340 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); 2341 2342 pipe_wm->pipe_enabled = cstate->base.active; 2343 pipe_wm->sprites_enabled = sprstate->visible; 2344 pipe_wm->sprites_scaled = config.sprites_scaled; 2345 2346 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2347 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) 2348 max_level = 1; 2349 2350 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2351 if (config.sprites_scaled) 2352 max_level = 0; 2353 2354 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); 2355 2356 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2357 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2358 2359 /* LP0 watermarks always use 1/2 DDB partitioning */ 2360 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2361 2362 /* At least LP0 must be valid */ 2363 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2364 return false; 2365 2366 ilk_compute_wm_reg_maximums(dev, 1, &max); 2367 2368 for (level = 1; level <= max_level; level++) { 2369 struct intel_wm_level wm = {}; 2370 2371 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); 2372 2373 /* 2374 * Disable any watermark level that exceeds the 2375 * register maximums since such watermarks are 2376 * always invalid. 2377 */ 2378 if (!ilk_validate_wm_level(level, &max, &wm)) 2379 break; 2380 2381 pipe_wm->wm[level] = wm; 2382 } 2383 2384 return true; 2385 } 2386 2387 /* 2388 * Merge the watermarks from all active pipes for a specific level. 2389 */ 2390 static void ilk_merge_wm_level(struct drm_device *dev, 2391 int level, 2392 struct intel_wm_level *ret_wm) 2393 { 2394 const struct intel_crtc *intel_crtc; 2395 2396 ret_wm->enable = true; 2397 2398 for_each_intel_crtc(dev, intel_crtc) { 2399 const struct intel_pipe_wm *active = &intel_crtc->wm.active; 2400 const struct intel_wm_level *wm = &active->wm[level]; 2401 2402 if (!active->pipe_enabled) 2403 continue; 2404 2405 /* 2406 * The watermark values may have been used in the past, 2407 * so we must maintain them in the registers for some 2408 * time even if the level is now disabled. 2409 */ 2410 if (!wm->enable) 2411 ret_wm->enable = false; 2412 2413 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2414 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2415 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2416 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2417 } 2418 } 2419 2420 /* 2421 * Merge all low power watermarks for all active pipes. 2422 */ 2423 static void ilk_wm_merge(struct drm_device *dev, 2424 const struct intel_wm_config *config, 2425 const struct ilk_wm_maximums *max, 2426 struct intel_pipe_wm *merged) 2427 { 2428 struct drm_i915_private *dev_priv = dev->dev_private; 2429 int level, max_level = ilk_wm_max_level(dev); 2430 int last_enabled_level = max_level; 2431 2432 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2433 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2434 config->num_pipes_active > 1) 2435 return; 2436 2437 /* ILK: FBC WM must be disabled always */ 2438 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2439 2440 /* merge each WM1+ level */ 2441 for (level = 1; level <= max_level; level++) { 2442 struct intel_wm_level *wm = &merged->wm[level]; 2443 2444 ilk_merge_wm_level(dev, level, wm); 2445 2446 if (level > last_enabled_level) 2447 wm->enable = false; 2448 else if (!ilk_validate_wm_level(level, max, wm)) 2449 /* make sure all following levels get disabled */ 2450 last_enabled_level = level - 1; 2451 2452 /* 2453 * The spec says it is preferred to disable 2454 * FBC WMs instead of disabling a WM level. 2455 */ 2456 if (wm->fbc_val > max->fbc) { 2457 if (wm->enable) 2458 merged->fbc_wm_enabled = false; 2459 wm->fbc_val = 0; 2460 } 2461 } 2462 2463 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2464 /* 2465 * FIXME this is racy. FBC might get enabled later. 2466 * What we should check here is whether FBC can be 2467 * enabled sometime later. 2468 */ 2469 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2470 intel_fbc_enabled(dev_priv)) { 2471 for (level = 2; level <= max_level; level++) { 2472 struct intel_wm_level *wm = &merged->wm[level]; 2473 2474 wm->enable = false; 2475 } 2476 } 2477 } 2478 2479 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2480 { 2481 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2482 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2483 } 2484 2485 /* The value we need to program into the WM_LPx latency field */ 2486 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2487 { 2488 struct drm_i915_private *dev_priv = dev->dev_private; 2489 2490 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2491 return 2 * level; 2492 else 2493 return dev_priv->wm.pri_latency[level]; 2494 } 2495 2496 static void ilk_compute_wm_results(struct drm_device *dev, 2497 const struct intel_pipe_wm *merged, 2498 enum intel_ddb_partitioning partitioning, 2499 struct ilk_wm_values *results) 2500 { 2501 struct intel_crtc *intel_crtc; 2502 int level, wm_lp; 2503 2504 results->enable_fbc_wm = merged->fbc_wm_enabled; 2505 results->partitioning = partitioning; 2506 2507 /* LP1+ register values */ 2508 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2509 const struct intel_wm_level *r; 2510 2511 level = ilk_wm_lp_to_level(wm_lp, merged); 2512 2513 r = &merged->wm[level]; 2514 2515 /* 2516 * Maintain the watermark values even if the level is 2517 * disabled. Doing otherwise could cause underruns. 2518 */ 2519 results->wm_lp[wm_lp - 1] = 2520 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2521 (r->pri_val << WM1_LP_SR_SHIFT) | 2522 r->cur_val; 2523 2524 if (r->enable) 2525 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2526 2527 if (INTEL_INFO(dev)->gen >= 8) 2528 results->wm_lp[wm_lp - 1] |= 2529 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2530 else 2531 results->wm_lp[wm_lp - 1] |= 2532 r->fbc_val << WM1_LP_FBC_SHIFT; 2533 2534 /* 2535 * Always set WM1S_LP_EN when spr_val != 0, even if the 2536 * level is disabled. Doing otherwise could cause underruns. 2537 */ 2538 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2539 WARN_ON(wm_lp != 1); 2540 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2541 } else 2542 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2543 } 2544 2545 /* LP0 register values */ 2546 for_each_intel_crtc(dev, intel_crtc) { 2547 enum i915_pipe pipe = intel_crtc->pipe; 2548 const struct intel_wm_level *r = 2549 &intel_crtc->wm.active.wm[0]; 2550 2551 if (WARN_ON(!r->enable)) 2552 continue; 2553 2554 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2555 2556 results->wm_pipe[pipe] = 2557 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2558 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2559 r->cur_val; 2560 } 2561 } 2562 2563 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2564 * case both are at the same level. Prefer r1 in case they're the same. */ 2565 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2566 struct intel_pipe_wm *r1, 2567 struct intel_pipe_wm *r2) 2568 { 2569 int level, max_level = ilk_wm_max_level(dev); 2570 int level1 = 0, level2 = 0; 2571 2572 for (level = 1; level <= max_level; level++) { 2573 if (r1->wm[level].enable) 2574 level1 = level; 2575 if (r2->wm[level].enable) 2576 level2 = level; 2577 } 2578 2579 if (level1 == level2) { 2580 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2581 return r2; 2582 else 2583 return r1; 2584 } else if (level1 > level2) { 2585 return r1; 2586 } else { 2587 return r2; 2588 } 2589 } 2590 2591 /* dirty bits used to track which watermarks need changes */ 2592 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2593 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2594 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2595 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2596 #define WM_DIRTY_FBC (1 << 24) 2597 #define WM_DIRTY_DDB (1 << 25) 2598 2599 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2600 const struct ilk_wm_values *old, 2601 const struct ilk_wm_values *new) 2602 { 2603 unsigned int dirty = 0; 2604 enum i915_pipe pipe; 2605 int wm_lp; 2606 2607 for_each_pipe(dev_priv, pipe) { 2608 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2609 dirty |= WM_DIRTY_LINETIME(pipe); 2610 /* Must disable LP1+ watermarks too */ 2611 dirty |= WM_DIRTY_LP_ALL; 2612 } 2613 2614 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2615 dirty |= WM_DIRTY_PIPE(pipe); 2616 /* Must disable LP1+ watermarks too */ 2617 dirty |= WM_DIRTY_LP_ALL; 2618 } 2619 } 2620 2621 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2622 dirty |= WM_DIRTY_FBC; 2623 /* Must disable LP1+ watermarks too */ 2624 dirty |= WM_DIRTY_LP_ALL; 2625 } 2626 2627 if (old->partitioning != new->partitioning) { 2628 dirty |= WM_DIRTY_DDB; 2629 /* Must disable LP1+ watermarks too */ 2630 dirty |= WM_DIRTY_LP_ALL; 2631 } 2632 2633 /* LP1+ watermarks already deemed dirty, no need to continue */ 2634 if (dirty & WM_DIRTY_LP_ALL) 2635 return dirty; 2636 2637 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2638 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2639 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2640 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2641 break; 2642 } 2643 2644 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2645 for (; wm_lp <= 3; wm_lp++) 2646 dirty |= WM_DIRTY_LP(wm_lp); 2647 2648 return dirty; 2649 } 2650 2651 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2652 unsigned int dirty) 2653 { 2654 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2655 bool changed = false; 2656 2657 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2658 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2659 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2660 changed = true; 2661 } 2662 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2663 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2664 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2665 changed = true; 2666 } 2667 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2668 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2669 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2670 changed = true; 2671 } 2672 2673 /* 2674 * Don't touch WM1S_LP_EN here. 2675 * Doing so could cause underruns. 2676 */ 2677 2678 return changed; 2679 } 2680 2681 /* 2682 * The spec says we shouldn't write when we don't need, because every write 2683 * causes WMs to be re-evaluated, expending some power. 2684 */ 2685 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2686 struct ilk_wm_values *results) 2687 { 2688 struct drm_device *dev = dev_priv->dev; 2689 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2690 unsigned int dirty; 2691 uint32_t val; 2692 2693 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2694 if (!dirty) 2695 return; 2696 2697 _ilk_disable_lp_wm(dev_priv, dirty); 2698 2699 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2700 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2701 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2702 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2703 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2704 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2705 2706 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2707 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2708 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2709 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2710 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2711 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2712 2713 if (dirty & WM_DIRTY_DDB) { 2714 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2715 val = I915_READ(WM_MISC); 2716 if (results->partitioning == INTEL_DDB_PART_1_2) 2717 val &= ~WM_MISC_DATA_PARTITION_5_6; 2718 else 2719 val |= WM_MISC_DATA_PARTITION_5_6; 2720 I915_WRITE(WM_MISC, val); 2721 } else { 2722 val = I915_READ(DISP_ARB_CTL2); 2723 if (results->partitioning == INTEL_DDB_PART_1_2) 2724 val &= ~DISP_DATA_PARTITION_5_6; 2725 else 2726 val |= DISP_DATA_PARTITION_5_6; 2727 I915_WRITE(DISP_ARB_CTL2, val); 2728 } 2729 } 2730 2731 if (dirty & WM_DIRTY_FBC) { 2732 val = I915_READ(DISP_ARB_CTL); 2733 if (results->enable_fbc_wm) 2734 val &= ~DISP_FBC_WM_DIS; 2735 else 2736 val |= DISP_FBC_WM_DIS; 2737 I915_WRITE(DISP_ARB_CTL, val); 2738 } 2739 2740 if (dirty & WM_DIRTY_LP(1) && 2741 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2742 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2743 2744 if (INTEL_INFO(dev)->gen >= 7) { 2745 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2746 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2747 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2748 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2749 } 2750 2751 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2752 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2753 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2754 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2755 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2756 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2757 2758 dev_priv->wm.hw = *results; 2759 } 2760 2761 static bool ilk_disable_lp_wm(struct drm_device *dev) 2762 { 2763 struct drm_i915_private *dev_priv = dev->dev_private; 2764 2765 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2766 } 2767 2768 /* 2769 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2770 * different active planes. 2771 */ 2772 2773 #define SKL_DDB_SIZE 896 /* in blocks */ 2774 #define BXT_DDB_SIZE 512 2775 2776 static void 2777 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2778 struct drm_crtc *for_crtc, 2779 const struct intel_wm_config *config, 2780 const struct skl_pipe_wm_parameters *params, 2781 struct skl_ddb_entry *alloc /* out */) 2782 { 2783 struct drm_crtc *crtc; 2784 unsigned int pipe_size, ddb_size; 2785 int nth_active_pipe; 2786 2787 if (!params->active) { 2788 alloc->start = 0; 2789 alloc->end = 0; 2790 return; 2791 } 2792 2793 if (IS_BROXTON(dev)) 2794 ddb_size = BXT_DDB_SIZE; 2795 else 2796 ddb_size = SKL_DDB_SIZE; 2797 2798 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2799 2800 nth_active_pipe = 0; 2801 for_each_crtc(dev, crtc) { 2802 if (!to_intel_crtc(crtc)->active) 2803 continue; 2804 2805 if (crtc == for_crtc) 2806 break; 2807 2808 nth_active_pipe++; 2809 } 2810 2811 pipe_size = ddb_size / config->num_pipes_active; 2812 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2813 alloc->end = alloc->start + pipe_size; 2814 } 2815 2816 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2817 { 2818 if (config->num_pipes_active == 1) 2819 return 32; 2820 2821 return 8; 2822 } 2823 2824 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2825 { 2826 entry->start = reg & 0x3ff; 2827 entry->end = (reg >> 16) & 0x3ff; 2828 if (entry->end) 2829 entry->end += 1; 2830 } 2831 2832 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2833 struct skl_ddb_allocation *ddb /* out */) 2834 { 2835 enum i915_pipe pipe; 2836 int plane; 2837 u32 val; 2838 2839 memset(ddb, 0, sizeof(*ddb)); 2840 2841 for_each_pipe(dev_priv, pipe) { 2842 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) 2843 continue; 2844 2845 for_each_plane(dev_priv, pipe, plane) { 2846 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2847 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2848 val); 2849 } 2850 2851 val = I915_READ(CUR_BUF_CFG(pipe)); 2852 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], 2853 val); 2854 } 2855 } 2856 2857 static unsigned int 2858 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) 2859 { 2860 2861 /* for planar format */ 2862 if (p->y_bytes_per_pixel) { 2863 if (y) /* y-plane data rate */ 2864 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; 2865 else /* uv-plane data rate */ 2866 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; 2867 } 2868 2869 /* for packed formats */ 2870 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; 2871 } 2872 2873 /* 2874 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2875 * a 8192x4096@32bpp framebuffer: 2876 * 3 * 4096 * 8192 * 4 < 2^32 2877 */ 2878 static unsigned int 2879 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, 2880 const struct skl_pipe_wm_parameters *params) 2881 { 2882 unsigned int total_data_rate = 0; 2883 int plane; 2884 2885 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2886 const struct intel_plane_wm_parameters *p; 2887 2888 p = ¶ms->plane[plane]; 2889 if (!p->enabled) 2890 continue; 2891 2892 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ 2893 if (p->y_bytes_per_pixel) { 2894 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ 2895 } 2896 } 2897 2898 return total_data_rate; 2899 } 2900 2901 static void 2902 skl_allocate_pipe_ddb(struct drm_crtc *crtc, 2903 const struct intel_wm_config *config, 2904 const struct skl_pipe_wm_parameters *params, 2905 struct skl_ddb_allocation *ddb /* out */) 2906 { 2907 struct drm_device *dev = crtc->dev; 2908 struct drm_i915_private *dev_priv = dev->dev_private; 2909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2910 enum i915_pipe pipe = intel_crtc->pipe; 2911 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2912 uint16_t alloc_size, start, cursor_blocks; 2913 uint16_t minimum[I915_MAX_PLANES]; 2914 uint16_t y_minimum[I915_MAX_PLANES]; 2915 unsigned int total_data_rate; 2916 int plane; 2917 2918 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); 2919 alloc_size = skl_ddb_entry_size(alloc); 2920 if (alloc_size == 0) { 2921 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2922 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, 2923 sizeof(ddb->plane[pipe][PLANE_CURSOR])); 2924 return; 2925 } 2926 2927 cursor_blocks = skl_cursor_allocation(config); 2928 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; 2929 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; 2930 2931 alloc_size -= cursor_blocks; 2932 alloc->end -= cursor_blocks; 2933 2934 /* 1. Allocate the mininum required blocks for each active plane */ 2935 for_each_plane(dev_priv, pipe, plane) { 2936 const struct intel_plane_wm_parameters *p; 2937 2938 p = ¶ms->plane[plane]; 2939 if (!p->enabled) 2940 continue; 2941 2942 minimum[plane] = 8; 2943 alloc_size -= minimum[plane]; 2944 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; 2945 alloc_size -= y_minimum[plane]; 2946 } 2947 2948 /* 2949 * 2. Distribute the remaining space in proportion to the amount of 2950 * data each plane needs to fetch from memory. 2951 * 2952 * FIXME: we may not allocate every single block here. 2953 */ 2954 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); 2955 2956 start = alloc->start; 2957 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2958 const struct intel_plane_wm_parameters *p; 2959 unsigned int data_rate, y_data_rate; 2960 uint16_t plane_blocks, y_plane_blocks = 0; 2961 2962 p = ¶ms->plane[plane]; 2963 if (!p->enabled) 2964 continue; 2965 2966 data_rate = skl_plane_relative_data_rate(p, 0); 2967 2968 /* 2969 * allocation for (packed formats) or (uv-plane part of planar format): 2970 * promote the expression to 64 bits to avoid overflowing, the 2971 * result is < available as data_rate / total_data_rate < 1 2972 */ 2973 plane_blocks = minimum[plane]; 2974 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 2975 total_data_rate); 2976 2977 ddb->plane[pipe][plane].start = start; 2978 ddb->plane[pipe][plane].end = start + plane_blocks; 2979 2980 start += plane_blocks; 2981 2982 /* 2983 * allocation for y_plane part of planar format: 2984 */ 2985 if (p->y_bytes_per_pixel) { 2986 y_data_rate = skl_plane_relative_data_rate(p, 1); 2987 y_plane_blocks = y_minimum[plane]; 2988 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 2989 total_data_rate); 2990 2991 ddb->y_plane[pipe][plane].start = start; 2992 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; 2993 2994 start += y_plane_blocks; 2995 } 2996 2997 } 2998 2999 } 3000 3001 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3002 { 3003 /* TODO: Take into account the scalers once we support them */ 3004 return config->base.adjusted_mode.crtc_clock; 3005 } 3006 3007 /* 3008 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3009 * for the read latency) and bytes_per_pixel should always be <= 8, so that 3010 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 3011 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 3012 */ 3013 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 3014 uint32_t latency) 3015 { 3016 uint32_t wm_intermediate_val, ret; 3017 3018 if (latency == 0) 3019 return UINT_MAX; 3020 3021 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; 3022 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3023 3024 return ret; 3025 } 3026 3027 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3028 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 3029 uint64_t tiling, uint32_t latency) 3030 { 3031 uint32_t ret; 3032 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3033 uint32_t wm_intermediate_val; 3034 3035 if (latency == 0) 3036 return UINT_MAX; 3037 3038 plane_bytes_per_line = horiz_pixels * bytes_per_pixel; 3039 3040 if (tiling == I915_FORMAT_MOD_Y_TILED || 3041 tiling == I915_FORMAT_MOD_Yf_TILED) { 3042 plane_bytes_per_line *= 4; 3043 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3044 plane_blocks_per_line /= 4; 3045 } else { 3046 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3047 } 3048 3049 wm_intermediate_val = latency * pixel_rate; 3050 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3051 plane_blocks_per_line; 3052 3053 return ret; 3054 } 3055 3056 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3057 const struct intel_crtc *intel_crtc) 3058 { 3059 struct drm_device *dev = intel_crtc->base.dev; 3060 struct drm_i915_private *dev_priv = dev->dev_private; 3061 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3062 enum i915_pipe pipe = intel_crtc->pipe; 3063 3064 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], 3065 sizeof(new_ddb->plane[pipe]))) 3066 return true; 3067 3068 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], 3069 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) 3070 return true; 3071 3072 return false; 3073 } 3074 3075 static void skl_compute_wm_global_parameters(struct drm_device *dev, 3076 struct intel_wm_config *config) 3077 { 3078 struct drm_crtc *crtc; 3079 struct drm_plane *plane; 3080 3081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3082 config->num_pipes_active += to_intel_crtc(crtc)->active; 3083 3084 /* FIXME: I don't think we need those two global parameters on SKL */ 3085 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3086 struct intel_plane *intel_plane = to_intel_plane(plane); 3087 3088 config->sprites_enabled |= intel_plane->wm.enabled; 3089 config->sprites_scaled |= intel_plane->wm.scaled; 3090 } 3091 } 3092 3093 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, 3094 struct skl_pipe_wm_parameters *p) 3095 { 3096 struct drm_device *dev = crtc->dev; 3097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3098 enum i915_pipe pipe = intel_crtc->pipe; 3099 struct drm_plane *plane; 3100 struct drm_framebuffer *fb; 3101 int i = 1; /* Index for sprite planes start */ 3102 3103 p->active = intel_crtc->active; 3104 if (p->active) { 3105 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 3106 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); 3107 3108 fb = crtc->primary->state->fb; 3109 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ 3110 if (fb) { 3111 p->plane[0].enabled = true; 3112 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3113 drm_format_plane_cpp(fb->pixel_format, 1) : 3114 drm_format_plane_cpp(fb->pixel_format, 0); 3115 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3116 drm_format_plane_cpp(fb->pixel_format, 0) : 0; 3117 p->plane[0].tiling = fb->modifier[0]; 3118 } else { 3119 p->plane[0].enabled = false; 3120 p->plane[0].bytes_per_pixel = 0; 3121 p->plane[0].y_bytes_per_pixel = 0; 3122 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; 3123 } 3124 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; 3125 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; 3126 p->plane[0].rotation = crtc->primary->state->rotation; 3127 3128 fb = crtc->cursor->state->fb; 3129 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; 3130 if (fb) { 3131 p->plane[PLANE_CURSOR].enabled = true; 3132 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; 3133 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; 3134 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; 3135 } else { 3136 p->plane[PLANE_CURSOR].enabled = false; 3137 p->plane[PLANE_CURSOR].bytes_per_pixel = 0; 3138 p->plane[PLANE_CURSOR].horiz_pixels = 64; 3139 p->plane[PLANE_CURSOR].vert_pixels = 64; 3140 } 3141 } 3142 3143 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3144 struct intel_plane *intel_plane = to_intel_plane(plane); 3145 3146 if (intel_plane->pipe == pipe && 3147 plane->type == DRM_PLANE_TYPE_OVERLAY) 3148 p->plane[i++] = intel_plane->wm; 3149 } 3150 } 3151 3152 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3153 struct skl_pipe_wm_parameters *p, 3154 struct intel_plane_wm_parameters *p_params, 3155 uint16_t ddb_allocation, 3156 int level, 3157 uint16_t *out_blocks, /* out */ 3158 uint8_t *out_lines /* out */) 3159 { 3160 uint32_t latency = dev_priv->wm.skl_latency[level]; 3161 uint32_t method1, method2; 3162 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3163 uint32_t res_blocks, res_lines; 3164 uint32_t selected_result; 3165 uint8_t bytes_per_pixel; 3166 3167 if (latency == 0 || !p->active || !p_params->enabled) 3168 return false; 3169 3170 bytes_per_pixel = p_params->y_bytes_per_pixel ? 3171 p_params->y_bytes_per_pixel : 3172 p_params->bytes_per_pixel; 3173 method1 = skl_wm_method1(p->pixel_rate, 3174 bytes_per_pixel, 3175 latency); 3176 method2 = skl_wm_method2(p->pixel_rate, 3177 p->pipe_htotal, 3178 p_params->horiz_pixels, 3179 bytes_per_pixel, 3180 p_params->tiling, 3181 latency); 3182 3183 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; 3184 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3185 3186 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3187 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { 3188 uint32_t min_scanlines = 4; 3189 uint32_t y_tile_minimum; 3190 if (intel_rotation_90_or_270(p_params->rotation)) { 3191 switch (p_params->bytes_per_pixel) { 3192 case 1: 3193 min_scanlines = 16; 3194 break; 3195 case 2: 3196 min_scanlines = 8; 3197 break; 3198 case 8: 3199 WARN(1, "Unsupported pixel depth for rotation"); 3200 } 3201 } 3202 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3203 selected_result = max(method2, y_tile_minimum); 3204 } else { 3205 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3206 selected_result = min(method1, method2); 3207 else 3208 selected_result = method1; 3209 } 3210 3211 res_blocks = selected_result + 1; 3212 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3213 3214 if (level >= 1 && level <= 7) { 3215 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3216 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) 3217 res_lines += 4; 3218 else 3219 res_blocks++; 3220 } 3221 3222 if (res_blocks >= ddb_allocation || res_lines > 31) 3223 return false; 3224 3225 *out_blocks = res_blocks; 3226 *out_lines = res_lines; 3227 3228 return true; 3229 } 3230 3231 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3232 struct skl_ddb_allocation *ddb, 3233 struct skl_pipe_wm_parameters *p, 3234 enum i915_pipe pipe, 3235 int level, 3236 int num_planes, 3237 struct skl_wm_level *result) 3238 { 3239 uint16_t ddb_blocks; 3240 int i; 3241 3242 for (i = 0; i < num_planes; i++) { 3243 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3244 3245 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3246 p, &p->plane[i], 3247 ddb_blocks, 3248 level, 3249 &result->plane_res_b[i], 3250 &result->plane_res_l[i]); 3251 } 3252 3253 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); 3254 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, 3255 &p->plane[PLANE_CURSOR], 3256 ddb_blocks, level, 3257 &result->plane_res_b[PLANE_CURSOR], 3258 &result->plane_res_l[PLANE_CURSOR]); 3259 } 3260 3261 static uint32_t 3262 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) 3263 { 3264 if (!to_intel_crtc(crtc)->active) 3265 return 0; 3266 3267 if (WARN_ON(p->pixel_rate == 0)) 3268 return 0; 3269 3270 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); 3271 } 3272 3273 static void skl_compute_transition_wm(struct drm_crtc *crtc, 3274 struct skl_pipe_wm_parameters *params, 3275 struct skl_wm_level *trans_wm /* out */) 3276 { 3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3278 int i; 3279 3280 if (!params->active) 3281 return; 3282 3283 /* Until we know more, just disable transition WMs */ 3284 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3285 trans_wm->plane_en[i] = false; 3286 trans_wm->plane_en[PLANE_CURSOR] = false; 3287 } 3288 3289 static void skl_compute_pipe_wm(struct drm_crtc *crtc, 3290 struct skl_ddb_allocation *ddb, 3291 struct skl_pipe_wm_parameters *params, 3292 struct skl_pipe_wm *pipe_wm) 3293 { 3294 struct drm_device *dev = crtc->dev; 3295 const struct drm_i915_private *dev_priv = dev->dev_private; 3296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3297 int level, max_level = ilk_wm_max_level(dev); 3298 3299 for (level = 0; level <= max_level; level++) { 3300 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, 3301 level, intel_num_planes(intel_crtc), 3302 &pipe_wm->wm[level]); 3303 } 3304 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); 3305 3306 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); 3307 } 3308 3309 static void skl_compute_wm_results(struct drm_device *dev, 3310 struct skl_pipe_wm_parameters *p, 3311 struct skl_pipe_wm *p_wm, 3312 struct skl_wm_values *r, 3313 struct intel_crtc *intel_crtc) 3314 { 3315 int level, max_level = ilk_wm_max_level(dev); 3316 enum i915_pipe pipe = intel_crtc->pipe; 3317 uint32_t temp; 3318 int i; 3319 3320 for (level = 0; level <= max_level; level++) { 3321 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3322 temp = 0; 3323 3324 temp |= p_wm->wm[level].plane_res_l[i] << 3325 PLANE_WM_LINES_SHIFT; 3326 temp |= p_wm->wm[level].plane_res_b[i]; 3327 if (p_wm->wm[level].plane_en[i]) 3328 temp |= PLANE_WM_EN; 3329 3330 r->plane[pipe][i][level] = temp; 3331 } 3332 3333 temp = 0; 3334 3335 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3336 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; 3337 3338 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) 3339 temp |= PLANE_WM_EN; 3340 3341 r->plane[pipe][PLANE_CURSOR][level] = temp; 3342 3343 } 3344 3345 /* transition WMs */ 3346 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3347 temp = 0; 3348 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3349 temp |= p_wm->trans_wm.plane_res_b[i]; 3350 if (p_wm->trans_wm.plane_en[i]) 3351 temp |= PLANE_WM_EN; 3352 3353 r->plane_trans[pipe][i] = temp; 3354 } 3355 3356 temp = 0; 3357 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3358 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; 3359 if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) 3360 temp |= PLANE_WM_EN; 3361 3362 r->plane_trans[pipe][PLANE_CURSOR] = temp; 3363 3364 r->wm_linetime[pipe] = p_wm->linetime; 3365 } 3366 3367 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, 3368 const struct skl_ddb_entry *entry) 3369 { 3370 if (entry->end) 3371 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3372 else 3373 I915_WRITE(reg, 0); 3374 } 3375 3376 static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3377 const struct skl_wm_values *new) 3378 { 3379 struct drm_device *dev = dev_priv->dev; 3380 struct intel_crtc *crtc; 3381 3382 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 3383 int i, level, max_level = ilk_wm_max_level(dev); 3384 enum i915_pipe pipe = crtc->pipe; 3385 3386 if (!new->dirty[pipe]) 3387 continue; 3388 3389 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3390 3391 for (level = 0; level <= max_level; level++) { 3392 for (i = 0; i < intel_num_planes(crtc); i++) 3393 I915_WRITE(PLANE_WM(pipe, i, level), 3394 new->plane[pipe][i][level]); 3395 I915_WRITE(CUR_WM(pipe, level), 3396 new->plane[pipe][PLANE_CURSOR][level]); 3397 } 3398 for (i = 0; i < intel_num_planes(crtc); i++) 3399 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3400 new->plane_trans[pipe][i]); 3401 I915_WRITE(CUR_WM_TRANS(pipe), 3402 new->plane_trans[pipe][PLANE_CURSOR]); 3403 3404 for (i = 0; i < intel_num_planes(crtc); i++) { 3405 skl_ddb_entry_write(dev_priv, 3406 PLANE_BUF_CFG(pipe, i), 3407 &new->ddb.plane[pipe][i]); 3408 skl_ddb_entry_write(dev_priv, 3409 PLANE_NV12_BUF_CFG(pipe, i), 3410 &new->ddb.y_plane[pipe][i]); 3411 } 3412 3413 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3414 &new->ddb.plane[pipe][PLANE_CURSOR]); 3415 } 3416 } 3417 3418 /* 3419 * When setting up a new DDB allocation arrangement, we need to correctly 3420 * sequence the times at which the new allocations for the pipes are taken into 3421 * account or we'll have pipes fetching from space previously allocated to 3422 * another pipe. 3423 * 3424 * Roughly the sequence looks like: 3425 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3426 * overlapping with a previous light-up pipe (another way to put it is: 3427 * pipes with their new allocation strickly included into their old ones). 3428 * 2. re-allocate the other pipes that get their allocation reduced 3429 * 3. allocate the pipes having their allocation increased 3430 * 3431 * Steps 1. and 2. are here to take care of the following case: 3432 * - Initially DDB looks like this: 3433 * | B | C | 3434 * - enable pipe A. 3435 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3436 * allocation 3437 * | A | B | C | 3438 * 3439 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3440 */ 3441 3442 static void 3443 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int pass) 3444 { 3445 int plane; 3446 3447 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3448 3449 for_each_plane(dev_priv, pipe, plane) { 3450 I915_WRITE(PLANE_SURF(pipe, plane), 3451 I915_READ(PLANE_SURF(pipe, plane))); 3452 } 3453 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3454 } 3455 3456 static bool 3457 skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3458 const struct skl_ddb_allocation *new, 3459 enum i915_pipe pipe) 3460 { 3461 uint16_t old_size, new_size; 3462 3463 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3464 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3465 3466 return old_size != new_size && 3467 new->pipe[pipe].start >= old->pipe[pipe].start && 3468 new->pipe[pipe].end <= old->pipe[pipe].end; 3469 } 3470 3471 static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3472 struct skl_wm_values *new_values) 3473 { 3474 struct drm_device *dev = dev_priv->dev; 3475 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3476 bool reallocated[I915_MAX_PIPES] = {}; 3477 struct intel_crtc *crtc; 3478 enum i915_pipe pipe; 3479 3480 new_ddb = &new_values->ddb; 3481 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3482 3483 /* 3484 * First pass: flush the pipes with the new allocation contained into 3485 * the old space. 3486 * 3487 * We'll wait for the vblank on those pipes to ensure we can safely 3488 * re-allocate the freed space without this pipe fetching from it. 3489 */ 3490 for_each_intel_crtc(dev, crtc) { 3491 if (!crtc->active) 3492 continue; 3493 3494 pipe = crtc->pipe; 3495 3496 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3497 continue; 3498 3499 skl_wm_flush_pipe(dev_priv, pipe, 1); 3500 intel_wait_for_vblank(dev, pipe); 3501 3502 reallocated[pipe] = true; 3503 } 3504 3505 3506 /* 3507 * Second pass: flush the pipes that are having their allocation 3508 * reduced, but overlapping with a previous allocation. 3509 * 3510 * Here as well we need to wait for the vblank to make sure the freed 3511 * space is not used anymore. 3512 */ 3513 for_each_intel_crtc(dev, crtc) { 3514 if (!crtc->active) 3515 continue; 3516 3517 pipe = crtc->pipe; 3518 3519 if (reallocated[pipe]) 3520 continue; 3521 3522 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3523 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3524 skl_wm_flush_pipe(dev_priv, pipe, 2); 3525 intel_wait_for_vblank(dev, pipe); 3526 reallocated[pipe] = true; 3527 } 3528 } 3529 3530 /* 3531 * Third pass: flush the pipes that got more space allocated. 3532 * 3533 * We don't need to actively wait for the update here, next vblank 3534 * will just get more DDB space with the correct WM values. 3535 */ 3536 for_each_intel_crtc(dev, crtc) { 3537 if (!crtc->active) 3538 continue; 3539 3540 pipe = crtc->pipe; 3541 3542 /* 3543 * At this point, only the pipes more space than before are 3544 * left to re-allocate. 3545 */ 3546 if (reallocated[pipe]) 3547 continue; 3548 3549 skl_wm_flush_pipe(dev_priv, pipe, 3); 3550 } 3551 } 3552 3553 static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3554 struct skl_pipe_wm_parameters *params, 3555 struct intel_wm_config *config, 3556 struct skl_ddb_allocation *ddb, /* out */ 3557 struct skl_pipe_wm *pipe_wm /* out */) 3558 { 3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3560 3561 skl_compute_wm_pipe_parameters(crtc, params); 3562 skl_allocate_pipe_ddb(crtc, config, params, ddb); 3563 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); 3564 3565 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) 3566 return false; 3567 3568 intel_crtc->wm.skl_active = *pipe_wm; 3569 3570 return true; 3571 } 3572 3573 static void skl_update_other_pipe_wm(struct drm_device *dev, 3574 struct drm_crtc *crtc, 3575 struct intel_wm_config *config, 3576 struct skl_wm_values *r) 3577 { 3578 struct intel_crtc *intel_crtc; 3579 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3580 3581 /* 3582 * If the WM update hasn't changed the allocation for this_crtc (the 3583 * crtc we are currently computing the new WM values for), other 3584 * enabled crtcs will keep the same allocation and we don't need to 3585 * recompute anything for them. 3586 */ 3587 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3588 return; 3589 3590 /* 3591 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3592 * other active pipes need new DDB allocation and WM values. 3593 */ 3594 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 3595 base.head) { 3596 struct skl_pipe_wm_parameters params = {}; 3597 struct skl_pipe_wm pipe_wm = {}; 3598 bool wm_changed; 3599 3600 if (this_crtc->pipe == intel_crtc->pipe) 3601 continue; 3602 3603 if (!intel_crtc->active) 3604 continue; 3605 3606 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3607 ¶ms, config, 3608 &r->ddb, &pipe_wm); 3609 3610 /* 3611 * If we end up re-computing the other pipe WM values, it's 3612 * because it was really needed, so we expect the WM values to 3613 * be different. 3614 */ 3615 WARN_ON(!wm_changed); 3616 3617 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); 3618 r->dirty[intel_crtc->pipe] = true; 3619 } 3620 } 3621 3622 static void skl_clear_wm(struct skl_wm_values *watermarks, enum i915_pipe pipe) 3623 { 3624 watermarks->wm_linetime[pipe] = 0; 3625 memset(watermarks->plane[pipe], 0, 3626 sizeof(uint32_t) * 8 * I915_MAX_PLANES); 3627 memset(watermarks->plane_trans[pipe], 3628 0, sizeof(uint32_t) * I915_MAX_PLANES); 3629 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; 3630 3631 /* Clear ddb entries for pipe */ 3632 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); 3633 memset(&watermarks->ddb.plane[pipe], 0, 3634 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3635 memset(&watermarks->ddb.y_plane[pipe], 0, 3636 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3637 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, 3638 sizeof(struct skl_ddb_entry)); 3639 3640 } 3641 3642 static void skl_update_wm(struct drm_crtc *crtc) 3643 { 3644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3645 struct drm_device *dev = crtc->dev; 3646 struct drm_i915_private *dev_priv = dev->dev_private; 3647 struct skl_pipe_wm_parameters params = {}; 3648 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3649 struct skl_pipe_wm pipe_wm = {}; 3650 struct intel_wm_config config = {}; 3651 3652 3653 /* Clear all dirty flags */ 3654 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); 3655 3656 skl_clear_wm(results, intel_crtc->pipe); 3657 3658 skl_compute_wm_global_parameters(dev, &config); 3659 3660 if (!skl_update_pipe_wm(crtc, ¶ms, &config, 3661 &results->ddb, &pipe_wm)) 3662 return; 3663 3664 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); 3665 results->dirty[intel_crtc->pipe] = true; 3666 3667 skl_update_other_pipe_wm(dev, crtc, &config, results); 3668 skl_write_wm_values(dev_priv, results); 3669 skl_flush_wm_values(dev_priv, results); 3670 3671 /* store the new configuration */ 3672 dev_priv->wm.skl_hw = *results; 3673 } 3674 3675 static void 3676 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, 3677 uint32_t sprite_width, uint32_t sprite_height, 3678 int pixel_size, bool enabled, bool scaled) 3679 { 3680 struct intel_plane *intel_plane = to_intel_plane(plane); 3681 struct drm_framebuffer *fb = plane->state->fb; 3682 3683 intel_plane->wm.enabled = enabled; 3684 intel_plane->wm.scaled = scaled; 3685 intel_plane->wm.horiz_pixels = sprite_width; 3686 intel_plane->wm.vert_pixels = sprite_height; 3687 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; 3688 3689 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ 3690 intel_plane->wm.bytes_per_pixel = 3691 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3692 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; 3693 intel_plane->wm.y_bytes_per_pixel = 3694 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3695 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; 3696 3697 /* 3698 * Framebuffer can be NULL on plane disable, but it does not 3699 * matter for watermarks if we assume no tiling in that case. 3700 */ 3701 if (fb) 3702 intel_plane->wm.tiling = fb->modifier[0]; 3703 intel_plane->wm.rotation = plane->state->rotation; 3704 3705 skl_update_wm(crtc); 3706 } 3707 3708 static void ilk_update_wm(struct drm_crtc *crtc) 3709 { 3710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3711 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3712 struct drm_device *dev = crtc->dev; 3713 struct drm_i915_private *dev_priv = dev->dev_private; 3714 struct ilk_wm_maximums max; 3715 static const struct ilk_wm_values zero_values; 3716 struct ilk_wm_values results = zero_values; 3717 enum intel_ddb_partitioning partitioning; 3718 static const struct intel_pipe_wm zero_wm; 3719 struct intel_pipe_wm pipe_wm = zero_wm; 3720 struct intel_pipe_wm lp_wm_1_2 = zero_wm, lp_wm_5_6 = zero_wm, 3721 *best_lp_wm; 3722 static const struct intel_wm_config zero_config; 3723 struct intel_wm_config config = zero_config; 3724 3725 WARN_ON(cstate->base.active != intel_crtc->active); 3726 3727 intel_compute_pipe_wm(cstate, &pipe_wm); 3728 3729 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 3730 return; 3731 3732 intel_crtc->wm.active = pipe_wm; 3733 3734 ilk_compute_wm_config(dev, &config); 3735 3736 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3737 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3738 3739 /* 5/6 split only in single pipe config on IVB+ */ 3740 if (INTEL_INFO(dev)->gen >= 7 && 3741 config.num_pipes_active == 1 && config.sprites_enabled) { 3742 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3743 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3744 3745 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3746 } else { 3747 best_lp_wm = &lp_wm_1_2; 3748 } 3749 3750 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3751 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3752 3753 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3754 3755 ilk_write_wm_values(dev_priv, &results); 3756 } 3757 3758 static void 3759 ilk_update_sprite_wm(struct drm_plane *plane, 3760 struct drm_crtc *crtc, 3761 uint32_t sprite_width, uint32_t sprite_height, 3762 int pixel_size, bool enabled, bool scaled) 3763 { 3764 struct drm_device *dev = plane->dev; 3765 struct intel_plane *intel_plane = to_intel_plane(plane); 3766 3767 /* 3768 * IVB workaround: must disable low power watermarks for at least 3769 * one frame before enabling scaling. LP watermarks can be re-enabled 3770 * when scaling is disabled. 3771 * 3772 * WaCxSRDisabledForSpriteScaling:ivb 3773 */ 3774 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 3775 intel_wait_for_vblank(dev, intel_plane->pipe); 3776 3777 ilk_update_wm(crtc); 3778 } 3779 3780 static void skl_pipe_wm_active_state(uint32_t val, 3781 struct skl_pipe_wm *active, 3782 bool is_transwm, 3783 bool is_cursor, 3784 int i, 3785 int level) 3786 { 3787 bool is_enabled = (val & PLANE_WM_EN) != 0; 3788 3789 if (!is_transwm) { 3790 if (!is_cursor) { 3791 active->wm[level].plane_en[i] = is_enabled; 3792 active->wm[level].plane_res_b[i] = 3793 val & PLANE_WM_BLOCKS_MASK; 3794 active->wm[level].plane_res_l[i] = 3795 (val >> PLANE_WM_LINES_SHIFT) & 3796 PLANE_WM_LINES_MASK; 3797 } else { 3798 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; 3799 active->wm[level].plane_res_b[PLANE_CURSOR] = 3800 val & PLANE_WM_BLOCKS_MASK; 3801 active->wm[level].plane_res_l[PLANE_CURSOR] = 3802 (val >> PLANE_WM_LINES_SHIFT) & 3803 PLANE_WM_LINES_MASK; 3804 } 3805 } else { 3806 if (!is_cursor) { 3807 active->trans_wm.plane_en[i] = is_enabled; 3808 active->trans_wm.plane_res_b[i] = 3809 val & PLANE_WM_BLOCKS_MASK; 3810 active->trans_wm.plane_res_l[i] = 3811 (val >> PLANE_WM_LINES_SHIFT) & 3812 PLANE_WM_LINES_MASK; 3813 } else { 3814 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; 3815 active->trans_wm.plane_res_b[PLANE_CURSOR] = 3816 val & PLANE_WM_BLOCKS_MASK; 3817 active->trans_wm.plane_res_l[PLANE_CURSOR] = 3818 (val >> PLANE_WM_LINES_SHIFT) & 3819 PLANE_WM_LINES_MASK; 3820 } 3821 } 3822 } 3823 3824 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3825 { 3826 struct drm_device *dev = crtc->dev; 3827 struct drm_i915_private *dev_priv = dev->dev_private; 3828 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3830 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; 3831 enum i915_pipe pipe = intel_crtc->pipe; 3832 int level, i, max_level; 3833 uint32_t temp; 3834 3835 max_level = ilk_wm_max_level(dev); 3836 3837 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3838 3839 for (level = 0; level <= max_level; level++) { 3840 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3841 hw->plane[pipe][i][level] = 3842 I915_READ(PLANE_WM(pipe, i, level)); 3843 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); 3844 } 3845 3846 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3847 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3848 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); 3849 3850 if (!intel_crtc->active) 3851 return; 3852 3853 hw->dirty[pipe] = true; 3854 3855 active->linetime = hw->wm_linetime[pipe]; 3856 3857 for (level = 0; level <= max_level; level++) { 3858 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3859 temp = hw->plane[pipe][i][level]; 3860 skl_pipe_wm_active_state(temp, active, false, 3861 false, i, level); 3862 } 3863 temp = hw->plane[pipe][PLANE_CURSOR][level]; 3864 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3865 } 3866 3867 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3868 temp = hw->plane_trans[pipe][i]; 3869 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3870 } 3871 3872 temp = hw->plane_trans[pipe][PLANE_CURSOR]; 3873 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3874 } 3875 3876 void skl_wm_get_hw_state(struct drm_device *dev) 3877 { 3878 struct drm_i915_private *dev_priv = dev->dev_private; 3879 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3880 struct drm_crtc *crtc; 3881 3882 skl_ddb_get_hw_state(dev_priv, ddb); 3883 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3884 skl_pipe_wm_get_hw_state(crtc); 3885 } 3886 3887 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3888 { 3889 struct drm_device *dev = crtc->dev; 3890 struct drm_i915_private *dev_priv = dev->dev_private; 3891 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3893 struct intel_pipe_wm *active = &intel_crtc->wm.active; 3894 enum i915_pipe pipe = intel_crtc->pipe; 3895 static const unsigned int wm0_pipe_reg[] = { 3896 [PIPE_A] = WM0_PIPEA_ILK, 3897 [PIPE_B] = WM0_PIPEB_ILK, 3898 [PIPE_C] = WM0_PIPEC_IVB, 3899 }; 3900 3901 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3902 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3903 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3904 3905 memset(active, 0, sizeof(*active)); 3906 3907 active->pipe_enabled = intel_crtc->active; 3908 3909 if (active->pipe_enabled) { 3910 u32 tmp = hw->wm_pipe[pipe]; 3911 3912 /* 3913 * For active pipes LP0 watermark is marked as 3914 * enabled, and LP1+ watermaks as disabled since 3915 * we can't really reverse compute them in case 3916 * multiple pipes are active. 3917 */ 3918 active->wm[0].enable = true; 3919 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3920 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3921 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3922 active->linetime = hw->wm_linetime[pipe]; 3923 } else { 3924 int level, max_level = ilk_wm_max_level(dev); 3925 3926 /* 3927 * For inactive pipes, all watermark levels 3928 * should be marked as enabled but zeroed, 3929 * which is what we'd compute them to. 3930 */ 3931 for (level = 0; level <= max_level; level++) 3932 active->wm[level].enable = true; 3933 } 3934 } 3935 3936 #define _FW_WM(value, plane) \ 3937 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3938 #define _FW_WM_VLV(value, plane) \ 3939 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3940 3941 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3942 struct vlv_wm_values *wm) 3943 { 3944 enum i915_pipe pipe; 3945 uint32_t tmp; 3946 3947 for_each_pipe(dev_priv, pipe) { 3948 tmp = I915_READ(VLV_DDL(pipe)); 3949 3950 wm->ddl[pipe].primary = 3951 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3952 wm->ddl[pipe].cursor = 3953 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3954 wm->ddl[pipe].sprite[0] = 3955 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3956 wm->ddl[pipe].sprite[1] = 3957 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3958 } 3959 3960 tmp = I915_READ(DSPFW1); 3961 wm->sr.plane = _FW_WM(tmp, SR); 3962 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3963 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3964 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3965 3966 tmp = I915_READ(DSPFW2); 3967 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3968 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3969 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3970 3971 tmp = I915_READ(DSPFW3); 3972 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 3973 3974 if (IS_CHERRYVIEW(dev_priv)) { 3975 tmp = I915_READ(DSPFW7_CHV); 3976 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3977 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3978 3979 tmp = I915_READ(DSPFW8_CHV); 3980 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 3981 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 3982 3983 tmp = I915_READ(DSPFW9_CHV); 3984 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 3985 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 3986 3987 tmp = I915_READ(DSPHOWM); 3988 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3989 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 3990 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 3991 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 3992 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 3993 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 3994 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 3995 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 3996 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 3997 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 3998 } else { 3999 tmp = I915_READ(DSPFW7); 4000 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 4001 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 4002 4003 tmp = I915_READ(DSPHOWM); 4004 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 4005 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4006 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4007 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4008 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4009 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4010 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4011 } 4012 } 4013 4014 #undef _FW_WM 4015 #undef _FW_WM_VLV 4016 4017 void vlv_wm_get_hw_state(struct drm_device *dev) 4018 { 4019 struct drm_i915_private *dev_priv = to_i915(dev); 4020 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 4021 struct intel_plane *plane; 4022 enum i915_pipe pipe; 4023 u32 val; 4024 4025 vlv_read_wm_values(dev_priv, wm); 4026 4027 for_each_intel_plane(dev, plane) { 4028 switch (plane->base.type) { 4029 int sprite; 4030 case DRM_PLANE_TYPE_CURSOR: 4031 plane->wm.fifo_size = 63; 4032 break; 4033 case DRM_PLANE_TYPE_PRIMARY: 4034 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 4035 break; 4036 case DRM_PLANE_TYPE_OVERLAY: 4037 sprite = plane->plane; 4038 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 4039 break; 4040 } 4041 } 4042 4043 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 4044 wm->level = VLV_WM_LEVEL_PM2; 4045 4046 if (IS_CHERRYVIEW(dev_priv)) { 4047 mutex_lock(&dev_priv->rps.hw_lock); 4048 4049 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 4050 if (val & DSP_MAXFIFO_PM5_ENABLE) 4051 wm->level = VLV_WM_LEVEL_PM5; 4052 4053 /* 4054 * If DDR DVFS is disabled in the BIOS, Punit 4055 * will never ack the request. So if that happens 4056 * assume we don't have to enable/disable DDR DVFS 4057 * dynamically. To test that just set the REQ_ACK 4058 * bit to poke the Punit, but don't change the 4059 * HIGH/LOW bits so that we don't actually change 4060 * the current state. 4061 */ 4062 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4063 val |= FORCE_DDR_FREQ_REQ_ACK; 4064 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4065 4066 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4067 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4068 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4069 "assuming DDR DVFS is disabled\n"); 4070 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4071 } else { 4072 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4073 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4074 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4075 } 4076 4077 mutex_unlock(&dev_priv->rps.hw_lock); 4078 } 4079 4080 for_each_pipe(dev_priv, pipe) 4081 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4082 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4083 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4084 4085 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4086 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4087 } 4088 4089 void ilk_wm_get_hw_state(struct drm_device *dev) 4090 { 4091 struct drm_i915_private *dev_priv = dev->dev_private; 4092 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4093 struct drm_crtc *crtc; 4094 4095 for_each_crtc(dev, crtc) 4096 ilk_pipe_wm_get_hw_state(crtc); 4097 4098 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4099 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4100 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4101 4102 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4103 if (INTEL_INFO(dev)->gen >= 7) { 4104 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4105 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4106 } 4107 4108 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4109 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4110 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4111 else if (IS_IVYBRIDGE(dev)) 4112 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4113 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4114 4115 hw->enable_fbc_wm = 4116 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4117 } 4118 4119 /** 4120 * intel_update_watermarks - update FIFO watermark values based on current modes 4121 * 4122 * Calculate watermark values for the various WM regs based on current mode 4123 * and plane configuration. 4124 * 4125 * There are several cases to deal with here: 4126 * - normal (i.e. non-self-refresh) 4127 * - self-refresh (SR) mode 4128 * - lines are large relative to FIFO size (buffer can hold up to 2) 4129 * - lines are small relative to FIFO size (buffer can hold more than 2 4130 * lines), so need to account for TLB latency 4131 * 4132 * The normal calculation is: 4133 * watermark = dotclock * bytes per pixel * latency 4134 * where latency is platform & configuration dependent (we assume pessimal 4135 * values here). 4136 * 4137 * The SR calculation is: 4138 * watermark = (trunc(latency/line time)+1) * surface width * 4139 * bytes per pixel 4140 * where 4141 * line time = htotal / dotclock 4142 * surface width = hdisplay for normal plane and 64 for cursor 4143 * and latency is assumed to be high, as above. 4144 * 4145 * The final value programmed to the register should always be rounded up, 4146 * and include an extra 2 entries to account for clock crossings. 4147 * 4148 * We don't use the sprite, so we can ignore that. And on Crestline we have 4149 * to set the non-SR watermarks to 8. 4150 */ 4151 void intel_update_watermarks(struct drm_crtc *crtc) 4152 { 4153 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4154 4155 if (dev_priv->display.update_wm) 4156 dev_priv->display.update_wm(crtc); 4157 } 4158 4159 void intel_update_sprite_watermarks(struct drm_plane *plane, 4160 struct drm_crtc *crtc, 4161 uint32_t sprite_width, 4162 uint32_t sprite_height, 4163 int pixel_size, 4164 bool enabled, bool scaled) 4165 { 4166 struct drm_i915_private *dev_priv = plane->dev->dev_private; 4167 4168 if (dev_priv->display.update_sprite_wm) 4169 dev_priv->display.update_sprite_wm(plane, crtc, 4170 sprite_width, sprite_height, 4171 pixel_size, enabled, scaled); 4172 } 4173 4174 /** 4175 * Lock protecting IPS related data structures 4176 */ 4177 DEFINE_SPINLOCK(mchdev_lock); 4178 4179 /* Global for IPS driver to get at the current i915 device. Protected by 4180 * mchdev_lock. */ 4181 static struct drm_i915_private *i915_mch_dev; 4182 4183 bool ironlake_set_drps(struct drm_device *dev, u8 val) 4184 { 4185 struct drm_i915_private *dev_priv = dev->dev_private; 4186 u16 rgvswctl; 4187 4188 assert_spin_locked(&mchdev_lock); 4189 4190 rgvswctl = I915_READ16(MEMSWCTL); 4191 if (rgvswctl & MEMCTL_CMD_STS) { 4192 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4193 return false; /* still busy with another command */ 4194 } 4195 4196 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4197 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4198 I915_WRITE16(MEMSWCTL, rgvswctl); 4199 POSTING_READ16(MEMSWCTL); 4200 4201 rgvswctl |= MEMCTL_CMD_STS; 4202 I915_WRITE16(MEMSWCTL, rgvswctl); 4203 4204 return true; 4205 } 4206 4207 static void ironlake_enable_drps(struct drm_device *dev) 4208 { 4209 struct drm_i915_private *dev_priv = dev->dev_private; 4210 u32 rgvmodectl = I915_READ(MEMMODECTL); 4211 u8 fmax, fmin, fstart, vstart; 4212 4213 spin_lock_irq(&mchdev_lock); 4214 4215 /* Enable temp reporting */ 4216 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4217 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4218 4219 /* 100ms RC evaluation intervals */ 4220 I915_WRITE(RCUPEI, 100000); 4221 I915_WRITE(RCDNEI, 100000); 4222 4223 /* Set max/min thresholds to 90ms and 80ms respectively */ 4224 I915_WRITE(RCBMAXAVG, 90000); 4225 I915_WRITE(RCBMINAVG, 80000); 4226 4227 I915_WRITE(MEMIHYST, 1); 4228 4229 /* Set up min, max, and cur for interrupt handling */ 4230 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4231 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4232 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4233 MEMMODE_FSTART_SHIFT; 4234 4235 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> 4236 PXVFREQ_PX_SHIFT; 4237 4238 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4239 dev_priv->ips.fstart = fstart; 4240 4241 dev_priv->ips.max_delay = fstart; 4242 dev_priv->ips.min_delay = fmin; 4243 dev_priv->ips.cur_delay = fstart; 4244 4245 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4246 fmax, fmin, fstart); 4247 4248 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4249 4250 /* 4251 * Interrupts will be enabled in ironlake_irq_postinstall 4252 */ 4253 4254 I915_WRITE(VIDSTART, vstart); 4255 POSTING_READ(VIDSTART); 4256 4257 rgvmodectl |= MEMMODE_SWMODE_EN; 4258 I915_WRITE(MEMMODECTL, rgvmodectl); 4259 4260 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4261 DRM_ERROR("stuck trying to change perf mode\n"); 4262 mdelay(1); 4263 4264 ironlake_set_drps(dev, fstart); 4265 4266 dev_priv->ips.last_count1 = I915_READ(DMIEC) + 4267 I915_READ(DDREC) + I915_READ(CSIEC); 4268 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4269 dev_priv->ips.last_count2 = I915_READ(GFXEC); 4270 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4271 4272 spin_unlock_irq(&mchdev_lock); 4273 } 4274 4275 static void ironlake_disable_drps(struct drm_device *dev) 4276 { 4277 struct drm_i915_private *dev_priv = dev->dev_private; 4278 u16 rgvswctl; 4279 4280 spin_lock_irq(&mchdev_lock); 4281 4282 rgvswctl = I915_READ16(MEMSWCTL); 4283 4284 /* Ack interrupts, disable EFC interrupt */ 4285 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4286 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4287 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4288 I915_WRITE(DEIIR, DE_PCU_EVENT); 4289 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4290 4291 /* Go back to the starting frequency */ 4292 ironlake_set_drps(dev, dev_priv->ips.fstart); 4293 mdelay(1); 4294 rgvswctl |= MEMCTL_CMD_STS; 4295 I915_WRITE(MEMSWCTL, rgvswctl); 4296 mdelay(1); 4297 4298 spin_unlock_irq(&mchdev_lock); 4299 } 4300 4301 /* There's a funny hw issue where the hw returns all 0 when reading from 4302 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4303 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4304 * all limits and the gpu stuck at whatever frequency it is at atm). 4305 */ 4306 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4307 { 4308 u32 limits; 4309 4310 /* Only set the down limit when we've reached the lowest level to avoid 4311 * getting more interrupts, otherwise leave this clear. This prevents a 4312 * race in the hw when coming out of rc6: There's a tiny window where 4313 * the hw runs at the minimal clock before selecting the desired 4314 * frequency, if the down threshold expires in that window we will not 4315 * receive a down interrupt. */ 4316 if (IS_GEN9(dev_priv->dev)) { 4317 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4318 if (val <= dev_priv->rps.min_freq_softlimit) 4319 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4320 } else { 4321 limits = dev_priv->rps.max_freq_softlimit << 24; 4322 if (val <= dev_priv->rps.min_freq_softlimit) 4323 limits |= dev_priv->rps.min_freq_softlimit << 16; 4324 } 4325 4326 return limits; 4327 } 4328 4329 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4330 { 4331 int new_power; 4332 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4333 u32 ei_up = 0, ei_down = 0; 4334 4335 new_power = dev_priv->rps.power; 4336 switch (dev_priv->rps.power) { 4337 case LOW_POWER: 4338 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4339 new_power = BETWEEN; 4340 break; 4341 4342 case BETWEEN: 4343 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4344 new_power = LOW_POWER; 4345 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4346 new_power = HIGH_POWER; 4347 break; 4348 4349 case HIGH_POWER: 4350 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4351 new_power = BETWEEN; 4352 break; 4353 } 4354 /* Max/min bins are special */ 4355 if (val <= dev_priv->rps.min_freq_softlimit) 4356 new_power = LOW_POWER; 4357 if (val >= dev_priv->rps.max_freq_softlimit) 4358 new_power = HIGH_POWER; 4359 if (new_power == dev_priv->rps.power) 4360 return; 4361 4362 /* Note the units here are not exactly 1us, but 1280ns. */ 4363 switch (new_power) { 4364 case LOW_POWER: 4365 /* Upclock if more than 95% busy over 16ms */ 4366 ei_up = 16000; 4367 threshold_up = 95; 4368 4369 /* Downclock if less than 85% busy over 32ms */ 4370 ei_down = 32000; 4371 threshold_down = 85; 4372 break; 4373 4374 case BETWEEN: 4375 /* Upclock if more than 90% busy over 13ms */ 4376 ei_up = 13000; 4377 threshold_up = 90; 4378 4379 /* Downclock if less than 75% busy over 32ms */ 4380 ei_down = 32000; 4381 threshold_down = 75; 4382 break; 4383 4384 case HIGH_POWER: 4385 /* Upclock if more than 85% busy over 10ms */ 4386 ei_up = 10000; 4387 threshold_up = 85; 4388 4389 /* Downclock if less than 60% busy over 32ms */ 4390 ei_down = 32000; 4391 threshold_down = 60; 4392 break; 4393 } 4394 4395 /* When byt can survive without system hang with dynamic 4396 * sw freq adjustments, this restriction can be lifted. 4397 */ 4398 if (IS_VALLEYVIEW(dev_priv)) 4399 goto skip_hw_write; 4400 4401 I915_WRITE(GEN6_RP_UP_EI, 4402 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4403 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4404 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4405 4406 I915_WRITE(GEN6_RP_DOWN_EI, 4407 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4408 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4409 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4410 4411 I915_WRITE(GEN6_RP_CONTROL, 4412 GEN6_RP_MEDIA_TURBO | 4413 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4414 GEN6_RP_MEDIA_IS_GFX | 4415 GEN6_RP_ENABLE | 4416 GEN6_RP_UP_BUSY_AVG | 4417 GEN6_RP_DOWN_IDLE_AVG); 4418 4419 skip_hw_write: 4420 dev_priv->rps.power = new_power; 4421 dev_priv->rps.up_threshold = threshold_up; 4422 dev_priv->rps.down_threshold = threshold_down; 4423 dev_priv->rps.last_adj = 0; 4424 } 4425 4426 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4427 { 4428 u32 mask = 0; 4429 4430 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ 4431 if (val > dev_priv->rps.min_freq_softlimit) 4432 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4433 if (val < dev_priv->rps.max_freq_softlimit) 4434 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4435 4436 mask &= dev_priv->pm_rps_events; 4437 4438 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4439 } 4440 4441 /* gen6_set_rps is called to update the frequency request, but should also be 4442 * called when the range (min_delay and max_delay) is modified so that we can 4443 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4444 static void gen6_set_rps(struct drm_device *dev, u8 val) 4445 { 4446 struct drm_i915_private *dev_priv = dev->dev_private; 4447 4448 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4449 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) 4450 return; 4451 4452 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4453 WARN_ON(val > dev_priv->rps.max_freq); 4454 WARN_ON(val < dev_priv->rps.min_freq); 4455 4456 /* min/max delay may still have been modified so be sure to 4457 * write the limits value. 4458 */ 4459 if (val != dev_priv->rps.cur_freq) { 4460 gen6_set_rps_thresholds(dev_priv, val); 4461 4462 if (IS_GEN9(dev)) 4463 I915_WRITE(GEN6_RPNSWREQ, 4464 GEN9_FREQUENCY(val)); 4465 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4466 I915_WRITE(GEN6_RPNSWREQ, 4467 HSW_FREQUENCY(val)); 4468 else 4469 I915_WRITE(GEN6_RPNSWREQ, 4470 GEN6_FREQUENCY(val) | 4471 GEN6_OFFSET(0) | 4472 GEN6_AGGRESSIVE_TURBO); 4473 } 4474 4475 /* Make sure we continue to get interrupts 4476 * until we hit the minimum or maximum frequencies. 4477 */ 4478 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4479 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4480 4481 POSTING_READ(GEN6_RPNSWREQ); 4482 4483 dev_priv->rps.cur_freq = val; 4484 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4485 } 4486 4487 static void valleyview_set_rps(struct drm_device *dev, u8 val) 4488 { 4489 struct drm_i915_private *dev_priv = dev->dev_private; 4490 4491 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4492 WARN_ON(val > dev_priv->rps.max_freq); 4493 WARN_ON(val < dev_priv->rps.min_freq); 4494 4495 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4496 "Odd GPU freq value\n")) 4497 val &= ~1; 4498 4499 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4500 4501 if (val != dev_priv->rps.cur_freq) { 4502 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4503 if (!IS_CHERRYVIEW(dev_priv)) 4504 gen6_set_rps_thresholds(dev_priv, val); 4505 } 4506 4507 dev_priv->rps.cur_freq = val; 4508 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4509 } 4510 4511 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4512 * 4513 * * If Gfx is Idle, then 4514 * 1. Forcewake Media well. 4515 * 2. Request idle freq. 4516 * 3. Release Forcewake of Media well. 4517 */ 4518 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4519 { 4520 u32 val = dev_priv->rps.idle_freq; 4521 4522 if (dev_priv->rps.cur_freq <= val) 4523 return; 4524 4525 /* Wake up the media well, as that takes a lot less 4526 * power than the Render well. */ 4527 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4528 valleyview_set_rps(dev_priv->dev, val); 4529 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4530 } 4531 4532 void gen6_rps_busy(struct drm_i915_private *dev_priv) 4533 { 4534 mutex_lock(&dev_priv->rps.hw_lock); 4535 if (dev_priv->rps.enabled) { 4536 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) 4537 gen6_rps_reset_ei(dev_priv); 4538 I915_WRITE(GEN6_PMINTRMSK, 4539 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4540 } 4541 mutex_unlock(&dev_priv->rps.hw_lock); 4542 } 4543 4544 void gen6_rps_idle(struct drm_i915_private *dev_priv) 4545 { 4546 struct drm_device *dev = dev_priv->dev; 4547 4548 mutex_lock(&dev_priv->rps.hw_lock); 4549 if (dev_priv->rps.enabled) { 4550 if (IS_VALLEYVIEW(dev)) 4551 vlv_set_rps_idle(dev_priv); 4552 else 4553 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4554 dev_priv->rps.last_adj = 0; 4555 I915_WRITE(GEN6_PMINTRMSK, 4556 gen6_sanitize_rps_pm_mask(dev_priv, ~0)); 4557 } 4558 mutex_unlock(&dev_priv->rps.hw_lock); 4559 4560 spin_lock(&dev_priv->rps.client_lock); 4561 while (!list_empty(&dev_priv->rps.clients)) 4562 list_del_init(dev_priv->rps.clients.next); 4563 spin_unlock(&dev_priv->rps.client_lock); 4564 } 4565 4566 void gen6_rps_boost(struct drm_i915_private *dev_priv, 4567 struct intel_rps_client *rps, 4568 unsigned long submitted) 4569 { 4570 /* This is intentionally racy! We peek at the state here, then 4571 * validate inside the RPS worker. 4572 */ 4573 if (!(dev_priv->mm.busy && 4574 dev_priv->rps.enabled && 4575 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4576 return; 4577 4578 /* Force a RPS boost (and don't count it against the client) if 4579 * the GPU is severely congested. 4580 */ 4581 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4582 rps = NULL; 4583 4584 spin_lock(&dev_priv->rps.client_lock); 4585 if (rps == NULL || list_empty(&rps->link)) { 4586 spin_lock_irq(&dev_priv->irq_lock); 4587 if (dev_priv->rps.interrupts_enabled) { 4588 dev_priv->rps.client_boost = true; 4589 queue_work(dev_priv->wq, &dev_priv->rps.work); 4590 } 4591 spin_unlock_irq(&dev_priv->irq_lock); 4592 4593 if (rps != NULL) { 4594 list_add(&rps->link, &dev_priv->rps.clients); 4595 rps->boosts++; 4596 } else 4597 dev_priv->rps.boosts++; 4598 } 4599 spin_unlock(&dev_priv->rps.client_lock); 4600 } 4601 4602 void intel_set_rps(struct drm_device *dev, u8 val) 4603 { 4604 if (IS_VALLEYVIEW(dev)) 4605 valleyview_set_rps(dev, val); 4606 else 4607 gen6_set_rps(dev, val); 4608 } 4609 4610 static void gen9_disable_rps(struct drm_device *dev) 4611 { 4612 struct drm_i915_private *dev_priv = dev->dev_private; 4613 4614 I915_WRITE(GEN6_RC_CONTROL, 0); 4615 I915_WRITE(GEN9_PG_ENABLE, 0); 4616 } 4617 4618 static void gen6_disable_rps(struct drm_device *dev) 4619 { 4620 struct drm_i915_private *dev_priv = dev->dev_private; 4621 4622 I915_WRITE(GEN6_RC_CONTROL, 0); 4623 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 4624 } 4625 4626 static void cherryview_disable_rps(struct drm_device *dev) 4627 { 4628 struct drm_i915_private *dev_priv = dev->dev_private; 4629 4630 I915_WRITE(GEN6_RC_CONTROL, 0); 4631 } 4632 4633 static void valleyview_disable_rps(struct drm_device *dev) 4634 { 4635 struct drm_i915_private *dev_priv = dev->dev_private; 4636 4637 /* we're doing forcewake before Disabling RC6, 4638 * This what the BIOS expects when going into suspend */ 4639 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4640 4641 I915_WRITE(GEN6_RC_CONTROL, 0); 4642 4643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4644 } 4645 4646 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4647 { 4648 if (IS_VALLEYVIEW(dev)) { 4649 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4650 mode = GEN6_RC_CTL_RC6_ENABLE; 4651 else 4652 mode = 0; 4653 } 4654 if (HAS_RC6p(dev)) 4655 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4656 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 4657 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 4658 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 4659 4660 else 4661 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4662 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 4663 } 4664 4665 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4666 { 4667 /* No RC6 before Ironlake and code is gone for ilk. */ 4668 if (INTEL_INFO(dev)->gen < 6) 4669 return 0; 4670 4671 /* Respect the kernel parameter if it is set */ 4672 if (enable_rc6 >= 0) { 4673 int mask; 4674 4675 if (HAS_RC6p(dev)) 4676 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4677 INTEL_RC6pp_ENABLE; 4678 else 4679 mask = INTEL_RC6_ENABLE; 4680 4681 if ((enable_rc6 & mask) != enable_rc6) 4682 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4683 enable_rc6 & mask, enable_rc6, mask); 4684 4685 return enable_rc6 & mask; 4686 } 4687 4688 if (IS_IVYBRIDGE(dev)) 4689 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4690 4691 return INTEL_RC6_ENABLE; 4692 } 4693 4694 int intel_enable_rc6(const struct drm_device *dev) 4695 { 4696 return i915.enable_rc6; 4697 } 4698 4699 static void gen6_init_rps_frequencies(struct drm_device *dev) 4700 { 4701 struct drm_i915_private *dev_priv = dev->dev_private; 4702 uint32_t rp_state_cap; 4703 u32 ddcc_status = 0; 4704 int ret; 4705 4706 /* All of these values are in units of 50MHz */ 4707 dev_priv->rps.cur_freq = 0; 4708 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4709 if (IS_BROXTON(dev)) { 4710 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4711 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4712 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4713 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4714 } else { 4715 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4716 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4717 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4718 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4719 } 4720 4721 /* hw_max = RP0 until we check for overclocking */ 4722 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4723 4724 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4725 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { 4726 ret = sandybridge_pcode_read(dev_priv, 4727 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4728 &ddcc_status); 4729 if (0 == ret) 4730 dev_priv->rps.efficient_freq = 4731 clamp_t(u8, 4732 ((ddcc_status >> 8) & 0xff), 4733 dev_priv->rps.min_freq, 4734 dev_priv->rps.max_freq); 4735 } 4736 4737 if (IS_SKYLAKE(dev)) { 4738 /* Store the frequency values in 16.66 MHZ units, which is 4739 the natural hardware unit for SKL */ 4740 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4741 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4742 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4743 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4744 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4745 } 4746 4747 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4748 4749 /* Preserve min/max settings in case of re-init */ 4750 if (dev_priv->rps.max_freq_softlimit == 0) 4751 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4752 4753 if (dev_priv->rps.min_freq_softlimit == 0) { 4754 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4755 dev_priv->rps.min_freq_softlimit = 4756 max_t(int, dev_priv->rps.efficient_freq, 4757 intel_freq_opcode(dev_priv, 450)); 4758 else 4759 dev_priv->rps.min_freq_softlimit = 4760 dev_priv->rps.min_freq; 4761 } 4762 } 4763 4764 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4765 static void gen9_enable_rps(struct drm_device *dev) 4766 { 4767 struct drm_i915_private *dev_priv = dev->dev_private; 4768 4769 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4770 4771 gen6_init_rps_frequencies(dev); 4772 4773 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4774 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { 4775 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4776 return; 4777 } 4778 4779 /* Program defaults and thresholds for RPS*/ 4780 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4781 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4782 4783 /* 1 second timeout*/ 4784 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4785 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4786 4787 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4788 4789 /* Leaning on the below call to gen6_set_rps to program/setup the 4790 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4791 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4792 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4793 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4794 4795 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4796 } 4797 4798 static void gen9_enable_rc6(struct drm_device *dev) 4799 { 4800 struct drm_i915_private *dev_priv = dev->dev_private; 4801 struct intel_engine_cs *ring; 4802 uint32_t rc6_mask = 0; 4803 int unused; 4804 4805 /* 1a: Software RC state - RC0 */ 4806 I915_WRITE(GEN6_RC_STATE, 0); 4807 4808 /* 1b: Get forcewake during program sequence. Although the driver 4809 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4810 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4811 4812 /* 2a: Disable RC states. */ 4813 I915_WRITE(GEN6_RC_CONTROL, 0); 4814 4815 /* 2b: Program RC6 thresholds.*/ 4816 4817 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4818 if (IS_SKYLAKE(dev)) 4819 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4820 else 4821 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4822 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4823 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4824 for_each_ring(ring, dev_priv, unused) 4825 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4826 4827 if (HAS_GUC_UCODE(dev)) 4828 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); 4829 4830 I915_WRITE(GEN6_RC_SLEEP, 0); 4831 4832 /* 2c: Program Coarse Power Gating Policies. */ 4833 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4834 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4835 4836 /* 3a: Enable RC6 */ 4837 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4838 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4839 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4840 "on" : "off"); 4841 /* WaRsUseTimeoutMode */ 4842 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || 4843 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { 4844 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ 4845 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4846 GEN7_RC_CTL_TO_MODE | 4847 rc6_mask); 4848 } else { 4849 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4850 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4851 GEN6_RC_CTL_EI_MODE(1) | 4852 rc6_mask); 4853 } 4854 4855 /* 4856 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4857 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4858 */ 4859 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || 4860 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0))) 4861 I915_WRITE(GEN9_PG_ENABLE, 0); 4862 else 4863 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4864 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); 4865 4866 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4867 4868 } 4869 4870 static void gen8_enable_rps(struct drm_device *dev) 4871 { 4872 struct drm_i915_private *dev_priv = dev->dev_private; 4873 struct intel_engine_cs *ring; 4874 uint32_t rc6_mask = 0; 4875 int unused; 4876 4877 /* 1a: Software RC state - RC0 */ 4878 I915_WRITE(GEN6_RC_STATE, 0); 4879 4880 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4881 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4882 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4883 4884 /* 2a: Disable RC states. */ 4885 I915_WRITE(GEN6_RC_CONTROL, 0); 4886 4887 /* Initialize rps frequencies */ 4888 gen6_init_rps_frequencies(dev); 4889 4890 /* 2b: Program RC6 thresholds.*/ 4891 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4892 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4893 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4894 for_each_ring(ring, dev_priv, unused) 4895 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4896 I915_WRITE(GEN6_RC_SLEEP, 0); 4897 if (IS_BROADWELL(dev)) 4898 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4899 else 4900 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4901 4902 /* 3: Enable RC6 */ 4903 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4904 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4905 intel_print_rc6_info(dev, rc6_mask); 4906 if (IS_BROADWELL(dev)) 4907 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4908 GEN7_RC_CTL_TO_MODE | 4909 rc6_mask); 4910 else 4911 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4912 GEN6_RC_CTL_EI_MODE(1) | 4913 rc6_mask); 4914 4915 /* 4 Program defaults and thresholds for RPS*/ 4916 I915_WRITE(GEN6_RPNSWREQ, 4917 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4918 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4919 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4920 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4921 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4922 4923 /* Docs recommend 900MHz, and 300 MHz respectively */ 4924 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4925 dev_priv->rps.max_freq_softlimit << 24 | 4926 dev_priv->rps.min_freq_softlimit << 16); 4927 4928 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4929 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4930 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4931 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4932 4933 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4934 4935 /* 5: Enable RPS */ 4936 I915_WRITE(GEN6_RP_CONTROL, 4937 GEN6_RP_MEDIA_TURBO | 4938 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4939 GEN6_RP_MEDIA_IS_GFX | 4940 GEN6_RP_ENABLE | 4941 GEN6_RP_UP_BUSY_AVG | 4942 GEN6_RP_DOWN_IDLE_AVG); 4943 4944 /* 6: Ring frequency + overclocking (our driver does this later */ 4945 4946 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4947 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4948 4949 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4950 } 4951 4952 static void gen6_enable_rps(struct drm_device *dev) 4953 { 4954 struct drm_i915_private *dev_priv = dev->dev_private; 4955 struct intel_engine_cs *ring; 4956 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4957 u32 gtfifodbg; 4958 int rc6_mode; 4959 int i, ret; 4960 4961 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4962 4963 /* Here begins a magic sequence of register writes to enable 4964 * auto-downclocking. 4965 * 4966 * Perhaps there might be some value in exposing these to 4967 * userspace... 4968 */ 4969 I915_WRITE(GEN6_RC_STATE, 0); 4970 4971 /* Clear the DBG now so we don't confuse earlier errors */ 4972 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 4973 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 4974 I915_WRITE(GTFIFODBG, gtfifodbg); 4975 } 4976 4977 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4978 4979 /* Initialize rps frequencies */ 4980 gen6_init_rps_frequencies(dev); 4981 4982 /* disable the counters and set deterministic thresholds */ 4983 I915_WRITE(GEN6_RC_CONTROL, 0); 4984 4985 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 4986 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 4987 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 4988 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 4989 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 4990 4991 for_each_ring(ring, dev_priv, i) 4992 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4993 4994 I915_WRITE(GEN6_RC_SLEEP, 0); 4995 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 4996 if (IS_IVYBRIDGE(dev)) 4997 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 4998 else 4999 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 5000 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 5001 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 5002 5003 /* Check if we are enabling RC6 */ 5004 rc6_mode = intel_enable_rc6(dev_priv->dev); 5005 if (rc6_mode & INTEL_RC6_ENABLE) 5006 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 5007 5008 /* We don't use those on Haswell */ 5009 if (!IS_HASWELL(dev)) { 5010 if (rc6_mode & INTEL_RC6p_ENABLE) 5011 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 5012 5013 if (rc6_mode & INTEL_RC6pp_ENABLE) 5014 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 5015 } 5016 5017 intel_print_rc6_info(dev, rc6_mask); 5018 5019 I915_WRITE(GEN6_RC_CONTROL, 5020 rc6_mask | 5021 GEN6_RC_CTL_EI_MODE(1) | 5022 GEN6_RC_CTL_HW_ENABLE); 5023 5024 /* Power down if completely idle for over 50ms */ 5025 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 5026 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5027 5028 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 5029 if (ret) 5030 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5031 5032 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5033 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 5034 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5035 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5036 (pcu_mbox & 0xff) * 50); 5037 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5038 } 5039 5040 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5041 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5042 5043 rc6vids = 0; 5044 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5045 if (IS_GEN6(dev) && ret) { 5046 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5047 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5048 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5049 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5050 rc6vids &= 0xffff00; 5051 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5052 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5053 if (ret) 5054 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5055 } 5056 5057 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5058 } 5059 5060 static void __gen6_update_ring_freq(struct drm_device *dev) 5061 { 5062 struct drm_i915_private *dev_priv = dev->dev_private; 5063 int min_freq = 15; 5064 unsigned int gpu_freq; 5065 unsigned int max_ia_freq, min_ring_freq; 5066 unsigned int max_gpu_freq, min_gpu_freq; 5067 int scaling_factor = 180; 5068 #ifndef __NetBSD__ 5069 struct cpufreq_policy *policy; 5070 #endif 5071 5072 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5073 5074 #ifdef __NetBSD__ 5075 { 5076 extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */ 5077 max_ia_freq = (tsc_freq / 1000); 5078 } 5079 #else 5080 policy = cpufreq_cpu_get(0); 5081 if (policy) { 5082 max_ia_freq = policy->cpuinfo.max_freq; 5083 cpufreq_cpu_put(policy); 5084 } else { 5085 /* 5086 * Default to measured freq if none found, PCU will ensure we 5087 * don't go over 5088 */ 5089 max_ia_freq = tsc_khz; 5090 } 5091 #endif 5092 5093 /* Convert from kHz to MHz */ 5094 max_ia_freq /= 1000; 5095 5096 min_ring_freq = I915_READ(DCLK) & 0xf; 5097 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5098 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5099 5100 if (IS_SKYLAKE(dev)) { 5101 /* Convert GT frequency to 50 HZ units */ 5102 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5103 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5104 } else { 5105 min_gpu_freq = dev_priv->rps.min_freq; 5106 max_gpu_freq = dev_priv->rps.max_freq; 5107 } 5108 5109 /* 5110 * For each potential GPU frequency, load a ring frequency we'd like 5111 * to use for memory access. We do this by specifying the IA frequency 5112 * the PCU should use as a reference to determine the ring frequency. 5113 */ 5114 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5115 int diff = max_gpu_freq - gpu_freq; 5116 unsigned int ia_freq = 0, ring_freq = 0; 5117 5118 if (IS_SKYLAKE(dev)) { 5119 /* 5120 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5121 * No floor required for ring frequency on SKL. 5122 */ 5123 ring_freq = gpu_freq; 5124 } else if (INTEL_INFO(dev)->gen >= 8) { 5125 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5126 ring_freq = max(min_ring_freq, gpu_freq); 5127 } else if (IS_HASWELL(dev)) { 5128 ring_freq = mult_frac(gpu_freq, 5, 4); 5129 ring_freq = max(min_ring_freq, ring_freq); 5130 /* leave ia_freq as the default, chosen by cpufreq */ 5131 } else { 5132 /* On older processors, there is no separate ring 5133 * clock domain, so in order to boost the bandwidth 5134 * of the ring, we need to upclock the CPU (ia_freq). 5135 * 5136 * For GPU frequencies less than 750MHz, 5137 * just use the lowest ring freq. 5138 */ 5139 if (gpu_freq < min_freq) 5140 ia_freq = 800; 5141 else 5142 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5143 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5144 } 5145 5146 sandybridge_pcode_write(dev_priv, 5147 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5148 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5149 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5150 gpu_freq); 5151 } 5152 } 5153 5154 void gen6_update_ring_freq(struct drm_device *dev) 5155 { 5156 struct drm_i915_private *dev_priv = dev->dev_private; 5157 5158 if (!HAS_CORE_RING_FREQ(dev)) 5159 return; 5160 5161 mutex_lock(&dev_priv->rps.hw_lock); 5162 __gen6_update_ring_freq(dev); 5163 mutex_unlock(&dev_priv->rps.hw_lock); 5164 } 5165 5166 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5167 { 5168 struct drm_device *dev = dev_priv->dev; 5169 u32 val, rp0; 5170 5171 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5172 5173 switch (INTEL_INFO(dev)->eu_total) { 5174 case 8: 5175 /* (2 * 4) config */ 5176 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5177 break; 5178 case 12: 5179 /* (2 * 6) config */ 5180 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5181 break; 5182 case 16: 5183 /* (2 * 8) config */ 5184 default: 5185 /* Setting (2 * 8) Min RP0 for any other combination */ 5186 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5187 break; 5188 } 5189 5190 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5191 5192 return rp0; 5193 } 5194 5195 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5196 { 5197 u32 val, rpe; 5198 5199 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5200 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5201 5202 return rpe; 5203 } 5204 5205 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5206 { 5207 u32 val, rp1; 5208 5209 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5210 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5211 5212 return rp1; 5213 } 5214 5215 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5216 { 5217 u32 val, rp1; 5218 5219 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5220 5221 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5222 5223 return rp1; 5224 } 5225 5226 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5227 { 5228 u32 val, rp0; 5229 5230 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5231 5232 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5233 /* Clamp to max */ 5234 rp0 = min_t(u32, rp0, 0xea); 5235 5236 return rp0; 5237 } 5238 5239 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5240 { 5241 u32 val, rpe; 5242 5243 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5244 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5245 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5246 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5247 5248 return rpe; 5249 } 5250 5251 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5252 { 5253 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5254 } 5255 5256 /* Check that the pctx buffer wasn't move under us. */ 5257 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5258 { 5259 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5260 5261 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5262 dev_priv->vlv_pctx->stolen->start); 5263 } 5264 5265 5266 /* Check that the pcbr address is not empty. */ 5267 static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5268 { 5269 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5270 5271 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5272 } 5273 5274 static void cherryview_setup_pctx(struct drm_device *dev) 5275 { 5276 struct drm_i915_private *dev_priv = dev->dev_private; 5277 unsigned long pctx_paddr, paddr; 5278 struct i915_gtt *gtt = &dev_priv->gtt; 5279 u32 pcbr; 5280 int pctx_size = 32*1024; 5281 5282 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5283 5284 pcbr = I915_READ(VLV_PCBR); 5285 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5286 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5287 paddr = (dev_priv->mm.stolen_base + 5288 (gtt->stolen_size - pctx_size)); 5289 5290 pctx_paddr = (paddr & (~4095)); 5291 I915_WRITE(VLV_PCBR, pctx_paddr); 5292 } 5293 5294 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5295 } 5296 5297 static void valleyview_setup_pctx(struct drm_device *dev) 5298 { 5299 struct drm_i915_private *dev_priv = dev->dev_private; 5300 struct drm_i915_gem_object *pctx; 5301 unsigned long pctx_paddr; 5302 u32 pcbr; 5303 int pctx_size = 24*1024; 5304 5305 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5306 5307 pcbr = I915_READ(VLV_PCBR); 5308 if (pcbr) { 5309 /* BIOS set it up already, grab the pre-alloc'd space */ 5310 int pcbr_offset; 5311 5312 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5313 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5314 pcbr_offset, 5315 I915_GTT_OFFSET_NONE, 5316 pctx_size); 5317 goto out; 5318 } 5319 5320 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5321 5322 /* 5323 * From the Gunit register HAS: 5324 * The Gfx driver is expected to program this register and ensure 5325 * proper allocation within Gfx stolen memory. For example, this 5326 * register should be programmed such than the PCBR range does not 5327 * overlap with other ranges, such as the frame buffer, protected 5328 * memory, or any other relevant ranges. 5329 */ 5330 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5331 if (!pctx) { 5332 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5333 return; 5334 } 5335 5336 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5337 I915_WRITE(VLV_PCBR, pctx_paddr); 5338 5339 out: 5340 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5341 dev_priv->vlv_pctx = pctx; 5342 } 5343 5344 static void valleyview_cleanup_pctx(struct drm_device *dev) 5345 { 5346 struct drm_i915_private *dev_priv = dev->dev_private; 5347 5348 if (WARN_ON(!dev_priv->vlv_pctx)) 5349 return; 5350 5351 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 5352 dev_priv->vlv_pctx = NULL; 5353 } 5354 5355 static void valleyview_init_gt_powersave(struct drm_device *dev) 5356 { 5357 struct drm_i915_private *dev_priv = dev->dev_private; 5358 u32 val; 5359 5360 valleyview_setup_pctx(dev); 5361 5362 mutex_lock(&dev_priv->rps.hw_lock); 5363 5364 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5365 switch ((val >> 6) & 3) { 5366 case 0: 5367 case 1: 5368 dev_priv->mem_freq = 800; 5369 break; 5370 case 2: 5371 dev_priv->mem_freq = 1066; 5372 break; 5373 case 3: 5374 dev_priv->mem_freq = 1333; 5375 break; 5376 } 5377 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5378 5379 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5380 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5381 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5382 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5383 dev_priv->rps.max_freq); 5384 5385 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5386 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5387 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5388 dev_priv->rps.efficient_freq); 5389 5390 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5391 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5392 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5393 dev_priv->rps.rp1_freq); 5394 5395 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5396 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5397 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5398 dev_priv->rps.min_freq); 5399 5400 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5401 5402 /* Preserve min/max settings in case of re-init */ 5403 if (dev_priv->rps.max_freq_softlimit == 0) 5404 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5405 5406 if (dev_priv->rps.min_freq_softlimit == 0) 5407 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5408 5409 mutex_unlock(&dev_priv->rps.hw_lock); 5410 } 5411 5412 static void cherryview_init_gt_powersave(struct drm_device *dev) 5413 { 5414 struct drm_i915_private *dev_priv = dev->dev_private; 5415 u32 val; 5416 5417 cherryview_setup_pctx(dev); 5418 5419 mutex_lock(&dev_priv->rps.hw_lock); 5420 5421 mutex_lock(&dev_priv->sb_lock); 5422 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5423 mutex_unlock(&dev_priv->sb_lock); 5424 5425 switch ((val >> 2) & 0x7) { 5426 case 3: 5427 dev_priv->mem_freq = 2000; 5428 break; 5429 default: 5430 dev_priv->mem_freq = 1600; 5431 break; 5432 } 5433 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5434 5435 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5436 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5437 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5438 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5439 dev_priv->rps.max_freq); 5440 5441 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5442 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5443 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5444 dev_priv->rps.efficient_freq); 5445 5446 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5447 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5448 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5449 dev_priv->rps.rp1_freq); 5450 5451 /* PUnit validated range is only [RPe, RP0] */ 5452 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5453 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5454 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5455 dev_priv->rps.min_freq); 5456 5457 WARN_ONCE((dev_priv->rps.max_freq | 5458 dev_priv->rps.efficient_freq | 5459 dev_priv->rps.rp1_freq | 5460 dev_priv->rps.min_freq) & 1, 5461 "Odd GPU freq values\n"); 5462 5463 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5464 5465 /* Preserve min/max settings in case of re-init */ 5466 if (dev_priv->rps.max_freq_softlimit == 0) 5467 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5468 5469 if (dev_priv->rps.min_freq_softlimit == 0) 5470 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5471 5472 mutex_unlock(&dev_priv->rps.hw_lock); 5473 } 5474 5475 static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5476 { 5477 valleyview_cleanup_pctx(dev); 5478 } 5479 5480 static void cherryview_enable_rps(struct drm_device *dev) 5481 { 5482 struct drm_i915_private *dev_priv = dev->dev_private; 5483 struct intel_engine_cs *ring; 5484 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5485 int i; 5486 5487 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5488 5489 gtfifodbg = I915_READ(GTFIFODBG); 5490 if (gtfifodbg) { 5491 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5492 gtfifodbg); 5493 I915_WRITE(GTFIFODBG, gtfifodbg); 5494 } 5495 5496 cherryview_check_pctx(dev_priv); 5497 5498 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5499 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5500 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5501 5502 /* Disable RC states. */ 5503 I915_WRITE(GEN6_RC_CONTROL, 0); 5504 5505 /* 2a: Program RC6 thresholds.*/ 5506 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5507 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5508 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5509 5510 for_each_ring(ring, dev_priv, i) 5511 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5512 I915_WRITE(GEN6_RC_SLEEP, 0); 5513 5514 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5515 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5516 5517 /* allows RC6 residency counter to work */ 5518 I915_WRITE(VLV_COUNTER_CONTROL, 5519 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5520 VLV_MEDIA_RC6_COUNT_EN | 5521 VLV_RENDER_RC6_COUNT_EN)); 5522 5523 /* For now we assume BIOS is allocating and populating the PCBR */ 5524 pcbr = I915_READ(VLV_PCBR); 5525 5526 /* 3: Enable RC6 */ 5527 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5528 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5529 rc6_mode = GEN7_RC_CTL_TO_MODE; 5530 5531 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5532 5533 /* 4 Program defaults and thresholds for RPS*/ 5534 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5535 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5536 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5537 I915_WRITE(GEN6_RP_UP_EI, 66000); 5538 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5539 5540 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5541 5542 /* 5: Enable RPS */ 5543 I915_WRITE(GEN6_RP_CONTROL, 5544 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5545 GEN6_RP_MEDIA_IS_GFX | 5546 GEN6_RP_ENABLE | 5547 GEN6_RP_UP_BUSY_AVG | 5548 GEN6_RP_DOWN_IDLE_AVG); 5549 5550 /* Setting Fixed Bias */ 5551 val = VLV_OVERRIDE_EN | 5552 VLV_SOC_TDP_EN | 5553 CHV_BIAS_CPU_50_SOC_50; 5554 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5555 5556 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5557 5558 /* RPS code assumes GPLL is used */ 5559 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5560 5561 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5562 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5563 5564 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5565 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5566 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5567 dev_priv->rps.cur_freq); 5568 5569 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5570 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5571 dev_priv->rps.efficient_freq); 5572 5573 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5574 5575 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5576 } 5577 5578 static void valleyview_enable_rps(struct drm_device *dev) 5579 { 5580 struct drm_i915_private *dev_priv = dev->dev_private; 5581 struct intel_engine_cs *ring; 5582 u32 gtfifodbg, val, rc6_mode = 0; 5583 int i; 5584 5585 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5586 5587 valleyview_check_pctx(dev_priv); 5588 5589 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5590 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5591 gtfifodbg); 5592 I915_WRITE(GTFIFODBG, gtfifodbg); 5593 } 5594 5595 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5596 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5597 5598 /* Disable RC states. */ 5599 I915_WRITE(GEN6_RC_CONTROL, 0); 5600 5601 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5602 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5603 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5604 I915_WRITE(GEN6_RP_UP_EI, 66000); 5605 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5606 5607 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5608 5609 I915_WRITE(GEN6_RP_CONTROL, 5610 GEN6_RP_MEDIA_TURBO | 5611 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5612 GEN6_RP_MEDIA_IS_GFX | 5613 GEN6_RP_ENABLE | 5614 GEN6_RP_UP_BUSY_AVG | 5615 GEN6_RP_DOWN_IDLE_CONT); 5616 5617 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5618 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5619 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5620 5621 for_each_ring(ring, dev_priv, i) 5622 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5623 5624 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5625 5626 /* allows RC6 residency counter to work */ 5627 I915_WRITE(VLV_COUNTER_CONTROL, 5628 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5629 VLV_RENDER_RC0_COUNT_EN | 5630 VLV_MEDIA_RC6_COUNT_EN | 5631 VLV_RENDER_RC6_COUNT_EN)); 5632 5633 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5634 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5635 5636 intel_print_rc6_info(dev, rc6_mode); 5637 5638 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5639 5640 /* Setting Fixed Bias */ 5641 val = VLV_OVERRIDE_EN | 5642 VLV_SOC_TDP_EN | 5643 VLV_BIAS_CPU_125_SOC_875; 5644 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5645 5646 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5647 5648 /* RPS code assumes GPLL is used */ 5649 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5650 5651 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5652 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5653 5654 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5655 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5656 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5657 dev_priv->rps.cur_freq); 5658 5659 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5660 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5661 dev_priv->rps.efficient_freq); 5662 5663 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5664 5665 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5666 } 5667 5668 static unsigned long intel_pxfreq(u32 vidfreq) 5669 { 5670 unsigned long freq; 5671 int div = (vidfreq & 0x3f0000) >> 16; 5672 int post = (vidfreq & 0x3000) >> 12; 5673 int pre = (vidfreq & 0x7); 5674 5675 if (!pre) 5676 return 0; 5677 5678 freq = ((div * 133333) / ((1<<post) * pre)); 5679 5680 return freq; 5681 } 5682 5683 static const struct cparams { 5684 u16 i; 5685 u16 t; 5686 u16 m; 5687 u16 c; 5688 } cparams[] = { 5689 { 1, 1333, 301, 28664 }, 5690 { 1, 1066, 294, 24460 }, 5691 { 1, 800, 294, 25192 }, 5692 { 0, 1333, 276, 27605 }, 5693 { 0, 1066, 276, 27605 }, 5694 { 0, 800, 231, 23784 }, 5695 }; 5696 5697 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5698 { 5699 u64 total_count, diff, ret; 5700 u32 count1, count2, count3, m = 0, c = 0; 5701 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5702 int i; 5703 5704 assert_spin_locked(&mchdev_lock); 5705 5706 diff1 = now - dev_priv->ips.last_time1; 5707 5708 /* Prevent division-by-zero if we are asking too fast. 5709 * Also, we don't get interesting results if we are polling 5710 * faster than once in 10ms, so just return the saved value 5711 * in such cases. 5712 */ 5713 if (diff1 <= 10) 5714 return dev_priv->ips.chipset_power; 5715 5716 count1 = I915_READ(DMIEC); 5717 count2 = I915_READ(DDREC); 5718 count3 = I915_READ(CSIEC); 5719 5720 total_count = count1 + count2 + count3; 5721 5722 /* FIXME: handle per-counter overflow */ 5723 if (total_count < dev_priv->ips.last_count1) { 5724 diff = ~0UL - dev_priv->ips.last_count1; 5725 diff += total_count; 5726 } else { 5727 diff = total_count - dev_priv->ips.last_count1; 5728 } 5729 5730 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5731 if (cparams[i].i == dev_priv->ips.c_m && 5732 cparams[i].t == dev_priv->ips.r_t) { 5733 m = cparams[i].m; 5734 c = cparams[i].c; 5735 break; 5736 } 5737 } 5738 5739 diff = div_u64(diff, diff1); 5740 ret = ((m * diff) + c); 5741 ret = div_u64(ret, 10); 5742 5743 dev_priv->ips.last_count1 = total_count; 5744 dev_priv->ips.last_time1 = now; 5745 5746 dev_priv->ips.chipset_power = ret; 5747 5748 return ret; 5749 } 5750 5751 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5752 { 5753 struct drm_device *dev = dev_priv->dev; 5754 unsigned long val; 5755 5756 if (INTEL_INFO(dev)->gen != 5) 5757 return 0; 5758 5759 spin_lock_irq(&mchdev_lock); 5760 5761 val = __i915_chipset_val(dev_priv); 5762 5763 spin_unlock_irq(&mchdev_lock); 5764 5765 return val; 5766 } 5767 5768 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5769 { 5770 unsigned long m, x, b; 5771 u32 tsfs; 5772 5773 tsfs = I915_READ(TSFS); 5774 5775 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5776 x = I915_READ8(TR1); 5777 5778 b = tsfs & TSFS_INTR_MASK; 5779 5780 return ((m * x) / 127) - b; 5781 } 5782 5783 static int _pxvid_to_vd(u8 pxvid) 5784 { 5785 if (pxvid == 0) 5786 return 0; 5787 5788 if (pxvid >= 8 && pxvid < 31) 5789 pxvid = 31; 5790 5791 return (pxvid + 2) * 125; 5792 } 5793 5794 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5795 { 5796 struct drm_device *dev = dev_priv->dev; 5797 const int vd = _pxvid_to_vd(pxvid); 5798 const int vm = vd - 1125; 5799 5800 if (INTEL_INFO(dev)->is_mobile) 5801 return vm > 0 ? vm : 0; 5802 5803 return vd; 5804 } 5805 5806 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5807 { 5808 u64 now, diff, diffms; 5809 u32 count; 5810 5811 assert_spin_locked(&mchdev_lock); 5812 5813 now = ktime_get_raw_ns(); 5814 diffms = now - dev_priv->ips.last_time2; 5815 do_div(diffms, NSEC_PER_MSEC); 5816 5817 /* Don't divide by 0 */ 5818 if (!diffms) 5819 return; 5820 5821 count = I915_READ(GFXEC); 5822 5823 if (count < dev_priv->ips.last_count2) { 5824 diff = ~0UL - dev_priv->ips.last_count2; 5825 diff += count; 5826 } else { 5827 diff = count - dev_priv->ips.last_count2; 5828 } 5829 5830 dev_priv->ips.last_count2 = count; 5831 dev_priv->ips.last_time2 = now; 5832 5833 /* More magic constants... */ 5834 diff = diff * 1181; 5835 diff = div_u64(diff, diffms * 10); 5836 dev_priv->ips.gfx_power = diff; 5837 } 5838 5839 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5840 { 5841 struct drm_device *dev = dev_priv->dev; 5842 5843 if (INTEL_INFO(dev)->gen != 5) 5844 return; 5845 5846 spin_lock_irq(&mchdev_lock); 5847 5848 __i915_update_gfx_val(dev_priv); 5849 5850 spin_unlock_irq(&mchdev_lock); 5851 } 5852 5853 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5854 { 5855 unsigned long t, corr, state1, corr2, state2; 5856 u32 pxvid, ext_v; 5857 5858 assert_spin_locked(&mchdev_lock); 5859 5860 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); 5861 pxvid = (pxvid >> 24) & 0x7f; 5862 ext_v = pvid_to_extvid(dev_priv, pxvid); 5863 5864 state1 = ext_v; 5865 5866 t = i915_mch_val(dev_priv); 5867 5868 /* Revel in the empirically derived constants */ 5869 5870 /* Correction factor in 1/100000 units */ 5871 if (t > 80) 5872 corr = ((t * 2349) + 135940); 5873 else if (t >= 50) 5874 corr = ((t * 964) + 29317); 5875 else /* < 50 */ 5876 corr = ((t * 301) + 1004); 5877 5878 corr = corr * ((150142 * state1) / 10000 - 78642); 5879 corr /= 100000; 5880 corr2 = (corr * dev_priv->ips.corr); 5881 5882 state2 = (corr2 * state1) / 10000; 5883 state2 /= 100; /* convert to mW */ 5884 5885 __i915_update_gfx_val(dev_priv); 5886 5887 return dev_priv->ips.gfx_power + state2; 5888 } 5889 5890 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5891 { 5892 struct drm_device *dev = dev_priv->dev; 5893 unsigned long val; 5894 5895 if (INTEL_INFO(dev)->gen != 5) 5896 return 0; 5897 5898 spin_lock_irq(&mchdev_lock); 5899 5900 val = __i915_gfx_val(dev_priv); 5901 5902 spin_unlock_irq(&mchdev_lock); 5903 5904 return val; 5905 } 5906 5907 /** 5908 * i915_read_mch_val - return value for IPS use 5909 * 5910 * Calculate and return a value for the IPS driver to use when deciding whether 5911 * we have thermal and power headroom to increase CPU or GPU power budget. 5912 */ 5913 unsigned long i915_read_mch_val(void) 5914 { 5915 struct drm_i915_private *dev_priv; 5916 unsigned long chipset_val, graphics_val, ret = 0; 5917 5918 spin_lock_irq(&mchdev_lock); 5919 if (!i915_mch_dev) 5920 goto out_unlock; 5921 dev_priv = i915_mch_dev; 5922 5923 chipset_val = __i915_chipset_val(dev_priv); 5924 graphics_val = __i915_gfx_val(dev_priv); 5925 5926 ret = chipset_val + graphics_val; 5927 5928 out_unlock: 5929 spin_unlock_irq(&mchdev_lock); 5930 5931 return ret; 5932 } 5933 EXPORT_SYMBOL_GPL(i915_read_mch_val); 5934 5935 /** 5936 * i915_gpu_raise - raise GPU frequency limit 5937 * 5938 * Raise the limit; IPS indicates we have thermal headroom. 5939 */ 5940 bool i915_gpu_raise(void) 5941 { 5942 struct drm_i915_private *dev_priv; 5943 bool ret = true; 5944 5945 spin_lock_irq(&mchdev_lock); 5946 if (!i915_mch_dev) { 5947 ret = false; 5948 goto out_unlock; 5949 } 5950 dev_priv = i915_mch_dev; 5951 5952 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5953 dev_priv->ips.max_delay--; 5954 5955 out_unlock: 5956 spin_unlock_irq(&mchdev_lock); 5957 5958 return ret; 5959 } 5960 EXPORT_SYMBOL_GPL(i915_gpu_raise); 5961 5962 /** 5963 * i915_gpu_lower - lower GPU frequency limit 5964 * 5965 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5966 * frequency maximum. 5967 */ 5968 bool i915_gpu_lower(void) 5969 { 5970 struct drm_i915_private *dev_priv; 5971 bool ret = true; 5972 5973 spin_lock_irq(&mchdev_lock); 5974 if (!i915_mch_dev) { 5975 ret = false; 5976 goto out_unlock; 5977 } 5978 dev_priv = i915_mch_dev; 5979 5980 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 5981 dev_priv->ips.max_delay++; 5982 5983 out_unlock: 5984 spin_unlock_irq(&mchdev_lock); 5985 5986 return ret; 5987 } 5988 EXPORT_SYMBOL_GPL(i915_gpu_lower); 5989 5990 /** 5991 * i915_gpu_busy - indicate GPU business to IPS 5992 * 5993 * Tell the IPS driver whether or not the GPU is busy. 5994 */ 5995 bool i915_gpu_busy(void) 5996 { 5997 struct drm_i915_private *dev_priv; 5998 struct intel_engine_cs *ring; 5999 bool ret = false; 6000 int i; 6001 6002 spin_lock_irq(&mchdev_lock); 6003 if (!i915_mch_dev) 6004 goto out_unlock; 6005 dev_priv = i915_mch_dev; 6006 6007 for_each_ring(ring, dev_priv, i) 6008 ret |= !list_empty(&ring->request_list); 6009 6010 out_unlock: 6011 spin_unlock_irq(&mchdev_lock); 6012 6013 return ret; 6014 } 6015 EXPORT_SYMBOL_GPL(i915_gpu_busy); 6016 6017 /** 6018 * i915_gpu_turbo_disable - disable graphics turbo 6019 * 6020 * Disable graphics turbo by resetting the max frequency and setting the 6021 * current frequency to the default. 6022 */ 6023 bool i915_gpu_turbo_disable(void) 6024 { 6025 struct drm_i915_private *dev_priv; 6026 bool ret = true; 6027 6028 spin_lock_irq(&mchdev_lock); 6029 if (!i915_mch_dev) { 6030 ret = false; 6031 goto out_unlock; 6032 } 6033 dev_priv = i915_mch_dev; 6034 6035 dev_priv->ips.max_delay = dev_priv->ips.fstart; 6036 6037 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 6038 ret = false; 6039 6040 out_unlock: 6041 spin_unlock_irq(&mchdev_lock); 6042 6043 return ret; 6044 } 6045 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 6046 6047 /** 6048 * Tells the intel_ips driver that the i915 driver is now loaded, if 6049 * IPS got loaded first. 6050 * 6051 * This awkward dance is so that neither module has to depend on the 6052 * other in order for IPS to do the appropriate communication of 6053 * GPU turbo limits to i915. 6054 */ 6055 static void 6056 ips_ping_for_i915_load(void) 6057 { 6058 #ifndef __NetBSD__ /* XXX IPS GPU turbo limits what? */ 6059 void (*link)(void); 6060 6061 link = symbol_get(ips_link_to_i915_driver); 6062 if (link) { 6063 link(); 6064 symbol_put(ips_link_to_i915_driver); 6065 } 6066 #endif 6067 } 6068 6069 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6070 { 6071 /* We only register the i915 ips part with intel-ips once everything is 6072 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6073 spin_lock_irq(&mchdev_lock); 6074 i915_mch_dev = dev_priv; 6075 spin_unlock_irq(&mchdev_lock); 6076 6077 ips_ping_for_i915_load(); 6078 } 6079 6080 void intel_gpu_ips_teardown(void) 6081 { 6082 spin_lock_irq(&mchdev_lock); 6083 i915_mch_dev = NULL; 6084 spin_unlock_irq(&mchdev_lock); 6085 } 6086 6087 static void intel_init_emon(struct drm_device *dev) 6088 { 6089 struct drm_i915_private *dev_priv = dev->dev_private; 6090 u32 lcfuse; 6091 u8 pxw[16]; 6092 int i; 6093 6094 /* Disable to program */ 6095 I915_WRITE(ECR, 0); 6096 POSTING_READ(ECR); 6097 6098 /* Program energy weights for various events */ 6099 I915_WRITE(SDEW, 0x15040d00); 6100 I915_WRITE(CSIEW0, 0x007f0000); 6101 I915_WRITE(CSIEW1, 0x1e220004); 6102 I915_WRITE(CSIEW2, 0x04000004); 6103 6104 for (i = 0; i < 5; i++) 6105 I915_WRITE(PEW(i), 0); 6106 for (i = 0; i < 3; i++) 6107 I915_WRITE(DEW(i), 0); 6108 6109 /* Program P-state weights to account for frequency power adjustment */ 6110 for (i = 0; i < 16; i++) { 6111 u32 pxvidfreq = I915_READ(PXVFREQ(i)); 6112 unsigned long freq = intel_pxfreq(pxvidfreq); 6113 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6114 PXVFREQ_PX_SHIFT; 6115 unsigned long val; 6116 6117 val = vid * vid; 6118 val *= (freq / 1000); 6119 val *= 255; 6120 val /= (127*127*900); 6121 if (val > 0xff) 6122 DRM_ERROR("bad pxval: %ld\n", val); 6123 pxw[i] = val; 6124 } 6125 /* Render standby states get 0 weight */ 6126 pxw[14] = 0; 6127 pxw[15] = 0; 6128 6129 for (i = 0; i < 4; i++) { 6130 u32 val = ((u32)pxw[i*4] << 24) | ((u32)pxw[(i*4)+1] << 16) | 6131 ((u32)pxw[(i*4)+2] << 8) | ((u32)pxw[(i*4)+3]); 6132 I915_WRITE(PXW(i), val); 6133 } 6134 6135 /* Adjust magic regs to magic values (more experimental results) */ 6136 I915_WRITE(OGW0, 0); 6137 I915_WRITE(OGW1, 0); 6138 I915_WRITE(EG0, 0x00007f00); 6139 I915_WRITE(EG1, 0x0000000e); 6140 I915_WRITE(EG2, 0x000e0000); 6141 I915_WRITE(EG3, 0x68000300); 6142 I915_WRITE(EG4, 0x42000000); 6143 I915_WRITE(EG5, 0x00140031); 6144 I915_WRITE(EG6, 0); 6145 I915_WRITE(EG7, 0); 6146 6147 for (i = 0; i < 8; i++) 6148 I915_WRITE(PXWL(i), 0); 6149 6150 /* Enable PMON + select events */ 6151 I915_WRITE(ECR, 0x80000019); 6152 6153 lcfuse = I915_READ(LCFUSE02); 6154 6155 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6156 } 6157 6158 void intel_init_gt_powersave(struct drm_device *dev) 6159 { 6160 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); 6161 6162 if (IS_CHERRYVIEW(dev)) 6163 cherryview_init_gt_powersave(dev); 6164 else if (IS_VALLEYVIEW(dev)) 6165 valleyview_init_gt_powersave(dev); 6166 } 6167 6168 void intel_cleanup_gt_powersave(struct drm_device *dev) 6169 { 6170 if (IS_CHERRYVIEW(dev)) 6171 return; 6172 else if (IS_VALLEYVIEW(dev)) 6173 valleyview_cleanup_gt_powersave(dev); 6174 } 6175 6176 static void gen6_suspend_rps(struct drm_device *dev) 6177 { 6178 struct drm_i915_private *dev_priv = dev->dev_private; 6179 6180 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6181 6182 gen6_disable_rps_interrupts(dev); 6183 } 6184 6185 /** 6186 * intel_suspend_gt_powersave - suspend PM work and helper threads 6187 * @dev: drm device 6188 * 6189 * We don't want to disable RC6 or other features here, we just want 6190 * to make sure any work we've queued has finished and won't bother 6191 * us while we're suspended. 6192 */ 6193 void intel_suspend_gt_powersave(struct drm_device *dev) 6194 { 6195 struct drm_i915_private *dev_priv = dev->dev_private; 6196 6197 if (INTEL_INFO(dev)->gen < 6) 6198 return; 6199 6200 gen6_suspend_rps(dev); 6201 6202 /* Force GPU to min freq during suspend */ 6203 gen6_rps_idle(dev_priv); 6204 } 6205 6206 void intel_disable_gt_powersave(struct drm_device *dev) 6207 { 6208 struct drm_i915_private *dev_priv = dev->dev_private; 6209 6210 if (IS_IRONLAKE_M(dev)) { 6211 ironlake_disable_drps(dev); 6212 } else if (INTEL_INFO(dev)->gen >= 6) { 6213 intel_suspend_gt_powersave(dev); 6214 6215 mutex_lock(&dev_priv->rps.hw_lock); 6216 if (INTEL_INFO(dev)->gen >= 9) 6217 gen9_disable_rps(dev); 6218 else if (IS_CHERRYVIEW(dev)) 6219 cherryview_disable_rps(dev); 6220 else if (IS_VALLEYVIEW(dev)) 6221 valleyview_disable_rps(dev); 6222 else 6223 gen6_disable_rps(dev); 6224 6225 dev_priv->rps.enabled = false; 6226 mutex_unlock(&dev_priv->rps.hw_lock); 6227 } 6228 } 6229 6230 static void intel_gen6_powersave_work(struct work_struct *work) 6231 { 6232 struct drm_i915_private *dev_priv = 6233 container_of(work, struct drm_i915_private, 6234 rps.delayed_resume_work.work); 6235 struct drm_device *dev = dev_priv->dev; 6236 6237 mutex_lock(&dev_priv->rps.hw_lock); 6238 6239 gen6_reset_rps_interrupts(dev); 6240 6241 if (IS_CHERRYVIEW(dev)) { 6242 cherryview_enable_rps(dev); 6243 } else if (IS_VALLEYVIEW(dev)) { 6244 valleyview_enable_rps(dev); 6245 } else if (INTEL_INFO(dev)->gen >= 9) { 6246 gen9_enable_rc6(dev); 6247 gen9_enable_rps(dev); 6248 if (IS_SKYLAKE(dev)) 6249 __gen6_update_ring_freq(dev); 6250 } else if (IS_BROADWELL(dev)) { 6251 gen8_enable_rps(dev); 6252 __gen6_update_ring_freq(dev); 6253 } else { 6254 gen6_enable_rps(dev); 6255 __gen6_update_ring_freq(dev); 6256 } 6257 6258 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6259 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6260 6261 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6262 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6263 6264 dev_priv->rps.enabled = true; 6265 6266 gen6_enable_rps_interrupts(dev); 6267 6268 mutex_unlock(&dev_priv->rps.hw_lock); 6269 6270 intel_runtime_pm_put(dev_priv); 6271 } 6272 6273 void intel_enable_gt_powersave(struct drm_device *dev) 6274 { 6275 struct drm_i915_private *dev_priv = dev->dev_private; 6276 6277 /* Powersaving is controlled by the host when inside a VM */ 6278 if (intel_vgpu_active(dev)) 6279 return; 6280 6281 if (IS_IRONLAKE_M(dev)) { 6282 mutex_lock(&dev->struct_mutex); 6283 ironlake_enable_drps(dev); 6284 intel_init_emon(dev); 6285 mutex_unlock(&dev->struct_mutex); 6286 } else if (INTEL_INFO(dev)->gen >= 6) { 6287 /* 6288 * PCU communication is slow and this doesn't need to be 6289 * done at any specific time, so do this out of our fast path 6290 * to make resume and init faster. 6291 * 6292 * We depend on the HW RC6 power context save/restore 6293 * mechanism when entering D3 through runtime PM suspend. So 6294 * disable RPM until RPS/RC6 is properly setup. We can only 6295 * get here via the driver load/system resume/runtime resume 6296 * paths, so the _noresume version is enough (and in case of 6297 * runtime resume it's necessary). 6298 */ 6299 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6300 round_jiffies_up_relative(HZ))) 6301 intel_runtime_pm_get_noresume(dev_priv); 6302 } 6303 } 6304 6305 void intel_reset_gt_powersave(struct drm_device *dev) 6306 { 6307 struct drm_i915_private *dev_priv = dev->dev_private; 6308 6309 if (INTEL_INFO(dev)->gen < 6) 6310 return; 6311 6312 gen6_suspend_rps(dev); 6313 dev_priv->rps.enabled = false; 6314 } 6315 6316 static void ibx_init_clock_gating(struct drm_device *dev) 6317 { 6318 struct drm_i915_private *dev_priv = dev->dev_private; 6319 6320 /* 6321 * On Ibex Peak and Cougar Point, we need to disable clock 6322 * gating for the panel power sequencer or it will fail to 6323 * start up when no ports are active. 6324 */ 6325 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6326 } 6327 6328 static void g4x_disable_trickle_feed(struct drm_device *dev) 6329 { 6330 struct drm_i915_private *dev_priv = dev->dev_private; 6331 enum i915_pipe pipe; 6332 6333 for_each_pipe(dev_priv, pipe) { 6334 I915_WRITE(DSPCNTR(pipe), 6335 I915_READ(DSPCNTR(pipe)) | 6336 DISPPLANE_TRICKLE_FEED_DISABLE); 6337 6338 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6339 POSTING_READ(DSPSURF(pipe)); 6340 } 6341 } 6342 6343 static void ilk_init_lp_watermarks(struct drm_device *dev) 6344 { 6345 struct drm_i915_private *dev_priv = dev->dev_private; 6346 6347 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6348 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6349 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6350 6351 /* 6352 * Don't touch WM1S_LP_EN here. 6353 * Doing so could cause underruns. 6354 */ 6355 } 6356 6357 static void ironlake_init_clock_gating(struct drm_device *dev) 6358 { 6359 struct drm_i915_private *dev_priv = dev->dev_private; 6360 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6361 6362 /* 6363 * Required for FBC 6364 * WaFbcDisableDpfcClockGating:ilk 6365 */ 6366 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6367 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6368 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6369 6370 I915_WRITE(PCH_3DCGDIS0, 6371 MARIUNIT_CLOCK_GATE_DISABLE | 6372 SVSMUNIT_CLOCK_GATE_DISABLE); 6373 I915_WRITE(PCH_3DCGDIS1, 6374 VFMUNIT_CLOCK_GATE_DISABLE); 6375 6376 /* 6377 * According to the spec the following bits should be set in 6378 * order to enable memory self-refresh 6379 * The bit 22/21 of 0x42004 6380 * The bit 5 of 0x42020 6381 * The bit 15 of 0x45000 6382 */ 6383 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6384 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6385 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6386 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6387 I915_WRITE(DISP_ARB_CTL, 6388 (I915_READ(DISP_ARB_CTL) | 6389 DISP_FBC_WM_DIS)); 6390 6391 ilk_init_lp_watermarks(dev); 6392 6393 /* 6394 * Based on the document from hardware guys the following bits 6395 * should be set unconditionally in order to enable FBC. 6396 * The bit 22 of 0x42000 6397 * The bit 22 of 0x42004 6398 * The bit 7,8,9 of 0x42020. 6399 */ 6400 if (IS_IRONLAKE_M(dev)) { 6401 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6402 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6403 I915_READ(ILK_DISPLAY_CHICKEN1) | 6404 ILK_FBCQ_DIS); 6405 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6406 I915_READ(ILK_DISPLAY_CHICKEN2) | 6407 ILK_DPARB_GATE); 6408 } 6409 6410 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6411 6412 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6413 I915_READ(ILK_DISPLAY_CHICKEN2) | 6414 ILK_ELPIN_409_SELECT); 6415 I915_WRITE(_3D_CHICKEN2, 6416 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6417 _3D_CHICKEN2_WM_READ_PIPELINED); 6418 6419 /* WaDisableRenderCachePipelinedFlush:ilk */ 6420 I915_WRITE(CACHE_MODE_0, 6421 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6422 6423 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6424 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6425 6426 g4x_disable_trickle_feed(dev); 6427 6428 ibx_init_clock_gating(dev); 6429 } 6430 6431 static void cpt_init_clock_gating(struct drm_device *dev) 6432 { 6433 struct drm_i915_private *dev_priv = dev->dev_private; 6434 int pipe; 6435 uint32_t val; 6436 6437 /* 6438 * On Ibex Peak and Cougar Point, we need to disable clock 6439 * gating for the panel power sequencer or it will fail to 6440 * start up when no ports are active. 6441 */ 6442 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6443 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6444 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6445 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6446 DPLS_EDP_PPS_FIX_DIS); 6447 /* The below fixes the weird display corruption, a few pixels shifted 6448 * downward, on (only) LVDS of some HP laptops with IVY. 6449 */ 6450 for_each_pipe(dev_priv, pipe) { 6451 val = I915_READ(TRANS_CHICKEN2(pipe)); 6452 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6453 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6454 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6455 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6456 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6457 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6458 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6459 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6460 } 6461 /* WADP0ClockGatingDisable */ 6462 for_each_pipe(dev_priv, pipe) { 6463 I915_WRITE(TRANS_CHICKEN1(pipe), 6464 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6465 } 6466 } 6467 6468 static void gen6_check_mch_setup(struct drm_device *dev) 6469 { 6470 struct drm_i915_private *dev_priv = dev->dev_private; 6471 uint32_t tmp; 6472 6473 tmp = I915_READ(MCH_SSKPD); 6474 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6475 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6476 tmp); 6477 } 6478 6479 static void gen6_init_clock_gating(struct drm_device *dev) 6480 { 6481 struct drm_i915_private *dev_priv = dev->dev_private; 6482 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6483 6484 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6485 6486 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6487 I915_READ(ILK_DISPLAY_CHICKEN2) | 6488 ILK_ELPIN_409_SELECT); 6489 6490 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6491 I915_WRITE(_3D_CHICKEN, 6492 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6493 6494 /* WaDisable_RenderCache_OperationalFlush:snb */ 6495 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6496 6497 /* 6498 * BSpec recoomends 8x4 when MSAA is used, 6499 * however in practice 16x4 seems fastest. 6500 * 6501 * Note that PS/WM thread counts depend on the WIZ hashing 6502 * disable bit, which we don't touch here, but it's good 6503 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6504 */ 6505 I915_WRITE(GEN6_GT_MODE, 6506 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6507 6508 ilk_init_lp_watermarks(dev); 6509 6510 I915_WRITE(CACHE_MODE_0, 6511 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6512 6513 I915_WRITE(GEN6_UCGCTL1, 6514 I915_READ(GEN6_UCGCTL1) | 6515 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6516 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6517 6518 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6519 * gating disable must be set. Failure to set it results in 6520 * flickering pixels due to Z write ordering failures after 6521 * some amount of runtime in the Mesa "fire" demo, and Unigine 6522 * Sanctuary and Tropics, and apparently anything else with 6523 * alpha test or pixel discard. 6524 * 6525 * According to the spec, bit 11 (RCCUNIT) must also be set, 6526 * but we didn't debug actual testcases to find it out. 6527 * 6528 * WaDisableRCCUnitClockGating:snb 6529 * WaDisableRCPBUnitClockGating:snb 6530 */ 6531 I915_WRITE(GEN6_UCGCTL2, 6532 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6533 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6534 6535 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6536 I915_WRITE(_3D_CHICKEN3, 6537 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6538 6539 /* 6540 * Bspec says: 6541 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6542 * 3DSTATE_SF number of SF output attributes is more than 16." 6543 */ 6544 I915_WRITE(_3D_CHICKEN3, 6545 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6546 6547 /* 6548 * According to the spec the following bits should be 6549 * set in order to enable memory self-refresh and fbc: 6550 * The bit21 and bit22 of 0x42000 6551 * The bit21 and bit22 of 0x42004 6552 * The bit5 and bit7 of 0x42020 6553 * The bit14 of 0x70180 6554 * The bit14 of 0x71180 6555 * 6556 * WaFbcAsynchFlipDisableFbcQueue:snb 6557 */ 6558 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6559 I915_READ(ILK_DISPLAY_CHICKEN1) | 6560 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6561 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6562 I915_READ(ILK_DISPLAY_CHICKEN2) | 6563 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6564 I915_WRITE(ILK_DSPCLK_GATE_D, 6565 I915_READ(ILK_DSPCLK_GATE_D) | 6566 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6567 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6568 6569 g4x_disable_trickle_feed(dev); 6570 6571 cpt_init_clock_gating(dev); 6572 6573 gen6_check_mch_setup(dev); 6574 } 6575 6576 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6577 { 6578 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6579 6580 /* 6581 * WaVSThreadDispatchOverride:ivb,vlv 6582 * 6583 * This actually overrides the dispatch 6584 * mode for all thread types. 6585 */ 6586 reg &= ~GEN7_FF_SCHED_MASK; 6587 reg |= GEN7_FF_TS_SCHED_HW; 6588 reg |= GEN7_FF_VS_SCHED_HW; 6589 reg |= GEN7_FF_DS_SCHED_HW; 6590 6591 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6592 } 6593 6594 static void lpt_init_clock_gating(struct drm_device *dev) 6595 { 6596 struct drm_i915_private *dev_priv = dev->dev_private; 6597 6598 /* 6599 * TODO: this bit should only be enabled when really needed, then 6600 * disabled when not needed anymore in order to save power. 6601 */ 6602 if (HAS_PCH_LPT_LP(dev)) 6603 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6604 I915_READ(SOUTH_DSPCLK_GATE_D) | 6605 PCH_LP_PARTITION_LEVEL_DISABLE); 6606 6607 /* WADPOClockGatingDisable:hsw */ 6608 I915_WRITE(TRANS_CHICKEN1(PIPE_A), 6609 I915_READ(TRANS_CHICKEN1(PIPE_A)) | 6610 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6611 } 6612 6613 static void lpt_suspend_hw(struct drm_device *dev) 6614 { 6615 struct drm_i915_private *dev_priv = dev->dev_private; 6616 6617 if (HAS_PCH_LPT_LP(dev)) { 6618 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6619 6620 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6621 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6622 } 6623 } 6624 6625 static void broadwell_init_clock_gating(struct drm_device *dev) 6626 { 6627 struct drm_i915_private *dev_priv = dev->dev_private; 6628 enum i915_pipe pipe; 6629 uint32_t misccpctl; 6630 6631 ilk_init_lp_watermarks(dev); 6632 6633 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6634 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6635 6636 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6637 I915_WRITE(CHICKEN_PAR1_1, 6638 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6639 6640 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6641 for_each_pipe(dev_priv, pipe) { 6642 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6643 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6644 BDW_DPRS_MASK_VBLANK_SRD); 6645 } 6646 6647 /* WaVSRefCountFullforceMissDisable:bdw */ 6648 /* WaDSRefCountFullforceMissDisable:bdw */ 6649 I915_WRITE(GEN7_FF_THREAD_MODE, 6650 I915_READ(GEN7_FF_THREAD_MODE) & 6651 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6652 6653 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6654 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6655 6656 /* WaDisableSDEUnitClockGating:bdw */ 6657 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6658 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6659 6660 /* 6661 * WaProgramL3SqcReg1Default:bdw 6662 * WaTempDisableDOPClkGating:bdw 6663 */ 6664 misccpctl = I915_READ(GEN7_MISCCPCTL); 6665 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6666 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6667 /* 6668 * Wait at least 100 clocks before re-enabling clock gating. See 6669 * the definition of L3SQCREG1 in BSpec. 6670 */ 6671 POSTING_READ(GEN8_L3SQCREG1); 6672 udelay(1); 6673 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6674 6675 /* 6676 * WaGttCachingOffByDefault:bdw 6677 * GTT cache may not work with big pages, so if those 6678 * are ever enabled GTT cache may need to be disabled. 6679 */ 6680 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6681 6682 lpt_init_clock_gating(dev); 6683 } 6684 6685 static void haswell_init_clock_gating(struct drm_device *dev) 6686 { 6687 struct drm_i915_private *dev_priv = dev->dev_private; 6688 6689 ilk_init_lp_watermarks(dev); 6690 6691 /* L3 caching of data atomics doesn't work -- disable it. */ 6692 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6693 I915_WRITE(HSW_ROW_CHICKEN3, 6694 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6695 6696 /* This is required by WaCatErrorRejectionIssue:hsw */ 6697 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6698 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6699 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6700 6701 /* WaVSRefCountFullforceMissDisable:hsw */ 6702 I915_WRITE(GEN7_FF_THREAD_MODE, 6703 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6704 6705 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6706 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6707 6708 /* enable HiZ Raw Stall Optimization */ 6709 I915_WRITE(CACHE_MODE_0_GEN7, 6710 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6711 6712 /* WaDisable4x2SubspanOptimization:hsw */ 6713 I915_WRITE(CACHE_MODE_1, 6714 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6715 6716 /* 6717 * BSpec recommends 8x4 when MSAA is used, 6718 * however in practice 16x4 seems fastest. 6719 * 6720 * Note that PS/WM thread counts depend on the WIZ hashing 6721 * disable bit, which we don't touch here, but it's good 6722 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6723 */ 6724 I915_WRITE(GEN7_GT_MODE, 6725 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6726 6727 /* WaSampleCChickenBitEnable:hsw */ 6728 I915_WRITE(HALF_SLICE_CHICKEN3, 6729 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6730 6731 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6732 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6733 6734 /* WaRsPkgCStateDisplayPMReq:hsw */ 6735 I915_WRITE(CHICKEN_PAR1_1, 6736 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6737 6738 lpt_init_clock_gating(dev); 6739 } 6740 6741 static void ivybridge_init_clock_gating(struct drm_device *dev) 6742 { 6743 struct drm_i915_private *dev_priv = dev->dev_private; 6744 uint32_t snpcr; 6745 6746 ilk_init_lp_watermarks(dev); 6747 6748 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6749 6750 /* WaDisableEarlyCull:ivb */ 6751 I915_WRITE(_3D_CHICKEN3, 6752 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6753 6754 /* WaDisableBackToBackFlipFix:ivb */ 6755 I915_WRITE(IVB_CHICKEN3, 6756 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6757 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6758 6759 /* WaDisablePSDDualDispatchEnable:ivb */ 6760 if (IS_IVB_GT1(dev)) 6761 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6762 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6763 6764 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6765 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6766 6767 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6768 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6769 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6770 6771 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6772 I915_WRITE(GEN7_L3CNTLREG1, 6773 GEN7_WA_FOR_GEN7_L3_CONTROL); 6774 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6775 GEN7_WA_L3_CHICKEN_MODE); 6776 if (IS_IVB_GT1(dev)) 6777 I915_WRITE(GEN7_ROW_CHICKEN2, 6778 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6779 else { 6780 /* must write both registers */ 6781 I915_WRITE(GEN7_ROW_CHICKEN2, 6782 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6783 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6784 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6785 } 6786 6787 /* WaForceL3Serialization:ivb */ 6788 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6789 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6790 6791 /* 6792 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6793 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6794 */ 6795 I915_WRITE(GEN6_UCGCTL2, 6796 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6797 6798 /* This is required by WaCatErrorRejectionIssue:ivb */ 6799 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6800 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6801 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6802 6803 g4x_disable_trickle_feed(dev); 6804 6805 gen7_setup_fixed_func_scheduler(dev_priv); 6806 6807 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6808 /* enable HiZ Raw Stall Optimization */ 6809 I915_WRITE(CACHE_MODE_0_GEN7, 6810 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6811 } 6812 6813 /* WaDisable4x2SubspanOptimization:ivb */ 6814 I915_WRITE(CACHE_MODE_1, 6815 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6816 6817 /* 6818 * BSpec recommends 8x4 when MSAA is used, 6819 * however in practice 16x4 seems fastest. 6820 * 6821 * Note that PS/WM thread counts depend on the WIZ hashing 6822 * disable bit, which we don't touch here, but it's good 6823 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6824 */ 6825 I915_WRITE(GEN7_GT_MODE, 6826 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6827 6828 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6829 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6830 snpcr |= GEN6_MBC_SNPCR_MED; 6831 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6832 6833 if (!HAS_PCH_NOP(dev)) 6834 cpt_init_clock_gating(dev); 6835 6836 gen6_check_mch_setup(dev); 6837 } 6838 6839 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6840 { 6841 u32 val; 6842 6843 /* 6844 * On driver load, a pipe may be active and driving a DSI display. 6845 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 6846 * (and never recovering) in this case. intel_dsi_post_disable() will 6847 * clear it when we turn off the display. 6848 */ 6849 val = I915_READ(DSPCLK_GATE_D); 6850 val &= DPOUNIT_CLOCK_GATE_DISABLE; 6851 val |= VRHUNIT_CLOCK_GATE_DISABLE; 6852 I915_WRITE(DSPCLK_GATE_D, val); 6853 6854 /* 6855 * Disable trickle feed and enable pnd deadline calculation 6856 */ 6857 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 6858 I915_WRITE(CBR1_VLV, 0); 6859 } 6860 6861 static void valleyview_init_clock_gating(struct drm_device *dev) 6862 { 6863 struct drm_i915_private *dev_priv = dev->dev_private; 6864 6865 vlv_init_display_clock_gating(dev_priv); 6866 6867 /* WaDisableEarlyCull:vlv */ 6868 I915_WRITE(_3D_CHICKEN3, 6869 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6870 6871 /* WaDisableBackToBackFlipFix:vlv */ 6872 I915_WRITE(IVB_CHICKEN3, 6873 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6874 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6875 6876 /* WaPsdDispatchEnable:vlv */ 6877 /* WaDisablePSDDualDispatchEnable:vlv */ 6878 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6879 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 6880 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6881 6882 /* WaDisable_RenderCache_OperationalFlush:vlv */ 6883 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6884 6885 /* WaForceL3Serialization:vlv */ 6886 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6887 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6888 6889 /* WaDisableDopClockGating:vlv */ 6890 I915_WRITE(GEN7_ROW_CHICKEN2, 6891 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6892 6893 /* This is required by WaCatErrorRejectionIssue:vlv */ 6894 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6895 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6896 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6897 6898 gen7_setup_fixed_func_scheduler(dev_priv); 6899 6900 /* 6901 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6902 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 6903 */ 6904 I915_WRITE(GEN6_UCGCTL2, 6905 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6906 6907 /* WaDisableL3Bank2xClockGate:vlv 6908 * Disabling L3 clock gating- MMIO 940c[25] = 1 6909 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 6910 I915_WRITE(GEN7_UCGCTL4, 6911 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 6912 6913 /* 6914 * BSpec says this must be set, even though 6915 * WaDisable4x2SubspanOptimization isn't listed for VLV. 6916 */ 6917 I915_WRITE(CACHE_MODE_1, 6918 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6919 6920 /* 6921 * BSpec recommends 8x4 when MSAA is used, 6922 * however in practice 16x4 seems fastest. 6923 * 6924 * Note that PS/WM thread counts depend on the WIZ hashing 6925 * disable bit, which we don't touch here, but it's good 6926 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6927 */ 6928 I915_WRITE(GEN7_GT_MODE, 6929 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6930 6931 /* 6932 * WaIncreaseL3CreditsForVLVB0:vlv 6933 * This is the hardware default actually. 6934 */ 6935 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 6936 6937 /* 6938 * WaDisableVLVClockGating_VBIIssue:vlv 6939 * Disable clock gating on th GCFG unit to prevent a delay 6940 * in the reporting of vblank events. 6941 */ 6942 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 6943 } 6944 6945 static void cherryview_init_clock_gating(struct drm_device *dev) 6946 { 6947 struct drm_i915_private *dev_priv = dev->dev_private; 6948 6949 vlv_init_display_clock_gating(dev_priv); 6950 6951 /* WaVSRefCountFullforceMissDisable:chv */ 6952 /* WaDSRefCountFullforceMissDisable:chv */ 6953 I915_WRITE(GEN7_FF_THREAD_MODE, 6954 I915_READ(GEN7_FF_THREAD_MODE) & 6955 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6956 6957 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 6958 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6959 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6960 6961 /* WaDisableCSUnitClockGating:chv */ 6962 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 6963 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6964 6965 /* WaDisableSDEUnitClockGating:chv */ 6966 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6967 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6968 6969 /* 6970 * GTT cache may not work with big pages, so if those 6971 * are ever enabled GTT cache may need to be disabled. 6972 */ 6973 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6974 } 6975 6976 static void g4x_init_clock_gating(struct drm_device *dev) 6977 { 6978 struct drm_i915_private *dev_priv = dev->dev_private; 6979 uint32_t dspclk_gate; 6980 6981 I915_WRITE(RENCLK_GATE_D1, 0); 6982 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 6983 GS_UNIT_CLOCK_GATE_DISABLE | 6984 CL_UNIT_CLOCK_GATE_DISABLE); 6985 I915_WRITE(RAMCLK_GATE_D, 0); 6986 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 6987 OVRUNIT_CLOCK_GATE_DISABLE | 6988 OVCUNIT_CLOCK_GATE_DISABLE; 6989 if (IS_GM45(dev)) 6990 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 6991 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 6992 6993 /* WaDisableRenderCachePipelinedFlush */ 6994 I915_WRITE(CACHE_MODE_0, 6995 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6996 6997 /* WaDisable_RenderCache_OperationalFlush:g4x */ 6998 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6999 7000 g4x_disable_trickle_feed(dev); 7001 } 7002 7003 static void crestline_init_clock_gating(struct drm_device *dev) 7004 { 7005 struct drm_i915_private *dev_priv = dev->dev_private; 7006 7007 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 7008 I915_WRITE(RENCLK_GATE_D2, 0); 7009 I915_WRITE(DSPCLK_GATE_D, 0); 7010 I915_WRITE(RAMCLK_GATE_D, 0); 7011 I915_WRITE16(DEUC, 0); 7012 I915_WRITE(MI_ARB_STATE, 7013 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7014 7015 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7016 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7017 } 7018 7019 static void broadwater_init_clock_gating(struct drm_device *dev) 7020 { 7021 struct drm_i915_private *dev_priv = dev->dev_private; 7022 7023 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 7024 I965_RCC_CLOCK_GATE_DISABLE | 7025 I965_RCPB_CLOCK_GATE_DISABLE | 7026 I965_ISC_CLOCK_GATE_DISABLE | 7027 I965_FBC_CLOCK_GATE_DISABLE); 7028 I915_WRITE(RENCLK_GATE_D2, 0); 7029 I915_WRITE(MI_ARB_STATE, 7030 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7031 7032 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7033 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7034 } 7035 7036 static void gen3_init_clock_gating(struct drm_device *dev) 7037 { 7038 struct drm_i915_private *dev_priv = dev->dev_private; 7039 u32 dstate = I915_READ(D_STATE); 7040 7041 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7042 DSTATE_DOT_CLOCK_GATING; 7043 I915_WRITE(D_STATE, dstate); 7044 7045 if (IS_PINEVIEW(dev)) 7046 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 7047 7048 /* IIR "flip pending" means done if this bit is set */ 7049 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 7050 7051 /* interrupts should cause a wake up from C3 */ 7052 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7053 7054 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7055 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7056 7057 I915_WRITE(MI_ARB_STATE, 7058 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7059 } 7060 7061 static void i85x_init_clock_gating(struct drm_device *dev) 7062 { 7063 struct drm_i915_private *dev_priv = dev->dev_private; 7064 7065 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7066 7067 /* interrupts should cause a wake up from C3 */ 7068 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7069 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7070 7071 I915_WRITE(MEM_MODE, 7072 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7073 } 7074 7075 static void i830_init_clock_gating(struct drm_device *dev) 7076 { 7077 struct drm_i915_private *dev_priv = dev->dev_private; 7078 7079 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7080 7081 I915_WRITE(MEM_MODE, 7082 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7083 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7084 } 7085 7086 void intel_init_clock_gating(struct drm_device *dev) 7087 { 7088 struct drm_i915_private *dev_priv = dev->dev_private; 7089 7090 if (dev_priv->display.init_clock_gating) 7091 dev_priv->display.init_clock_gating(dev); 7092 } 7093 7094 void intel_suspend_hw(struct drm_device *dev) 7095 { 7096 if (HAS_PCH_LPT(dev)) 7097 lpt_suspend_hw(dev); 7098 } 7099 7100 /* Set up chip specific power management-related functions */ 7101 void intel_init_pm(struct drm_device *dev) 7102 { 7103 struct drm_i915_private *dev_priv = dev->dev_private; 7104 7105 intel_fbc_init(dev_priv); 7106 7107 /* For cxsr */ 7108 if (IS_PINEVIEW(dev)) 7109 i915_pineview_get_mem_freq(dev); 7110 else if (IS_GEN5(dev)) 7111 i915_ironlake_get_mem_freq(dev); 7112 7113 /* For FIFO watermark updates */ 7114 if (INTEL_INFO(dev)->gen >= 9) { 7115 skl_setup_wm_latency(dev); 7116 7117 if (IS_BROXTON(dev)) 7118 dev_priv->display.init_clock_gating = 7119 bxt_init_clock_gating; 7120 dev_priv->display.update_wm = skl_update_wm; 7121 dev_priv->display.update_sprite_wm = skl_update_sprite_wm; 7122 } else if (HAS_PCH_SPLIT(dev)) { 7123 ilk_setup_wm_latency(dev); 7124 7125 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7126 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7127 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7128 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7129 dev_priv->display.update_wm = ilk_update_wm; 7130 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 7131 } else { 7132 DRM_DEBUG_KMS("Failed to read display plane latency. " 7133 "Disable CxSR\n"); 7134 } 7135 7136 if (IS_GEN5(dev)) 7137 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7138 else if (IS_GEN6(dev)) 7139 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7140 else if (IS_IVYBRIDGE(dev)) 7141 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7142 else if (IS_HASWELL(dev)) 7143 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7144 else if (INTEL_INFO(dev)->gen == 8) 7145 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7146 } else if (IS_CHERRYVIEW(dev)) { 7147 vlv_setup_wm_latency(dev); 7148 7149 dev_priv->display.update_wm = vlv_update_wm; 7150 dev_priv->display.init_clock_gating = 7151 cherryview_init_clock_gating; 7152 } else if (IS_VALLEYVIEW(dev)) { 7153 vlv_setup_wm_latency(dev); 7154 7155 dev_priv->display.update_wm = vlv_update_wm; 7156 dev_priv->display.init_clock_gating = 7157 valleyview_init_clock_gating; 7158 } else if (IS_PINEVIEW(dev)) { 7159 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7160 dev_priv->is_ddr3, 7161 dev_priv->fsb_freq, 7162 dev_priv->mem_freq)) { 7163 DRM_INFO("failed to find known CxSR latency " 7164 "(found ddr%s fsb freq %d, mem freq %d), " 7165 "disabling CxSR\n", 7166 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7167 dev_priv->fsb_freq, dev_priv->mem_freq); 7168 /* Disable CxSR and never update its watermark again */ 7169 intel_set_memory_cxsr(dev_priv, false); 7170 dev_priv->display.update_wm = NULL; 7171 } else 7172 dev_priv->display.update_wm = pineview_update_wm; 7173 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7174 } else if (IS_G4X(dev)) { 7175 dev_priv->display.update_wm = g4x_update_wm; 7176 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7177 } else if (IS_GEN4(dev)) { 7178 dev_priv->display.update_wm = i965_update_wm; 7179 if (IS_CRESTLINE(dev)) 7180 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7181 else if (IS_BROADWATER(dev)) 7182 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7183 } else if (IS_GEN3(dev)) { 7184 dev_priv->display.update_wm = i9xx_update_wm; 7185 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7186 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7187 } else if (IS_GEN2(dev)) { 7188 if (INTEL_INFO(dev)->num_pipes == 1) { 7189 dev_priv->display.update_wm = i845_update_wm; 7190 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7191 } else { 7192 dev_priv->display.update_wm = i9xx_update_wm; 7193 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7194 } 7195 7196 if (IS_I85X(dev) || IS_I865G(dev)) 7197 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7198 else 7199 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7200 } else { 7201 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7202 } 7203 } 7204 7205 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7206 { 7207 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7208 7209 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7210 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7211 return -EAGAIN; 7212 } 7213 7214 I915_WRITE(GEN6_PCODE_DATA, *val); 7215 I915_WRITE(GEN6_PCODE_DATA1, 0); 7216 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7217 7218 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7219 500)) { 7220 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7221 return -ETIMEDOUT; 7222 } 7223 7224 *val = I915_READ(GEN6_PCODE_DATA); 7225 I915_WRITE(GEN6_PCODE_DATA, 0); 7226 7227 return 0; 7228 } 7229 7230 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7231 { 7232 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7233 7234 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7235 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7236 return -EAGAIN; 7237 } 7238 7239 I915_WRITE(GEN6_PCODE_DATA, val); 7240 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7241 7242 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7243 500)) { 7244 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7245 return -ETIMEDOUT; 7246 } 7247 7248 I915_WRITE(GEN6_PCODE_DATA, 0); 7249 7250 return 0; 7251 } 7252 7253 static int vlv_gpu_freq_div(unsigned int czclk_freq) 7254 { 7255 switch (czclk_freq) { 7256 case 200: 7257 return 10; 7258 case 267: 7259 return 12; 7260 case 320: 7261 case 333: 7262 return 16; 7263 case 400: 7264 return 20; 7265 default: 7266 return -1; 7267 } 7268 } 7269 7270 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7271 { 7272 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7273 7274 div = vlv_gpu_freq_div(czclk_freq); 7275 if (div < 0) 7276 return div; 7277 7278 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7279 } 7280 7281 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7282 { 7283 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7284 7285 mul = vlv_gpu_freq_div(czclk_freq); 7286 if (mul < 0) 7287 return mul; 7288 7289 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7290 } 7291 7292 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7293 { 7294 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7295 7296 div = vlv_gpu_freq_div(czclk_freq) / 2; 7297 if (div < 0) 7298 return div; 7299 7300 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7301 } 7302 7303 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7304 { 7305 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7306 7307 mul = vlv_gpu_freq_div(czclk_freq) / 2; 7308 if (mul < 0) 7309 return mul; 7310 7311 /* CHV needs even values */ 7312 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7313 } 7314 7315 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7316 { 7317 if (IS_GEN9(dev_priv->dev)) 7318 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7319 GEN9_FREQ_SCALER); 7320 else if (IS_CHERRYVIEW(dev_priv->dev)) 7321 return chv_gpu_freq(dev_priv, val); 7322 else if (IS_VALLEYVIEW(dev_priv->dev)) 7323 return byt_gpu_freq(dev_priv, val); 7324 else 7325 return val * GT_FREQUENCY_MULTIPLIER; 7326 } 7327 7328 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7329 { 7330 if (IS_GEN9(dev_priv->dev)) 7331 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7332 GT_FREQUENCY_MULTIPLIER); 7333 else if (IS_CHERRYVIEW(dev_priv->dev)) 7334 return chv_freq_opcode(dev_priv, val); 7335 else if (IS_VALLEYVIEW(dev_priv->dev)) 7336 return byt_freq_opcode(dev_priv, val); 7337 else 7338 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7339 } 7340 7341 struct request_boost { 7342 struct work_struct work; 7343 struct drm_i915_gem_request *req; 7344 }; 7345 7346 static void __intel_rps_boost_work(struct work_struct *work) 7347 { 7348 struct request_boost *boost = container_of(work, struct request_boost, work); 7349 struct drm_i915_gem_request *req = boost->req; 7350 7351 if (!i915_gem_request_completed(req, true)) 7352 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7353 req->emitted_jiffies); 7354 7355 i915_gem_request_unreference__unlocked(req); 7356 kfree(boost); 7357 } 7358 7359 void intel_queue_rps_boost_for_request(struct drm_device *dev, 7360 struct drm_i915_gem_request *req) 7361 { 7362 struct request_boost *boost; 7363 7364 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7365 return; 7366 7367 if (i915_gem_request_completed(req, true)) 7368 return; 7369 7370 boost = kmalloc(sizeof(*boost), GFP_ATOMIC); 7371 if (boost == NULL) 7372 return; 7373 7374 i915_gem_request_reference(req); 7375 boost->req = req; 7376 7377 INIT_WORK(&boost->work, __intel_rps_boost_work); 7378 queue_work(to_i915(dev)->wq, &boost->work); 7379 } 7380 7381 void intel_pm_setup(struct drm_device *dev) 7382 { 7383 struct drm_i915_private *dev_priv = dev->dev_private; 7384 7385 #ifdef __NetBSD__ 7386 linux_mutex_init(&dev_priv->rps.hw_lock); 7387 #else 7388 mutex_init(&dev_priv->rps.hw_lock); 7389 #endif 7390 spin_lock_init(&dev_priv->rps.client_lock); 7391 7392 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7393 intel_gen6_powersave_work); 7394 INIT_LIST_HEAD(&dev_priv->rps.clients); 7395 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7396 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7397 7398 dev_priv->pm.suspended = false; 7399 } 7400
Indexes created Sat Oct 11 19:10:01 GMT 2025