intel_pm.c revision 1.17.2.2
1 /* $NetBSD: intel_pm.c,v 1.17.2.2 2020/01/31 11:25:09 martin Exp $ */ 2 3 /* 4 * Copyright 2012 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.17.2.2 2020/01/31 11:25:09 martin Exp $"); 32 33 #include <linux/bitops.h> 34 #include <linux/cpufreq.h> 35 #include <linux/export.h> 36 #include "i915_drv.h" 37 #include "i915_trace.h" 38 #include "intel_drv.h" 39 #ifndef __NetBSD__ 40 #include "../../../platform/x86/intel_ips.h" 41 #endif 42 #include <linux/module.h> 43 #include <linux/log2.h> 44 #include <linux/math64.h> 45 #include <linux/time.h> 46 47 /** 48 * RC6 is a special power stage which allows the GPU to enter an very 49 * low-voltage mode when idle, using down to 0V while at this stage. This 50 * stage is entered automatically when the GPU is idle when RC6 support is 51 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 52 * 53 * There are different RC6 modes available in Intel GPU, which differentiate 54 * among each other with the latency required to enter and leave RC6 and 55 * voltage consumed by the GPU in different states. 56 * 57 * The combination of the following flags define which states GPU is allowed 58 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 59 * RC6pp is deepest RC6. Their support by hardware varies according to the 60 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 61 * which brings the most power savings; deeper states save more power, but 62 * require higher latency to switch to and wake up. 63 */ 64 #define INTEL_RC6_ENABLE (1<<0) 65 #define INTEL_RC6p_ENABLE (1<<1) 66 #define INTEL_RC6pp_ENABLE (1<<2) 67 68 static void bxt_init_clock_gating(struct drm_device *dev) 69 { 70 struct drm_i915_private *dev_priv = dev->dev_private; 71 72 /* WaDisableSDEUnitClockGating:bxt */ 73 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 74 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 75 76 /* 77 * FIXME: 78 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 79 */ 80 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 81 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 82 83 /* 84 * Lower the display internal timeout. 85 * This is needed to avoid any hard hangs when DSI port PLL 86 * is off and a MMIO access is attempted by any privilege 87 * application, using batch buffers or any other means. 88 */ 89 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 90 } 91 92 static void i915_pineview_get_mem_freq(struct drm_device *dev) 93 { 94 struct drm_i915_private *dev_priv = dev->dev_private; 95 u32 tmp; 96 97 tmp = I915_READ(CLKCFG); 98 99 switch (tmp & CLKCFG_FSB_MASK) { 100 case CLKCFG_FSB_533: 101 dev_priv->fsb_freq = 533; /* 133*4 */ 102 break; 103 case CLKCFG_FSB_800: 104 dev_priv->fsb_freq = 800; /* 200*4 */ 105 break; 106 case CLKCFG_FSB_667: 107 dev_priv->fsb_freq = 667; /* 167*4 */ 108 break; 109 case CLKCFG_FSB_400: 110 dev_priv->fsb_freq = 400; /* 100*4 */ 111 break; 112 } 113 114 switch (tmp & CLKCFG_MEM_MASK) { 115 case CLKCFG_MEM_533: 116 dev_priv->mem_freq = 533; 117 break; 118 case CLKCFG_MEM_667: 119 dev_priv->mem_freq = 667; 120 break; 121 case CLKCFG_MEM_800: 122 dev_priv->mem_freq = 800; 123 break; 124 } 125 126 /* detect pineview DDR3 setting */ 127 tmp = I915_READ(CSHRDDR3CTL); 128 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 129 } 130 131 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 132 { 133 struct drm_i915_private *dev_priv = dev->dev_private; 134 u16 ddrpll, csipll; 135 136 ddrpll = I915_READ16(DDRMPLL1); 137 csipll = I915_READ16(CSIPLL0); 138 139 switch (ddrpll & 0xff) { 140 case 0xc: 141 dev_priv->mem_freq = 800; 142 break; 143 case 0x10: 144 dev_priv->mem_freq = 1066; 145 break; 146 case 0x14: 147 dev_priv->mem_freq = 1333; 148 break; 149 case 0x18: 150 dev_priv->mem_freq = 1600; 151 break; 152 default: 153 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 154 ddrpll & 0xff); 155 dev_priv->mem_freq = 0; 156 break; 157 } 158 159 dev_priv->ips.r_t = dev_priv->mem_freq; 160 161 switch (csipll & 0x3ff) { 162 case 0x00c: 163 dev_priv->fsb_freq = 3200; 164 break; 165 case 0x00e: 166 dev_priv->fsb_freq = 3733; 167 break; 168 case 0x010: 169 dev_priv->fsb_freq = 4266; 170 break; 171 case 0x012: 172 dev_priv->fsb_freq = 4800; 173 break; 174 case 0x014: 175 dev_priv->fsb_freq = 5333; 176 break; 177 case 0x016: 178 dev_priv->fsb_freq = 5866; 179 break; 180 case 0x018: 181 dev_priv->fsb_freq = 6400; 182 break; 183 default: 184 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 185 csipll & 0x3ff); 186 dev_priv->fsb_freq = 0; 187 break; 188 } 189 190 if (dev_priv->fsb_freq == 3200) { 191 dev_priv->ips.c_m = 0; 192 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 193 dev_priv->ips.c_m = 1; 194 } else { 195 dev_priv->ips.c_m = 2; 196 } 197 } 198 199 static const struct cxsr_latency cxsr_latency_table[] = { 200 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 201 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 202 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 203 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 204 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 205 206 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 207 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 208 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 209 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 210 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 211 212 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 213 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 214 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 215 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 216 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 217 218 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 219 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 220 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 221 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 222 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 223 224 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 225 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 226 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 227 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 228 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 229 230 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 231 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 232 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 233 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 234 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 235 }; 236 237 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 238 int is_ddr3, 239 int fsb, 240 int mem) 241 { 242 const struct cxsr_latency *latency; 243 int i; 244 245 if (fsb == 0 || mem == 0) 246 return NULL; 247 248 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 249 latency = &cxsr_latency_table[i]; 250 if (is_desktop == latency->is_desktop && 251 is_ddr3 == latency->is_ddr3 && 252 fsb == latency->fsb_freq && mem == latency->mem_freq) 253 return latency; 254 } 255 256 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 257 258 return NULL; 259 } 260 261 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 262 { 263 u32 val; 264 265 mutex_lock(&dev_priv->rps.hw_lock); 266 267 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 268 if (enable) 269 val &= ~FORCE_DDR_HIGH_FREQ; 270 else 271 val |= FORCE_DDR_HIGH_FREQ; 272 val &= ~FORCE_DDR_LOW_FREQ; 273 val |= FORCE_DDR_FREQ_REQ_ACK; 274 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 275 276 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 277 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 278 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 279 280 mutex_unlock(&dev_priv->rps.hw_lock); 281 } 282 283 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 284 { 285 u32 val; 286 287 mutex_lock(&dev_priv->rps.hw_lock); 288 289 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 290 if (enable) 291 val |= DSP_MAXFIFO_PM5_ENABLE; 292 else 293 val &= ~DSP_MAXFIFO_PM5_ENABLE; 294 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 295 296 mutex_unlock(&dev_priv->rps.hw_lock); 297 } 298 299 #define FW_WM(value, plane) \ 300 (((u32)(value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 301 302 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 303 { 304 struct drm_device *dev = dev_priv->dev; 305 u32 val; 306 307 if (IS_VALLEYVIEW(dev)) { 308 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 309 POSTING_READ(FW_BLC_SELF_VLV); 310 dev_priv->wm.vlv.cxsr = enable; 311 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 312 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 313 POSTING_READ(FW_BLC_SELF); 314 } else if (IS_PINEVIEW(dev)) { 315 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 316 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 317 I915_WRITE(DSPFW3, val); 318 POSTING_READ(DSPFW3); 319 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 320 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 321 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 322 I915_WRITE(FW_BLC_SELF, val); 323 POSTING_READ(FW_BLC_SELF); 324 } else if (IS_I915GM(dev)) { 325 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 326 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 327 I915_WRITE(INSTPM, val); 328 POSTING_READ(INSTPM); 329 } else { 330 return; 331 } 332 333 DRM_DEBUG_KMS("memory self-refresh is %s\n", 334 enable ? "enabled" : "disabled"); 335 } 336 337 338 /* 339 * Latency for FIFO fetches is dependent on several factors: 340 * - memory configuration (speed, channels) 341 * - chipset 342 * - current MCH state 343 * It can be fairly high in some situations, so here we assume a fairly 344 * pessimal value. It's a tradeoff between extra memory fetches (if we 345 * set this value too high, the FIFO will fetch frequently to stay full) 346 * and power consumption (set it too low to save power and we might see 347 * FIFO underruns and display "flicker"). 348 * 349 * A value of 5us seems to be a good balance; safe for very low end 350 * platforms but not overly aggressive on lower latency configs. 351 */ 352 static const int pessimal_latency_ns = 5000; 353 354 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 355 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 356 357 static int vlv_get_fifo_size(struct drm_device *dev, 358 enum i915_pipe pipe, int plane) 359 { 360 struct drm_i915_private *dev_priv = dev->dev_private; 361 int sprite0_start, sprite1_start, size; 362 363 switch (pipe) { 364 uint32_t dsparb, dsparb2, dsparb3; 365 case PIPE_A: 366 dsparb = I915_READ(DSPARB); 367 dsparb2 = I915_READ(DSPARB2); 368 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 369 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 370 break; 371 case PIPE_B: 372 dsparb = I915_READ(DSPARB); 373 dsparb2 = I915_READ(DSPARB2); 374 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 375 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 376 break; 377 case PIPE_C: 378 dsparb2 = I915_READ(DSPARB2); 379 dsparb3 = I915_READ(DSPARB3); 380 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 381 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 382 break; 383 default: 384 return 0; 385 } 386 387 switch (plane) { 388 case 0: 389 size = sprite0_start; 390 break; 391 case 1: 392 size = sprite1_start - sprite0_start; 393 break; 394 case 2: 395 size = 512 - 1 - sprite1_start; 396 break; 397 default: 398 return 0; 399 } 400 401 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 402 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 403 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 404 size); 405 406 return size; 407 } 408 409 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 410 { 411 struct drm_i915_private *dev_priv = dev->dev_private; 412 uint32_t dsparb = I915_READ(DSPARB); 413 int size; 414 415 size = dsparb & 0x7f; 416 if (plane) 417 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 418 419 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 420 plane ? "B" : "A", size); 421 422 return size; 423 } 424 425 static int i830_get_fifo_size(struct drm_device *dev, int plane) 426 { 427 struct drm_i915_private *dev_priv = dev->dev_private; 428 uint32_t dsparb = I915_READ(DSPARB); 429 int size; 430 431 size = dsparb & 0x1ff; 432 if (plane) 433 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 434 size >>= 1; /* Convert to cachelines */ 435 436 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 437 plane ? "B" : "A", size); 438 439 return size; 440 } 441 442 static int i845_get_fifo_size(struct drm_device *dev, int plane) 443 { 444 struct drm_i915_private *dev_priv = dev->dev_private; 445 uint32_t dsparb = I915_READ(DSPARB); 446 int size; 447 448 size = dsparb & 0x7f; 449 size >>= 2; /* Convert to cachelines */ 450 451 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 452 plane ? "B" : "A", 453 size); 454 455 return size; 456 } 457 458 /* Pineview has different values for various configs */ 459 static const struct intel_watermark_params pineview_display_wm = { 460 .fifo_size = PINEVIEW_DISPLAY_FIFO, 461 .max_wm = PINEVIEW_MAX_WM, 462 .default_wm = PINEVIEW_DFT_WM, 463 .guard_size = PINEVIEW_GUARD_WM, 464 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 465 }; 466 static const struct intel_watermark_params pineview_display_hplloff_wm = { 467 .fifo_size = PINEVIEW_DISPLAY_FIFO, 468 .max_wm = PINEVIEW_MAX_WM, 469 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 470 .guard_size = PINEVIEW_GUARD_WM, 471 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 472 }; 473 static const struct intel_watermark_params pineview_cursor_wm = { 474 .fifo_size = PINEVIEW_CURSOR_FIFO, 475 .max_wm = PINEVIEW_CURSOR_MAX_WM, 476 .default_wm = PINEVIEW_CURSOR_DFT_WM, 477 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 478 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 479 }; 480 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 481 .fifo_size = PINEVIEW_CURSOR_FIFO, 482 .max_wm = PINEVIEW_CURSOR_MAX_WM, 483 .default_wm = PINEVIEW_CURSOR_DFT_WM, 484 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 485 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 486 }; 487 static const struct intel_watermark_params g4x_wm_info = { 488 .fifo_size = G4X_FIFO_SIZE, 489 .max_wm = G4X_MAX_WM, 490 .default_wm = G4X_MAX_WM, 491 .guard_size = 2, 492 .cacheline_size = G4X_FIFO_LINE_SIZE, 493 }; 494 static const struct intel_watermark_params g4x_cursor_wm_info = { 495 .fifo_size = I965_CURSOR_FIFO, 496 .max_wm = I965_CURSOR_MAX_WM, 497 .default_wm = I965_CURSOR_DFT_WM, 498 .guard_size = 2, 499 .cacheline_size = G4X_FIFO_LINE_SIZE, 500 }; 501 static const struct intel_watermark_params valleyview_wm_info __unused = { 502 .fifo_size = VALLEYVIEW_FIFO_SIZE, 503 .max_wm = VALLEYVIEW_MAX_WM, 504 .default_wm = VALLEYVIEW_MAX_WM, 505 .guard_size = 2, 506 .cacheline_size = G4X_FIFO_LINE_SIZE, 507 }; 508 static const struct intel_watermark_params valleyview_cursor_wm_info __unused = { 509 .fifo_size = I965_CURSOR_FIFO, 510 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 511 .default_wm = I965_CURSOR_DFT_WM, 512 .guard_size = 2, 513 .cacheline_size = G4X_FIFO_LINE_SIZE, 514 }; 515 static const struct intel_watermark_params i965_cursor_wm_info = { 516 .fifo_size = I965_CURSOR_FIFO, 517 .max_wm = I965_CURSOR_MAX_WM, 518 .default_wm = I965_CURSOR_DFT_WM, 519 .guard_size = 2, 520 .cacheline_size = I915_FIFO_LINE_SIZE, 521 }; 522 static const struct intel_watermark_params i945_wm_info = { 523 .fifo_size = I945_FIFO_SIZE, 524 .max_wm = I915_MAX_WM, 525 .default_wm = 1, 526 .guard_size = 2, 527 .cacheline_size = I915_FIFO_LINE_SIZE, 528 }; 529 static const struct intel_watermark_params i915_wm_info = { 530 .fifo_size = I915_FIFO_SIZE, 531 .max_wm = I915_MAX_WM, 532 .default_wm = 1, 533 .guard_size = 2, 534 .cacheline_size = I915_FIFO_LINE_SIZE, 535 }; 536 static const struct intel_watermark_params i830_a_wm_info = { 537 .fifo_size = I855GM_FIFO_SIZE, 538 .max_wm = I915_MAX_WM, 539 .default_wm = 1, 540 .guard_size = 2, 541 .cacheline_size = I830_FIFO_LINE_SIZE, 542 }; 543 static const struct intel_watermark_params i830_bc_wm_info = { 544 .fifo_size = I855GM_FIFO_SIZE, 545 .max_wm = I915_MAX_WM/2, 546 .default_wm = 1, 547 .guard_size = 2, 548 .cacheline_size = I830_FIFO_LINE_SIZE, 549 }; 550 static const struct intel_watermark_params i845_wm_info = { 551 .fifo_size = I830_FIFO_SIZE, 552 .max_wm = I915_MAX_WM, 553 .default_wm = 1, 554 .guard_size = 2, 555 .cacheline_size = I830_FIFO_LINE_SIZE, 556 }; 557 558 /** 559 * intel_calculate_wm - calculate watermark level 560 * @clock_in_khz: pixel clock 561 * @wm: chip FIFO params 562 * @pixel_size: display pixel size 563 * @latency_ns: memory latency for the platform 564 * 565 * Calculate the watermark level (the level at which the display plane will 566 * start fetching from memory again). Each chip has a different display 567 * FIFO size and allocation, so the caller needs to figure that out and pass 568 * in the correct intel_watermark_params structure. 569 * 570 * As the pixel clock runs, the FIFO will be drained at a rate that depends 571 * on the pixel size. When it reaches the watermark level, it'll start 572 * fetching FIFO line sized based chunks from memory until the FIFO fills 573 * past the watermark point. If the FIFO drains completely, a FIFO underrun 574 * will occur, and a display engine hang could result. 575 */ 576 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 577 const struct intel_watermark_params *wm, 578 int fifo_size, 579 int pixel_size, 580 unsigned long latency_ns) 581 { 582 long entries_required, wm_size; 583 584 /* 585 * Note: we need to make sure we don't overflow for various clock & 586 * latency values. 587 * clocks go from a few thousand to several hundred thousand. 588 * latency is usually a few thousand 589 */ 590 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 591 1000; 592 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 593 594 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 595 596 wm_size = fifo_size - (entries_required + wm->guard_size); 597 598 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 599 600 /* Don't promote wm_size to unsigned... */ 601 if (wm_size > (long)wm->max_wm) 602 wm_size = wm->max_wm; 603 if (wm_size <= 0) 604 wm_size = wm->default_wm; 605 606 /* 607 * Bspec seems to indicate that the value shouldn't be lower than 608 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 609 * Lets go for 8 which is the burst size since certain platforms 610 * already use a hardcoded 8 (which is what the spec says should be 611 * done). 612 */ 613 if (wm_size <= 8) 614 wm_size = 8; 615 616 return wm_size; 617 } 618 619 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 620 { 621 struct drm_crtc *crtc, *enabled = NULL; 622 623 for_each_crtc(dev, crtc) { 624 if (intel_crtc_active(crtc)) { 625 if (enabled) 626 return NULL; 627 enabled = crtc; 628 } 629 } 630 631 return enabled; 632 } 633 634 static void pineview_update_wm(struct drm_crtc *unused_crtc) 635 { 636 struct drm_device *dev = unused_crtc->dev; 637 struct drm_i915_private *dev_priv = dev->dev_private; 638 struct drm_crtc *crtc; 639 const struct cxsr_latency *latency; 640 u32 reg; 641 unsigned long wm; 642 643 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 644 dev_priv->fsb_freq, dev_priv->mem_freq); 645 if (!latency) { 646 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 647 intel_set_memory_cxsr(dev_priv, false); 648 return; 649 } 650 651 crtc = single_enabled_crtc(dev); 652 if (crtc) { 653 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 654 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 655 int clock = adjusted_mode->crtc_clock; 656 657 /* Display SR */ 658 wm = intel_calculate_wm(clock, &pineview_display_wm, 659 pineview_display_wm.fifo_size, 660 pixel_size, latency->display_sr); 661 reg = I915_READ(DSPFW1); 662 reg &= ~DSPFW_SR_MASK; 663 reg |= FW_WM(wm, SR); 664 I915_WRITE(DSPFW1, reg); 665 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 666 667 /* cursor SR */ 668 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 669 pineview_display_wm.fifo_size, 670 pixel_size, latency->cursor_sr); 671 reg = I915_READ(DSPFW3); 672 reg &= ~DSPFW_CURSOR_SR_MASK; 673 reg |= FW_WM(wm, CURSOR_SR); 674 I915_WRITE(DSPFW3, reg); 675 676 /* Display HPLL off SR */ 677 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 678 pineview_display_hplloff_wm.fifo_size, 679 pixel_size, latency->display_hpll_disable); 680 reg = I915_READ(DSPFW3); 681 reg &= ~DSPFW_HPLL_SR_MASK; 682 reg |= FW_WM(wm, HPLL_SR); 683 I915_WRITE(DSPFW3, reg); 684 685 /* cursor HPLL off SR */ 686 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 687 pineview_display_hplloff_wm.fifo_size, 688 pixel_size, latency->cursor_hpll_disable); 689 reg = I915_READ(DSPFW3); 690 reg &= ~DSPFW_HPLL_CURSOR_MASK; 691 reg |= FW_WM(wm, HPLL_CURSOR); 692 I915_WRITE(DSPFW3, reg); 693 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 694 695 intel_set_memory_cxsr(dev_priv, true); 696 } else { 697 intel_set_memory_cxsr(dev_priv, false); 698 } 699 } 700 701 static bool g4x_compute_wm0(struct drm_device *dev, 702 int plane, 703 const struct intel_watermark_params *display, 704 int display_latency_ns, 705 const struct intel_watermark_params *cursor, 706 int cursor_latency_ns, 707 int *plane_wm, 708 int *cursor_wm) 709 { 710 struct drm_crtc *crtc; 711 const struct drm_display_mode *adjusted_mode; 712 int htotal, hdisplay, clock, pixel_size; 713 int line_time_us, line_count; 714 int entries, tlb_miss; 715 716 crtc = intel_get_crtc_for_plane(dev, plane); 717 if (!intel_crtc_active(crtc)) { 718 *cursor_wm = cursor->guard_size; 719 *plane_wm = display->guard_size; 720 return false; 721 } 722 723 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 724 clock = adjusted_mode->crtc_clock; 725 htotal = adjusted_mode->crtc_htotal; 726 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 727 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 728 729 /* Use the small buffer method to calculate plane watermark */ 730 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 731 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 732 if (tlb_miss > 0) 733 entries += tlb_miss; 734 entries = DIV_ROUND_UP(entries, display->cacheline_size); 735 *plane_wm = entries + display->guard_size; 736 if (*plane_wm > (int)display->max_wm) 737 *plane_wm = display->max_wm; 738 739 /* Use the large buffer method to calculate cursor watermark */ 740 line_time_us = max(htotal * 1000 / clock, 1); 741 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 742 entries = line_count * crtc->cursor->state->crtc_w * pixel_size; 743 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 744 if (tlb_miss > 0) 745 entries += tlb_miss; 746 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 747 *cursor_wm = entries + cursor->guard_size; 748 if (*cursor_wm > (int)cursor->max_wm) 749 *cursor_wm = (int)cursor->max_wm; 750 751 return true; 752 } 753 754 /* 755 * Check the wm result. 756 * 757 * If any calculated watermark values is larger than the maximum value that 758 * can be programmed into the associated watermark register, that watermark 759 * must be disabled. 760 */ 761 static bool g4x_check_srwm(struct drm_device *dev, 762 int display_wm, int cursor_wm, 763 const struct intel_watermark_params *display, 764 const struct intel_watermark_params *cursor) 765 { 766 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 767 display_wm, cursor_wm); 768 769 if (display_wm > display->max_wm) { 770 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 771 display_wm, display->max_wm); 772 return false; 773 } 774 775 if (cursor_wm > cursor->max_wm) { 776 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 777 cursor_wm, cursor->max_wm); 778 return false; 779 } 780 781 if (!(display_wm || cursor_wm)) { 782 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 783 return false; 784 } 785 786 return true; 787 } 788 789 static bool g4x_compute_srwm(struct drm_device *dev, 790 int plane, 791 int latency_ns, 792 const struct intel_watermark_params *display, 793 const struct intel_watermark_params *cursor, 794 int *display_wm, int *cursor_wm) 795 { 796 struct drm_crtc *crtc; 797 const struct drm_display_mode *adjusted_mode; 798 int hdisplay, htotal, pixel_size, clock; 799 unsigned long line_time_us; 800 int line_count, line_size; 801 int small, large; 802 int entries; 803 804 if (!latency_ns) { 805 *display_wm = *cursor_wm = 0; 806 return false; 807 } 808 809 crtc = intel_get_crtc_for_plane(dev, plane); 810 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 811 clock = adjusted_mode->crtc_clock; 812 htotal = adjusted_mode->crtc_htotal; 813 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 814 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 815 816 line_time_us = max(htotal * 1000 / clock, 1); 817 line_count = (latency_ns / line_time_us + 1000) / 1000; 818 line_size = hdisplay * pixel_size; 819 820 /* Use the minimum of the small and large buffer method for primary */ 821 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 822 large = line_count * line_size; 823 824 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 825 *display_wm = entries + display->guard_size; 826 827 /* calculate the self-refresh watermark for display cursor */ 828 entries = line_count * pixel_size * crtc->cursor->state->crtc_w; 829 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 830 *cursor_wm = entries + cursor->guard_size; 831 832 return g4x_check_srwm(dev, 833 *display_wm, *cursor_wm, 834 display, cursor); 835 } 836 837 #define FW_WM_VLV(value, plane) \ 838 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 839 840 static void vlv_write_wm_values(struct intel_crtc *crtc, 841 const struct vlv_wm_values *wm) 842 { 843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 844 enum i915_pipe pipe = crtc->pipe; 845 846 I915_WRITE(VLV_DDL(pipe), 847 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 848 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 849 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 850 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 851 852 I915_WRITE(DSPFW1, 853 FW_WM(wm->sr.plane, SR) | 854 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 855 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 856 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 857 I915_WRITE(DSPFW2, 858 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 859 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 860 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 861 I915_WRITE(DSPFW3, 862 FW_WM(wm->sr.cursor, CURSOR_SR)); 863 864 if (IS_CHERRYVIEW(dev_priv)) { 865 I915_WRITE(DSPFW7_CHV, 866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 868 I915_WRITE(DSPFW8_CHV, 869 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 870 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 871 I915_WRITE(DSPFW9_CHV, 872 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 873 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 874 I915_WRITE(DSPHOWM, 875 FW_WM(wm->sr.plane >> 9, SR_HI) | 876 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 877 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 878 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 885 } else { 886 I915_WRITE(DSPFW7, 887 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 888 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 889 I915_WRITE(DSPHOWM, 890 FW_WM(wm->sr.plane >> 9, SR_HI) | 891 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 892 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 893 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 894 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 895 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 896 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 897 } 898 899 /* zero (unused) WM1 watermarks */ 900 I915_WRITE(DSPFW4, 0); 901 I915_WRITE(DSPFW5, 0); 902 I915_WRITE(DSPFW6, 0); 903 I915_WRITE(DSPHOWM1, 0); 904 905 POSTING_READ(DSPFW1); 906 } 907 908 #undef FW_WM_VLV 909 910 enum vlv_wm_level { 911 VLV_WM_LEVEL_PM2, 912 VLV_WM_LEVEL_PM5, 913 VLV_WM_LEVEL_DDR_DVFS, 914 }; 915 916 /* latency must be in 0.1us units. */ 917 static unsigned int vlv_wm_method2(unsigned int pixel_rate, 918 unsigned int pipe_htotal, 919 unsigned int horiz_pixels, 920 unsigned int bytes_per_pixel, 921 unsigned int latency) 922 { 923 unsigned int ret; 924 925 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 926 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 927 ret = DIV_ROUND_UP(ret, 64); 928 929 return ret; 930 } 931 932 static void vlv_setup_wm_latency(struct drm_device *dev) 933 { 934 struct drm_i915_private *dev_priv = dev->dev_private; 935 936 /* all latencies in usec */ 937 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 938 939 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 940 941 if (IS_CHERRYVIEW(dev_priv)) { 942 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 943 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 944 945 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 946 } 947 } 948 949 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 950 struct intel_crtc *crtc, 951 const struct intel_plane_state *state, 952 int level) 953 { 954 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 955 int clock, htotal, pixel_size, width, wm; 956 957 if (dev_priv->wm.pri_latency[level] == 0) 958 return USHRT_MAX; 959 960 if (!state->visible) 961 return 0; 962 963 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 964 clock = crtc->config->base.adjusted_mode.crtc_clock; 965 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 966 width = crtc->config->pipe_src_w; 967 if (WARN_ON(htotal == 0)) 968 htotal = 1; 969 970 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 971 /* 972 * FIXME the formula gives values that are 973 * too big for the cursor FIFO, and hence we 974 * would never be able to use cursors. For 975 * now just hardcode the watermark. 976 */ 977 wm = 63; 978 } else { 979 wm = vlv_wm_method2(clock, htotal, width, pixel_size, 980 dev_priv->wm.pri_latency[level] * 10); 981 } 982 983 return min_t(int, wm, USHRT_MAX); 984 } 985 986 static void vlv_compute_fifo(struct intel_crtc *crtc) 987 { 988 struct drm_device *dev = crtc->base.dev; 989 struct vlv_wm_state *wm_state = &crtc->wm_state; 990 struct intel_plane *plane; 991 unsigned int total_rate = 0; 992 const int fifo_size = 512 - 1; 993 int fifo_extra, fifo_left = fifo_size; 994 995 for_each_intel_plane_on_crtc(dev, crtc, plane) { 996 struct intel_plane_state *state = 997 to_intel_plane_state(plane->base.state); 998 999 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1000 continue; 1001 1002 if (state->visible) { 1003 wm_state->num_active_planes++; 1004 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1005 } 1006 } 1007 1008 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1009 struct intel_plane_state *state = 1010 to_intel_plane_state(plane->base.state); 1011 unsigned int rate; 1012 1013 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1014 plane->wm.fifo_size = 63; 1015 continue; 1016 } 1017 1018 if (!state->visible) { 1019 plane->wm.fifo_size = 0; 1020 continue; 1021 } 1022 1023 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1024 plane->wm.fifo_size = fifo_size * rate / total_rate; 1025 fifo_left -= plane->wm.fifo_size; 1026 } 1027 1028 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1029 1030 /* spread the remainder evenly */ 1031 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1032 int plane_extra; 1033 1034 if (fifo_left == 0) 1035 break; 1036 1037 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1038 continue; 1039 1040 /* give it all to the first plane if none are active */ 1041 if (plane->wm.fifo_size == 0 && 1042 wm_state->num_active_planes) 1043 continue; 1044 1045 plane_extra = min(fifo_extra, fifo_left); 1046 plane->wm.fifo_size += plane_extra; 1047 fifo_left -= plane_extra; 1048 } 1049 1050 WARN_ON(fifo_left != 0); 1051 } 1052 1053 static void vlv_invert_wms(struct intel_crtc *crtc) 1054 { 1055 struct vlv_wm_state *wm_state = &crtc->wm_state; 1056 int level; 1057 1058 for (level = 0; level < wm_state->num_levels; level++) { 1059 struct drm_device *dev = crtc->base.dev; 1060 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1061 struct intel_plane *plane; 1062 1063 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1064 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1065 1066 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1067 switch (plane->base.type) { 1068 int sprite; 1069 case DRM_PLANE_TYPE_CURSOR: 1070 wm_state->wm[level].cursor = plane->wm.fifo_size - 1071 wm_state->wm[level].cursor; 1072 break; 1073 case DRM_PLANE_TYPE_PRIMARY: 1074 wm_state->wm[level].primary = plane->wm.fifo_size - 1075 wm_state->wm[level].primary; 1076 break; 1077 case DRM_PLANE_TYPE_OVERLAY: 1078 sprite = plane->plane; 1079 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1080 wm_state->wm[level].sprite[sprite]; 1081 break; 1082 } 1083 } 1084 } 1085 } 1086 1087 static void vlv_compute_wm(struct intel_crtc *crtc) 1088 { 1089 struct drm_device *dev = crtc->base.dev; 1090 struct vlv_wm_state *wm_state = &crtc->wm_state; 1091 struct intel_plane *plane; 1092 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1093 int level; 1094 1095 memset(wm_state, 0, sizeof(*wm_state)); 1096 1097 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1098 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1099 1100 wm_state->num_active_planes = 0; 1101 1102 vlv_compute_fifo(crtc); 1103 1104 if (wm_state->num_active_planes != 1) 1105 wm_state->cxsr = false; 1106 1107 if (wm_state->cxsr) { 1108 for (level = 0; level < wm_state->num_levels; level++) { 1109 wm_state->sr[level].plane = sr_fifo_size; 1110 wm_state->sr[level].cursor = 63; 1111 } 1112 } 1113 1114 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1115 struct intel_plane_state *state = 1116 to_intel_plane_state(plane->base.state); 1117 1118 if (!state->visible) 1119 continue; 1120 1121 /* normal watermarks */ 1122 for (level = 0; level < wm_state->num_levels; level++) { 1123 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1124 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1125 1126 /* hack */ 1127 if (WARN_ON(level == 0 && wm > max_wm)) 1128 wm = max_wm; 1129 1130 if (wm > plane->wm.fifo_size) 1131 break; 1132 1133 switch (plane->base.type) { 1134 int sprite; 1135 case DRM_PLANE_TYPE_CURSOR: 1136 wm_state->wm[level].cursor = wm; 1137 break; 1138 case DRM_PLANE_TYPE_PRIMARY: 1139 wm_state->wm[level].primary = wm; 1140 break; 1141 case DRM_PLANE_TYPE_OVERLAY: 1142 sprite = plane->plane; 1143 wm_state->wm[level].sprite[sprite] = wm; 1144 break; 1145 } 1146 } 1147 1148 wm_state->num_levels = level; 1149 1150 if (!wm_state->cxsr) 1151 continue; 1152 1153 /* maxfifo watermarks */ 1154 switch (plane->base.type) { 1155 int sprite, level; 1156 case DRM_PLANE_TYPE_CURSOR: 1157 for (level = 0; level < wm_state->num_levels; level++) 1158 wm_state->sr[level].cursor = 1159 wm_state->wm[level].cursor; 1160 break; 1161 case DRM_PLANE_TYPE_PRIMARY: 1162 for (level = 0; level < wm_state->num_levels; level++) 1163 wm_state->sr[level].plane = 1164 min(wm_state->sr[level].plane, 1165 wm_state->wm[level].primary); 1166 break; 1167 case DRM_PLANE_TYPE_OVERLAY: 1168 sprite = plane->plane; 1169 for (level = 0; level < wm_state->num_levels; level++) 1170 wm_state->sr[level].plane = 1171 min(wm_state->sr[level].plane, 1172 wm_state->wm[level].sprite[sprite]); 1173 break; 1174 } 1175 } 1176 1177 /* clear any (partially) filled invalid levels */ 1178 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1179 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1180 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1181 } 1182 1183 vlv_invert_wms(crtc); 1184 } 1185 1186 #define VLV_FIFO(plane, value) \ 1187 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1188 1189 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1190 { 1191 struct drm_device *dev = crtc->base.dev; 1192 struct drm_i915_private *dev_priv = to_i915(dev); 1193 struct intel_plane *plane; 1194 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1195 1196 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1197 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1198 WARN_ON(plane->wm.fifo_size != 63); 1199 continue; 1200 } 1201 1202 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1203 sprite0_start = plane->wm.fifo_size; 1204 else if (plane->plane == 0) 1205 sprite1_start = sprite0_start + plane->wm.fifo_size; 1206 else 1207 fifo_size = sprite1_start + plane->wm.fifo_size; 1208 } 1209 1210 WARN_ON(fifo_size != 512 - 1); 1211 1212 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1213 pipe_name(crtc->pipe), sprite0_start, 1214 sprite1_start, fifo_size); 1215 1216 switch (crtc->pipe) { 1217 uint32_t dsparb, dsparb2, dsparb3; 1218 case PIPE_A: 1219 dsparb = I915_READ(DSPARB); 1220 dsparb2 = I915_READ(DSPARB2); 1221 1222 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1223 VLV_FIFO(SPRITEB, 0xff)); 1224 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1225 VLV_FIFO(SPRITEB, sprite1_start)); 1226 1227 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1228 VLV_FIFO(SPRITEB_HI, 0x1)); 1229 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1230 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1231 1232 I915_WRITE(DSPARB, dsparb); 1233 I915_WRITE(DSPARB2, dsparb2); 1234 break; 1235 case PIPE_B: 1236 dsparb = I915_READ(DSPARB); 1237 dsparb2 = I915_READ(DSPARB2); 1238 1239 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1240 VLV_FIFO(SPRITED, 0xff)); 1241 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1242 VLV_FIFO(SPRITED, sprite1_start)); 1243 1244 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1245 VLV_FIFO(SPRITED_HI, 0xff)); 1246 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1247 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1248 1249 I915_WRITE(DSPARB, dsparb); 1250 I915_WRITE(DSPARB2, dsparb2); 1251 break; 1252 case PIPE_C: 1253 dsparb3 = I915_READ(DSPARB3); 1254 dsparb2 = I915_READ(DSPARB2); 1255 1256 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1257 VLV_FIFO(SPRITEF, 0xff)); 1258 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1259 VLV_FIFO(SPRITEF, sprite1_start)); 1260 1261 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1262 VLV_FIFO(SPRITEF_HI, 0xff)); 1263 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1264 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1265 1266 I915_WRITE(DSPARB3, dsparb3); 1267 I915_WRITE(DSPARB2, dsparb2); 1268 break; 1269 default: 1270 break; 1271 } 1272 } 1273 1274 #undef VLV_FIFO 1275 1276 static void vlv_merge_wm(struct drm_device *dev, 1277 struct vlv_wm_values *wm) 1278 { 1279 struct intel_crtc *crtc; 1280 int num_active_crtcs = 0; 1281 1282 wm->level = to_i915(dev)->wm.max_level; 1283 wm->cxsr = true; 1284 1285 for_each_intel_crtc(dev, crtc) { 1286 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1287 1288 if (!crtc->active) 1289 continue; 1290 1291 if (!wm_state->cxsr) 1292 wm->cxsr = false; 1293 1294 num_active_crtcs++; 1295 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1296 } 1297 1298 if (num_active_crtcs != 1) 1299 wm->cxsr = false; 1300 1301 if (num_active_crtcs > 1) 1302 wm->level = VLV_WM_LEVEL_PM2; 1303 1304 for_each_intel_crtc(dev, crtc) { 1305 struct vlv_wm_state *wm_state = &crtc->wm_state; 1306 enum i915_pipe pipe = crtc->pipe; 1307 1308 if (!crtc->active) 1309 continue; 1310 1311 wm->pipe[pipe] = wm_state->wm[wm->level]; 1312 if (wm->cxsr) 1313 wm->sr = wm_state->sr[wm->level]; 1314 1315 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1316 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1317 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1318 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1319 } 1320 } 1321 1322 static void vlv_update_wm(struct drm_crtc *crtc) 1323 { 1324 struct drm_device *dev = crtc->dev; 1325 struct drm_i915_private *dev_priv = dev->dev_private; 1326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1327 enum i915_pipe pipe = intel_crtc->pipe; 1328 struct vlv_wm_values wm = {}; 1329 1330 vlv_compute_wm(intel_crtc); 1331 vlv_merge_wm(dev, &wm); 1332 1333 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1334 /* FIXME should be part of crtc atomic commit */ 1335 vlv_pipe_set_fifo_size(intel_crtc); 1336 return; 1337 } 1338 1339 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1340 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1341 chv_set_memory_dvfs(dev_priv, false); 1342 1343 if (wm.level < VLV_WM_LEVEL_PM5 && 1344 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1345 chv_set_memory_pm5(dev_priv, false); 1346 1347 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1348 intel_set_memory_cxsr(dev_priv, false); 1349 1350 /* FIXME should be part of crtc atomic commit */ 1351 vlv_pipe_set_fifo_size(intel_crtc); 1352 1353 vlv_write_wm_values(intel_crtc, &wm); 1354 1355 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1356 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1357 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1358 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1359 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1360 1361 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1362 intel_set_memory_cxsr(dev_priv, true); 1363 1364 if (wm.level >= VLV_WM_LEVEL_PM5 && 1365 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1366 chv_set_memory_pm5(dev_priv, true); 1367 1368 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1369 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1370 chv_set_memory_dvfs(dev_priv, true); 1371 1372 dev_priv->wm.vlv = wm; 1373 } 1374 1375 #define single_plane_enabled(mask) is_power_of_2(mask) 1376 1377 static void g4x_update_wm(struct drm_crtc *crtc) 1378 { 1379 struct drm_device *dev = crtc->dev; 1380 static const int sr_latency_ns = 12000; 1381 struct drm_i915_private *dev_priv = dev->dev_private; 1382 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1383 int plane_sr, cursor_sr; 1384 unsigned int enabled = 0; 1385 bool cxsr_enabled; 1386 1387 if (g4x_compute_wm0(dev, PIPE_A, 1388 &g4x_wm_info, pessimal_latency_ns, 1389 &g4x_cursor_wm_info, pessimal_latency_ns, 1390 &planea_wm, &cursora_wm)) 1391 enabled |= 1 << PIPE_A; 1392 1393 if (g4x_compute_wm0(dev, PIPE_B, 1394 &g4x_wm_info, pessimal_latency_ns, 1395 &g4x_cursor_wm_info, pessimal_latency_ns, 1396 &planeb_wm, &cursorb_wm)) 1397 enabled |= 1 << PIPE_B; 1398 1399 if (single_plane_enabled(enabled) && 1400 g4x_compute_srwm(dev, ffs(enabled) - 1, 1401 sr_latency_ns, 1402 &g4x_wm_info, 1403 &g4x_cursor_wm_info, 1404 &plane_sr, &cursor_sr)) { 1405 cxsr_enabled = true; 1406 } else { 1407 cxsr_enabled = false; 1408 intel_set_memory_cxsr(dev_priv, false); 1409 plane_sr = cursor_sr = 0; 1410 } 1411 1412 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1413 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1414 planea_wm, cursora_wm, 1415 planeb_wm, cursorb_wm, 1416 plane_sr, cursor_sr); 1417 1418 I915_WRITE(DSPFW1, 1419 FW_WM(plane_sr, SR) | 1420 FW_WM(cursorb_wm, CURSORB) | 1421 FW_WM(planeb_wm, PLANEB) | 1422 FW_WM(planea_wm, PLANEA)); 1423 I915_WRITE(DSPFW2, 1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1425 FW_WM(cursora_wm, CURSORA)); 1426 /* HPLL off in SR has some issues on G4x... disable it */ 1427 I915_WRITE(DSPFW3, 1428 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1429 FW_WM(cursor_sr, CURSOR_SR)); 1430 1431 if (cxsr_enabled) 1432 intel_set_memory_cxsr(dev_priv, true); 1433 } 1434 1435 static void i965_update_wm(struct drm_crtc *unused_crtc) 1436 { 1437 struct drm_device *dev = unused_crtc->dev; 1438 struct drm_i915_private *dev_priv = dev->dev_private; 1439 struct drm_crtc *crtc; 1440 int srwm = 1; 1441 int cursor_sr = 16; 1442 bool cxsr_enabled; 1443 1444 /* Calc sr entries for one plane configs */ 1445 crtc = single_enabled_crtc(dev); 1446 if (crtc) { 1447 /* self-refresh has much higher latency */ 1448 static const int sr_latency_ns = 12000; 1449 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1450 int clock = adjusted_mode->crtc_clock; 1451 int htotal = adjusted_mode->crtc_htotal; 1452 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1453 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 1454 unsigned long line_time_us; 1455 int entries; 1456 1457 line_time_us = max(htotal * 1000 / clock, 1); 1458 1459 /* Use ns/us then divide to preserve precision */ 1460 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1461 pixel_size * hdisplay; 1462 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1463 srwm = I965_FIFO_SIZE - entries; 1464 if (srwm < 0) 1465 srwm = 1; 1466 srwm &= 0x1ff; 1467 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1468 entries, srwm); 1469 1470 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1471 pixel_size * crtc->cursor->state->crtc_w; 1472 entries = DIV_ROUND_UP(entries, 1473 i965_cursor_wm_info.cacheline_size); 1474 cursor_sr = i965_cursor_wm_info.fifo_size - 1475 (entries + i965_cursor_wm_info.guard_size); 1476 1477 if (cursor_sr > i965_cursor_wm_info.max_wm) 1478 cursor_sr = i965_cursor_wm_info.max_wm; 1479 1480 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1481 "cursor %d\n", srwm, cursor_sr); 1482 1483 cxsr_enabled = true; 1484 } else { 1485 cxsr_enabled = false; 1486 /* Turn off self refresh if both pipes are enabled */ 1487 intel_set_memory_cxsr(dev_priv, false); 1488 } 1489 1490 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1491 srwm); 1492 1493 /* 965 has limitations... */ 1494 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1495 FW_WM(8, CURSORB) | 1496 FW_WM(8, PLANEB) | 1497 FW_WM(8, PLANEA)); 1498 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1499 FW_WM(8, PLANEC_OLD)); 1500 /* update cursor SR watermark */ 1501 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1502 1503 if (cxsr_enabled) 1504 intel_set_memory_cxsr(dev_priv, true); 1505 } 1506 1507 #undef FW_WM 1508 1509 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1510 { 1511 struct drm_device *dev = unused_crtc->dev; 1512 struct drm_i915_private *dev_priv = dev->dev_private; 1513 const struct intel_watermark_params *wm_info; 1514 uint32_t fwater_lo; 1515 uint32_t fwater_hi; 1516 int cwm, srwm = 1; 1517 int fifo_size; 1518 int planea_wm, planeb_wm; 1519 struct drm_crtc *crtc, *enabled = NULL; 1520 1521 if (IS_I945GM(dev)) 1522 wm_info = &i945_wm_info; 1523 else if (!IS_GEN2(dev)) 1524 wm_info = &i915_wm_info; 1525 else 1526 wm_info = &i830_a_wm_info; 1527 1528 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1529 crtc = intel_get_crtc_for_plane(dev, 0); 1530 if (intel_crtc_active(crtc)) { 1531 const struct drm_display_mode *adjusted_mode; 1532 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1533 if (IS_GEN2(dev)) 1534 cpp = 4; 1535 1536 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1537 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1538 wm_info, fifo_size, cpp, 1539 pessimal_latency_ns); 1540 enabled = crtc; 1541 } else { 1542 planea_wm = fifo_size - wm_info->guard_size; 1543 if (planea_wm > (long)wm_info->max_wm) 1544 planea_wm = wm_info->max_wm; 1545 } 1546 1547 if (IS_GEN2(dev)) 1548 wm_info = &i830_bc_wm_info; 1549 1550 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1551 crtc = intel_get_crtc_for_plane(dev, 1); 1552 if (intel_crtc_active(crtc)) { 1553 const struct drm_display_mode *adjusted_mode; 1554 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1555 if (IS_GEN2(dev)) 1556 cpp = 4; 1557 1558 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1559 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1560 wm_info, fifo_size, cpp, 1561 pessimal_latency_ns); 1562 if (enabled == NULL) 1563 enabled = crtc; 1564 else 1565 enabled = NULL; 1566 } else { 1567 planeb_wm = fifo_size - wm_info->guard_size; 1568 if (planeb_wm > (long)wm_info->max_wm) 1569 planeb_wm = wm_info->max_wm; 1570 } 1571 1572 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1573 1574 if (IS_I915GM(dev) && enabled) { 1575 struct drm_i915_gem_object *obj; 1576 1577 obj = intel_fb_obj(enabled->primary->state->fb); 1578 1579 /* self-refresh seems busted with untiled */ 1580 if (obj->tiling_mode == I915_TILING_NONE) 1581 enabled = NULL; 1582 } 1583 1584 /* 1585 * Overlay gets an aggressive default since video jitter is bad. 1586 */ 1587 cwm = 2; 1588 1589 /* Play safe and disable self-refresh before adjusting watermarks. */ 1590 intel_set_memory_cxsr(dev_priv, false); 1591 1592 /* Calc sr entries for one plane configs */ 1593 if (HAS_FW_BLC(dev) && enabled) { 1594 /* self-refresh has much higher latency */ 1595 static const int sr_latency_ns = 6000; 1596 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; 1597 int clock = adjusted_mode->crtc_clock; 1598 int htotal = adjusted_mode->crtc_htotal; 1599 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1600 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; 1601 unsigned long line_time_us; 1602 int entries; 1603 1604 line_time_us = max(htotal * 1000 / clock, 1); 1605 1606 /* Use ns/us then divide to preserve precision */ 1607 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1608 pixel_size * hdisplay; 1609 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1610 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1611 srwm = wm_info->fifo_size - entries; 1612 if (srwm < 0) 1613 srwm = 1; 1614 1615 if (IS_I945G(dev) || IS_I945GM(dev)) 1616 I915_WRITE(FW_BLC_SELF, 1617 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1618 else if (IS_I915GM(dev)) 1619 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1620 } 1621 1622 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1623 planea_wm, planeb_wm, cwm, srwm); 1624 1625 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1626 fwater_hi = (cwm & 0x1f); 1627 1628 /* Set request length to 8 cachelines per fetch */ 1629 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1630 fwater_hi = fwater_hi | (1 << 8); 1631 1632 I915_WRITE(FW_BLC, fwater_lo); 1633 I915_WRITE(FW_BLC2, fwater_hi); 1634 1635 if (enabled) 1636 intel_set_memory_cxsr(dev_priv, true); 1637 } 1638 1639 static void i845_update_wm(struct drm_crtc *unused_crtc) 1640 { 1641 struct drm_device *dev = unused_crtc->dev; 1642 struct drm_i915_private *dev_priv = dev->dev_private; 1643 struct drm_crtc *crtc; 1644 const struct drm_display_mode *adjusted_mode; 1645 uint32_t fwater_lo; 1646 int planea_wm; 1647 1648 crtc = single_enabled_crtc(dev); 1649 if (crtc == NULL) 1650 return; 1651 1652 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1653 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1654 &i845_wm_info, 1655 dev_priv->display.get_fifo_size(dev, 0), 1656 4, pessimal_latency_ns); 1657 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1658 fwater_lo |= (3<<8) | planea_wm; 1659 1660 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1661 1662 I915_WRITE(FW_BLC, fwater_lo); 1663 } 1664 1665 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1666 { 1667 uint32_t pixel_rate; 1668 1669 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1670 1671 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1672 * adjust the pixel_rate here. */ 1673 1674 if (pipe_config->pch_pfit.enabled) { 1675 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1676 uint32_t pfit_size = pipe_config->pch_pfit.size; 1677 1678 pipe_w = pipe_config->pipe_src_w; 1679 pipe_h = pipe_config->pipe_src_h; 1680 1681 pfit_w = (pfit_size >> 16) & 0xFFFF; 1682 pfit_h = pfit_size & 0xFFFF; 1683 if (pipe_w < pfit_w) 1684 pipe_w = pfit_w; 1685 if (pipe_h < pfit_h) 1686 pipe_h = pfit_h; 1687 1688 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1689 pfit_w * pfit_h); 1690 } 1691 1692 return pixel_rate; 1693 } 1694 1695 /* latency must be in 0.1us units. */ 1696 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1697 uint32_t latency) 1698 { 1699 uint64_t ret; 1700 1701 if (WARN(latency == 0, "Latency value missing\n")) 1702 return UINT_MAX; 1703 1704 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1705 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1706 1707 return ret; 1708 } 1709 1710 /* latency must be in 0.1us units. */ 1711 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1712 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1713 uint32_t latency) 1714 { 1715 uint32_t ret; 1716 1717 if (WARN(latency == 0, "Latency value missing\n")) 1718 return UINT_MAX; 1719 1720 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1721 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1722 ret = DIV_ROUND_UP(ret, 64) + 2; 1723 return ret; 1724 } 1725 1726 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1727 uint8_t bytes_per_pixel) 1728 { 1729 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1730 } 1731 1732 struct skl_pipe_wm_parameters { 1733 bool active; 1734 uint32_t pipe_htotal; 1735 uint32_t pixel_rate; /* in KHz */ 1736 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; 1737 }; 1738 1739 struct ilk_wm_maximums { 1740 uint16_t pri; 1741 uint16_t spr; 1742 uint16_t cur; 1743 uint16_t fbc; 1744 }; 1745 1746 /* used in computing the new watermarks state */ 1747 struct intel_wm_config { 1748 unsigned int num_pipes_active; 1749 bool sprites_enabled; 1750 bool sprites_scaled; 1751 }; 1752 1753 /* 1754 * For both WM_PIPE and WM_LP. 1755 * mem_value must be in 0.1us units. 1756 */ 1757 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 1758 const struct intel_plane_state *pstate, 1759 uint32_t mem_value, 1760 bool is_lp) 1761 { 1762 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1763 uint32_t method1, method2; 1764 1765 if (!cstate->base.active || !pstate->visible) 1766 return 0; 1767 1768 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1769 1770 if (!is_lp) 1771 return method1; 1772 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1774 cstate->base.adjusted_mode.crtc_htotal, 1775 drm_rect_width(&pstate->dst), 1776 bpp, 1777 mem_value); 1778 1779 return min(method1, method2); 1780 } 1781 1782 /* 1783 * For both WM_PIPE and WM_LP. 1784 * mem_value must be in 0.1us units. 1785 */ 1786 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 1787 const struct intel_plane_state *pstate, 1788 uint32_t mem_value) 1789 { 1790 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1791 uint32_t method1, method2; 1792 1793 if (!cstate->base.active || !pstate->visible) 1794 return 0; 1795 1796 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1797 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1798 cstate->base.adjusted_mode.crtc_htotal, 1799 drm_rect_width(&pstate->dst), 1800 bpp, 1801 mem_value); 1802 return min(method1, method2); 1803 } 1804 1805 /* 1806 * For both WM_PIPE and WM_LP. 1807 * mem_value must be in 0.1us units. 1808 */ 1809 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 1810 const struct intel_plane_state *pstate, 1811 uint32_t mem_value) 1812 { 1813 /* 1814 * We treat the cursor plane as always-on for the purposes of watermark 1815 * calculation. Until we have two-stage watermark programming merged, 1816 * this is necessary to avoid flickering. 1817 */ 1818 int cpp = 4; 1819 int width = pstate->visible ? pstate->base.crtc_w : 64; 1820 1821 if (!cstate->base.active) 1822 return 0; 1823 1824 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1825 cstate->base.adjusted_mode.crtc_htotal, 1826 width, cpp, mem_value); 1827 } 1828 1829 /* Only for WM_LP. */ 1830 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 1831 const struct intel_plane_state *pstate, 1832 uint32_t pri_val) 1833 { 1834 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1835 1836 if (!cstate->base.active || !pstate->visible) 1837 return 0; 1838 1839 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); 1840 } 1841 1842 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1843 { 1844 if (INTEL_INFO(dev)->gen >= 8) 1845 return 3072; 1846 else if (INTEL_INFO(dev)->gen >= 7) 1847 return 768; 1848 else 1849 return 512; 1850 } 1851 1852 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1853 int level, bool is_sprite) 1854 { 1855 if (INTEL_INFO(dev)->gen >= 8) 1856 /* BDW primary/sprite plane watermarks */ 1857 return level == 0 ? 255 : 2047; 1858 else if (INTEL_INFO(dev)->gen >= 7) 1859 /* IVB/HSW primary/sprite plane watermarks */ 1860 return level == 0 ? 127 : 1023; 1861 else if (!is_sprite) 1862 /* ILK/SNB primary plane watermarks */ 1863 return level == 0 ? 127 : 511; 1864 else 1865 /* ILK/SNB sprite plane watermarks */ 1866 return level == 0 ? 63 : 255; 1867 } 1868 1869 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1870 int level) 1871 { 1872 if (INTEL_INFO(dev)->gen >= 7) 1873 return level == 0 ? 63 : 255; 1874 else 1875 return level == 0 ? 31 : 63; 1876 } 1877 1878 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1879 { 1880 if (INTEL_INFO(dev)->gen >= 8) 1881 return 31; 1882 else 1883 return 15; 1884 } 1885 1886 /* Calculate the maximum primary/sprite plane watermark */ 1887 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1888 int level, 1889 const struct intel_wm_config *config, 1890 enum intel_ddb_partitioning ddb_partitioning, 1891 bool is_sprite) 1892 { 1893 unsigned int fifo_size = ilk_display_fifo_size(dev); 1894 1895 /* if sprites aren't enabled, sprites get nothing */ 1896 if (is_sprite && !config->sprites_enabled) 1897 return 0; 1898 1899 /* HSW allows LP1+ watermarks even with multiple pipes */ 1900 if (level == 0 || config->num_pipes_active > 1) { 1901 fifo_size /= INTEL_INFO(dev)->num_pipes; 1902 1903 /* 1904 * For some reason the non self refresh 1905 * FIFO size is only half of the self 1906 * refresh FIFO size on ILK/SNB. 1907 */ 1908 if (INTEL_INFO(dev)->gen <= 6) 1909 fifo_size /= 2; 1910 } 1911 1912 if (config->sprites_enabled) { 1913 /* level 0 is always calculated with 1:1 split */ 1914 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1915 if (is_sprite) 1916 fifo_size *= 5; 1917 fifo_size /= 6; 1918 } else { 1919 fifo_size /= 2; 1920 } 1921 } 1922 1923 /* clamp to max that the registers can hold */ 1924 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1925 } 1926 1927 /* Calculate the maximum cursor plane watermark */ 1928 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1929 int level, 1930 const struct intel_wm_config *config) 1931 { 1932 /* HSW LP1+ watermarks w/ multiple pipes */ 1933 if (level > 0 && config->num_pipes_active > 1) 1934 return 64; 1935 1936 /* otherwise just report max that registers can hold */ 1937 return ilk_cursor_wm_reg_max(dev, level); 1938 } 1939 1940 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1941 int level, 1942 const struct intel_wm_config *config, 1943 enum intel_ddb_partitioning ddb_partitioning, 1944 struct ilk_wm_maximums *max) 1945 { 1946 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1947 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1948 max->cur = ilk_cursor_wm_max(dev, level, config); 1949 max->fbc = ilk_fbc_wm_reg_max(dev); 1950 } 1951 1952 static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 1953 int level, 1954 struct ilk_wm_maximums *max) 1955 { 1956 max->pri = ilk_plane_wm_reg_max(dev, level, false); 1957 max->spr = ilk_plane_wm_reg_max(dev, level, true); 1958 max->cur = ilk_cursor_wm_reg_max(dev, level); 1959 max->fbc = ilk_fbc_wm_reg_max(dev); 1960 } 1961 1962 static bool ilk_validate_wm_level(int level, 1963 const struct ilk_wm_maximums *max, 1964 struct intel_wm_level *result) 1965 { 1966 bool ret; 1967 1968 /* already determined to be invalid? */ 1969 if (!result->enable) 1970 return false; 1971 1972 result->enable = result->pri_val <= max->pri && 1973 result->spr_val <= max->spr && 1974 result->cur_val <= max->cur; 1975 1976 ret = result->enable; 1977 1978 /* 1979 * HACK until we can pre-compute everything, 1980 * and thus fail gracefully if LP0 watermarks 1981 * are exceeded... 1982 */ 1983 if (level == 0 && !result->enable) { 1984 if (result->pri_val > max->pri) 1985 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1986 level, result->pri_val, max->pri); 1987 if (result->spr_val > max->spr) 1988 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1989 level, result->spr_val, max->spr); 1990 if (result->cur_val > max->cur) 1991 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1992 level, result->cur_val, max->cur); 1993 1994 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1995 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1996 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1997 result->enable = true; 1998 } 1999 2000 return ret; 2001 } 2002 2003 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 2004 const struct intel_crtc *intel_crtc, 2005 int level, 2006 struct intel_crtc_state *cstate, 2007 struct intel_wm_level *result) 2008 { 2009 struct intel_plane *intel_plane; 2010 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 2011 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 2012 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 2013 2014 /* WM1+ latency values stored in 0.5us units */ 2015 if (level > 0) { 2016 pri_latency *= 5; 2017 spr_latency *= 5; 2018 cur_latency *= 5; 2019 } 2020 2021 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { 2022 struct intel_plane_state *pstate = 2023 to_intel_plane_state(intel_plane->base.state); 2024 2025 switch (intel_plane->base.type) { 2026 case DRM_PLANE_TYPE_PRIMARY: 2027 result->pri_val = ilk_compute_pri_wm(cstate, pstate, 2028 pri_latency, 2029 level); 2030 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, 2031 result->pri_val); 2032 break; 2033 case DRM_PLANE_TYPE_OVERLAY: 2034 result->spr_val = ilk_compute_spr_wm(cstate, pstate, 2035 spr_latency); 2036 break; 2037 case DRM_PLANE_TYPE_CURSOR: 2038 result->cur_val = ilk_compute_cur_wm(cstate, pstate, 2039 cur_latency); 2040 break; 2041 } 2042 } 2043 2044 result->enable = true; 2045 } 2046 2047 static uint32_t 2048 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 2049 { 2050 struct drm_i915_private *dev_priv = dev->dev_private; 2051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2052 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 2053 u32 linetime, ips_linetime; 2054 2055 if (!intel_crtc->active) 2056 return 0; 2057 2058 /* The WM are computed with base on how long it takes to fill a single 2059 * row at the given clock rate, multiplied by 8. 2060 * */ 2061 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2062 adjusted_mode->crtc_clock); 2063 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2064 dev_priv->cdclk_freq); 2065 2066 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2067 PIPE_WM_LINETIME_TIME(linetime); 2068 } 2069 2070 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2071 { 2072 struct drm_i915_private *dev_priv = dev->dev_private; 2073 2074 if (IS_GEN9(dev)) { 2075 uint32_t val; 2076 int ret, i; 2077 int level, max_level = ilk_wm_max_level(dev); 2078 2079 /* read the first set of memory latencies[0:3] */ 2080 val = 0; /* data0 to be programmed to 0 for first set */ 2081 mutex_lock(&dev_priv->rps.hw_lock); 2082 ret = sandybridge_pcode_read(dev_priv, 2083 GEN9_PCODE_READ_MEM_LATENCY, 2084 &val); 2085 mutex_unlock(&dev_priv->rps.hw_lock); 2086 2087 if (ret) { 2088 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2089 return; 2090 } 2091 2092 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2093 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2094 GEN9_MEM_LATENCY_LEVEL_MASK; 2095 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2096 GEN9_MEM_LATENCY_LEVEL_MASK; 2097 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2098 GEN9_MEM_LATENCY_LEVEL_MASK; 2099 2100 /* read the second set of memory latencies[4:7] */ 2101 val = 1; /* data0 to be programmed to 1 for second set */ 2102 mutex_lock(&dev_priv->rps.hw_lock); 2103 ret = sandybridge_pcode_read(dev_priv, 2104 GEN9_PCODE_READ_MEM_LATENCY, 2105 &val); 2106 mutex_unlock(&dev_priv->rps.hw_lock); 2107 if (ret) { 2108 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2109 return; 2110 } 2111 2112 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2113 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2114 GEN9_MEM_LATENCY_LEVEL_MASK; 2115 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2116 GEN9_MEM_LATENCY_LEVEL_MASK; 2117 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2118 GEN9_MEM_LATENCY_LEVEL_MASK; 2119 2120 /* 2121 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 2122 * need to be disabled. We make sure to sanitize the values out 2123 * of the punit to satisfy this requirement. 2124 */ 2125 for (level = 1; level <= max_level; level++) { 2126 if (wm[level] == 0) { 2127 for (i = level + 1; i <= max_level; i++) 2128 wm[i] = 0; 2129 break; 2130 } 2131 } 2132 2133 /* 2134 * WaWmMemoryReadLatency:skl 2135 * 2136 * punit doesn't take into account the read latency so we need 2137 * to add 2us to the various latency levels we retrieve from the 2138 * punit when level 0 response data us 0us. 2139 */ 2140 if (wm[0] == 0) { 2141 wm[0] += 2; 2142 for (level = 1; level <= max_level; level++) { 2143 if (wm[level] == 0) 2144 break; 2145 wm[level] += 2; 2146 } 2147 } 2148 2149 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2150 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2151 2152 wm[0] = (sskpd >> 56) & 0xFF; 2153 if (wm[0] == 0) 2154 wm[0] = sskpd & 0xF; 2155 wm[1] = (sskpd >> 4) & 0xFF; 2156 wm[2] = (sskpd >> 12) & 0xFF; 2157 wm[3] = (sskpd >> 20) & 0x1FF; 2158 wm[4] = (sskpd >> 32) & 0x1FF; 2159 } else if (INTEL_INFO(dev)->gen >= 6) { 2160 uint32_t sskpd = I915_READ(MCH_SSKPD); 2161 2162 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2163 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2164 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2165 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2166 } else if (INTEL_INFO(dev)->gen >= 5) { 2167 uint32_t mltr = I915_READ(MLTR_ILK); 2168 2169 /* ILK primary LP0 latency is 700 ns */ 2170 wm[0] = 7; 2171 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2172 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2173 } 2174 } 2175 2176 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2177 { 2178 /* ILK sprite LP0 latency is 1300 ns */ 2179 if (INTEL_INFO(dev)->gen == 5) 2180 wm[0] = 13; 2181 } 2182 2183 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2184 { 2185 /* ILK cursor LP0 latency is 1300 ns */ 2186 if (INTEL_INFO(dev)->gen == 5) 2187 wm[0] = 13; 2188 2189 /* WaDoubleCursorLP3Latency:ivb */ 2190 if (IS_IVYBRIDGE(dev)) 2191 wm[3] *= 2; 2192 } 2193 2194 int ilk_wm_max_level(const struct drm_device *dev) 2195 { 2196 /* how many WM levels are we expecting */ 2197 if (INTEL_INFO(dev)->gen >= 9) 2198 return 7; 2199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2200 return 4; 2201 else if (INTEL_INFO(dev)->gen >= 6) 2202 return 3; 2203 else 2204 return 2; 2205 } 2206 2207 static void intel_print_wm_latency(struct drm_device *dev, 2208 const char *name, 2209 const uint16_t wm[8]) 2210 { 2211 int level, max_level = ilk_wm_max_level(dev); 2212 2213 for (level = 0; level <= max_level; level++) { 2214 unsigned int latency = wm[level]; 2215 2216 if (latency == 0) { 2217 DRM_ERROR("%s WM%d latency not provided\n", 2218 name, level); 2219 continue; 2220 } 2221 2222 /* 2223 * - latencies are in us on gen9. 2224 * - before then, WM1+ latency values are in 0.5us units 2225 */ 2226 if (IS_GEN9(dev)) 2227 latency *= 10; 2228 else if (level > 0) 2229 latency *= 5; 2230 2231 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2232 name, level, wm[level], 2233 latency / 10, latency % 10); 2234 } 2235 } 2236 2237 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2238 uint16_t wm[5], uint16_t min) 2239 { 2240 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2241 2242 if (wm[0] >= min) 2243 return false; 2244 2245 wm[0] = max(wm[0], min); 2246 for (level = 1; level <= max_level; level++) 2247 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2248 2249 return true; 2250 } 2251 2252 static void snb_wm_latency_quirk(struct drm_device *dev) 2253 { 2254 struct drm_i915_private *dev_priv = dev->dev_private; 2255 bool changed; 2256 2257 /* 2258 * The BIOS provided WM memory latency values are often 2259 * inadequate for high resolution displays. Adjust them. 2260 */ 2261 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2262 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2263 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2264 2265 if (!changed) 2266 return; 2267 2268 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2269 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2270 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2271 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2272 } 2273 2274 static void ilk_setup_wm_latency(struct drm_device *dev) 2275 { 2276 struct drm_i915_private *dev_priv = dev->dev_private; 2277 2278 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2279 2280 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2281 sizeof(dev_priv->wm.pri_latency)); 2282 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2283 sizeof(dev_priv->wm.pri_latency)); 2284 2285 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2286 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2287 2288 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2289 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2290 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2291 2292 if (IS_GEN6(dev)) 2293 snb_wm_latency_quirk(dev); 2294 } 2295 2296 static void skl_setup_wm_latency(struct drm_device *dev) 2297 { 2298 struct drm_i915_private *dev_priv = dev->dev_private; 2299 2300 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2301 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2302 } 2303 2304 static void ilk_compute_wm_config(struct drm_device *dev, 2305 struct intel_wm_config *config) 2306 { 2307 struct intel_crtc *intel_crtc; 2308 2309 /* Compute the currently _active_ config */ 2310 for_each_intel_crtc(dev, intel_crtc) { 2311 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; 2312 2313 if (!wm->pipe_enabled) 2314 continue; 2315 2316 config->sprites_enabled |= wm->sprites_enabled; 2317 config->sprites_scaled |= wm->sprites_scaled; 2318 config->num_pipes_active++; 2319 } 2320 } 2321 2322 /* Compute new watermarks for the pipe */ 2323 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, 2324 struct intel_pipe_wm *pipe_wm) 2325 { 2326 struct drm_crtc *crtc = cstate->base.crtc; 2327 struct drm_device *dev = crtc->dev; 2328 const struct drm_i915_private *dev_priv = dev->dev_private; 2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2330 struct intel_plane *intel_plane; 2331 struct intel_plane_state *sprstate = NULL; 2332 int level, max_level = ilk_wm_max_level(dev); 2333 /* LP0 watermark maximums depend on this pipe alone */ 2334 struct intel_wm_config config = { 2335 .num_pipes_active = 1, 2336 }; 2337 struct ilk_wm_maximums max; 2338 2339 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2340 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { 2341 sprstate = to_intel_plane_state(intel_plane->base.state); 2342 break; 2343 } 2344 } 2345 2346 config.sprites_enabled = sprstate->visible; 2347 config.sprites_scaled = sprstate->visible && 2348 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || 2349 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); 2350 2351 pipe_wm->pipe_enabled = cstate->base.active; 2352 pipe_wm->sprites_enabled = sprstate->visible; 2353 pipe_wm->sprites_scaled = config.sprites_scaled; 2354 2355 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2356 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) 2357 max_level = 1; 2358 2359 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2360 if (config.sprites_scaled) 2361 max_level = 0; 2362 2363 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); 2364 2365 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2366 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2367 2368 /* LP0 watermarks always use 1/2 DDB partitioning */ 2369 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2370 2371 /* At least LP0 must be valid */ 2372 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2373 return false; 2374 2375 ilk_compute_wm_reg_maximums(dev, 1, &max); 2376 2377 for (level = 1; level <= max_level; level++) { 2378 struct intel_wm_level wm = {}; 2379 2380 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); 2381 2382 /* 2383 * Disable any watermark level that exceeds the 2384 * register maximums since such watermarks are 2385 * always invalid. 2386 */ 2387 if (!ilk_validate_wm_level(level, &max, &wm)) 2388 break; 2389 2390 pipe_wm->wm[level] = wm; 2391 } 2392 2393 return true; 2394 } 2395 2396 /* 2397 * Merge the watermarks from all active pipes for a specific level. 2398 */ 2399 static void ilk_merge_wm_level(struct drm_device *dev, 2400 int level, 2401 struct intel_wm_level *ret_wm) 2402 { 2403 const struct intel_crtc *intel_crtc; 2404 2405 ret_wm->enable = true; 2406 2407 for_each_intel_crtc(dev, intel_crtc) { 2408 const struct intel_pipe_wm *active = &intel_crtc->wm.active; 2409 const struct intel_wm_level *wm = &active->wm[level]; 2410 2411 if (!active->pipe_enabled) 2412 continue; 2413 2414 /* 2415 * The watermark values may have been used in the past, 2416 * so we must maintain them in the registers for some 2417 * time even if the level is now disabled. 2418 */ 2419 if (!wm->enable) 2420 ret_wm->enable = false; 2421 2422 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2423 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2424 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2425 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2426 } 2427 } 2428 2429 /* 2430 * Merge all low power watermarks for all active pipes. 2431 */ 2432 static void ilk_wm_merge(struct drm_device *dev, 2433 const struct intel_wm_config *config, 2434 const struct ilk_wm_maximums *max, 2435 struct intel_pipe_wm *merged) 2436 { 2437 struct drm_i915_private *dev_priv = dev->dev_private; 2438 int level, max_level = ilk_wm_max_level(dev); 2439 int last_enabled_level = max_level; 2440 2441 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2442 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2443 config->num_pipes_active > 1) 2444 return; 2445 2446 /* ILK: FBC WM must be disabled always */ 2447 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2448 2449 /* merge each WM1+ level */ 2450 for (level = 1; level <= max_level; level++) { 2451 struct intel_wm_level *wm = &merged->wm[level]; 2452 2453 ilk_merge_wm_level(dev, level, wm); 2454 2455 if (level > last_enabled_level) 2456 wm->enable = false; 2457 else if (!ilk_validate_wm_level(level, max, wm)) 2458 /* make sure all following levels get disabled */ 2459 last_enabled_level = level - 1; 2460 2461 /* 2462 * The spec says it is preferred to disable 2463 * FBC WMs instead of disabling a WM level. 2464 */ 2465 if (wm->fbc_val > max->fbc) { 2466 if (wm->enable) 2467 merged->fbc_wm_enabled = false; 2468 wm->fbc_val = 0; 2469 } 2470 } 2471 2472 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2473 /* 2474 * FIXME this is racy. FBC might get enabled later. 2475 * What we should check here is whether FBC can be 2476 * enabled sometime later. 2477 */ 2478 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2479 intel_fbc_enabled(dev_priv)) { 2480 for (level = 2; level <= max_level; level++) { 2481 struct intel_wm_level *wm = &merged->wm[level]; 2482 2483 wm->enable = false; 2484 } 2485 } 2486 } 2487 2488 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2489 { 2490 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2491 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2492 } 2493 2494 /* The value we need to program into the WM_LPx latency field */ 2495 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2496 { 2497 struct drm_i915_private *dev_priv = dev->dev_private; 2498 2499 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2500 return 2 * level; 2501 else 2502 return dev_priv->wm.pri_latency[level]; 2503 } 2504 2505 static void ilk_compute_wm_results(struct drm_device *dev, 2506 const struct intel_pipe_wm *merged, 2507 enum intel_ddb_partitioning partitioning, 2508 struct ilk_wm_values *results) 2509 { 2510 struct intel_crtc *intel_crtc; 2511 int level, wm_lp; 2512 2513 results->enable_fbc_wm = merged->fbc_wm_enabled; 2514 results->partitioning = partitioning; 2515 2516 /* LP1+ register values */ 2517 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2518 const struct intel_wm_level *r; 2519 2520 level = ilk_wm_lp_to_level(wm_lp, merged); 2521 2522 r = &merged->wm[level]; 2523 2524 /* 2525 * Maintain the watermark values even if the level is 2526 * disabled. Doing otherwise could cause underruns. 2527 */ 2528 results->wm_lp[wm_lp - 1] = 2529 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2530 (r->pri_val << WM1_LP_SR_SHIFT) | 2531 r->cur_val; 2532 2533 if (r->enable) 2534 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2535 2536 if (INTEL_INFO(dev)->gen >= 8) 2537 results->wm_lp[wm_lp - 1] |= 2538 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2539 else 2540 results->wm_lp[wm_lp - 1] |= 2541 r->fbc_val << WM1_LP_FBC_SHIFT; 2542 2543 /* 2544 * Always set WM1S_LP_EN when spr_val != 0, even if the 2545 * level is disabled. Doing otherwise could cause underruns. 2546 */ 2547 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2548 WARN_ON(wm_lp != 1); 2549 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2550 } else 2551 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2552 } 2553 2554 /* LP0 register values */ 2555 for_each_intel_crtc(dev, intel_crtc) { 2556 enum i915_pipe pipe = intel_crtc->pipe; 2557 const struct intel_wm_level *r = 2558 &intel_crtc->wm.active.wm[0]; 2559 2560 if (WARN_ON(!r->enable)) 2561 continue; 2562 2563 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2564 2565 results->wm_pipe[pipe] = 2566 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2567 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2568 r->cur_val; 2569 } 2570 } 2571 2572 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2573 * case both are at the same level. Prefer r1 in case they're the same. */ 2574 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2575 struct intel_pipe_wm *r1, 2576 struct intel_pipe_wm *r2) 2577 { 2578 int level, max_level = ilk_wm_max_level(dev); 2579 int level1 = 0, level2 = 0; 2580 2581 for (level = 1; level <= max_level; level++) { 2582 if (r1->wm[level].enable) 2583 level1 = level; 2584 if (r2->wm[level].enable) 2585 level2 = level; 2586 } 2587 2588 if (level1 == level2) { 2589 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2590 return r2; 2591 else 2592 return r1; 2593 } else if (level1 > level2) { 2594 return r1; 2595 } else { 2596 return r2; 2597 } 2598 } 2599 2600 /* dirty bits used to track which watermarks need changes */ 2601 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2602 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2603 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2604 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2605 #define WM_DIRTY_FBC (1 << 24) 2606 #define WM_DIRTY_DDB (1 << 25) 2607 2608 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2609 const struct ilk_wm_values *old, 2610 const struct ilk_wm_values *new) 2611 { 2612 unsigned int dirty = 0; 2613 enum i915_pipe pipe; 2614 int wm_lp; 2615 2616 for_each_pipe(dev_priv, pipe) { 2617 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2618 dirty |= WM_DIRTY_LINETIME(pipe); 2619 /* Must disable LP1+ watermarks too */ 2620 dirty |= WM_DIRTY_LP_ALL; 2621 } 2622 2623 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2624 dirty |= WM_DIRTY_PIPE(pipe); 2625 /* Must disable LP1+ watermarks too */ 2626 dirty |= WM_DIRTY_LP_ALL; 2627 } 2628 } 2629 2630 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2631 dirty |= WM_DIRTY_FBC; 2632 /* Must disable LP1+ watermarks too */ 2633 dirty |= WM_DIRTY_LP_ALL; 2634 } 2635 2636 if (old->partitioning != new->partitioning) { 2637 dirty |= WM_DIRTY_DDB; 2638 /* Must disable LP1+ watermarks too */ 2639 dirty |= WM_DIRTY_LP_ALL; 2640 } 2641 2642 /* LP1+ watermarks already deemed dirty, no need to continue */ 2643 if (dirty & WM_DIRTY_LP_ALL) 2644 return dirty; 2645 2646 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2647 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2648 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2649 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2650 break; 2651 } 2652 2653 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2654 for (; wm_lp <= 3; wm_lp++) 2655 dirty |= WM_DIRTY_LP(wm_lp); 2656 2657 return dirty; 2658 } 2659 2660 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2661 unsigned int dirty) 2662 { 2663 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2664 bool changed = false; 2665 2666 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2667 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2668 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2669 changed = true; 2670 } 2671 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2672 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2673 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2674 changed = true; 2675 } 2676 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2677 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2678 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2679 changed = true; 2680 } 2681 2682 /* 2683 * Don't touch WM1S_LP_EN here. 2684 * Doing so could cause underruns. 2685 */ 2686 2687 return changed; 2688 } 2689 2690 /* 2691 * The spec says we shouldn't write when we don't need, because every write 2692 * causes WMs to be re-evaluated, expending some power. 2693 */ 2694 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2695 struct ilk_wm_values *results) 2696 { 2697 struct drm_device *dev = dev_priv->dev; 2698 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2699 unsigned int dirty; 2700 uint32_t val; 2701 2702 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2703 if (!dirty) 2704 return; 2705 2706 _ilk_disable_lp_wm(dev_priv, dirty); 2707 2708 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2709 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2710 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2711 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2712 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2713 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2714 2715 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2716 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2717 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2718 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2719 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2720 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2721 2722 if (dirty & WM_DIRTY_DDB) { 2723 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2724 val = I915_READ(WM_MISC); 2725 if (results->partitioning == INTEL_DDB_PART_1_2) 2726 val &= ~WM_MISC_DATA_PARTITION_5_6; 2727 else 2728 val |= WM_MISC_DATA_PARTITION_5_6; 2729 I915_WRITE(WM_MISC, val); 2730 } else { 2731 val = I915_READ(DISP_ARB_CTL2); 2732 if (results->partitioning == INTEL_DDB_PART_1_2) 2733 val &= ~DISP_DATA_PARTITION_5_6; 2734 else 2735 val |= DISP_DATA_PARTITION_5_6; 2736 I915_WRITE(DISP_ARB_CTL2, val); 2737 } 2738 } 2739 2740 if (dirty & WM_DIRTY_FBC) { 2741 val = I915_READ(DISP_ARB_CTL); 2742 if (results->enable_fbc_wm) 2743 val &= ~DISP_FBC_WM_DIS; 2744 else 2745 val |= DISP_FBC_WM_DIS; 2746 I915_WRITE(DISP_ARB_CTL, val); 2747 } 2748 2749 if (dirty & WM_DIRTY_LP(1) && 2750 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2751 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2752 2753 if (INTEL_INFO(dev)->gen >= 7) { 2754 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2755 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2756 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2757 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2758 } 2759 2760 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2761 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2763 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2764 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2765 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2766 2767 dev_priv->wm.hw = *results; 2768 } 2769 2770 static bool ilk_disable_lp_wm(struct drm_device *dev) 2771 { 2772 struct drm_i915_private *dev_priv = dev->dev_private; 2773 2774 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2775 } 2776 2777 /* 2778 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2779 * different active planes. 2780 */ 2781 2782 #define SKL_DDB_SIZE 896 /* in blocks */ 2783 #define BXT_DDB_SIZE 512 2784 2785 static void 2786 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2787 struct drm_crtc *for_crtc, 2788 const struct intel_wm_config *config, 2789 const struct skl_pipe_wm_parameters *params, 2790 struct skl_ddb_entry *alloc /* out */) 2791 { 2792 struct drm_crtc *crtc; 2793 unsigned int pipe_size, ddb_size; 2794 int nth_active_pipe; 2795 2796 if (!params->active) { 2797 alloc->start = 0; 2798 alloc->end = 0; 2799 return; 2800 } 2801 2802 if (IS_BROXTON(dev)) 2803 ddb_size = BXT_DDB_SIZE; 2804 else 2805 ddb_size = SKL_DDB_SIZE; 2806 2807 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2808 2809 nth_active_pipe = 0; 2810 for_each_crtc(dev, crtc) { 2811 if (!to_intel_crtc(crtc)->active) 2812 continue; 2813 2814 if (crtc == for_crtc) 2815 break; 2816 2817 nth_active_pipe++; 2818 } 2819 2820 pipe_size = ddb_size / config->num_pipes_active; 2821 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2822 alloc->end = alloc->start + pipe_size; 2823 } 2824 2825 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2826 { 2827 if (config->num_pipes_active == 1) 2828 return 32; 2829 2830 return 8; 2831 } 2832 2833 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2834 { 2835 entry->start = reg & 0x3ff; 2836 entry->end = (reg >> 16) & 0x3ff; 2837 if (entry->end) 2838 entry->end += 1; 2839 } 2840 2841 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2842 struct skl_ddb_allocation *ddb /* out */) 2843 { 2844 enum i915_pipe pipe; 2845 int plane; 2846 u32 val; 2847 2848 memset(ddb, 0, sizeof(*ddb)); 2849 2850 for_each_pipe(dev_priv, pipe) { 2851 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) 2852 continue; 2853 2854 for_each_plane(dev_priv, pipe, plane) { 2855 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2856 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2857 val); 2858 } 2859 2860 val = I915_READ(CUR_BUF_CFG(pipe)); 2861 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], 2862 val); 2863 } 2864 } 2865 2866 static unsigned int 2867 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) 2868 { 2869 2870 /* for planar format */ 2871 if (p->y_bytes_per_pixel) { 2872 if (y) /* y-plane data rate */ 2873 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; 2874 else /* uv-plane data rate */ 2875 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; 2876 } 2877 2878 /* for packed formats */ 2879 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; 2880 } 2881 2882 /* 2883 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2884 * a 8192x4096@32bpp framebuffer: 2885 * 3 * 4096 * 8192 * 4 < 2^32 2886 */ 2887 static unsigned int 2888 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, 2889 const struct skl_pipe_wm_parameters *params) 2890 { 2891 unsigned int total_data_rate = 0; 2892 int plane; 2893 2894 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2895 const struct intel_plane_wm_parameters *p; 2896 2897 p = ¶ms->plane[plane]; 2898 if (!p->enabled) 2899 continue; 2900 2901 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ 2902 if (p->y_bytes_per_pixel) { 2903 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ 2904 } 2905 } 2906 2907 return total_data_rate; 2908 } 2909 2910 static void 2911 skl_allocate_pipe_ddb(struct drm_crtc *crtc, 2912 const struct intel_wm_config *config, 2913 const struct skl_pipe_wm_parameters *params, 2914 struct skl_ddb_allocation *ddb /* out */) 2915 { 2916 struct drm_device *dev = crtc->dev; 2917 struct drm_i915_private *dev_priv = dev->dev_private; 2918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2919 enum i915_pipe pipe = intel_crtc->pipe; 2920 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2921 uint16_t alloc_size, start, cursor_blocks; 2922 uint16_t minimum[I915_MAX_PLANES]; 2923 uint16_t y_minimum[I915_MAX_PLANES]; 2924 unsigned int total_data_rate; 2925 int plane; 2926 2927 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); 2928 alloc_size = skl_ddb_entry_size(alloc); 2929 if (alloc_size == 0) { 2930 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2931 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, 2932 sizeof(ddb->plane[pipe][PLANE_CURSOR])); 2933 return; 2934 } 2935 2936 cursor_blocks = skl_cursor_allocation(config); 2937 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; 2938 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; 2939 2940 alloc_size -= cursor_blocks; 2941 alloc->end -= cursor_blocks; 2942 2943 /* 1. Allocate the mininum required blocks for each active plane */ 2944 for_each_plane(dev_priv, pipe, plane) { 2945 const struct intel_plane_wm_parameters *p; 2946 2947 p = ¶ms->plane[plane]; 2948 if (!p->enabled) 2949 continue; 2950 2951 minimum[plane] = 8; 2952 alloc_size -= minimum[plane]; 2953 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; 2954 alloc_size -= y_minimum[plane]; 2955 } 2956 2957 /* 2958 * 2. Distribute the remaining space in proportion to the amount of 2959 * data each plane needs to fetch from memory. 2960 * 2961 * FIXME: we may not allocate every single block here. 2962 */ 2963 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); 2964 2965 start = alloc->start; 2966 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2967 const struct intel_plane_wm_parameters *p; 2968 unsigned int data_rate, y_data_rate; 2969 uint16_t plane_blocks, y_plane_blocks = 0; 2970 2971 p = ¶ms->plane[plane]; 2972 if (!p->enabled) 2973 continue; 2974 2975 data_rate = skl_plane_relative_data_rate(p, 0); 2976 2977 /* 2978 * allocation for (packed formats) or (uv-plane part of planar format): 2979 * promote the expression to 64 bits to avoid overflowing, the 2980 * result is < available as data_rate / total_data_rate < 1 2981 */ 2982 plane_blocks = minimum[plane]; 2983 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 2984 total_data_rate); 2985 2986 ddb->plane[pipe][plane].start = start; 2987 ddb->plane[pipe][plane].end = start + plane_blocks; 2988 2989 start += plane_blocks; 2990 2991 /* 2992 * allocation for y_plane part of planar format: 2993 */ 2994 if (p->y_bytes_per_pixel) { 2995 y_data_rate = skl_plane_relative_data_rate(p, 1); 2996 y_plane_blocks = y_minimum[plane]; 2997 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 2998 total_data_rate); 2999 3000 ddb->y_plane[pipe][plane].start = start; 3001 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; 3002 3003 start += y_plane_blocks; 3004 } 3005 3006 } 3007 3008 } 3009 3010 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3011 { 3012 /* TODO: Take into account the scalers once we support them */ 3013 return config->base.adjusted_mode.crtc_clock; 3014 } 3015 3016 /* 3017 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3018 * for the read latency) and bytes_per_pixel should always be <= 8, so that 3019 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 3020 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 3021 */ 3022 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 3023 uint32_t latency) 3024 { 3025 uint32_t wm_intermediate_val, ret; 3026 3027 if (latency == 0) 3028 return UINT_MAX; 3029 3030 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; 3031 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3032 3033 return ret; 3034 } 3035 3036 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3037 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 3038 uint64_t tiling, uint32_t latency) 3039 { 3040 uint32_t ret; 3041 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3042 uint32_t wm_intermediate_val; 3043 3044 if (latency == 0) 3045 return UINT_MAX; 3046 3047 plane_bytes_per_line = horiz_pixels * bytes_per_pixel; 3048 3049 if (tiling == I915_FORMAT_MOD_Y_TILED || 3050 tiling == I915_FORMAT_MOD_Yf_TILED) { 3051 plane_bytes_per_line *= 4; 3052 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3053 plane_blocks_per_line /= 4; 3054 } else { 3055 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3056 } 3057 3058 wm_intermediate_val = latency * pixel_rate; 3059 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3060 plane_blocks_per_line; 3061 3062 return ret; 3063 } 3064 3065 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3066 const struct intel_crtc *intel_crtc) 3067 { 3068 struct drm_device *dev = intel_crtc->base.dev; 3069 struct drm_i915_private *dev_priv = dev->dev_private; 3070 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3071 enum i915_pipe pipe = intel_crtc->pipe; 3072 3073 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], 3074 sizeof(new_ddb->plane[pipe]))) 3075 return true; 3076 3077 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], 3078 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) 3079 return true; 3080 3081 return false; 3082 } 3083 3084 static void skl_compute_wm_global_parameters(struct drm_device *dev, 3085 struct intel_wm_config *config) 3086 { 3087 struct drm_crtc *crtc; 3088 struct drm_plane *plane; 3089 3090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3091 config->num_pipes_active += to_intel_crtc(crtc)->active; 3092 3093 /* FIXME: I don't think we need those two global parameters on SKL */ 3094 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3095 struct intel_plane *intel_plane = to_intel_plane(plane); 3096 3097 config->sprites_enabled |= intel_plane->wm.enabled; 3098 config->sprites_scaled |= intel_plane->wm.scaled; 3099 } 3100 } 3101 3102 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, 3103 struct skl_pipe_wm_parameters *p) 3104 { 3105 struct drm_device *dev = crtc->dev; 3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3107 enum i915_pipe pipe = intel_crtc->pipe; 3108 struct drm_plane *plane; 3109 struct drm_framebuffer *fb; 3110 int i = 1; /* Index for sprite planes start */ 3111 3112 p->active = intel_crtc->active; 3113 if (p->active) { 3114 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 3115 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); 3116 3117 fb = crtc->primary->state->fb; 3118 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ 3119 if (fb) { 3120 p->plane[0].enabled = true; 3121 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3122 drm_format_plane_cpp(fb->pixel_format, 1) : 3123 drm_format_plane_cpp(fb->pixel_format, 0); 3124 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3125 drm_format_plane_cpp(fb->pixel_format, 0) : 0; 3126 p->plane[0].tiling = fb->modifier[0]; 3127 } else { 3128 p->plane[0].enabled = false; 3129 p->plane[0].bytes_per_pixel = 0; 3130 p->plane[0].y_bytes_per_pixel = 0; 3131 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; 3132 } 3133 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; 3134 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; 3135 p->plane[0].rotation = crtc->primary->state->rotation; 3136 3137 fb = crtc->cursor->state->fb; 3138 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; 3139 if (fb) { 3140 p->plane[PLANE_CURSOR].enabled = true; 3141 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; 3142 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; 3143 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; 3144 } else { 3145 p->plane[PLANE_CURSOR].enabled = false; 3146 p->plane[PLANE_CURSOR].bytes_per_pixel = 0; 3147 p->plane[PLANE_CURSOR].horiz_pixels = 64; 3148 p->plane[PLANE_CURSOR].vert_pixels = 64; 3149 } 3150 } 3151 3152 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3153 struct intel_plane *intel_plane = to_intel_plane(plane); 3154 3155 if (intel_plane->pipe == pipe && 3156 plane->type == DRM_PLANE_TYPE_OVERLAY) 3157 p->plane[i++] = intel_plane->wm; 3158 } 3159 } 3160 3161 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3162 struct skl_pipe_wm_parameters *p, 3163 struct intel_plane_wm_parameters *p_params, 3164 uint16_t ddb_allocation, 3165 int level, 3166 uint16_t *out_blocks, /* out */ 3167 uint8_t *out_lines /* out */) 3168 { 3169 uint32_t latency = dev_priv->wm.skl_latency[level]; 3170 uint32_t method1, method2; 3171 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3172 uint32_t res_blocks, res_lines; 3173 uint32_t selected_result; 3174 uint8_t bytes_per_pixel; 3175 3176 if (latency == 0 || !p->active || !p_params->enabled) 3177 return false; 3178 3179 bytes_per_pixel = p_params->y_bytes_per_pixel ? 3180 p_params->y_bytes_per_pixel : 3181 p_params->bytes_per_pixel; 3182 method1 = skl_wm_method1(p->pixel_rate, 3183 bytes_per_pixel, 3184 latency); 3185 method2 = skl_wm_method2(p->pixel_rate, 3186 p->pipe_htotal, 3187 p_params->horiz_pixels, 3188 bytes_per_pixel, 3189 p_params->tiling, 3190 latency); 3191 3192 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; 3193 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3194 3195 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3196 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { 3197 uint32_t min_scanlines = 4; 3198 uint32_t y_tile_minimum; 3199 if (intel_rotation_90_or_270(p_params->rotation)) { 3200 switch (p_params->bytes_per_pixel) { 3201 case 1: 3202 min_scanlines = 16; 3203 break; 3204 case 2: 3205 min_scanlines = 8; 3206 break; 3207 case 8: 3208 WARN(1, "Unsupported pixel depth for rotation"); 3209 } 3210 } 3211 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3212 selected_result = max(method2, y_tile_minimum); 3213 } else { 3214 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3215 selected_result = min(method1, method2); 3216 else 3217 selected_result = method1; 3218 } 3219 3220 res_blocks = selected_result + 1; 3221 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3222 3223 if (level >= 1 && level <= 7) { 3224 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3225 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) 3226 res_lines += 4; 3227 else 3228 res_blocks++; 3229 } 3230 3231 if (res_blocks >= ddb_allocation || res_lines > 31) 3232 return false; 3233 3234 *out_blocks = res_blocks; 3235 *out_lines = res_lines; 3236 3237 return true; 3238 } 3239 3240 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3241 struct skl_ddb_allocation *ddb, 3242 struct skl_pipe_wm_parameters *p, 3243 enum i915_pipe pipe, 3244 int level, 3245 int num_planes, 3246 struct skl_wm_level *result) 3247 { 3248 uint16_t ddb_blocks; 3249 int i; 3250 3251 for (i = 0; i < num_planes; i++) { 3252 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3253 3254 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3255 p, &p->plane[i], 3256 ddb_blocks, 3257 level, 3258 &result->plane_res_b[i], 3259 &result->plane_res_l[i]); 3260 } 3261 3262 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); 3263 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, 3264 &p->plane[PLANE_CURSOR], 3265 ddb_blocks, level, 3266 &result->plane_res_b[PLANE_CURSOR], 3267 &result->plane_res_l[PLANE_CURSOR]); 3268 } 3269 3270 static uint32_t 3271 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) 3272 { 3273 if (!to_intel_crtc(crtc)->active) 3274 return 0; 3275 3276 if (WARN_ON(p->pixel_rate == 0)) 3277 return 0; 3278 3279 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); 3280 } 3281 3282 static void skl_compute_transition_wm(struct drm_crtc *crtc, 3283 struct skl_pipe_wm_parameters *params, 3284 struct skl_wm_level *trans_wm /* out */) 3285 { 3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3287 int i; 3288 3289 if (!params->active) 3290 return; 3291 3292 /* Until we know more, just disable transition WMs */ 3293 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3294 trans_wm->plane_en[i] = false; 3295 trans_wm->plane_en[PLANE_CURSOR] = false; 3296 } 3297 3298 static void skl_compute_pipe_wm(struct drm_crtc *crtc, 3299 struct skl_ddb_allocation *ddb, 3300 struct skl_pipe_wm_parameters *params, 3301 struct skl_pipe_wm *pipe_wm) 3302 { 3303 struct drm_device *dev = crtc->dev; 3304 const struct drm_i915_private *dev_priv = dev->dev_private; 3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3306 int level, max_level = ilk_wm_max_level(dev); 3307 3308 for (level = 0; level <= max_level; level++) { 3309 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, 3310 level, intel_num_planes(intel_crtc), 3311 &pipe_wm->wm[level]); 3312 } 3313 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); 3314 3315 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); 3316 } 3317 3318 static void skl_compute_wm_results(struct drm_device *dev, 3319 struct skl_pipe_wm_parameters *p, 3320 struct skl_pipe_wm *p_wm, 3321 struct skl_wm_values *r, 3322 struct intel_crtc *intel_crtc) 3323 { 3324 int level, max_level = ilk_wm_max_level(dev); 3325 enum i915_pipe pipe = intel_crtc->pipe; 3326 uint32_t temp; 3327 int i; 3328 3329 for (level = 0; level <= max_level; level++) { 3330 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3331 temp = 0; 3332 3333 temp |= p_wm->wm[level].plane_res_l[i] << 3334 PLANE_WM_LINES_SHIFT; 3335 temp |= p_wm->wm[level].plane_res_b[i]; 3336 if (p_wm->wm[level].plane_en[i]) 3337 temp |= PLANE_WM_EN; 3338 3339 r->plane[pipe][i][level] = temp; 3340 } 3341 3342 temp = 0; 3343 3344 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3345 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; 3346 3347 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) 3348 temp |= PLANE_WM_EN; 3349 3350 r->plane[pipe][PLANE_CURSOR][level] = temp; 3351 3352 } 3353 3354 /* transition WMs */ 3355 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3356 temp = 0; 3357 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3358 temp |= p_wm->trans_wm.plane_res_b[i]; 3359 if (p_wm->trans_wm.plane_en[i]) 3360 temp |= PLANE_WM_EN; 3361 3362 r->plane_trans[pipe][i] = temp; 3363 } 3364 3365 temp = 0; 3366 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3367 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; 3368 if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) 3369 temp |= PLANE_WM_EN; 3370 3371 r->plane_trans[pipe][PLANE_CURSOR] = temp; 3372 3373 r->wm_linetime[pipe] = p_wm->linetime; 3374 } 3375 3376 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, 3377 const struct skl_ddb_entry *entry) 3378 { 3379 if (entry->end) 3380 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3381 else 3382 I915_WRITE(reg, 0); 3383 } 3384 3385 static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3386 const struct skl_wm_values *new) 3387 { 3388 struct drm_device *dev = dev_priv->dev; 3389 struct intel_crtc *crtc; 3390 3391 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 3392 int i, level, max_level = ilk_wm_max_level(dev); 3393 enum i915_pipe pipe = crtc->pipe; 3394 3395 if (!new->dirty[pipe]) 3396 continue; 3397 3398 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3399 3400 for (level = 0; level <= max_level; level++) { 3401 for (i = 0; i < intel_num_planes(crtc); i++) 3402 I915_WRITE(PLANE_WM(pipe, i, level), 3403 new->plane[pipe][i][level]); 3404 I915_WRITE(CUR_WM(pipe, level), 3405 new->plane[pipe][PLANE_CURSOR][level]); 3406 } 3407 for (i = 0; i < intel_num_planes(crtc); i++) 3408 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3409 new->plane_trans[pipe][i]); 3410 I915_WRITE(CUR_WM_TRANS(pipe), 3411 new->plane_trans[pipe][PLANE_CURSOR]); 3412 3413 for (i = 0; i < intel_num_planes(crtc); i++) { 3414 skl_ddb_entry_write(dev_priv, 3415 PLANE_BUF_CFG(pipe, i), 3416 &new->ddb.plane[pipe][i]); 3417 skl_ddb_entry_write(dev_priv, 3418 PLANE_NV12_BUF_CFG(pipe, i), 3419 &new->ddb.y_plane[pipe][i]); 3420 } 3421 3422 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3423 &new->ddb.plane[pipe][PLANE_CURSOR]); 3424 } 3425 } 3426 3427 /* 3428 * When setting up a new DDB allocation arrangement, we need to correctly 3429 * sequence the times at which the new allocations for the pipes are taken into 3430 * account or we'll have pipes fetching from space previously allocated to 3431 * another pipe. 3432 * 3433 * Roughly the sequence looks like: 3434 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3435 * overlapping with a previous light-up pipe (another way to put it is: 3436 * pipes with their new allocation strickly included into their old ones). 3437 * 2. re-allocate the other pipes that get their allocation reduced 3438 * 3. allocate the pipes having their allocation increased 3439 * 3440 * Steps 1. and 2. are here to take care of the following case: 3441 * - Initially DDB looks like this: 3442 * | B | C | 3443 * - enable pipe A. 3444 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3445 * allocation 3446 * | A | B | C | 3447 * 3448 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3449 */ 3450 3451 static void 3452 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int pass) 3453 { 3454 int plane; 3455 3456 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3457 3458 for_each_plane(dev_priv, pipe, plane) { 3459 I915_WRITE(PLANE_SURF(pipe, plane), 3460 I915_READ(PLANE_SURF(pipe, plane))); 3461 } 3462 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3463 } 3464 3465 static bool 3466 skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3467 const struct skl_ddb_allocation *new, 3468 enum i915_pipe pipe) 3469 { 3470 uint16_t old_size, new_size; 3471 3472 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3473 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3474 3475 return old_size != new_size && 3476 new->pipe[pipe].start >= old->pipe[pipe].start && 3477 new->pipe[pipe].end <= old->pipe[pipe].end; 3478 } 3479 3480 static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3481 struct skl_wm_values *new_values) 3482 { 3483 struct drm_device *dev = dev_priv->dev; 3484 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3485 bool reallocated[I915_MAX_PIPES] = {}; 3486 struct intel_crtc *crtc; 3487 enum i915_pipe pipe; 3488 3489 new_ddb = &new_values->ddb; 3490 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3491 3492 /* 3493 * First pass: flush the pipes with the new allocation contained into 3494 * the old space. 3495 * 3496 * We'll wait for the vblank on those pipes to ensure we can safely 3497 * re-allocate the freed space without this pipe fetching from it. 3498 */ 3499 for_each_intel_crtc(dev, crtc) { 3500 if (!crtc->active) 3501 continue; 3502 3503 pipe = crtc->pipe; 3504 3505 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3506 continue; 3507 3508 skl_wm_flush_pipe(dev_priv, pipe, 1); 3509 intel_wait_for_vblank(dev, pipe); 3510 3511 reallocated[pipe] = true; 3512 } 3513 3514 3515 /* 3516 * Second pass: flush the pipes that are having their allocation 3517 * reduced, but overlapping with a previous allocation. 3518 * 3519 * Here as well we need to wait for the vblank to make sure the freed 3520 * space is not used anymore. 3521 */ 3522 for_each_intel_crtc(dev, crtc) { 3523 if (!crtc->active) 3524 continue; 3525 3526 pipe = crtc->pipe; 3527 3528 if (reallocated[pipe]) 3529 continue; 3530 3531 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3532 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3533 skl_wm_flush_pipe(dev_priv, pipe, 2); 3534 intel_wait_for_vblank(dev, pipe); 3535 reallocated[pipe] = true; 3536 } 3537 } 3538 3539 /* 3540 * Third pass: flush the pipes that got more space allocated. 3541 * 3542 * We don't need to actively wait for the update here, next vblank 3543 * will just get more DDB space with the correct WM values. 3544 */ 3545 for_each_intel_crtc(dev, crtc) { 3546 if (!crtc->active) 3547 continue; 3548 3549 pipe = crtc->pipe; 3550 3551 /* 3552 * At this point, only the pipes more space than before are 3553 * left to re-allocate. 3554 */ 3555 if (reallocated[pipe]) 3556 continue; 3557 3558 skl_wm_flush_pipe(dev_priv, pipe, 3); 3559 } 3560 } 3561 3562 static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3563 struct skl_pipe_wm_parameters *params, 3564 struct intel_wm_config *config, 3565 struct skl_ddb_allocation *ddb, /* out */ 3566 struct skl_pipe_wm *pipe_wm /* out */) 3567 { 3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3569 3570 skl_compute_wm_pipe_parameters(crtc, params); 3571 skl_allocate_pipe_ddb(crtc, config, params, ddb); 3572 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); 3573 3574 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) 3575 return false; 3576 3577 intel_crtc->wm.skl_active = *pipe_wm; 3578 3579 return true; 3580 } 3581 3582 static void skl_update_other_pipe_wm(struct drm_device *dev, 3583 struct drm_crtc *crtc, 3584 struct intel_wm_config *config, 3585 struct skl_wm_values *r) 3586 { 3587 struct intel_crtc *intel_crtc; 3588 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3589 3590 /* 3591 * If the WM update hasn't changed the allocation for this_crtc (the 3592 * crtc we are currently computing the new WM values for), other 3593 * enabled crtcs will keep the same allocation and we don't need to 3594 * recompute anything for them. 3595 */ 3596 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3597 return; 3598 3599 /* 3600 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3601 * other active pipes need new DDB allocation and WM values. 3602 */ 3603 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 3604 base.head) { 3605 struct skl_pipe_wm_parameters params = {}; 3606 struct skl_pipe_wm pipe_wm = {}; 3607 bool wm_changed; 3608 3609 if (this_crtc->pipe == intel_crtc->pipe) 3610 continue; 3611 3612 if (!intel_crtc->active) 3613 continue; 3614 3615 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3616 ¶ms, config, 3617 &r->ddb, &pipe_wm); 3618 3619 /* 3620 * If we end up re-computing the other pipe WM values, it's 3621 * because it was really needed, so we expect the WM values to 3622 * be different. 3623 */ 3624 WARN_ON(!wm_changed); 3625 3626 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); 3627 r->dirty[intel_crtc->pipe] = true; 3628 } 3629 } 3630 3631 static void skl_clear_wm(struct skl_wm_values *watermarks, enum i915_pipe pipe) 3632 { 3633 watermarks->wm_linetime[pipe] = 0; 3634 memset(watermarks->plane[pipe], 0, 3635 sizeof(uint32_t) * 8 * I915_MAX_PLANES); 3636 memset(watermarks->plane_trans[pipe], 3637 0, sizeof(uint32_t) * I915_MAX_PLANES); 3638 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; 3639 3640 /* Clear ddb entries for pipe */ 3641 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); 3642 memset(&watermarks->ddb.plane[pipe], 0, 3643 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3644 memset(&watermarks->ddb.y_plane[pipe], 0, 3645 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3646 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, 3647 sizeof(struct skl_ddb_entry)); 3648 3649 } 3650 3651 static void skl_update_wm(struct drm_crtc *crtc) 3652 { 3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3654 struct drm_device *dev = crtc->dev; 3655 struct drm_i915_private *dev_priv = dev->dev_private; 3656 struct skl_pipe_wm_parameters params = {}; 3657 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3658 struct skl_pipe_wm pipe_wm = {}; 3659 struct intel_wm_config config = {}; 3660 3661 3662 /* Clear all dirty flags */ 3663 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); 3664 3665 skl_clear_wm(results, intel_crtc->pipe); 3666 3667 skl_compute_wm_global_parameters(dev, &config); 3668 3669 if (!skl_update_pipe_wm(crtc, ¶ms, &config, 3670 &results->ddb, &pipe_wm)) 3671 return; 3672 3673 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); 3674 results->dirty[intel_crtc->pipe] = true; 3675 3676 skl_update_other_pipe_wm(dev, crtc, &config, results); 3677 skl_write_wm_values(dev_priv, results); 3678 skl_flush_wm_values(dev_priv, results); 3679 3680 /* store the new configuration */ 3681 dev_priv->wm.skl_hw = *results; 3682 } 3683 3684 static void 3685 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, 3686 uint32_t sprite_width, uint32_t sprite_height, 3687 int pixel_size, bool enabled, bool scaled) 3688 { 3689 struct intel_plane *intel_plane = to_intel_plane(plane); 3690 struct drm_framebuffer *fb = plane->state->fb; 3691 3692 intel_plane->wm.enabled = enabled; 3693 intel_plane->wm.scaled = scaled; 3694 intel_plane->wm.horiz_pixels = sprite_width; 3695 intel_plane->wm.vert_pixels = sprite_height; 3696 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; 3697 3698 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ 3699 intel_plane->wm.bytes_per_pixel = 3700 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3701 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; 3702 intel_plane->wm.y_bytes_per_pixel = 3703 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3704 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; 3705 3706 /* 3707 * Framebuffer can be NULL on plane disable, but it does not 3708 * matter for watermarks if we assume no tiling in that case. 3709 */ 3710 if (fb) 3711 intel_plane->wm.tiling = fb->modifier[0]; 3712 intel_plane->wm.rotation = plane->state->rotation; 3713 3714 skl_update_wm(crtc); 3715 } 3716 3717 static void ilk_update_wm(struct drm_crtc *crtc) 3718 { 3719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3720 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3721 struct drm_device *dev = crtc->dev; 3722 struct drm_i915_private *dev_priv = dev->dev_private; 3723 struct ilk_wm_maximums max; 3724 static const struct ilk_wm_values zero_values; 3725 struct ilk_wm_values results = zero_values; 3726 enum intel_ddb_partitioning partitioning; 3727 static const struct intel_pipe_wm zero_wm; 3728 struct intel_pipe_wm pipe_wm = zero_wm; 3729 struct intel_pipe_wm lp_wm_1_2 = zero_wm, lp_wm_5_6 = zero_wm, 3730 *best_lp_wm; 3731 static const struct intel_wm_config zero_config; 3732 struct intel_wm_config config = zero_config; 3733 3734 WARN_ON(cstate->base.active != intel_crtc->active); 3735 3736 intel_compute_pipe_wm(cstate, &pipe_wm); 3737 3738 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 3739 return; 3740 3741 intel_crtc->wm.active = pipe_wm; 3742 3743 ilk_compute_wm_config(dev, &config); 3744 3745 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3746 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3747 3748 /* 5/6 split only in single pipe config on IVB+ */ 3749 if (INTEL_INFO(dev)->gen >= 7 && 3750 config.num_pipes_active == 1 && config.sprites_enabled) { 3751 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3752 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3753 3754 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3755 } else { 3756 best_lp_wm = &lp_wm_1_2; 3757 } 3758 3759 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3760 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3761 3762 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3763 3764 ilk_write_wm_values(dev_priv, &results); 3765 } 3766 3767 static void 3768 ilk_update_sprite_wm(struct drm_plane *plane, 3769 struct drm_crtc *crtc, 3770 uint32_t sprite_width, uint32_t sprite_height, 3771 int pixel_size, bool enabled, bool scaled) 3772 { 3773 struct drm_device *dev = plane->dev; 3774 struct intel_plane *intel_plane = to_intel_plane(plane); 3775 3776 /* 3777 * IVB workaround: must disable low power watermarks for at least 3778 * one frame before enabling scaling. LP watermarks can be re-enabled 3779 * when scaling is disabled. 3780 * 3781 * WaCxSRDisabledForSpriteScaling:ivb 3782 */ 3783 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 3784 intel_wait_for_vblank(dev, intel_plane->pipe); 3785 3786 ilk_update_wm(crtc); 3787 } 3788 3789 static void skl_pipe_wm_active_state(uint32_t val, 3790 struct skl_pipe_wm *active, 3791 bool is_transwm, 3792 bool is_cursor, 3793 int i, 3794 int level) 3795 { 3796 bool is_enabled = (val & PLANE_WM_EN) != 0; 3797 3798 if (!is_transwm) { 3799 if (!is_cursor) { 3800 active->wm[level].plane_en[i] = is_enabled; 3801 active->wm[level].plane_res_b[i] = 3802 val & PLANE_WM_BLOCKS_MASK; 3803 active->wm[level].plane_res_l[i] = 3804 (val >> PLANE_WM_LINES_SHIFT) & 3805 PLANE_WM_LINES_MASK; 3806 } else { 3807 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; 3808 active->wm[level].plane_res_b[PLANE_CURSOR] = 3809 val & PLANE_WM_BLOCKS_MASK; 3810 active->wm[level].plane_res_l[PLANE_CURSOR] = 3811 (val >> PLANE_WM_LINES_SHIFT) & 3812 PLANE_WM_LINES_MASK; 3813 } 3814 } else { 3815 if (!is_cursor) { 3816 active->trans_wm.plane_en[i] = is_enabled; 3817 active->trans_wm.plane_res_b[i] = 3818 val & PLANE_WM_BLOCKS_MASK; 3819 active->trans_wm.plane_res_l[i] = 3820 (val >> PLANE_WM_LINES_SHIFT) & 3821 PLANE_WM_LINES_MASK; 3822 } else { 3823 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; 3824 active->trans_wm.plane_res_b[PLANE_CURSOR] = 3825 val & PLANE_WM_BLOCKS_MASK; 3826 active->trans_wm.plane_res_l[PLANE_CURSOR] = 3827 (val >> PLANE_WM_LINES_SHIFT) & 3828 PLANE_WM_LINES_MASK; 3829 } 3830 } 3831 } 3832 3833 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3834 { 3835 struct drm_device *dev = crtc->dev; 3836 struct drm_i915_private *dev_priv = dev->dev_private; 3837 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3839 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; 3840 enum i915_pipe pipe = intel_crtc->pipe; 3841 int level, i, max_level; 3842 uint32_t temp; 3843 3844 max_level = ilk_wm_max_level(dev); 3845 3846 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3847 3848 for (level = 0; level <= max_level; level++) { 3849 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3850 hw->plane[pipe][i][level] = 3851 I915_READ(PLANE_WM(pipe, i, level)); 3852 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); 3853 } 3854 3855 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3856 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3857 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); 3858 3859 if (!intel_crtc->active) 3860 return; 3861 3862 hw->dirty[pipe] = true; 3863 3864 active->linetime = hw->wm_linetime[pipe]; 3865 3866 for (level = 0; level <= max_level; level++) { 3867 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3868 temp = hw->plane[pipe][i][level]; 3869 skl_pipe_wm_active_state(temp, active, false, 3870 false, i, level); 3871 } 3872 temp = hw->plane[pipe][PLANE_CURSOR][level]; 3873 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3874 } 3875 3876 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3877 temp = hw->plane_trans[pipe][i]; 3878 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3879 } 3880 3881 temp = hw->plane_trans[pipe][PLANE_CURSOR]; 3882 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3883 } 3884 3885 void skl_wm_get_hw_state(struct drm_device *dev) 3886 { 3887 struct drm_i915_private *dev_priv = dev->dev_private; 3888 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3889 struct drm_crtc *crtc; 3890 3891 skl_ddb_get_hw_state(dev_priv, ddb); 3892 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3893 skl_pipe_wm_get_hw_state(crtc); 3894 } 3895 3896 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3897 { 3898 struct drm_device *dev = crtc->dev; 3899 struct drm_i915_private *dev_priv = dev->dev_private; 3900 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3902 struct intel_pipe_wm *active = &intel_crtc->wm.active; 3903 enum i915_pipe pipe = intel_crtc->pipe; 3904 static const unsigned int wm0_pipe_reg[] = { 3905 [PIPE_A] = WM0_PIPEA_ILK, 3906 [PIPE_B] = WM0_PIPEB_ILK, 3907 [PIPE_C] = WM0_PIPEC_IVB, 3908 }; 3909 3910 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3911 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3912 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3913 3914 memset(active, 0, sizeof(*active)); 3915 3916 active->pipe_enabled = intel_crtc->active; 3917 3918 if (active->pipe_enabled) { 3919 u32 tmp = hw->wm_pipe[pipe]; 3920 3921 /* 3922 * For active pipes LP0 watermark is marked as 3923 * enabled, and LP1+ watermaks as disabled since 3924 * we can't really reverse compute them in case 3925 * multiple pipes are active. 3926 */ 3927 active->wm[0].enable = true; 3928 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3929 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3930 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3931 active->linetime = hw->wm_linetime[pipe]; 3932 } else { 3933 int level, max_level = ilk_wm_max_level(dev); 3934 3935 /* 3936 * For inactive pipes, all watermark levels 3937 * should be marked as enabled but zeroed, 3938 * which is what we'd compute them to. 3939 */ 3940 for (level = 0; level <= max_level; level++) 3941 active->wm[level].enable = true; 3942 } 3943 } 3944 3945 #define _FW_WM(value, plane) \ 3946 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3947 #define _FW_WM_VLV(value, plane) \ 3948 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3949 3950 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3951 struct vlv_wm_values *wm) 3952 { 3953 enum i915_pipe pipe; 3954 uint32_t tmp; 3955 3956 for_each_pipe(dev_priv, pipe) { 3957 tmp = I915_READ(VLV_DDL(pipe)); 3958 3959 wm->ddl[pipe].primary = 3960 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3961 wm->ddl[pipe].cursor = 3962 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3963 wm->ddl[pipe].sprite[0] = 3964 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3965 wm->ddl[pipe].sprite[1] = 3966 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3967 } 3968 3969 tmp = I915_READ(DSPFW1); 3970 wm->sr.plane = _FW_WM(tmp, SR); 3971 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3972 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3973 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3974 3975 tmp = I915_READ(DSPFW2); 3976 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3977 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3978 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3979 3980 tmp = I915_READ(DSPFW3); 3981 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 3982 3983 if (IS_CHERRYVIEW(dev_priv)) { 3984 tmp = I915_READ(DSPFW7_CHV); 3985 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3986 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3987 3988 tmp = I915_READ(DSPFW8_CHV); 3989 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 3990 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 3991 3992 tmp = I915_READ(DSPFW9_CHV); 3993 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 3994 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 3995 3996 tmp = I915_READ(DSPHOWM); 3997 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3998 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 3999 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 4000 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 4001 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4002 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4003 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4004 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4005 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4006 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4007 } else { 4008 tmp = I915_READ(DSPFW7); 4009 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 4010 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 4011 4012 tmp = I915_READ(DSPHOWM); 4013 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 4014 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4015 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4016 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4017 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4018 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4019 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4020 } 4021 } 4022 4023 #undef _FW_WM 4024 #undef _FW_WM_VLV 4025 4026 void vlv_wm_get_hw_state(struct drm_device *dev) 4027 { 4028 struct drm_i915_private *dev_priv = to_i915(dev); 4029 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 4030 struct intel_plane *plane; 4031 enum i915_pipe pipe; 4032 u32 val; 4033 4034 vlv_read_wm_values(dev_priv, wm); 4035 4036 for_each_intel_plane(dev, plane) { 4037 switch (plane->base.type) { 4038 int sprite; 4039 case DRM_PLANE_TYPE_CURSOR: 4040 plane->wm.fifo_size = 63; 4041 break; 4042 case DRM_PLANE_TYPE_PRIMARY: 4043 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 4044 break; 4045 case DRM_PLANE_TYPE_OVERLAY: 4046 sprite = plane->plane; 4047 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 4048 break; 4049 } 4050 } 4051 4052 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 4053 wm->level = VLV_WM_LEVEL_PM2; 4054 4055 if (IS_CHERRYVIEW(dev_priv)) { 4056 mutex_lock(&dev_priv->rps.hw_lock); 4057 4058 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 4059 if (val & DSP_MAXFIFO_PM5_ENABLE) 4060 wm->level = VLV_WM_LEVEL_PM5; 4061 4062 /* 4063 * If DDR DVFS is disabled in the BIOS, Punit 4064 * will never ack the request. So if that happens 4065 * assume we don't have to enable/disable DDR DVFS 4066 * dynamically. To test that just set the REQ_ACK 4067 * bit to poke the Punit, but don't change the 4068 * HIGH/LOW bits so that we don't actually change 4069 * the current state. 4070 */ 4071 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4072 val |= FORCE_DDR_FREQ_REQ_ACK; 4073 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4074 4075 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4076 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4077 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4078 "assuming DDR DVFS is disabled\n"); 4079 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4080 } else { 4081 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4082 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4083 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4084 } 4085 4086 mutex_unlock(&dev_priv->rps.hw_lock); 4087 } 4088 4089 for_each_pipe(dev_priv, pipe) 4090 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4091 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4092 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4093 4094 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4095 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4096 } 4097 4098 void ilk_wm_get_hw_state(struct drm_device *dev) 4099 { 4100 struct drm_i915_private *dev_priv = dev->dev_private; 4101 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4102 struct drm_crtc *crtc; 4103 4104 for_each_crtc(dev, crtc) 4105 ilk_pipe_wm_get_hw_state(crtc); 4106 4107 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4108 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4109 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4110 4111 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4112 if (INTEL_INFO(dev)->gen >= 7) { 4113 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4114 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4115 } 4116 4117 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4118 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4119 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4120 else if (IS_IVYBRIDGE(dev)) 4121 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4122 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4123 4124 hw->enable_fbc_wm = 4125 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4126 } 4127 4128 /** 4129 * intel_update_watermarks - update FIFO watermark values based on current modes 4130 * 4131 * Calculate watermark values for the various WM regs based on current mode 4132 * and plane configuration. 4133 * 4134 * There are several cases to deal with here: 4135 * - normal (i.e. non-self-refresh) 4136 * - self-refresh (SR) mode 4137 * - lines are large relative to FIFO size (buffer can hold up to 2) 4138 * - lines are small relative to FIFO size (buffer can hold more than 2 4139 * lines), so need to account for TLB latency 4140 * 4141 * The normal calculation is: 4142 * watermark = dotclock * bytes per pixel * latency 4143 * where latency is platform & configuration dependent (we assume pessimal 4144 * values here). 4145 * 4146 * The SR calculation is: 4147 * watermark = (trunc(latency/line time)+1) * surface width * 4148 * bytes per pixel 4149 * where 4150 * line time = htotal / dotclock 4151 * surface width = hdisplay for normal plane and 64 for cursor 4152 * and latency is assumed to be high, as above. 4153 * 4154 * The final value programmed to the register should always be rounded up, 4155 * and include an extra 2 entries to account for clock crossings. 4156 * 4157 * We don't use the sprite, so we can ignore that. And on Crestline we have 4158 * to set the non-SR watermarks to 8. 4159 */ 4160 void intel_update_watermarks(struct drm_crtc *crtc) 4161 { 4162 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4163 4164 if (dev_priv->display.update_wm) 4165 dev_priv->display.update_wm(crtc); 4166 } 4167 4168 void intel_update_sprite_watermarks(struct drm_plane *plane, 4169 struct drm_crtc *crtc, 4170 uint32_t sprite_width, 4171 uint32_t sprite_height, 4172 int pixel_size, 4173 bool enabled, bool scaled) 4174 { 4175 struct drm_i915_private *dev_priv = plane->dev->dev_private; 4176 4177 if (dev_priv->display.update_sprite_wm) 4178 dev_priv->display.update_sprite_wm(plane, crtc, 4179 sprite_width, sprite_height, 4180 pixel_size, enabled, scaled); 4181 } 4182 4183 /** 4184 * Lock protecting IPS related data structures 4185 */ 4186 #ifdef __NetBSD__ 4187 spinlock_t mchdev_lock; 4188 #else 4189 DEFINE_SPINLOCK(mchdev_lock); 4190 #endif 4191 4192 /* Global for IPS driver to get at the current i915 device. Protected by 4193 * mchdev_lock. */ 4194 static struct drm_i915_private *i915_mch_dev; 4195 4196 bool ironlake_set_drps(struct drm_device *dev, u8 val) 4197 { 4198 struct drm_i915_private *dev_priv = dev->dev_private; 4199 u16 rgvswctl; 4200 4201 assert_spin_locked(&mchdev_lock); 4202 4203 rgvswctl = I915_READ16(MEMSWCTL); 4204 if (rgvswctl & MEMCTL_CMD_STS) { 4205 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4206 return false; /* still busy with another command */ 4207 } 4208 4209 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4210 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4211 I915_WRITE16(MEMSWCTL, rgvswctl); 4212 POSTING_READ16(MEMSWCTL); 4213 4214 rgvswctl |= MEMCTL_CMD_STS; 4215 I915_WRITE16(MEMSWCTL, rgvswctl); 4216 4217 return true; 4218 } 4219 4220 static void ironlake_enable_drps(struct drm_device *dev) 4221 { 4222 struct drm_i915_private *dev_priv = dev->dev_private; 4223 u32 rgvmodectl = I915_READ(MEMMODECTL); 4224 u8 fmax, fmin, fstart, vstart; 4225 4226 spin_lock_irq(&mchdev_lock); 4227 4228 /* Enable temp reporting */ 4229 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4230 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4231 4232 /* 100ms RC evaluation intervals */ 4233 I915_WRITE(RCUPEI, 100000); 4234 I915_WRITE(RCDNEI, 100000); 4235 4236 /* Set max/min thresholds to 90ms and 80ms respectively */ 4237 I915_WRITE(RCBMAXAVG, 90000); 4238 I915_WRITE(RCBMINAVG, 80000); 4239 4240 I915_WRITE(MEMIHYST, 1); 4241 4242 /* Set up min, max, and cur for interrupt handling */ 4243 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4244 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4245 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4246 MEMMODE_FSTART_SHIFT; 4247 4248 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> 4249 PXVFREQ_PX_SHIFT; 4250 4251 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4252 dev_priv->ips.fstart = fstart; 4253 4254 dev_priv->ips.max_delay = fstart; 4255 dev_priv->ips.min_delay = fmin; 4256 dev_priv->ips.cur_delay = fstart; 4257 4258 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4259 fmax, fmin, fstart); 4260 4261 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4262 4263 /* 4264 * Interrupts will be enabled in ironlake_irq_postinstall 4265 */ 4266 4267 I915_WRITE(VIDSTART, vstart); 4268 POSTING_READ(VIDSTART); 4269 4270 rgvmodectl |= MEMMODE_SWMODE_EN; 4271 I915_WRITE(MEMMODECTL, rgvmodectl); 4272 4273 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4274 DRM_ERROR("stuck trying to change perf mode\n"); 4275 mdelay(1); 4276 4277 ironlake_set_drps(dev, fstart); 4278 4279 dev_priv->ips.last_count1 = I915_READ(DMIEC) + 4280 I915_READ(DDREC) + I915_READ(CSIEC); 4281 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4282 dev_priv->ips.last_count2 = I915_READ(GFXEC); 4283 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4284 4285 spin_unlock_irq(&mchdev_lock); 4286 } 4287 4288 static void ironlake_disable_drps(struct drm_device *dev) 4289 { 4290 struct drm_i915_private *dev_priv = dev->dev_private; 4291 u16 rgvswctl; 4292 4293 spin_lock_irq(&mchdev_lock); 4294 4295 rgvswctl = I915_READ16(MEMSWCTL); 4296 4297 /* Ack interrupts, disable EFC interrupt */ 4298 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4299 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4300 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4301 I915_WRITE(DEIIR, DE_PCU_EVENT); 4302 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4303 4304 /* Go back to the starting frequency */ 4305 ironlake_set_drps(dev, dev_priv->ips.fstart); 4306 mdelay(1); 4307 rgvswctl |= MEMCTL_CMD_STS; 4308 I915_WRITE(MEMSWCTL, rgvswctl); 4309 mdelay(1); 4310 4311 spin_unlock_irq(&mchdev_lock); 4312 } 4313 4314 /* There's a funny hw issue where the hw returns all 0 when reading from 4315 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4316 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4317 * all limits and the gpu stuck at whatever frequency it is at atm). 4318 */ 4319 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4320 { 4321 u32 limits; 4322 4323 /* Only set the down limit when we've reached the lowest level to avoid 4324 * getting more interrupts, otherwise leave this clear. This prevents a 4325 * race in the hw when coming out of rc6: There's a tiny window where 4326 * the hw runs at the minimal clock before selecting the desired 4327 * frequency, if the down threshold expires in that window we will not 4328 * receive a down interrupt. */ 4329 if (IS_GEN9(dev_priv->dev)) { 4330 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4331 if (val <= dev_priv->rps.min_freq_softlimit) 4332 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4333 } else { 4334 limits = dev_priv->rps.max_freq_softlimit << 24; 4335 if (val <= dev_priv->rps.min_freq_softlimit) 4336 limits |= dev_priv->rps.min_freq_softlimit << 16; 4337 } 4338 4339 return limits; 4340 } 4341 4342 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4343 { 4344 int new_power; 4345 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4346 u32 ei_up = 0, ei_down = 0; 4347 4348 new_power = dev_priv->rps.power; 4349 switch (dev_priv->rps.power) { 4350 case LOW_POWER: 4351 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4352 new_power = BETWEEN; 4353 break; 4354 4355 case BETWEEN: 4356 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4357 new_power = LOW_POWER; 4358 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4359 new_power = HIGH_POWER; 4360 break; 4361 4362 case HIGH_POWER: 4363 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4364 new_power = BETWEEN; 4365 break; 4366 } 4367 /* Max/min bins are special */ 4368 if (val <= dev_priv->rps.min_freq_softlimit) 4369 new_power = LOW_POWER; 4370 if (val >= dev_priv->rps.max_freq_softlimit) 4371 new_power = HIGH_POWER; 4372 if (new_power == dev_priv->rps.power) 4373 return; 4374 4375 /* Note the units here are not exactly 1us, but 1280ns. */ 4376 switch (new_power) { 4377 case LOW_POWER: 4378 /* Upclock if more than 95% busy over 16ms */ 4379 ei_up = 16000; 4380 threshold_up = 95; 4381 4382 /* Downclock if less than 85% busy over 32ms */ 4383 ei_down = 32000; 4384 threshold_down = 85; 4385 break; 4386 4387 case BETWEEN: 4388 /* Upclock if more than 90% busy over 13ms */ 4389 ei_up = 13000; 4390 threshold_up = 90; 4391 4392 /* Downclock if less than 75% busy over 32ms */ 4393 ei_down = 32000; 4394 threshold_down = 75; 4395 break; 4396 4397 case HIGH_POWER: 4398 /* Upclock if more than 85% busy over 10ms */ 4399 ei_up = 10000; 4400 threshold_up = 85; 4401 4402 /* Downclock if less than 60% busy over 32ms */ 4403 ei_down = 32000; 4404 threshold_down = 60; 4405 break; 4406 } 4407 4408 /* When byt can survive without system hang with dynamic 4409 * sw freq adjustments, this restriction can be lifted. 4410 */ 4411 if (IS_VALLEYVIEW(dev_priv)) 4412 goto skip_hw_write; 4413 4414 I915_WRITE(GEN6_RP_UP_EI, 4415 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4416 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4417 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4418 4419 I915_WRITE(GEN6_RP_DOWN_EI, 4420 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4421 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4422 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4423 4424 I915_WRITE(GEN6_RP_CONTROL, 4425 GEN6_RP_MEDIA_TURBO | 4426 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4427 GEN6_RP_MEDIA_IS_GFX | 4428 GEN6_RP_ENABLE | 4429 GEN6_RP_UP_BUSY_AVG | 4430 GEN6_RP_DOWN_IDLE_AVG); 4431 4432 skip_hw_write: 4433 dev_priv->rps.power = new_power; 4434 dev_priv->rps.up_threshold = threshold_up; 4435 dev_priv->rps.down_threshold = threshold_down; 4436 dev_priv->rps.last_adj = 0; 4437 } 4438 4439 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4440 { 4441 u32 mask = 0; 4442 4443 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ 4444 if (val > dev_priv->rps.min_freq_softlimit) 4445 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4446 if (val < dev_priv->rps.max_freq_softlimit) 4447 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4448 4449 mask &= dev_priv->pm_rps_events; 4450 4451 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4452 } 4453 4454 /* gen6_set_rps is called to update the frequency request, but should also be 4455 * called when the range (min_delay and max_delay) is modified so that we can 4456 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4457 static void gen6_set_rps(struct drm_device *dev, u8 val) 4458 { 4459 struct drm_i915_private *dev_priv = dev->dev_private; 4460 4461 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4462 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) 4463 return; 4464 4465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4466 WARN_ON(val > dev_priv->rps.max_freq); 4467 WARN_ON(val < dev_priv->rps.min_freq); 4468 4469 /* min/max delay may still have been modified so be sure to 4470 * write the limits value. 4471 */ 4472 if (val != dev_priv->rps.cur_freq) { 4473 gen6_set_rps_thresholds(dev_priv, val); 4474 4475 if (IS_GEN9(dev)) 4476 I915_WRITE(GEN6_RPNSWREQ, 4477 GEN9_FREQUENCY(val)); 4478 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4479 I915_WRITE(GEN6_RPNSWREQ, 4480 HSW_FREQUENCY(val)); 4481 else 4482 I915_WRITE(GEN6_RPNSWREQ, 4483 GEN6_FREQUENCY(val) | 4484 GEN6_OFFSET(0) | 4485 GEN6_AGGRESSIVE_TURBO); 4486 } 4487 4488 /* Make sure we continue to get interrupts 4489 * until we hit the minimum or maximum frequencies. 4490 */ 4491 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4492 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4493 4494 POSTING_READ(GEN6_RPNSWREQ); 4495 4496 dev_priv->rps.cur_freq = val; 4497 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4498 } 4499 4500 static void valleyview_set_rps(struct drm_device *dev, u8 val) 4501 { 4502 struct drm_i915_private *dev_priv = dev->dev_private; 4503 4504 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4505 WARN_ON(val > dev_priv->rps.max_freq); 4506 WARN_ON(val < dev_priv->rps.min_freq); 4507 4508 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4509 "Odd GPU freq value\n")) 4510 val &= ~1; 4511 4512 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4513 4514 if (val != dev_priv->rps.cur_freq) { 4515 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4516 if (!IS_CHERRYVIEW(dev_priv)) 4517 gen6_set_rps_thresholds(dev_priv, val); 4518 } 4519 4520 dev_priv->rps.cur_freq = val; 4521 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4522 } 4523 4524 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4525 * 4526 * * If Gfx is Idle, then 4527 * 1. Forcewake Media well. 4528 * 2. Request idle freq. 4529 * 3. Release Forcewake of Media well. 4530 */ 4531 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4532 { 4533 u32 val = dev_priv->rps.idle_freq; 4534 4535 if (dev_priv->rps.cur_freq <= val) 4536 return; 4537 4538 /* Wake up the media well, as that takes a lot less 4539 * power than the Render well. */ 4540 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4541 valleyview_set_rps(dev_priv->dev, val); 4542 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4543 } 4544 4545 void gen6_rps_busy(struct drm_i915_private *dev_priv) 4546 { 4547 mutex_lock(&dev_priv->rps.hw_lock); 4548 if (dev_priv->rps.enabled) { 4549 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) 4550 gen6_rps_reset_ei(dev_priv); 4551 I915_WRITE(GEN6_PMINTRMSK, 4552 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4553 } 4554 mutex_unlock(&dev_priv->rps.hw_lock); 4555 } 4556 4557 void gen6_rps_idle(struct drm_i915_private *dev_priv) 4558 { 4559 struct drm_device *dev = dev_priv->dev; 4560 4561 mutex_lock(&dev_priv->rps.hw_lock); 4562 if (dev_priv->rps.enabled) { 4563 if (IS_VALLEYVIEW(dev)) 4564 vlv_set_rps_idle(dev_priv); 4565 else 4566 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4567 dev_priv->rps.last_adj = 0; 4568 I915_WRITE(GEN6_PMINTRMSK, 4569 gen6_sanitize_rps_pm_mask(dev_priv, ~0)); 4570 } 4571 mutex_unlock(&dev_priv->rps.hw_lock); 4572 4573 spin_lock(&dev_priv->rps.client_lock); 4574 while (!list_empty(&dev_priv->rps.clients)) 4575 list_del_init(dev_priv->rps.clients.next); 4576 spin_unlock(&dev_priv->rps.client_lock); 4577 } 4578 4579 void gen6_rps_boost(struct drm_i915_private *dev_priv, 4580 struct intel_rps_client *rps, 4581 unsigned long submitted) 4582 { 4583 /* This is intentionally racy! We peek at the state here, then 4584 * validate inside the RPS worker. 4585 */ 4586 if (!(dev_priv->mm.busy && 4587 dev_priv->rps.enabled && 4588 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4589 return; 4590 4591 /* Force a RPS boost (and don't count it against the client) if 4592 * the GPU is severely congested. 4593 */ 4594 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4595 rps = NULL; 4596 4597 spin_lock(&dev_priv->rps.client_lock); 4598 if (rps == NULL || list_empty(&rps->link)) { 4599 spin_lock_irq(&dev_priv->irq_lock); 4600 if (dev_priv->rps.interrupts_enabled) { 4601 dev_priv->rps.client_boost = true; 4602 queue_work(dev_priv->wq, &dev_priv->rps.work); 4603 } 4604 spin_unlock_irq(&dev_priv->irq_lock); 4605 4606 if (rps != NULL) { 4607 list_add(&rps->link, &dev_priv->rps.clients); 4608 rps->boosts++; 4609 } else 4610 dev_priv->rps.boosts++; 4611 } 4612 spin_unlock(&dev_priv->rps.client_lock); 4613 } 4614 4615 void intel_set_rps(struct drm_device *dev, u8 val) 4616 { 4617 if (IS_VALLEYVIEW(dev)) 4618 valleyview_set_rps(dev, val); 4619 else 4620 gen6_set_rps(dev, val); 4621 } 4622 4623 static void gen9_disable_rc6(struct drm_device *dev) 4624 { 4625 struct drm_i915_private *dev_priv = dev->dev_private; 4626 4627 I915_WRITE(GEN6_RC_CONTROL, 0); 4628 } 4629 4630 static void gen9_disable_rps(struct drm_device *dev) 4631 { 4632 struct drm_i915_private *dev_priv = dev->dev_private; 4633 4634 I915_WRITE(GEN9_PG_ENABLE, 0); 4635 } 4636 4637 static void gen6_disable_rc6(struct drm_device *dev) 4638 { 4639 struct drm_i915_private *dev_priv = dev->dev_private; 4640 4641 I915_WRITE(GEN6_RC_CONTROL, 0); 4642 } 4643 4644 static void gen6_disable_rps(struct drm_device *dev) 4645 { 4646 struct drm_i915_private *dev_priv = dev->dev_private; 4647 4648 I915_WRITE(GEN6_RPNSWREQ, 1UL << 31); 4649 } 4650 4651 static void cherryview_disable_rc6(struct drm_device *dev) 4652 { 4653 struct drm_i915_private *dev_priv = dev->dev_private; 4654 4655 I915_WRITE(GEN6_RC_CONTROL, 0); 4656 } 4657 4658 static void valleyview_disable_rc6(struct drm_device *dev) 4659 { 4660 struct drm_i915_private *dev_priv = dev->dev_private; 4661 4662 /* we're doing forcewake before Disabling RC6, 4663 * This what the BIOS expects when going into suspend */ 4664 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4665 4666 I915_WRITE(GEN6_RC_CONTROL, 0); 4667 4668 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4669 } 4670 4671 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4672 { 4673 if (IS_VALLEYVIEW(dev)) { 4674 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4675 mode = GEN6_RC_CTL_RC6_ENABLE; 4676 else 4677 mode = 0; 4678 } 4679 if (HAS_RC6p(dev)) 4680 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4681 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 4682 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 4683 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 4684 4685 else 4686 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4687 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 4688 } 4689 4690 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4691 { 4692 /* No RC6 before Ironlake and code is gone for ilk. */ 4693 if (INTEL_INFO(dev)->gen < 6) 4694 return 0; 4695 4696 /* Respect the kernel parameter if it is set */ 4697 if (enable_rc6 >= 0) { 4698 int mask; 4699 4700 if (HAS_RC6p(dev)) 4701 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4702 INTEL_RC6pp_ENABLE; 4703 else 4704 mask = INTEL_RC6_ENABLE; 4705 4706 if ((enable_rc6 & mask) != enable_rc6) 4707 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4708 enable_rc6 & mask, enable_rc6, mask); 4709 4710 return enable_rc6 & mask; 4711 } 4712 4713 if (IS_IVYBRIDGE(dev)) 4714 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4715 4716 return INTEL_RC6_ENABLE; 4717 } 4718 4719 int intel_enable_rc6(const struct drm_device *dev) 4720 { 4721 return i915.enable_rc6; 4722 } 4723 4724 static void gen6_init_rps_frequencies(struct drm_device *dev) 4725 { 4726 struct drm_i915_private *dev_priv = dev->dev_private; 4727 uint32_t rp_state_cap; 4728 u32 ddcc_status = 0; 4729 int ret; 4730 4731 /* All of these values are in units of 50MHz */ 4732 dev_priv->rps.cur_freq = 0; 4733 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4734 if (IS_BROXTON(dev)) { 4735 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4736 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4737 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4738 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4739 } else { 4740 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4741 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4742 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4743 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4744 } 4745 4746 /* hw_max = RP0 until we check for overclocking */ 4747 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4748 4749 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4750 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || 4751 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4752 ret = sandybridge_pcode_read(dev_priv, 4753 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4754 &ddcc_status); 4755 if (0 == ret) 4756 dev_priv->rps.efficient_freq = 4757 clamp_t(u8, 4758 ((ddcc_status >> 8) & 0xff), 4759 dev_priv->rps.min_freq, 4760 dev_priv->rps.max_freq); 4761 } 4762 4763 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4764 /* Store the frequency values in 16.66 MHZ units, which is 4765 the natural hardware unit for SKL */ 4766 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4767 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4768 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4769 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4770 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4771 } 4772 4773 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4774 4775 /* Preserve min/max settings in case of re-init */ 4776 if (dev_priv->rps.max_freq_softlimit == 0) 4777 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4778 4779 if (dev_priv->rps.min_freq_softlimit == 0) { 4780 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4781 dev_priv->rps.min_freq_softlimit = 4782 max_t(int, dev_priv->rps.efficient_freq, 4783 intel_freq_opcode(dev_priv, 450)); 4784 else 4785 dev_priv->rps.min_freq_softlimit = 4786 dev_priv->rps.min_freq; 4787 } 4788 } 4789 4790 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4791 static void gen9_enable_rps(struct drm_device *dev) 4792 { 4793 struct drm_i915_private *dev_priv = dev->dev_private; 4794 4795 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4796 4797 gen6_init_rps_frequencies(dev); 4798 4799 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4800 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { 4801 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4802 return; 4803 } 4804 4805 /* Program defaults and thresholds for RPS*/ 4806 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4807 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4808 4809 /* 1 second timeout*/ 4810 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4811 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4812 4813 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4814 4815 /* Leaning on the below call to gen6_set_rps to program/setup the 4816 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4817 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4818 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4819 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4820 4821 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4822 } 4823 4824 static void gen9_enable_rc6(struct drm_device *dev) 4825 { 4826 struct drm_i915_private *dev_priv = dev->dev_private; 4827 struct intel_engine_cs *ring; 4828 uint32_t rc6_mask = 0; 4829 int unused; 4830 4831 /* 1a: Software RC state - RC0 */ 4832 I915_WRITE(GEN6_RC_STATE, 0); 4833 4834 /* 1b: Get forcewake during program sequence. Although the driver 4835 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4836 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4837 4838 /* 2a: Disable RC states. */ 4839 I915_WRITE(GEN6_RC_CONTROL, 0); 4840 4841 /* 2b: Program RC6 thresholds.*/ 4842 4843 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4844 if (IS_SKYLAKE(dev)) 4845 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4846 else 4847 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4848 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4849 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4850 for_each_ring(ring, dev_priv, unused) 4851 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4852 4853 if (HAS_GUC_UCODE(dev)) 4854 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); 4855 4856 I915_WRITE(GEN6_RC_SLEEP, 0); 4857 4858 /* 2c: Program Coarse Power Gating Policies. */ 4859 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4860 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4861 4862 /* 3a: Enable RC6 */ 4863 if (!dev_priv->rps.ctx_corrupted && 4864 intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4865 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4866 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4867 "on" : "off"); 4868 /* WaRsUseTimeoutMode */ 4869 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || 4870 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { 4871 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ 4872 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4873 GEN7_RC_CTL_TO_MODE | 4874 rc6_mask); 4875 } else { 4876 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4877 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4878 GEN6_RC_CTL_EI_MODE(1) | 4879 rc6_mask); 4880 } 4881 4882 /* 4883 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4884 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4885 */ 4886 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || 4887 INTEL_INFO(dev)->gen == 9) 4888 I915_WRITE(GEN9_PG_ENABLE, 0); 4889 else 4890 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4891 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); 4892 4893 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4894 4895 } 4896 4897 static void gen8_enable_rps(struct drm_device *dev) 4898 { 4899 struct drm_i915_private *dev_priv = dev->dev_private; 4900 struct intel_engine_cs *ring; 4901 uint32_t rc6_mask = 0; 4902 int unused; 4903 4904 /* 1a: Software RC state - RC0 */ 4905 I915_WRITE(GEN6_RC_STATE, 0); 4906 4907 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4908 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4909 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4910 4911 /* 2a: Disable RC states. */ 4912 I915_WRITE(GEN6_RC_CONTROL, 0); 4913 4914 /* Initialize rps frequencies */ 4915 gen6_init_rps_frequencies(dev); 4916 4917 /* 2b: Program RC6 thresholds.*/ 4918 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4919 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4920 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4921 for_each_ring(ring, dev_priv, unused) 4922 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4923 I915_WRITE(GEN6_RC_SLEEP, 0); 4924 if (IS_BROADWELL(dev)) 4925 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4926 else 4927 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4928 4929 /* 3: Enable RC6 */ 4930 if (!dev_priv->rps.ctx_corrupted && 4931 intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4932 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4933 intel_print_rc6_info(dev, rc6_mask); 4934 if (IS_BROADWELL(dev)) 4935 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4936 GEN7_RC_CTL_TO_MODE | 4937 rc6_mask); 4938 else 4939 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4940 GEN6_RC_CTL_EI_MODE(1) | 4941 rc6_mask); 4942 4943 /* 4 Program defaults and thresholds for RPS*/ 4944 I915_WRITE(GEN6_RPNSWREQ, 4945 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4946 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4947 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4948 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4949 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4950 4951 /* Docs recommend 900MHz, and 300 MHz respectively */ 4952 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4953 dev_priv->rps.max_freq_softlimit << 24 | 4954 dev_priv->rps.min_freq_softlimit << 16); 4955 4956 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4957 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4958 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4959 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4960 4961 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4962 4963 /* 5: Enable RPS */ 4964 I915_WRITE(GEN6_RP_CONTROL, 4965 GEN6_RP_MEDIA_TURBO | 4966 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4967 GEN6_RP_MEDIA_IS_GFX | 4968 GEN6_RP_ENABLE | 4969 GEN6_RP_UP_BUSY_AVG | 4970 GEN6_RP_DOWN_IDLE_AVG); 4971 4972 /* 6: Ring frequency + overclocking (our driver does this later */ 4973 4974 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4975 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4976 4977 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4978 } 4979 4980 static void gen6_enable_rps(struct drm_device *dev) 4981 { 4982 struct drm_i915_private *dev_priv = dev->dev_private; 4983 struct intel_engine_cs *ring; 4984 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4985 u32 gtfifodbg; 4986 int rc6_mode; 4987 int i, ret; 4988 4989 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4990 4991 /* Here begins a magic sequence of register writes to enable 4992 * auto-downclocking. 4993 * 4994 * Perhaps there might be some value in exposing these to 4995 * userspace... 4996 */ 4997 I915_WRITE(GEN6_RC_STATE, 0); 4998 4999 /* Clear the DBG now so we don't confuse earlier errors */ 5000 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5001 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 5002 I915_WRITE(GTFIFODBG, gtfifodbg); 5003 } 5004 5005 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5006 5007 /* Initialize rps frequencies */ 5008 gen6_init_rps_frequencies(dev); 5009 5010 /* disable the counters and set deterministic thresholds */ 5011 I915_WRITE(GEN6_RC_CONTROL, 0); 5012 5013 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 5014 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 5015 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 5016 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5017 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5018 5019 for_each_ring(ring, dev_priv, i) 5020 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5021 5022 I915_WRITE(GEN6_RC_SLEEP, 0); 5023 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 5024 if (IS_IVYBRIDGE(dev)) 5025 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 5026 else 5027 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 5028 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 5029 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 5030 5031 /* Check if we are enabling RC6 */ 5032 rc6_mode = intel_enable_rc6(dev_priv->dev); 5033 if (rc6_mode & INTEL_RC6_ENABLE) 5034 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 5035 5036 /* We don't use those on Haswell */ 5037 if (!IS_HASWELL(dev)) { 5038 if (rc6_mode & INTEL_RC6p_ENABLE) 5039 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 5040 5041 if (rc6_mode & INTEL_RC6pp_ENABLE) 5042 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 5043 } 5044 5045 intel_print_rc6_info(dev, rc6_mask); 5046 5047 I915_WRITE(GEN6_RC_CONTROL, 5048 rc6_mask | 5049 GEN6_RC_CTL_EI_MODE(1) | 5050 GEN6_RC_CTL_HW_ENABLE); 5051 5052 /* Power down if completely idle for over 50ms */ 5053 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 5054 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5055 5056 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 5057 if (ret) 5058 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5059 5060 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5061 if (!ret && (pcu_mbox & __BIT(31))) { /* OC supported */ 5062 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5063 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5064 (pcu_mbox & 0xff) * 50); 5065 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5066 } 5067 5068 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5069 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5070 5071 rc6vids = 0; 5072 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5073 if (IS_GEN6(dev) && ret) { 5074 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5075 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5076 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5077 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5078 rc6vids &= 0xffff00; 5079 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5080 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5081 if (ret) 5082 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5083 } 5084 5085 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5086 } 5087 5088 static void __gen6_update_ring_freq(struct drm_device *dev) 5089 { 5090 struct drm_i915_private *dev_priv = dev->dev_private; 5091 int min_freq = 15; 5092 unsigned int gpu_freq; 5093 unsigned int max_ia_freq, min_ring_freq; 5094 unsigned int max_gpu_freq, min_gpu_freq; 5095 int scaling_factor = 180; 5096 #ifndef __NetBSD__ 5097 struct cpufreq_policy *policy; 5098 #endif 5099 5100 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5101 5102 #ifdef __NetBSD__ 5103 { 5104 extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */ 5105 max_ia_freq = (tsc_freq / 1000); 5106 } 5107 #else 5108 policy = cpufreq_cpu_get(0); 5109 if (policy) { 5110 max_ia_freq = policy->cpuinfo.max_freq; 5111 cpufreq_cpu_put(policy); 5112 } else { 5113 /* 5114 * Default to measured freq if none found, PCU will ensure we 5115 * don't go over 5116 */ 5117 max_ia_freq = tsc_khz; 5118 } 5119 #endif 5120 5121 /* Convert from kHz to MHz */ 5122 max_ia_freq /= 1000; 5123 5124 min_ring_freq = I915_READ(DCLK) & 0xf; 5125 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5126 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5127 5128 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5129 /* Convert GT frequency to 50 HZ units */ 5130 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5131 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5132 } else { 5133 min_gpu_freq = dev_priv->rps.min_freq; 5134 max_gpu_freq = dev_priv->rps.max_freq; 5135 } 5136 5137 /* 5138 * For each potential GPU frequency, load a ring frequency we'd like 5139 * to use for memory access. We do this by specifying the IA frequency 5140 * the PCU should use as a reference to determine the ring frequency. 5141 */ 5142 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5143 int diff = max_gpu_freq - gpu_freq; 5144 unsigned int ia_freq = 0, ring_freq = 0; 5145 5146 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5147 /* 5148 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5149 * No floor required for ring frequency on SKL. 5150 */ 5151 ring_freq = gpu_freq; 5152 } else if (INTEL_INFO(dev)->gen >= 8) { 5153 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5154 ring_freq = max(min_ring_freq, gpu_freq); 5155 } else if (IS_HASWELL(dev)) { 5156 ring_freq = mult_frac(gpu_freq, 5, 4); 5157 ring_freq = max(min_ring_freq, ring_freq); 5158 /* leave ia_freq as the default, chosen by cpufreq */ 5159 } else { 5160 /* On older processors, there is no separate ring 5161 * clock domain, so in order to boost the bandwidth 5162 * of the ring, we need to upclock the CPU (ia_freq). 5163 * 5164 * For GPU frequencies less than 750MHz, 5165 * just use the lowest ring freq. 5166 */ 5167 if (gpu_freq < min_freq) 5168 ia_freq = 800; 5169 else 5170 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5171 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5172 } 5173 5174 sandybridge_pcode_write(dev_priv, 5175 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5176 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5177 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5178 gpu_freq); 5179 } 5180 } 5181 5182 void gen6_update_ring_freq(struct drm_device *dev) 5183 { 5184 struct drm_i915_private *dev_priv = dev->dev_private; 5185 5186 if (!HAS_CORE_RING_FREQ(dev)) 5187 return; 5188 5189 mutex_lock(&dev_priv->rps.hw_lock); 5190 __gen6_update_ring_freq(dev); 5191 mutex_unlock(&dev_priv->rps.hw_lock); 5192 } 5193 5194 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5195 { 5196 struct drm_device *dev = dev_priv->dev; 5197 u32 val, rp0; 5198 5199 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5200 5201 switch (INTEL_INFO(dev)->eu_total) { 5202 case 8: 5203 /* (2 * 4) config */ 5204 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5205 break; 5206 case 12: 5207 /* (2 * 6) config */ 5208 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5209 break; 5210 case 16: 5211 /* (2 * 8) config */ 5212 default: 5213 /* Setting (2 * 8) Min RP0 for any other combination */ 5214 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5215 break; 5216 } 5217 5218 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5219 5220 return rp0; 5221 } 5222 5223 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5224 { 5225 u32 val, rpe; 5226 5227 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5228 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5229 5230 return rpe; 5231 } 5232 5233 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5234 { 5235 u32 val, rp1; 5236 5237 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5238 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5239 5240 return rp1; 5241 } 5242 5243 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5244 { 5245 u32 val, rp1; 5246 5247 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5248 5249 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5250 5251 return rp1; 5252 } 5253 5254 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5255 { 5256 u32 val, rp0; 5257 5258 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5259 5260 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5261 /* Clamp to max */ 5262 rp0 = min_t(u32, rp0, 0xea); 5263 5264 return rp0; 5265 } 5266 5267 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5268 { 5269 u32 val, rpe; 5270 5271 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5272 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5273 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5274 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5275 5276 return rpe; 5277 } 5278 5279 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5280 { 5281 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5282 } 5283 5284 /* Check that the pctx buffer wasn't move under us. */ 5285 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5286 { 5287 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5288 5289 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5290 dev_priv->vlv_pctx->stolen->start); 5291 } 5292 5293 5294 /* Check that the pcbr address is not empty. */ 5295 static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5296 { 5297 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5298 5299 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5300 } 5301 5302 static void cherryview_setup_pctx(struct drm_device *dev) 5303 { 5304 struct drm_i915_private *dev_priv = dev->dev_private; 5305 unsigned long pctx_paddr, paddr; 5306 struct i915_gtt *gtt = &dev_priv->gtt; 5307 u32 pcbr; 5308 int pctx_size = 32*1024; 5309 5310 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5311 5312 pcbr = I915_READ(VLV_PCBR); 5313 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5314 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5315 paddr = (dev_priv->mm.stolen_base + 5316 (gtt->stolen_size - pctx_size)); 5317 5318 pctx_paddr = (paddr & (~4095)); 5319 I915_WRITE(VLV_PCBR, pctx_paddr); 5320 } 5321 5322 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5323 } 5324 5325 static void valleyview_setup_pctx(struct drm_device *dev) 5326 { 5327 struct drm_i915_private *dev_priv = dev->dev_private; 5328 struct drm_i915_gem_object *pctx; 5329 unsigned long pctx_paddr; 5330 u32 pcbr; 5331 int pctx_size = 24*1024; 5332 5333 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5334 5335 pcbr = I915_READ(VLV_PCBR); 5336 if (pcbr) { 5337 /* BIOS set it up already, grab the pre-alloc'd space */ 5338 int pcbr_offset; 5339 5340 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5341 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5342 pcbr_offset, 5343 I915_GTT_OFFSET_NONE, 5344 pctx_size); 5345 goto out; 5346 } 5347 5348 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5349 5350 /* 5351 * From the Gunit register HAS: 5352 * The Gfx driver is expected to program this register and ensure 5353 * proper allocation within Gfx stolen memory. For example, this 5354 * register should be programmed such than the PCBR range does not 5355 * overlap with other ranges, such as the frame buffer, protected 5356 * memory, or any other relevant ranges. 5357 */ 5358 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5359 if (!pctx) { 5360 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5361 return; 5362 } 5363 5364 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5365 I915_WRITE(VLV_PCBR, pctx_paddr); 5366 5367 out: 5368 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5369 dev_priv->vlv_pctx = pctx; 5370 } 5371 5372 static void valleyview_cleanup_pctx(struct drm_device *dev) 5373 { 5374 struct drm_i915_private *dev_priv = dev->dev_private; 5375 5376 if (WARN_ON(!dev_priv->vlv_pctx)) 5377 return; 5378 5379 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 5380 dev_priv->vlv_pctx = NULL; 5381 } 5382 5383 static void valleyview_init_gt_powersave(struct drm_device *dev) 5384 { 5385 struct drm_i915_private *dev_priv = dev->dev_private; 5386 u32 val; 5387 5388 valleyview_setup_pctx(dev); 5389 5390 mutex_lock(&dev_priv->rps.hw_lock); 5391 5392 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5393 switch ((val >> 6) & 3) { 5394 case 0: 5395 case 1: 5396 dev_priv->mem_freq = 800; 5397 break; 5398 case 2: 5399 dev_priv->mem_freq = 1066; 5400 break; 5401 case 3: 5402 dev_priv->mem_freq = 1333; 5403 break; 5404 } 5405 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5406 5407 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5408 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5409 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5410 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5411 dev_priv->rps.max_freq); 5412 5413 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5414 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5415 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5416 dev_priv->rps.efficient_freq); 5417 5418 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5419 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5420 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5421 dev_priv->rps.rp1_freq); 5422 5423 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5424 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5425 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5426 dev_priv->rps.min_freq); 5427 5428 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5429 5430 /* Preserve min/max settings in case of re-init */ 5431 if (dev_priv->rps.max_freq_softlimit == 0) 5432 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5433 5434 if (dev_priv->rps.min_freq_softlimit == 0) 5435 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5436 5437 mutex_unlock(&dev_priv->rps.hw_lock); 5438 } 5439 5440 static void cherryview_init_gt_powersave(struct drm_device *dev) 5441 { 5442 struct drm_i915_private *dev_priv = dev->dev_private; 5443 u32 val; 5444 5445 cherryview_setup_pctx(dev); 5446 5447 mutex_lock(&dev_priv->rps.hw_lock); 5448 5449 mutex_lock(&dev_priv->sb_lock); 5450 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5451 mutex_unlock(&dev_priv->sb_lock); 5452 5453 switch ((val >> 2) & 0x7) { 5454 case 3: 5455 dev_priv->mem_freq = 2000; 5456 break; 5457 default: 5458 dev_priv->mem_freq = 1600; 5459 break; 5460 } 5461 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5462 5463 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5464 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5465 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5466 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5467 dev_priv->rps.max_freq); 5468 5469 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5470 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5471 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5472 dev_priv->rps.efficient_freq); 5473 5474 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5475 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5476 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5477 dev_priv->rps.rp1_freq); 5478 5479 /* PUnit validated range is only [RPe, RP0] */ 5480 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5481 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5482 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5483 dev_priv->rps.min_freq); 5484 5485 WARN_ONCE((dev_priv->rps.max_freq | 5486 dev_priv->rps.efficient_freq | 5487 dev_priv->rps.rp1_freq | 5488 dev_priv->rps.min_freq) & 1, 5489 "Odd GPU freq values\n"); 5490 5491 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5492 5493 /* Preserve min/max settings in case of re-init */ 5494 if (dev_priv->rps.max_freq_softlimit == 0) 5495 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5496 5497 if (dev_priv->rps.min_freq_softlimit == 0) 5498 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5499 5500 mutex_unlock(&dev_priv->rps.hw_lock); 5501 } 5502 5503 static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5504 { 5505 valleyview_cleanup_pctx(dev); 5506 } 5507 5508 static void cherryview_enable_rps(struct drm_device *dev) 5509 { 5510 struct drm_i915_private *dev_priv = dev->dev_private; 5511 struct intel_engine_cs *ring; 5512 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5513 int i; 5514 5515 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5516 5517 gtfifodbg = I915_READ(GTFIFODBG); 5518 if (gtfifodbg) { 5519 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5520 gtfifodbg); 5521 I915_WRITE(GTFIFODBG, gtfifodbg); 5522 } 5523 5524 cherryview_check_pctx(dev_priv); 5525 5526 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5527 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5528 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5529 5530 /* Disable RC states. */ 5531 I915_WRITE(GEN6_RC_CONTROL, 0); 5532 5533 /* 2a: Program RC6 thresholds.*/ 5534 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5535 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5536 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5537 5538 for_each_ring(ring, dev_priv, i) 5539 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5540 I915_WRITE(GEN6_RC_SLEEP, 0); 5541 5542 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5543 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5544 5545 /* allows RC6 residency counter to work */ 5546 I915_WRITE(VLV_COUNTER_CONTROL, 5547 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5548 VLV_MEDIA_RC6_COUNT_EN | 5549 VLV_RENDER_RC6_COUNT_EN)); 5550 5551 /* For now we assume BIOS is allocating and populating the PCBR */ 5552 pcbr = I915_READ(VLV_PCBR); 5553 5554 /* 3: Enable RC6 */ 5555 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5556 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5557 rc6_mode = GEN7_RC_CTL_TO_MODE; 5558 5559 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5560 5561 /* 4 Program defaults and thresholds for RPS*/ 5562 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5563 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5564 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5565 I915_WRITE(GEN6_RP_UP_EI, 66000); 5566 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5567 5568 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5569 5570 /* 5: Enable RPS */ 5571 I915_WRITE(GEN6_RP_CONTROL, 5572 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5573 GEN6_RP_MEDIA_IS_GFX | 5574 GEN6_RP_ENABLE | 5575 GEN6_RP_UP_BUSY_AVG | 5576 GEN6_RP_DOWN_IDLE_AVG); 5577 5578 /* Setting Fixed Bias */ 5579 val = VLV_OVERRIDE_EN | 5580 VLV_SOC_TDP_EN | 5581 CHV_BIAS_CPU_50_SOC_50; 5582 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5583 5584 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5585 5586 /* RPS code assumes GPLL is used */ 5587 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5588 5589 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5590 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5591 5592 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5593 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5594 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5595 dev_priv->rps.cur_freq); 5596 5597 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5598 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5599 dev_priv->rps.efficient_freq); 5600 5601 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5602 5603 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5604 } 5605 5606 static void valleyview_enable_rps(struct drm_device *dev) 5607 { 5608 struct drm_i915_private *dev_priv = dev->dev_private; 5609 struct intel_engine_cs *ring; 5610 u32 gtfifodbg, val, rc6_mode = 0; 5611 int i; 5612 5613 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5614 5615 valleyview_check_pctx(dev_priv); 5616 5617 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5618 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5619 gtfifodbg); 5620 I915_WRITE(GTFIFODBG, gtfifodbg); 5621 } 5622 5623 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5624 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5625 5626 /* Disable RC states. */ 5627 I915_WRITE(GEN6_RC_CONTROL, 0); 5628 5629 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5630 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5631 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5632 I915_WRITE(GEN6_RP_UP_EI, 66000); 5633 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5634 5635 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5636 5637 I915_WRITE(GEN6_RP_CONTROL, 5638 GEN6_RP_MEDIA_TURBO | 5639 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5640 GEN6_RP_MEDIA_IS_GFX | 5641 GEN6_RP_ENABLE | 5642 GEN6_RP_UP_BUSY_AVG | 5643 GEN6_RP_DOWN_IDLE_CONT); 5644 5645 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5646 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5647 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5648 5649 for_each_ring(ring, dev_priv, i) 5650 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5651 5652 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5653 5654 /* allows RC6 residency counter to work */ 5655 I915_WRITE(VLV_COUNTER_CONTROL, 5656 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5657 VLV_RENDER_RC0_COUNT_EN | 5658 VLV_MEDIA_RC6_COUNT_EN | 5659 VLV_RENDER_RC6_COUNT_EN)); 5660 5661 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5662 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5663 5664 intel_print_rc6_info(dev, rc6_mode); 5665 5666 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5667 5668 /* Setting Fixed Bias */ 5669 val = VLV_OVERRIDE_EN | 5670 VLV_SOC_TDP_EN | 5671 VLV_BIAS_CPU_125_SOC_875; 5672 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5673 5674 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5675 5676 /* RPS code assumes GPLL is used */ 5677 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5678 5679 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5680 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5681 5682 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5683 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5684 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5685 dev_priv->rps.cur_freq); 5686 5687 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5688 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5689 dev_priv->rps.efficient_freq); 5690 5691 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5692 5693 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5694 } 5695 5696 static unsigned long intel_pxfreq(u32 vidfreq) 5697 { 5698 unsigned long freq; 5699 int div = (vidfreq & 0x3f0000) >> 16; 5700 int post = (vidfreq & 0x3000) >> 12; 5701 int pre = (vidfreq & 0x7); 5702 5703 if (!pre) 5704 return 0; 5705 5706 freq = ((div * 133333) / ((1<<post) * pre)); 5707 5708 return freq; 5709 } 5710 5711 static const struct cparams { 5712 u16 i; 5713 u16 t; 5714 u16 m; 5715 u16 c; 5716 } cparams[] = { 5717 { 1, 1333, 301, 28664 }, 5718 { 1, 1066, 294, 24460 }, 5719 { 1, 800, 294, 25192 }, 5720 { 0, 1333, 276, 27605 }, 5721 { 0, 1066, 276, 27605 }, 5722 { 0, 800, 231, 23784 }, 5723 }; 5724 5725 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5726 { 5727 u64 total_count, diff, ret; 5728 u32 count1, count2, count3, m = 0, c = 0; 5729 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5730 int i; 5731 5732 assert_spin_locked(&mchdev_lock); 5733 5734 diff1 = now - dev_priv->ips.last_time1; 5735 5736 /* Prevent division-by-zero if we are asking too fast. 5737 * Also, we don't get interesting results if we are polling 5738 * faster than once in 10ms, so just return the saved value 5739 * in such cases. 5740 */ 5741 if (diff1 <= 10) 5742 return dev_priv->ips.chipset_power; 5743 5744 count1 = I915_READ(DMIEC); 5745 count2 = I915_READ(DDREC); 5746 count3 = I915_READ(CSIEC); 5747 5748 total_count = count1 + count2 + count3; 5749 5750 /* FIXME: handle per-counter overflow */ 5751 if (total_count < dev_priv->ips.last_count1) { 5752 diff = ~0UL - dev_priv->ips.last_count1; 5753 diff += total_count; 5754 } else { 5755 diff = total_count - dev_priv->ips.last_count1; 5756 } 5757 5758 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5759 if (cparams[i].i == dev_priv->ips.c_m && 5760 cparams[i].t == dev_priv->ips.r_t) { 5761 m = cparams[i].m; 5762 c = cparams[i].c; 5763 break; 5764 } 5765 } 5766 5767 diff = div_u64(diff, diff1); 5768 ret = ((m * diff) + c); 5769 ret = div_u64(ret, 10); 5770 5771 dev_priv->ips.last_count1 = total_count; 5772 dev_priv->ips.last_time1 = now; 5773 5774 dev_priv->ips.chipset_power = ret; 5775 5776 return ret; 5777 } 5778 5779 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5780 { 5781 struct drm_device *dev = dev_priv->dev; 5782 unsigned long val; 5783 5784 if (INTEL_INFO(dev)->gen != 5) 5785 return 0; 5786 5787 spin_lock_irq(&mchdev_lock); 5788 5789 val = __i915_chipset_val(dev_priv); 5790 5791 spin_unlock_irq(&mchdev_lock); 5792 5793 return val; 5794 } 5795 5796 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5797 { 5798 unsigned long m, x, b; 5799 u32 tsfs; 5800 5801 tsfs = I915_READ(TSFS); 5802 5803 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5804 x = I915_READ8(TR1); 5805 5806 b = tsfs & TSFS_INTR_MASK; 5807 5808 return ((m * x) / 127) - b; 5809 } 5810 5811 static int _pxvid_to_vd(u8 pxvid) 5812 { 5813 if (pxvid == 0) 5814 return 0; 5815 5816 if (pxvid >= 8 && pxvid < 31) 5817 pxvid = 31; 5818 5819 return (pxvid + 2) * 125; 5820 } 5821 5822 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5823 { 5824 struct drm_device *dev = dev_priv->dev; 5825 const int vd = _pxvid_to_vd(pxvid); 5826 const int vm = vd - 1125; 5827 5828 if (INTEL_INFO(dev)->is_mobile) 5829 return vm > 0 ? vm : 0; 5830 5831 return vd; 5832 } 5833 5834 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5835 { 5836 u64 now, diff, diffms; 5837 u32 count; 5838 5839 assert_spin_locked(&mchdev_lock); 5840 5841 now = ktime_get_raw_ns(); 5842 diffms = now - dev_priv->ips.last_time2; 5843 do_div(diffms, NSEC_PER_MSEC); 5844 5845 /* Don't divide by 0 */ 5846 if (!diffms) 5847 return; 5848 5849 count = I915_READ(GFXEC); 5850 5851 if (count < dev_priv->ips.last_count2) { 5852 diff = ~0UL - dev_priv->ips.last_count2; 5853 diff += count; 5854 } else { 5855 diff = count - dev_priv->ips.last_count2; 5856 } 5857 5858 dev_priv->ips.last_count2 = count; 5859 dev_priv->ips.last_time2 = now; 5860 5861 /* More magic constants... */ 5862 diff = diff * 1181; 5863 diff = div_u64(diff, diffms * 10); 5864 dev_priv->ips.gfx_power = diff; 5865 } 5866 5867 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5868 { 5869 struct drm_device *dev = dev_priv->dev; 5870 5871 if (INTEL_INFO(dev)->gen != 5) 5872 return; 5873 5874 spin_lock_irq(&mchdev_lock); 5875 5876 __i915_update_gfx_val(dev_priv); 5877 5878 spin_unlock_irq(&mchdev_lock); 5879 } 5880 5881 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5882 { 5883 unsigned long t, corr, state1, corr2, state2; 5884 u32 pxvid, ext_v; 5885 5886 assert_spin_locked(&mchdev_lock); 5887 5888 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); 5889 pxvid = (pxvid >> 24) & 0x7f; 5890 ext_v = pvid_to_extvid(dev_priv, pxvid); 5891 5892 state1 = ext_v; 5893 5894 t = i915_mch_val(dev_priv); 5895 5896 /* Revel in the empirically derived constants */ 5897 5898 /* Correction factor in 1/100000 units */ 5899 if (t > 80) 5900 corr = ((t * 2349) + 135940); 5901 else if (t >= 50) 5902 corr = ((t * 964) + 29317); 5903 else /* < 50 */ 5904 corr = ((t * 301) + 1004); 5905 5906 corr = corr * ((150142 * state1) / 10000 - 78642); 5907 corr /= 100000; 5908 corr2 = (corr * dev_priv->ips.corr); 5909 5910 state2 = (corr2 * state1) / 10000; 5911 state2 /= 100; /* convert to mW */ 5912 5913 __i915_update_gfx_val(dev_priv); 5914 5915 return dev_priv->ips.gfx_power + state2; 5916 } 5917 5918 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5919 { 5920 struct drm_device *dev = dev_priv->dev; 5921 unsigned long val; 5922 5923 if (INTEL_INFO(dev)->gen != 5) 5924 return 0; 5925 5926 spin_lock_irq(&mchdev_lock); 5927 5928 val = __i915_gfx_val(dev_priv); 5929 5930 spin_unlock_irq(&mchdev_lock); 5931 5932 return val; 5933 } 5934 5935 /** 5936 * i915_read_mch_val - return value for IPS use 5937 * 5938 * Calculate and return a value for the IPS driver to use when deciding whether 5939 * we have thermal and power headroom to increase CPU or GPU power budget. 5940 */ 5941 unsigned long i915_read_mch_val(void) 5942 { 5943 struct drm_i915_private *dev_priv; 5944 unsigned long chipset_val, graphics_val, ret = 0; 5945 5946 spin_lock_irq(&mchdev_lock); 5947 if (!i915_mch_dev) 5948 goto out_unlock; 5949 dev_priv = i915_mch_dev; 5950 5951 chipset_val = __i915_chipset_val(dev_priv); 5952 graphics_val = __i915_gfx_val(dev_priv); 5953 5954 ret = chipset_val + graphics_val; 5955 5956 out_unlock: 5957 spin_unlock_irq(&mchdev_lock); 5958 5959 return ret; 5960 } 5961 EXPORT_SYMBOL_GPL(i915_read_mch_val); 5962 5963 /** 5964 * i915_gpu_raise - raise GPU frequency limit 5965 * 5966 * Raise the limit; IPS indicates we have thermal headroom. 5967 */ 5968 bool i915_gpu_raise(void) 5969 { 5970 struct drm_i915_private *dev_priv; 5971 bool ret = true; 5972 5973 spin_lock_irq(&mchdev_lock); 5974 if (!i915_mch_dev) { 5975 ret = false; 5976 goto out_unlock; 5977 } 5978 dev_priv = i915_mch_dev; 5979 5980 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5981 dev_priv->ips.max_delay--; 5982 5983 out_unlock: 5984 spin_unlock_irq(&mchdev_lock); 5985 5986 return ret; 5987 } 5988 EXPORT_SYMBOL_GPL(i915_gpu_raise); 5989 5990 /** 5991 * i915_gpu_lower - lower GPU frequency limit 5992 * 5993 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5994 * frequency maximum. 5995 */ 5996 bool i915_gpu_lower(void) 5997 { 5998 struct drm_i915_private *dev_priv; 5999 bool ret = true; 6000 6001 spin_lock_irq(&mchdev_lock); 6002 if (!i915_mch_dev) { 6003 ret = false; 6004 goto out_unlock; 6005 } 6006 dev_priv = i915_mch_dev; 6007 6008 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 6009 dev_priv->ips.max_delay++; 6010 6011 out_unlock: 6012 spin_unlock_irq(&mchdev_lock); 6013 6014 return ret; 6015 } 6016 EXPORT_SYMBOL_GPL(i915_gpu_lower); 6017 6018 /** 6019 * i915_gpu_busy - indicate GPU business to IPS 6020 * 6021 * Tell the IPS driver whether or not the GPU is busy. 6022 */ 6023 bool i915_gpu_busy(void) 6024 { 6025 struct drm_i915_private *dev_priv; 6026 struct intel_engine_cs *ring; 6027 bool ret = false; 6028 int i; 6029 6030 spin_lock_irq(&mchdev_lock); 6031 if (!i915_mch_dev) 6032 goto out_unlock; 6033 dev_priv = i915_mch_dev; 6034 6035 for_each_ring(ring, dev_priv, i) 6036 ret |= !list_empty(&ring->request_list); 6037 6038 out_unlock: 6039 spin_unlock_irq(&mchdev_lock); 6040 6041 return ret; 6042 } 6043 EXPORT_SYMBOL_GPL(i915_gpu_busy); 6044 6045 /** 6046 * i915_gpu_turbo_disable - disable graphics turbo 6047 * 6048 * Disable graphics turbo by resetting the max frequency and setting the 6049 * current frequency to the default. 6050 */ 6051 bool i915_gpu_turbo_disable(void) 6052 { 6053 struct drm_i915_private *dev_priv; 6054 bool ret = true; 6055 6056 spin_lock_irq(&mchdev_lock); 6057 if (!i915_mch_dev) { 6058 ret = false; 6059 goto out_unlock; 6060 } 6061 dev_priv = i915_mch_dev; 6062 6063 dev_priv->ips.max_delay = dev_priv->ips.fstart; 6064 6065 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 6066 ret = false; 6067 6068 out_unlock: 6069 spin_unlock_irq(&mchdev_lock); 6070 6071 return ret; 6072 } 6073 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 6074 6075 /** 6076 * Tells the intel_ips driver that the i915 driver is now loaded, if 6077 * IPS got loaded first. 6078 * 6079 * This awkward dance is so that neither module has to depend on the 6080 * other in order for IPS to do the appropriate communication of 6081 * GPU turbo limits to i915. 6082 */ 6083 static void 6084 ips_ping_for_i915_load(void) 6085 { 6086 #ifndef __NetBSD__ /* XXX IPS GPU turbo limits what? */ 6087 void (*link)(void); 6088 6089 link = symbol_get(ips_link_to_i915_driver); 6090 if (link) { 6091 link(); 6092 symbol_put(ips_link_to_i915_driver); 6093 } 6094 #endif 6095 } 6096 6097 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6098 { 6099 /* We only register the i915 ips part with intel-ips once everything is 6100 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6101 spin_lock_irq(&mchdev_lock); 6102 i915_mch_dev = dev_priv; 6103 spin_unlock_irq(&mchdev_lock); 6104 6105 ips_ping_for_i915_load(); 6106 } 6107 6108 void intel_gpu_ips_teardown(void) 6109 { 6110 spin_lock_irq(&mchdev_lock); 6111 i915_mch_dev = NULL; 6112 spin_unlock_irq(&mchdev_lock); 6113 } 6114 6115 static void intel_init_emon(struct drm_device *dev) 6116 { 6117 struct drm_i915_private *dev_priv = dev->dev_private; 6118 u32 lcfuse; 6119 u8 pxw[16]; 6120 int i; 6121 6122 /* Disable to program */ 6123 I915_WRITE(ECR, 0); 6124 POSTING_READ(ECR); 6125 6126 /* Program energy weights for various events */ 6127 I915_WRITE(SDEW, 0x15040d00); 6128 I915_WRITE(CSIEW0, 0x007f0000); 6129 I915_WRITE(CSIEW1, 0x1e220004); 6130 I915_WRITE(CSIEW2, 0x04000004); 6131 6132 for (i = 0; i < 5; i++) 6133 I915_WRITE(PEW(i), 0); 6134 for (i = 0; i < 3; i++) 6135 I915_WRITE(DEW(i), 0); 6136 6137 /* Program P-state weights to account for frequency power adjustment */ 6138 for (i = 0; i < 16; i++) { 6139 u32 pxvidfreq = I915_READ(PXVFREQ(i)); 6140 unsigned long freq = intel_pxfreq(pxvidfreq); 6141 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6142 PXVFREQ_PX_SHIFT; 6143 unsigned long val; 6144 6145 val = vid * vid; 6146 val *= (freq / 1000); 6147 val *= 255; 6148 val /= (127*127*900); 6149 if (val > 0xff) 6150 DRM_ERROR("bad pxval: %ld\n", val); 6151 pxw[i] = val; 6152 } 6153 /* Render standby states get 0 weight */ 6154 pxw[14] = 0; 6155 pxw[15] = 0; 6156 6157 for (i = 0; i < 4; i++) { 6158 u32 val = ((u32)pxw[i*4] << 24) | ((u32)pxw[(i*4)+1] << 16) | 6159 ((u32)pxw[(i*4)+2] << 8) | ((u32)pxw[(i*4)+3]); 6160 I915_WRITE(PXW(i), val); 6161 } 6162 6163 /* Adjust magic regs to magic values (more experimental results) */ 6164 I915_WRITE(OGW0, 0); 6165 I915_WRITE(OGW1, 0); 6166 I915_WRITE(EG0, 0x00007f00); 6167 I915_WRITE(EG1, 0x0000000e); 6168 I915_WRITE(EG2, 0x000e0000); 6169 I915_WRITE(EG3, 0x68000300); 6170 I915_WRITE(EG4, 0x42000000); 6171 I915_WRITE(EG5, 0x00140031); 6172 I915_WRITE(EG6, 0); 6173 I915_WRITE(EG7, 0); 6174 6175 for (i = 0; i < 8; i++) 6176 I915_WRITE(PXWL(i), 0); 6177 6178 /* Enable PMON + select events */ 6179 I915_WRITE(ECR, 0x80000019); 6180 6181 lcfuse = I915_READ(LCFUSE02); 6182 6183 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6184 } 6185 6186 static bool i915_rc6_ctx_corrupted(struct drm_i915_private *dev_priv) 6187 { 6188 return !I915_READ(GEN8_RC6_CTX_INFO); 6189 } 6190 6191 static void i915_rc6_ctx_wa_init(struct drm_i915_private *i915) 6192 { 6193 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 6194 return; 6195 6196 if (i915_rc6_ctx_corrupted(i915)) { 6197 DRM_INFO("RC6 context corrupted, disabling runtime power management\n"); 6198 i915->rps.ctx_corrupted = true; 6199 intel_runtime_pm_get(i915); 6200 } 6201 } 6202 6203 static void i915_rc6_ctx_wa_cleanup(struct drm_i915_private *i915) 6204 { 6205 if (i915->rps.ctx_corrupted) { 6206 intel_runtime_pm_put(i915); 6207 i915->rps.ctx_corrupted = false; 6208 } 6209 } 6210 6211 /** 6212 * i915_rc6_ctx_wa_suspend - system suspend sequence for the RC6 CTX WA 6213 * @i915: i915 device 6214 * 6215 * Perform any steps needed to clean up the RC6 CTX WA before system suspend. 6216 */ 6217 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915) 6218 { 6219 if (i915->rps.ctx_corrupted) 6220 intel_runtime_pm_put(i915); 6221 } 6222 6223 /** 6224 * i915_rc6_ctx_wa_resume - system resume sequence for the RC6 CTX WA 6225 * @i915: i915 device 6226 * 6227 * Perform any steps needed to re-init the RC6 CTX WA after system resume. 6228 */ 6229 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915) 6230 { 6231 if (!i915->rps.ctx_corrupted) 6232 return; 6233 6234 if (i915_rc6_ctx_corrupted(i915)) { 6235 intel_runtime_pm_get(i915); 6236 return; 6237 } 6238 6239 DRM_INFO("RC6 context restored, re-enabling runtime power management\n"); 6240 i915->rps.ctx_corrupted = false; 6241 } 6242 6243 static void intel_disable_rc6(struct drm_device *dev); 6244 6245 /** 6246 * i915_rc6_ctx_wa_check - check for a new RC6 CTX corruption 6247 * @i915: i915 device 6248 * 6249 * Check if an RC6 CTX corruption has happened since the last check and if so 6250 * disable RC6 and runtime power management. 6251 * 6252 * Return false if no context corruption has happened since the last call of 6253 * this function, true otherwise. 6254 */ 6255 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915) 6256 { 6257 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 6258 return false; 6259 6260 if (i915->rps.ctx_corrupted) 6261 return false; 6262 6263 if (!i915_rc6_ctx_corrupted(i915)) 6264 return false; 6265 6266 DRM_NOTE("RC6 context corruption, disabling runtime power management\n"); 6267 6268 intel_disable_rc6(i915->dev); 6269 i915->rps.ctx_corrupted = true; 6270 intel_runtime_pm_get_noresume(i915); 6271 6272 return true; 6273 } 6274 6275 void intel_init_gt_powersave(struct drm_device *dev) 6276 { 6277 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); 6278 6279 i915_rc6_ctx_wa_init(to_i915(dev)); 6280 6281 if (IS_CHERRYVIEW(dev)) 6282 cherryview_init_gt_powersave(dev); 6283 else if (IS_VALLEYVIEW(dev)) 6284 valleyview_init_gt_powersave(dev); 6285 } 6286 6287 void intel_cleanup_gt_powersave(struct drm_device *dev) 6288 { 6289 if (IS_CHERRYVIEW(dev)) 6290 return; 6291 else if (IS_VALLEYVIEW(dev)) 6292 valleyview_cleanup_gt_powersave(dev); 6293 6294 i915_rc6_ctx_wa_cleanup(to_i915(dev)); 6295 } 6296 6297 static void gen6_suspend_rps(struct drm_device *dev) 6298 { 6299 struct drm_i915_private *dev_priv = dev->dev_private; 6300 6301 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6302 6303 gen6_disable_rps_interrupts(dev); 6304 } 6305 6306 /** 6307 * intel_suspend_gt_powersave - suspend PM work and helper threads 6308 * @dev: drm device 6309 * 6310 * We don't want to disable RC6 or other features here, we just want 6311 * to make sure any work we've queued has finished and won't bother 6312 * us while we're suspended. 6313 */ 6314 void intel_suspend_gt_powersave(struct drm_device *dev) 6315 { 6316 struct drm_i915_private *dev_priv = dev->dev_private; 6317 6318 if (INTEL_INFO(dev)->gen < 6) 6319 return; 6320 6321 gen6_suspend_rps(dev); 6322 6323 /* Force GPU to min freq during suspend */ 6324 gen6_rps_idle(dev_priv); 6325 } 6326 6327 static void __intel_disable_rc6(struct drm_device *dev) 6328 { 6329 if (INTEL_INFO(dev)->gen >= 9) 6330 gen9_disable_rc6(dev); 6331 else if (IS_CHERRYVIEW(dev)) 6332 cherryview_disable_rc6(dev); 6333 else if (IS_VALLEYVIEW(dev)) 6334 valleyview_disable_rc6(dev); 6335 else 6336 gen6_disable_rc6(dev); 6337 } 6338 6339 static void intel_disable_rc6(struct drm_device *dev) 6340 { 6341 struct drm_i915_private *dev_priv = to_i915(dev); 6342 6343 mutex_lock(&dev_priv->rps.hw_lock); 6344 __intel_disable_rc6(dev); 6345 mutex_unlock(&dev_priv->rps.hw_lock); 6346 } 6347 6348 static void intel_disable_rps(struct drm_device *dev) 6349 { 6350 if (IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev)) 6351 return; 6352 6353 if (INTEL_INFO(dev)->gen >= 9) 6354 gen9_disable_rps(dev); 6355 else 6356 gen6_disable_rps(dev); 6357 } 6358 6359 void intel_disable_gt_powersave(struct drm_device *dev) 6360 { 6361 struct drm_i915_private *dev_priv = dev->dev_private; 6362 6363 if (IS_IRONLAKE_M(dev)) { 6364 ironlake_disable_drps(dev); 6365 } else if (INTEL_INFO(dev)->gen >= 6) { 6366 intel_suspend_gt_powersave(dev); 6367 6368 mutex_lock(&dev_priv->rps.hw_lock); 6369 6370 __intel_disable_rc6(dev); 6371 intel_disable_rps(dev); 6372 6373 dev_priv->rps.enabled = false; 6374 6375 mutex_unlock(&dev_priv->rps.hw_lock); 6376 } 6377 } 6378 6379 static void intel_gen6_powersave_work(struct work_struct *work) 6380 { 6381 struct drm_i915_private *dev_priv = 6382 container_of(work, struct drm_i915_private, 6383 rps.delayed_resume_work.work); 6384 struct drm_device *dev = dev_priv->dev; 6385 6386 mutex_lock(&dev_priv->rps.hw_lock); 6387 6388 gen6_reset_rps_interrupts(dev); 6389 6390 if (IS_CHERRYVIEW(dev)) { 6391 cherryview_enable_rps(dev); 6392 } else if (IS_VALLEYVIEW(dev)) { 6393 valleyview_enable_rps(dev); 6394 } else if (INTEL_INFO(dev)->gen >= 9) { 6395 gen9_enable_rc6(dev); 6396 gen9_enable_rps(dev); 6397 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 6398 __gen6_update_ring_freq(dev); 6399 } else if (IS_BROADWELL(dev)) { 6400 gen8_enable_rps(dev); 6401 __gen6_update_ring_freq(dev); 6402 } else { 6403 gen6_enable_rps(dev); 6404 __gen6_update_ring_freq(dev); 6405 } 6406 6407 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6408 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6409 6410 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6411 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6412 6413 dev_priv->rps.enabled = true; 6414 6415 gen6_enable_rps_interrupts(dev); 6416 6417 mutex_unlock(&dev_priv->rps.hw_lock); 6418 6419 intel_runtime_pm_put(dev_priv); 6420 } 6421 6422 void intel_enable_gt_powersave(struct drm_device *dev) 6423 { 6424 struct drm_i915_private *dev_priv = dev->dev_private; 6425 6426 /* Powersaving is controlled by the host when inside a VM */ 6427 if (intel_vgpu_active(dev)) 6428 return; 6429 6430 if (IS_IRONLAKE_M(dev)) { 6431 mutex_lock(&dev->struct_mutex); 6432 ironlake_enable_drps(dev); 6433 intel_init_emon(dev); 6434 mutex_unlock(&dev->struct_mutex); 6435 } else if (INTEL_INFO(dev)->gen >= 6) { 6436 /* 6437 * PCU communication is slow and this doesn't need to be 6438 * done at any specific time, so do this out of our fast path 6439 * to make resume and init faster. 6440 * 6441 * We depend on the HW RC6 power context save/restore 6442 * mechanism when entering D3 through runtime PM suspend. So 6443 * disable RPM until RPS/RC6 is properly setup. We can only 6444 * get here via the driver load/system resume/runtime resume 6445 * paths, so the _noresume version is enough (and in case of 6446 * runtime resume it's necessary). 6447 */ 6448 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6449 round_jiffies_up_relative(HZ))) 6450 intel_runtime_pm_get_noresume(dev_priv); 6451 } 6452 } 6453 6454 void intel_reset_gt_powersave(struct drm_device *dev) 6455 { 6456 struct drm_i915_private *dev_priv = dev->dev_private; 6457 6458 if (INTEL_INFO(dev)->gen < 6) 6459 return; 6460 6461 gen6_suspend_rps(dev); 6462 dev_priv->rps.enabled = false; 6463 } 6464 6465 static void ibx_init_clock_gating(struct drm_device *dev) 6466 { 6467 struct drm_i915_private *dev_priv = dev->dev_private; 6468 6469 /* 6470 * On Ibex Peak and Cougar Point, we need to disable clock 6471 * gating for the panel power sequencer or it will fail to 6472 * start up when no ports are active. 6473 */ 6474 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6475 } 6476 6477 static void g4x_disable_trickle_feed(struct drm_device *dev) 6478 { 6479 struct drm_i915_private *dev_priv = dev->dev_private; 6480 enum i915_pipe pipe; 6481 6482 for_each_pipe(dev_priv, pipe) { 6483 I915_WRITE(DSPCNTR(pipe), 6484 I915_READ(DSPCNTR(pipe)) | 6485 DISPPLANE_TRICKLE_FEED_DISABLE); 6486 6487 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6488 POSTING_READ(DSPSURF(pipe)); 6489 } 6490 } 6491 6492 static void ilk_init_lp_watermarks(struct drm_device *dev) 6493 { 6494 struct drm_i915_private *dev_priv = dev->dev_private; 6495 6496 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6497 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6498 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6499 6500 /* 6501 * Don't touch WM1S_LP_EN here. 6502 * Doing so could cause underruns. 6503 */ 6504 } 6505 6506 static void ironlake_init_clock_gating(struct drm_device *dev) 6507 { 6508 struct drm_i915_private *dev_priv = dev->dev_private; 6509 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6510 6511 /* 6512 * Required for FBC 6513 * WaFbcDisableDpfcClockGating:ilk 6514 */ 6515 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6516 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6517 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6518 6519 I915_WRITE(PCH_3DCGDIS0, 6520 MARIUNIT_CLOCK_GATE_DISABLE | 6521 SVSMUNIT_CLOCK_GATE_DISABLE); 6522 I915_WRITE(PCH_3DCGDIS1, 6523 VFMUNIT_CLOCK_GATE_DISABLE); 6524 6525 /* 6526 * According to the spec the following bits should be set in 6527 * order to enable memory self-refresh 6528 * The bit 22/21 of 0x42004 6529 * The bit 5 of 0x42020 6530 * The bit 15 of 0x45000 6531 */ 6532 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6533 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6534 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6535 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6536 I915_WRITE(DISP_ARB_CTL, 6537 (I915_READ(DISP_ARB_CTL) | 6538 DISP_FBC_WM_DIS)); 6539 6540 ilk_init_lp_watermarks(dev); 6541 6542 /* 6543 * Based on the document from hardware guys the following bits 6544 * should be set unconditionally in order to enable FBC. 6545 * The bit 22 of 0x42000 6546 * The bit 22 of 0x42004 6547 * The bit 7,8,9 of 0x42020. 6548 */ 6549 if (IS_IRONLAKE_M(dev)) { 6550 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6551 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6552 I915_READ(ILK_DISPLAY_CHICKEN1) | 6553 ILK_FBCQ_DIS); 6554 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6555 I915_READ(ILK_DISPLAY_CHICKEN2) | 6556 ILK_DPARB_GATE); 6557 } 6558 6559 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6560 6561 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6562 I915_READ(ILK_DISPLAY_CHICKEN2) | 6563 ILK_ELPIN_409_SELECT); 6564 I915_WRITE(_3D_CHICKEN2, 6565 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6566 _3D_CHICKEN2_WM_READ_PIPELINED); 6567 6568 /* WaDisableRenderCachePipelinedFlush:ilk */ 6569 I915_WRITE(CACHE_MODE_0, 6570 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6571 6572 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6573 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6574 6575 g4x_disable_trickle_feed(dev); 6576 6577 ibx_init_clock_gating(dev); 6578 } 6579 6580 static void cpt_init_clock_gating(struct drm_device *dev) 6581 { 6582 struct drm_i915_private *dev_priv = dev->dev_private; 6583 int pipe; 6584 uint32_t val; 6585 6586 /* 6587 * On Ibex Peak and Cougar Point, we need to disable clock 6588 * gating for the panel power sequencer or it will fail to 6589 * start up when no ports are active. 6590 */ 6591 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6592 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6593 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6594 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6595 DPLS_EDP_PPS_FIX_DIS); 6596 /* The below fixes the weird display corruption, a few pixels shifted 6597 * downward, on (only) LVDS of some HP laptops with IVY. 6598 */ 6599 for_each_pipe(dev_priv, pipe) { 6600 val = I915_READ(TRANS_CHICKEN2(pipe)); 6601 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6602 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6603 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6604 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6605 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6606 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6607 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6608 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6609 } 6610 /* WADP0ClockGatingDisable */ 6611 for_each_pipe(dev_priv, pipe) { 6612 I915_WRITE(TRANS_CHICKEN1(pipe), 6613 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6614 } 6615 } 6616 6617 static void gen6_check_mch_setup(struct drm_device *dev) 6618 { 6619 struct drm_i915_private *dev_priv = dev->dev_private; 6620 uint32_t tmp; 6621 6622 tmp = I915_READ(MCH_SSKPD); 6623 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6624 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6625 tmp); 6626 } 6627 6628 static void gen6_init_clock_gating(struct drm_device *dev) 6629 { 6630 struct drm_i915_private *dev_priv = dev->dev_private; 6631 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6632 6633 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6634 6635 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6636 I915_READ(ILK_DISPLAY_CHICKEN2) | 6637 ILK_ELPIN_409_SELECT); 6638 6639 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6640 I915_WRITE(_3D_CHICKEN, 6641 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6642 6643 /* WaDisable_RenderCache_OperationalFlush:snb */ 6644 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6645 6646 /* 6647 * BSpec recoomends 8x4 when MSAA is used, 6648 * however in practice 16x4 seems fastest. 6649 * 6650 * Note that PS/WM thread counts depend on the WIZ hashing 6651 * disable bit, which we don't touch here, but it's good 6652 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6653 */ 6654 I915_WRITE(GEN6_GT_MODE, 6655 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6656 6657 ilk_init_lp_watermarks(dev); 6658 6659 I915_WRITE(CACHE_MODE_0, 6660 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6661 6662 I915_WRITE(GEN6_UCGCTL1, 6663 I915_READ(GEN6_UCGCTL1) | 6664 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6665 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6666 6667 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6668 * gating disable must be set. Failure to set it results in 6669 * flickering pixels due to Z write ordering failures after 6670 * some amount of runtime in the Mesa "fire" demo, and Unigine 6671 * Sanctuary and Tropics, and apparently anything else with 6672 * alpha test or pixel discard. 6673 * 6674 * According to the spec, bit 11 (RCCUNIT) must also be set, 6675 * but we didn't debug actual testcases to find it out. 6676 * 6677 * WaDisableRCCUnitClockGating:snb 6678 * WaDisableRCPBUnitClockGating:snb 6679 */ 6680 I915_WRITE(GEN6_UCGCTL2, 6681 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6682 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6683 6684 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6685 I915_WRITE(_3D_CHICKEN3, 6686 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6687 6688 /* 6689 * Bspec says: 6690 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6691 * 3DSTATE_SF number of SF output attributes is more than 16." 6692 */ 6693 I915_WRITE(_3D_CHICKEN3, 6694 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6695 6696 /* 6697 * According to the spec the following bits should be 6698 * set in order to enable memory self-refresh and fbc: 6699 * The bit21 and bit22 of 0x42000 6700 * The bit21 and bit22 of 0x42004 6701 * The bit5 and bit7 of 0x42020 6702 * The bit14 of 0x70180 6703 * The bit14 of 0x71180 6704 * 6705 * WaFbcAsynchFlipDisableFbcQueue:snb 6706 */ 6707 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6708 I915_READ(ILK_DISPLAY_CHICKEN1) | 6709 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6710 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6711 I915_READ(ILK_DISPLAY_CHICKEN2) | 6712 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6713 I915_WRITE(ILK_DSPCLK_GATE_D, 6714 I915_READ(ILK_DSPCLK_GATE_D) | 6715 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6716 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6717 6718 g4x_disable_trickle_feed(dev); 6719 6720 cpt_init_clock_gating(dev); 6721 6722 gen6_check_mch_setup(dev); 6723 } 6724 6725 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6726 { 6727 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6728 6729 /* 6730 * WaVSThreadDispatchOverride:ivb,vlv 6731 * 6732 * This actually overrides the dispatch 6733 * mode for all thread types. 6734 */ 6735 reg &= ~GEN7_FF_SCHED_MASK; 6736 reg |= GEN7_FF_TS_SCHED_HW; 6737 reg |= GEN7_FF_VS_SCHED_HW; 6738 reg |= GEN7_FF_DS_SCHED_HW; 6739 6740 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6741 } 6742 6743 static void lpt_init_clock_gating(struct drm_device *dev) 6744 { 6745 struct drm_i915_private *dev_priv = dev->dev_private; 6746 6747 /* 6748 * TODO: this bit should only be enabled when really needed, then 6749 * disabled when not needed anymore in order to save power. 6750 */ 6751 if (HAS_PCH_LPT_LP(dev)) 6752 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6753 I915_READ(SOUTH_DSPCLK_GATE_D) | 6754 PCH_LP_PARTITION_LEVEL_DISABLE); 6755 6756 /* WADPOClockGatingDisable:hsw */ 6757 I915_WRITE(TRANS_CHICKEN1(PIPE_A), 6758 I915_READ(TRANS_CHICKEN1(PIPE_A)) | 6759 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6760 } 6761 6762 static void lpt_suspend_hw(struct drm_device *dev) 6763 { 6764 struct drm_i915_private *dev_priv = dev->dev_private; 6765 6766 if (HAS_PCH_LPT_LP(dev)) { 6767 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6768 6769 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6770 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6771 } 6772 } 6773 6774 static void broadwell_init_clock_gating(struct drm_device *dev) 6775 { 6776 struct drm_i915_private *dev_priv = dev->dev_private; 6777 enum i915_pipe pipe; 6778 uint32_t misccpctl; 6779 6780 ilk_init_lp_watermarks(dev); 6781 6782 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6783 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6784 6785 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6786 I915_WRITE(CHICKEN_PAR1_1, 6787 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6788 6789 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6790 for_each_pipe(dev_priv, pipe) { 6791 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6792 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6793 BDW_DPRS_MASK_VBLANK_SRD); 6794 } 6795 6796 /* WaVSRefCountFullforceMissDisable:bdw */ 6797 /* WaDSRefCountFullforceMissDisable:bdw */ 6798 I915_WRITE(GEN7_FF_THREAD_MODE, 6799 I915_READ(GEN7_FF_THREAD_MODE) & 6800 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6801 6802 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6803 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6804 6805 /* WaDisableSDEUnitClockGating:bdw */ 6806 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6807 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6808 6809 /* 6810 * WaProgramL3SqcReg1Default:bdw 6811 * WaTempDisableDOPClkGating:bdw 6812 */ 6813 misccpctl = I915_READ(GEN7_MISCCPCTL); 6814 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6815 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6816 /* 6817 * Wait at least 100 clocks before re-enabling clock gating. See 6818 * the definition of L3SQCREG1 in BSpec. 6819 */ 6820 POSTING_READ(GEN8_L3SQCREG1); 6821 udelay(1); 6822 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6823 6824 /* 6825 * WaGttCachingOffByDefault:bdw 6826 * GTT cache may not work with big pages, so if those 6827 * are ever enabled GTT cache may need to be disabled. 6828 */ 6829 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6830 6831 lpt_init_clock_gating(dev); 6832 } 6833 6834 static void haswell_init_clock_gating(struct drm_device *dev) 6835 { 6836 struct drm_i915_private *dev_priv = dev->dev_private; 6837 6838 ilk_init_lp_watermarks(dev); 6839 6840 /* L3 caching of data atomics doesn't work -- disable it. */ 6841 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6842 I915_WRITE(HSW_ROW_CHICKEN3, 6843 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6844 6845 /* This is required by WaCatErrorRejectionIssue:hsw */ 6846 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6847 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6848 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6849 6850 /* WaVSRefCountFullforceMissDisable:hsw */ 6851 I915_WRITE(GEN7_FF_THREAD_MODE, 6852 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6853 6854 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6855 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6856 6857 /* enable HiZ Raw Stall Optimization */ 6858 I915_WRITE(CACHE_MODE_0_GEN7, 6859 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6860 6861 /* WaDisable4x2SubspanOptimization:hsw */ 6862 I915_WRITE(CACHE_MODE_1, 6863 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6864 6865 /* 6866 * BSpec recommends 8x4 when MSAA is used, 6867 * however in practice 16x4 seems fastest. 6868 * 6869 * Note that PS/WM thread counts depend on the WIZ hashing 6870 * disable bit, which we don't touch here, but it's good 6871 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6872 */ 6873 I915_WRITE(GEN7_GT_MODE, 6874 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6875 6876 /* WaSampleCChickenBitEnable:hsw */ 6877 I915_WRITE(HALF_SLICE_CHICKEN3, 6878 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6879 6880 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6881 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6882 6883 /* WaRsPkgCStateDisplayPMReq:hsw */ 6884 I915_WRITE(CHICKEN_PAR1_1, 6885 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6886 6887 lpt_init_clock_gating(dev); 6888 } 6889 6890 static void ivybridge_init_clock_gating(struct drm_device *dev) 6891 { 6892 struct drm_i915_private *dev_priv = dev->dev_private; 6893 uint32_t snpcr; 6894 6895 ilk_init_lp_watermarks(dev); 6896 6897 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6898 6899 /* WaDisableEarlyCull:ivb */ 6900 I915_WRITE(_3D_CHICKEN3, 6901 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6902 6903 /* WaDisableBackToBackFlipFix:ivb */ 6904 I915_WRITE(IVB_CHICKEN3, 6905 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6906 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6907 6908 /* WaDisablePSDDualDispatchEnable:ivb */ 6909 if (IS_IVB_GT1(dev)) 6910 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6911 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6912 6913 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6914 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6915 6916 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6917 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6918 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6919 6920 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6921 I915_WRITE(GEN7_L3CNTLREG1, 6922 GEN7_WA_FOR_GEN7_L3_CONTROL); 6923 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6924 GEN7_WA_L3_CHICKEN_MODE); 6925 if (IS_IVB_GT1(dev)) 6926 I915_WRITE(GEN7_ROW_CHICKEN2, 6927 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6928 else { 6929 /* must write both registers */ 6930 I915_WRITE(GEN7_ROW_CHICKEN2, 6931 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6932 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6933 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6934 } 6935 6936 /* WaForceL3Serialization:ivb */ 6937 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6938 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6939 6940 /* 6941 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6942 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6943 */ 6944 I915_WRITE(GEN6_UCGCTL2, 6945 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6946 6947 /* This is required by WaCatErrorRejectionIssue:ivb */ 6948 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6949 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6950 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6951 6952 g4x_disable_trickle_feed(dev); 6953 6954 gen7_setup_fixed_func_scheduler(dev_priv); 6955 6956 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6957 /* enable HiZ Raw Stall Optimization */ 6958 I915_WRITE(CACHE_MODE_0_GEN7, 6959 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6960 } 6961 6962 /* WaDisable4x2SubspanOptimization:ivb */ 6963 I915_WRITE(CACHE_MODE_1, 6964 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6965 6966 /* 6967 * BSpec recommends 8x4 when MSAA is used, 6968 * however in practice 16x4 seems fastest. 6969 * 6970 * Note that PS/WM thread counts depend on the WIZ hashing 6971 * disable bit, which we don't touch here, but it's good 6972 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6973 */ 6974 I915_WRITE(GEN7_GT_MODE, 6975 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6976 6977 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6978 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6979 snpcr |= GEN6_MBC_SNPCR_MED; 6980 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6981 6982 if (!HAS_PCH_NOP(dev)) 6983 cpt_init_clock_gating(dev); 6984 6985 gen6_check_mch_setup(dev); 6986 } 6987 6988 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6989 { 6990 u32 val; 6991 6992 /* 6993 * On driver load, a pipe may be active and driving a DSI display. 6994 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 6995 * (and never recovering) in this case. intel_dsi_post_disable() will 6996 * clear it when we turn off the display. 6997 */ 6998 val = I915_READ(DSPCLK_GATE_D); 6999 val &= DPOUNIT_CLOCK_GATE_DISABLE; 7000 val |= VRHUNIT_CLOCK_GATE_DISABLE; 7001 I915_WRITE(DSPCLK_GATE_D, val); 7002 7003 /* 7004 * Disable trickle feed and enable pnd deadline calculation 7005 */ 7006 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 7007 I915_WRITE(CBR1_VLV, 0); 7008 } 7009 7010 static void valleyview_init_clock_gating(struct drm_device *dev) 7011 { 7012 struct drm_i915_private *dev_priv = dev->dev_private; 7013 7014 vlv_init_display_clock_gating(dev_priv); 7015 7016 /* WaDisableEarlyCull:vlv */ 7017 I915_WRITE(_3D_CHICKEN3, 7018 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 7019 7020 /* WaDisableBackToBackFlipFix:vlv */ 7021 I915_WRITE(IVB_CHICKEN3, 7022 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 7023 CHICKEN3_DGMG_DONE_FIX_DISABLE); 7024 7025 /* WaPsdDispatchEnable:vlv */ 7026 /* WaDisablePSDDualDispatchEnable:vlv */ 7027 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 7028 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 7029 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 7030 7031 /* WaDisable_RenderCache_OperationalFlush:vlv */ 7032 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7033 7034 /* WaForceL3Serialization:vlv */ 7035 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 7036 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 7037 7038 /* WaDisableDopClockGating:vlv */ 7039 I915_WRITE(GEN7_ROW_CHICKEN2, 7040 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 7041 7042 /* This is required by WaCatErrorRejectionIssue:vlv */ 7043 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 7044 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 7045 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 7046 7047 gen7_setup_fixed_func_scheduler(dev_priv); 7048 7049 /* 7050 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 7051 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 7052 */ 7053 I915_WRITE(GEN6_UCGCTL2, 7054 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 7055 7056 /* WaDisableL3Bank2xClockGate:vlv 7057 * Disabling L3 clock gating- MMIO 940c[25] = 1 7058 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 7059 I915_WRITE(GEN7_UCGCTL4, 7060 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 7061 7062 /* 7063 * BSpec says this must be set, even though 7064 * WaDisable4x2SubspanOptimization isn't listed for VLV. 7065 */ 7066 I915_WRITE(CACHE_MODE_1, 7067 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 7068 7069 /* 7070 * BSpec recommends 8x4 when MSAA is used, 7071 * however in practice 16x4 seems fastest. 7072 * 7073 * Note that PS/WM thread counts depend on the WIZ hashing 7074 * disable bit, which we don't touch here, but it's good 7075 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 7076 */ 7077 I915_WRITE(GEN7_GT_MODE, 7078 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 7079 7080 /* 7081 * WaIncreaseL3CreditsForVLVB0:vlv 7082 * This is the hardware default actually. 7083 */ 7084 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 7085 7086 /* 7087 * WaDisableVLVClockGating_VBIIssue:vlv 7088 * Disable clock gating on th GCFG unit to prevent a delay 7089 * in the reporting of vblank events. 7090 */ 7091 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 7092 } 7093 7094 static void cherryview_init_clock_gating(struct drm_device *dev) 7095 { 7096 struct drm_i915_private *dev_priv = dev->dev_private; 7097 7098 vlv_init_display_clock_gating(dev_priv); 7099 7100 /* WaVSRefCountFullforceMissDisable:chv */ 7101 /* WaDSRefCountFullforceMissDisable:chv */ 7102 I915_WRITE(GEN7_FF_THREAD_MODE, 7103 I915_READ(GEN7_FF_THREAD_MODE) & 7104 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 7105 7106 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 7107 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 7108 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 7109 7110 /* WaDisableCSUnitClockGating:chv */ 7111 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 7112 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 7113 7114 /* WaDisableSDEUnitClockGating:chv */ 7115 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 7116 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 7117 7118 /* 7119 * GTT cache may not work with big pages, so if those 7120 * are ever enabled GTT cache may need to be disabled. 7121 */ 7122 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 7123 } 7124 7125 static void g4x_init_clock_gating(struct drm_device *dev) 7126 { 7127 struct drm_i915_private *dev_priv = dev->dev_private; 7128 uint32_t dspclk_gate; 7129 7130 I915_WRITE(RENCLK_GATE_D1, 0); 7131 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 7132 GS_UNIT_CLOCK_GATE_DISABLE | 7133 CL_UNIT_CLOCK_GATE_DISABLE); 7134 I915_WRITE(RAMCLK_GATE_D, 0); 7135 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 7136 OVRUNIT_CLOCK_GATE_DISABLE | 7137 OVCUNIT_CLOCK_GATE_DISABLE; 7138 if (IS_GM45(dev)) 7139 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 7140 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 7141 7142 /* WaDisableRenderCachePipelinedFlush */ 7143 I915_WRITE(CACHE_MODE_0, 7144 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 7145 7146 /* WaDisable_RenderCache_OperationalFlush:g4x */ 7147 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7148 7149 g4x_disable_trickle_feed(dev); 7150 } 7151 7152 static void crestline_init_clock_gating(struct drm_device *dev) 7153 { 7154 struct drm_i915_private *dev_priv = dev->dev_private; 7155 7156 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 7157 I915_WRITE(RENCLK_GATE_D2, 0); 7158 I915_WRITE(DSPCLK_GATE_D, 0); 7159 I915_WRITE(RAMCLK_GATE_D, 0); 7160 I915_WRITE16(DEUC, 0); 7161 I915_WRITE(MI_ARB_STATE, 7162 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7163 7164 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7165 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7166 } 7167 7168 static void broadwater_init_clock_gating(struct drm_device *dev) 7169 { 7170 struct drm_i915_private *dev_priv = dev->dev_private; 7171 7172 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 7173 I965_RCC_CLOCK_GATE_DISABLE | 7174 I965_RCPB_CLOCK_GATE_DISABLE | 7175 I965_ISC_CLOCK_GATE_DISABLE | 7176 I965_FBC_CLOCK_GATE_DISABLE); 7177 I915_WRITE(RENCLK_GATE_D2, 0); 7178 I915_WRITE(MI_ARB_STATE, 7179 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7180 7181 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7182 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7183 } 7184 7185 static void gen3_init_clock_gating(struct drm_device *dev) 7186 { 7187 struct drm_i915_private *dev_priv = dev->dev_private; 7188 u32 dstate = I915_READ(D_STATE); 7189 7190 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7191 DSTATE_DOT_CLOCK_GATING; 7192 I915_WRITE(D_STATE, dstate); 7193 7194 if (IS_PINEVIEW(dev)) 7195 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 7196 7197 /* IIR "flip pending" means done if this bit is set */ 7198 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 7199 7200 /* interrupts should cause a wake up from C3 */ 7201 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7202 7203 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7204 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7205 7206 I915_WRITE(MI_ARB_STATE, 7207 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7208 } 7209 7210 static void i85x_init_clock_gating(struct drm_device *dev) 7211 { 7212 struct drm_i915_private *dev_priv = dev->dev_private; 7213 7214 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7215 7216 /* interrupts should cause a wake up from C3 */ 7217 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7218 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7219 7220 I915_WRITE(MEM_MODE, 7221 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7222 } 7223 7224 static void i830_init_clock_gating(struct drm_device *dev) 7225 { 7226 struct drm_i915_private *dev_priv = dev->dev_private; 7227 7228 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7229 7230 I915_WRITE(MEM_MODE, 7231 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7232 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7233 } 7234 7235 void intel_init_clock_gating(struct drm_device *dev) 7236 { 7237 struct drm_i915_private *dev_priv = dev->dev_private; 7238 7239 if (dev_priv->display.init_clock_gating) 7240 dev_priv->display.init_clock_gating(dev); 7241 } 7242 7243 void intel_suspend_hw(struct drm_device *dev) 7244 { 7245 if (HAS_PCH_LPT(dev)) 7246 lpt_suspend_hw(dev); 7247 } 7248 7249 /* Set up chip specific power management-related functions */ 7250 void intel_init_pm(struct drm_device *dev) 7251 { 7252 struct drm_i915_private *dev_priv = dev->dev_private; 7253 7254 intel_fbc_init(dev_priv); 7255 7256 /* For cxsr */ 7257 if (IS_PINEVIEW(dev)) 7258 i915_pineview_get_mem_freq(dev); 7259 else if (IS_GEN5(dev)) 7260 i915_ironlake_get_mem_freq(dev); 7261 7262 /* For FIFO watermark updates */ 7263 if (INTEL_INFO(dev)->gen >= 9) { 7264 skl_setup_wm_latency(dev); 7265 7266 if (IS_BROXTON(dev)) 7267 dev_priv->display.init_clock_gating = 7268 bxt_init_clock_gating; 7269 dev_priv->display.update_wm = skl_update_wm; 7270 dev_priv->display.update_sprite_wm = skl_update_sprite_wm; 7271 } else if (HAS_PCH_SPLIT(dev)) { 7272 ilk_setup_wm_latency(dev); 7273 7274 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7275 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7276 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7277 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7278 dev_priv->display.update_wm = ilk_update_wm; 7279 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 7280 } else { 7281 DRM_DEBUG_KMS("Failed to read display plane latency. " 7282 "Disable CxSR\n"); 7283 } 7284 7285 if (IS_GEN5(dev)) 7286 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7287 else if (IS_GEN6(dev)) 7288 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7289 else if (IS_IVYBRIDGE(dev)) 7290 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7291 else if (IS_HASWELL(dev)) 7292 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7293 else if (INTEL_INFO(dev)->gen == 8) 7294 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7295 } else if (IS_CHERRYVIEW(dev)) { 7296 vlv_setup_wm_latency(dev); 7297 7298 dev_priv->display.update_wm = vlv_update_wm; 7299 dev_priv->display.init_clock_gating = 7300 cherryview_init_clock_gating; 7301 } else if (IS_VALLEYVIEW(dev)) { 7302 vlv_setup_wm_latency(dev); 7303 7304 dev_priv->display.update_wm = vlv_update_wm; 7305 dev_priv->display.init_clock_gating = 7306 valleyview_init_clock_gating; 7307 } else if (IS_PINEVIEW(dev)) { 7308 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7309 dev_priv->is_ddr3, 7310 dev_priv->fsb_freq, 7311 dev_priv->mem_freq)) { 7312 DRM_INFO("failed to find known CxSR latency " 7313 "(found ddr%s fsb freq %d, mem freq %d), " 7314 "disabling CxSR\n", 7315 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7316 dev_priv->fsb_freq, dev_priv->mem_freq); 7317 /* Disable CxSR and never update its watermark again */ 7318 intel_set_memory_cxsr(dev_priv, false); 7319 dev_priv->display.update_wm = NULL; 7320 } else 7321 dev_priv->display.update_wm = pineview_update_wm; 7322 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7323 } else if (IS_G4X(dev)) { 7324 dev_priv->display.update_wm = g4x_update_wm; 7325 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7326 } else if (IS_GEN4(dev)) { 7327 dev_priv->display.update_wm = i965_update_wm; 7328 if (IS_CRESTLINE(dev)) 7329 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7330 else if (IS_BROADWATER(dev)) 7331 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7332 } else if (IS_GEN3(dev)) { 7333 dev_priv->display.update_wm = i9xx_update_wm; 7334 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7335 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7336 } else if (IS_GEN2(dev)) { 7337 if (INTEL_INFO(dev)->num_pipes == 1) { 7338 dev_priv->display.update_wm = i845_update_wm; 7339 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7340 } else { 7341 dev_priv->display.update_wm = i9xx_update_wm; 7342 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7343 } 7344 7345 if (IS_I85X(dev) || IS_I865G(dev)) 7346 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7347 else 7348 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7349 } else { 7350 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7351 } 7352 } 7353 7354 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7355 { 7356 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7357 7358 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7359 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7360 return -EAGAIN; 7361 } 7362 7363 I915_WRITE(GEN6_PCODE_DATA, *val); 7364 I915_WRITE(GEN6_PCODE_DATA1, 0); 7365 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7366 7367 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7368 500)) { 7369 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7370 return -ETIMEDOUT; 7371 } 7372 7373 *val = I915_READ(GEN6_PCODE_DATA); 7374 I915_WRITE(GEN6_PCODE_DATA, 0); 7375 7376 return 0; 7377 } 7378 7379 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7380 { 7381 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7382 7383 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7384 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7385 return -EAGAIN; 7386 } 7387 7388 I915_WRITE(GEN6_PCODE_DATA, val); 7389 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7390 7391 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7392 500)) { 7393 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7394 return -ETIMEDOUT; 7395 } 7396 7397 I915_WRITE(GEN6_PCODE_DATA, 0); 7398 7399 return 0; 7400 } 7401 7402 static int vlv_gpu_freq_div(unsigned int czclk_freq) 7403 { 7404 switch (czclk_freq) { 7405 case 200: 7406 return 10; 7407 case 267: 7408 return 12; 7409 case 320: 7410 case 333: 7411 return 16; 7412 case 400: 7413 return 20; 7414 default: 7415 return -1; 7416 } 7417 } 7418 7419 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7420 { 7421 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7422 7423 div = vlv_gpu_freq_div(czclk_freq); 7424 if (div < 0) 7425 return div; 7426 7427 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7428 } 7429 7430 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7431 { 7432 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7433 7434 mul = vlv_gpu_freq_div(czclk_freq); 7435 if (mul < 0) 7436 return mul; 7437 7438 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7439 } 7440 7441 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7442 { 7443 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7444 7445 div = vlv_gpu_freq_div(czclk_freq) / 2; 7446 if (div < 0) 7447 return div; 7448 7449 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7450 } 7451 7452 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7453 { 7454 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7455 7456 mul = vlv_gpu_freq_div(czclk_freq) / 2; 7457 if (mul < 0) 7458 return mul; 7459 7460 /* CHV needs even values */ 7461 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7462 } 7463 7464 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7465 { 7466 if (IS_GEN9(dev_priv->dev)) 7467 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7468 GEN9_FREQ_SCALER); 7469 else if (IS_CHERRYVIEW(dev_priv->dev)) 7470 return chv_gpu_freq(dev_priv, val); 7471 else if (IS_VALLEYVIEW(dev_priv->dev)) 7472 return byt_gpu_freq(dev_priv, val); 7473 else 7474 return val * GT_FREQUENCY_MULTIPLIER; 7475 } 7476 7477 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7478 { 7479 if (IS_GEN9(dev_priv->dev)) 7480 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7481 GT_FREQUENCY_MULTIPLIER); 7482 else if (IS_CHERRYVIEW(dev_priv->dev)) 7483 return chv_freq_opcode(dev_priv, val); 7484 else if (IS_VALLEYVIEW(dev_priv->dev)) 7485 return byt_freq_opcode(dev_priv, val); 7486 else 7487 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7488 } 7489 7490 struct request_boost { 7491 struct work_struct work; 7492 struct drm_i915_gem_request *req; 7493 }; 7494 7495 static void __intel_rps_boost_work(struct work_struct *work) 7496 { 7497 struct request_boost *boost = container_of(work, struct request_boost, work); 7498 struct drm_i915_gem_request *req = boost->req; 7499 7500 if (!i915_gem_request_completed(req, true)) 7501 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7502 req->emitted_jiffies); 7503 7504 i915_gem_request_unreference__unlocked(req); 7505 kfree(boost); 7506 } 7507 7508 void intel_queue_rps_boost_for_request(struct drm_device *dev, 7509 struct drm_i915_gem_request *req) 7510 { 7511 struct request_boost *boost; 7512 7513 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7514 return; 7515 7516 if (i915_gem_request_completed(req, true)) 7517 return; 7518 7519 boost = kmalloc(sizeof(*boost), GFP_ATOMIC); 7520 if (boost == NULL) 7521 return; 7522 7523 i915_gem_request_reference(req); 7524 boost->req = req; 7525 7526 INIT_WORK(&boost->work, __intel_rps_boost_work); 7527 queue_work(to_i915(dev)->wq, &boost->work); 7528 } 7529 7530 void intel_pm_setup(struct drm_device *dev) 7531 { 7532 struct drm_i915_private *dev_priv = dev->dev_private; 7533 7534 #ifdef __NetBSD__ 7535 linux_mutex_init(&dev_priv->rps.hw_lock); 7536 #else 7537 mutex_init(&dev_priv->rps.hw_lock); 7538 #endif 7539 spin_lock_init(&dev_priv->rps.client_lock); 7540 7541 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7542 intel_gen6_powersave_work); 7543 INIT_LIST_HEAD(&dev_priv->rps.clients); 7544 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7545 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7546 7547 dev_priv->pm.suspended = false; 7548 } 7549
Indexes created Sat Oct 11 19:10:01 GMT 2025