intel_pm.c revision 1.2.4.2
1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 25 * 26 */ 27 28 #include <linux/cpufreq.h> 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 #ifndef __NetBSD__ 32 #include "../../../platform/x86/intel_ips.h" 33 #endif 34 #include <linux/module.h> 35 #include <linux/kgdb.h> 36 #include <linux/log2.h> 37 #include <linux/math64.h> 38 #include <linux/time.h> 39 #include <asm/param.h> 40 41 #define FORCEWAKE_ACK_TIMEOUT_MS 2 42 43 /* FBC, or Frame Buffer Compression, is a technique employed to compress the 44 * framebuffer contents in-memory, aiming at reducing the required bandwidth 45 * during in-memory transfers and, therefore, reduce the power packet. 46 * 47 * The benefits of FBC are mostly visible with solid backgrounds and 48 * variation-less patterns. 49 * 50 * FBC-related functionality can be enabled by the means of the 51 * i915.i915_enable_fbc parameter 52 */ 53 54 static bool intel_crtc_active(struct drm_crtc *crtc) 55 { 56 /* Be paranoid as we can arrive here with only partial 57 * state retrieved from the hardware during setup. 58 */ 59 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; 60 } 61 62 static void i8xx_disable_fbc(struct drm_device *dev) 63 { 64 struct drm_i915_private *dev_priv = dev->dev_private; 65 u32 fbc_ctl; 66 67 /* Disable compression */ 68 fbc_ctl = I915_READ(FBC_CONTROL); 69 if ((fbc_ctl & FBC_CTL_EN) == 0) 70 return; 71 72 fbc_ctl &= ~FBC_CTL_EN; 73 I915_WRITE(FBC_CONTROL, fbc_ctl); 74 75 /* Wait for compressing bit to clear */ 76 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 77 DRM_DEBUG_KMS("FBC idle timed out\n"); 78 return; 79 } 80 81 DRM_DEBUG_KMS("disabled FBC\n"); 82 } 83 84 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 85 { 86 struct drm_device *dev = crtc->dev; 87 struct drm_i915_private *dev_priv = dev->dev_private; 88 struct drm_framebuffer *fb = crtc->fb; 89 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 90 struct drm_i915_gem_object *obj = intel_fb->obj; 91 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 92 int cfb_pitch; 93 int plane, i; 94 u32 fbc_ctl, fbc_ctl2; 95 96 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; 97 if (fb->pitches[0] < cfb_pitch) 98 cfb_pitch = fb->pitches[0]; 99 100 /* FBC_CTL wants 64B units */ 101 cfb_pitch = (cfb_pitch / 64) - 1; 102 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; 103 104 /* Clear old tags */ 105 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 106 I915_WRITE(FBC_TAG + (i * 4), 0); 107 108 /* Set it up... */ 109 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 110 fbc_ctl2 |= plane; 111 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 112 I915_WRITE(FBC_FENCE_OFF, crtc->y); 113 114 /* enable it... */ 115 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 116 if (IS_I945GM(dev)) 117 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 118 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 119 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 120 fbc_ctl |= obj->fence_reg; 121 I915_WRITE(FBC_CONTROL, fbc_ctl); 122 123 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 124 cfb_pitch, crtc->y, intel_crtc->plane); 125 } 126 127 static bool i8xx_fbc_enabled(struct drm_device *dev) 128 { 129 struct drm_i915_private *dev_priv = dev->dev_private; 130 131 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 132 } 133 134 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 135 { 136 struct drm_device *dev = crtc->dev; 137 struct drm_i915_private *dev_priv = dev->dev_private; 138 struct drm_framebuffer *fb = crtc->fb; 139 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 140 struct drm_i915_gem_object *obj = intel_fb->obj; 141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 142 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 143 unsigned long stall_watermark = 200; 144 u32 dpfc_ctl; 145 146 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 147 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 148 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); 149 150 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 151 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 152 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 153 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 154 155 /* enable it... */ 156 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 157 158 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 159 } 160 161 static void g4x_disable_fbc(struct drm_device *dev) 162 { 163 struct drm_i915_private *dev_priv = dev->dev_private; 164 u32 dpfc_ctl; 165 166 /* Disable compression */ 167 dpfc_ctl = I915_READ(DPFC_CONTROL); 168 if (dpfc_ctl & DPFC_CTL_EN) { 169 dpfc_ctl &= ~DPFC_CTL_EN; 170 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 171 172 DRM_DEBUG_KMS("disabled FBC\n"); 173 } 174 } 175 176 static bool g4x_fbc_enabled(struct drm_device *dev) 177 { 178 struct drm_i915_private *dev_priv = dev->dev_private; 179 180 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 181 } 182 183 static void sandybridge_blit_fbc_update(struct drm_device *dev) 184 { 185 struct drm_i915_private *dev_priv = dev->dev_private; 186 u32 blt_ecoskpd; 187 188 /* Make sure blitter notifies FBC of writes */ 189 gen6_gt_force_wake_get(dev_priv); 190 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 191 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 192 GEN6_BLITTER_LOCK_SHIFT; 193 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 194 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 195 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 196 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 197 GEN6_BLITTER_LOCK_SHIFT); 198 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 199 POSTING_READ(GEN6_BLITTER_ECOSKPD); 200 gen6_gt_force_wake_put(dev_priv); 201 } 202 203 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 204 { 205 struct drm_device *dev = crtc->dev; 206 struct drm_i915_private *dev_priv = dev->dev_private; 207 struct drm_framebuffer *fb = crtc->fb; 208 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 209 struct drm_i915_gem_object *obj = intel_fb->obj; 210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 211 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 212 unsigned long stall_watermark = 200; 213 u32 dpfc_ctl; 214 215 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 216 dpfc_ctl &= DPFC_RESERVED; 217 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 218 /* Set persistent mode for front-buffer rendering, ala X. */ 219 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 220 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 221 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 222 223 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 224 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 225 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 226 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 227 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 228 /* enable it... */ 229 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 230 231 if (IS_GEN6(dev)) { 232 I915_WRITE(SNB_DPFC_CTL_SA, 233 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 234 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 235 sandybridge_blit_fbc_update(dev); 236 } 237 238 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 239 } 240 241 static void ironlake_disable_fbc(struct drm_device *dev) 242 { 243 struct drm_i915_private *dev_priv = dev->dev_private; 244 u32 dpfc_ctl; 245 246 /* Disable compression */ 247 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 248 if (dpfc_ctl & DPFC_CTL_EN) { 249 dpfc_ctl &= ~DPFC_CTL_EN; 250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 251 252 DRM_DEBUG_KMS("disabled FBC\n"); 253 } 254 } 255 256 static bool ironlake_fbc_enabled(struct drm_device *dev) 257 { 258 struct drm_i915_private *dev_priv = dev->dev_private; 259 260 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 261 } 262 263 bool intel_fbc_enabled(struct drm_device *dev) 264 { 265 struct drm_i915_private *dev_priv = dev->dev_private; 266 267 if (!dev_priv->display.fbc_enabled) 268 return false; 269 270 return dev_priv->display.fbc_enabled(dev); 271 } 272 273 static void intel_fbc_work_fn(struct work_struct *__work) 274 { 275 struct intel_fbc_work *work = 276 container_of(to_delayed_work(__work), 277 struct intel_fbc_work, work); 278 struct drm_device *dev = work->crtc->dev; 279 struct drm_i915_private *dev_priv = dev->dev_private; 280 281 mutex_lock(&dev->struct_mutex); 282 if (work == dev_priv->fbc_work) { 283 /* Double check that we haven't switched fb without cancelling 284 * the prior work. 285 */ 286 if (work->crtc->fb == work->fb) { 287 dev_priv->display.enable_fbc(work->crtc, 288 work->interval); 289 290 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; 291 dev_priv->cfb_fb = work->crtc->fb->base.id; 292 dev_priv->cfb_y = work->crtc->y; 293 } 294 295 dev_priv->fbc_work = NULL; 296 } 297 mutex_unlock(&dev->struct_mutex); 298 299 kfree(work); 300 } 301 302 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 303 { 304 if (dev_priv->fbc_work == NULL) 305 return; 306 307 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 308 309 /* Synchronisation is provided by struct_mutex and checking of 310 * dev_priv->fbc_work, so we can perform the cancellation 311 * entirely asynchronously. 312 */ 313 if (cancel_delayed_work(&dev_priv->fbc_work->work)) 314 /* tasklet was killed before being run, clean up */ 315 kfree(dev_priv->fbc_work); 316 317 /* Mark the work as no longer wanted so that if it does 318 * wake-up (because the work was already running and waiting 319 * for our mutex), it will discover that is no longer 320 * necessary to run. 321 */ 322 dev_priv->fbc_work = NULL; 323 } 324 325 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 326 { 327 struct intel_fbc_work *work; 328 struct drm_device *dev = crtc->dev; 329 struct drm_i915_private *dev_priv = dev->dev_private; 330 331 if (!dev_priv->display.enable_fbc) 332 return; 333 334 intel_cancel_fbc_work(dev_priv); 335 336 work = kzalloc(sizeof *work, GFP_KERNEL); 337 if (work == NULL) { 338 dev_priv->display.enable_fbc(crtc, interval); 339 return; 340 } 341 342 work->crtc = crtc; 343 work->fb = crtc->fb; 344 work->interval = interval; 345 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 346 347 dev_priv->fbc_work = work; 348 349 DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); 350 351 /* Delay the actual enabling to let pageflipping cease and the 352 * display to settle before starting the compression. Note that 353 * this delay also serves a second purpose: it allows for a 354 * vblank to pass after disabling the FBC before we attempt 355 * to modify the control registers. 356 * 357 * A more complicated solution would involve tracking vblanks 358 * following the termination of the page-flipping sequence 359 * and indeed performing the enable as a co-routine and not 360 * waiting synchronously upon the vblank. 361 */ 362 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 363 } 364 365 void intel_disable_fbc(struct drm_device *dev) 366 { 367 struct drm_i915_private *dev_priv = dev->dev_private; 368 369 intel_cancel_fbc_work(dev_priv); 370 371 if (!dev_priv->display.disable_fbc) 372 return; 373 374 dev_priv->display.disable_fbc(dev); 375 dev_priv->cfb_plane = -1; 376 } 377 378 /** 379 * intel_update_fbc - enable/disable FBC as needed 380 * @dev: the drm_device 381 * 382 * Set up the framebuffer compression hardware at mode set time. We 383 * enable it if possible: 384 * - plane A only (on pre-965) 385 * - no pixel mulitply/line duplication 386 * - no alpha buffer discard 387 * - no dual wide 388 * - framebuffer <= 2048 in width, 1536 in height 389 * 390 * We can't assume that any compression will take place (worst case), 391 * so the compressed buffer has to be the same size as the uncompressed 392 * one. It also must reside (along with the line length buffer) in 393 * stolen memory. 394 * 395 * We need to enable/disable FBC on a global basis. 396 */ 397 void intel_update_fbc(struct drm_device *dev) 398 { 399 struct drm_i915_private *dev_priv = dev->dev_private; 400 struct drm_crtc *crtc = NULL, *tmp_crtc; 401 struct intel_crtc *intel_crtc; 402 struct drm_framebuffer *fb; 403 struct intel_framebuffer *intel_fb; 404 struct drm_i915_gem_object *obj; 405 int enable_fbc; 406 407 if (!i915_powersave) 408 return; 409 410 if (!I915_HAS_FBC(dev)) 411 return; 412 413 /* 414 * If FBC is already on, we just have to verify that we can 415 * keep it that way... 416 * Need to disable if: 417 * - more than one pipe is active 418 * - changing FBC params (stride, fence, mode) 419 * - new fb is too large to fit in compressed buffer 420 * - going to an unsupported config (interlace, pixel multiply, etc.) 421 */ 422 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 423 if (intel_crtc_active(tmp_crtc) && 424 !to_intel_crtc(tmp_crtc)->primary_disabled) { 425 if (crtc) { 426 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 427 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 428 goto out_disable; 429 } 430 crtc = tmp_crtc; 431 } 432 } 433 434 if (!crtc || crtc->fb == NULL) { 435 DRM_DEBUG_KMS("no output, disabling\n"); 436 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; 437 goto out_disable; 438 } 439 440 intel_crtc = to_intel_crtc(crtc); 441 fb = crtc->fb; 442 intel_fb = to_intel_framebuffer(fb); 443 obj = intel_fb->obj; 444 445 enable_fbc = i915_enable_fbc; 446 if (enable_fbc < 0) { 447 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 448 enable_fbc = 1; 449 if (INTEL_INFO(dev)->gen <= 6) 450 enable_fbc = 0; 451 } 452 if (!enable_fbc) { 453 DRM_DEBUG_KMS("fbc disabled per module param\n"); 454 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; 455 goto out_disable; 456 } 457 if (intel_fb->obj->base.size > dev_priv->cfb_size) { 458 DRM_DEBUG_KMS("framebuffer too large, disabling " 459 "compression\n"); 460 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 461 goto out_disable; 462 } 463 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || 464 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { 465 DRM_DEBUG_KMS("mode incompatible with compression, " 466 "disabling\n"); 467 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 468 goto out_disable; 469 } 470 if ((crtc->mode.hdisplay > 2048) || 471 (crtc->mode.vdisplay > 1536)) { 472 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 473 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 474 goto out_disable; 475 } 476 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { 477 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 478 dev_priv->no_fbc_reason = FBC_BAD_PLANE; 479 goto out_disable; 480 } 481 482 /* The use of a CPU fence is mandatory in order to detect writes 483 * by the CPU to the scanout and trigger updates to the FBC. 484 */ 485 if (obj->tiling_mode != I915_TILING_X || 486 obj->fence_reg == I915_FENCE_REG_NONE) { 487 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 488 dev_priv->no_fbc_reason = FBC_NOT_TILED; 489 goto out_disable; 490 } 491 492 /* If the kernel debugger is active, always disable compression */ 493 if (in_dbg_master()) 494 goto out_disable; 495 496 /* If the scanout has not changed, don't modify the FBC settings. 497 * Note that we make the fundamental assumption that the fb->obj 498 * cannot be unpinned (and have its GTT offset and fence revoked) 499 * without first being decoupled from the scanout and FBC disabled. 500 */ 501 if (dev_priv->cfb_plane == intel_crtc->plane && 502 dev_priv->cfb_fb == fb->base.id && 503 dev_priv->cfb_y == crtc->y) 504 return; 505 506 if (intel_fbc_enabled(dev)) { 507 /* We update FBC along two paths, after changing fb/crtc 508 * configuration (modeswitching) and after page-flipping 509 * finishes. For the latter, we know that not only did 510 * we disable the FBC at the start of the page-flip 511 * sequence, but also more than one vblank has passed. 512 * 513 * For the former case of modeswitching, it is possible 514 * to switch between two FBC valid configurations 515 * instantaneously so we do need to disable the FBC 516 * before we can modify its control registers. We also 517 * have to wait for the next vblank for that to take 518 * effect. However, since we delay enabling FBC we can 519 * assume that a vblank has passed since disabling and 520 * that we can safely alter the registers in the deferred 521 * callback. 522 * 523 * In the scenario that we go from a valid to invalid 524 * and then back to valid FBC configuration we have 525 * no strict enforcement that a vblank occurred since 526 * disabling the FBC. However, along all current pipe 527 * disabling paths we do need to wait for a vblank at 528 * some point. And we wait before enabling FBC anyway. 529 */ 530 DRM_DEBUG_KMS("disabling active FBC for update\n"); 531 intel_disable_fbc(dev); 532 } 533 534 intel_enable_fbc(crtc, 500); 535 return; 536 537 out_disable: 538 /* Multiple disables should be harmless */ 539 if (intel_fbc_enabled(dev)) { 540 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 541 intel_disable_fbc(dev); 542 } 543 } 544 545 static void i915_pineview_get_mem_freq(struct drm_device *dev) 546 { 547 drm_i915_private_t *dev_priv = dev->dev_private; 548 u32 tmp; 549 550 tmp = I915_READ(CLKCFG); 551 552 switch (tmp & CLKCFG_FSB_MASK) { 553 case CLKCFG_FSB_533: 554 dev_priv->fsb_freq = 533; /* 133*4 */ 555 break; 556 case CLKCFG_FSB_800: 557 dev_priv->fsb_freq = 800; /* 200*4 */ 558 break; 559 case CLKCFG_FSB_667: 560 dev_priv->fsb_freq = 667; /* 167*4 */ 561 break; 562 case CLKCFG_FSB_400: 563 dev_priv->fsb_freq = 400; /* 100*4 */ 564 break; 565 } 566 567 switch (tmp & CLKCFG_MEM_MASK) { 568 case CLKCFG_MEM_533: 569 dev_priv->mem_freq = 533; 570 break; 571 case CLKCFG_MEM_667: 572 dev_priv->mem_freq = 667; 573 break; 574 case CLKCFG_MEM_800: 575 dev_priv->mem_freq = 800; 576 break; 577 } 578 579 /* detect pineview DDR3 setting */ 580 tmp = I915_READ(CSHRDDR3CTL); 581 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 582 } 583 584 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 585 { 586 drm_i915_private_t *dev_priv = dev->dev_private; 587 u16 ddrpll, csipll; 588 589 ddrpll = I915_READ16(DDRMPLL1); 590 csipll = I915_READ16(CSIPLL0); 591 592 switch (ddrpll & 0xff) { 593 case 0xc: 594 dev_priv->mem_freq = 800; 595 break; 596 case 0x10: 597 dev_priv->mem_freq = 1066; 598 break; 599 case 0x14: 600 dev_priv->mem_freq = 1333; 601 break; 602 case 0x18: 603 dev_priv->mem_freq = 1600; 604 break; 605 default: 606 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 607 ddrpll & 0xff); 608 dev_priv->mem_freq = 0; 609 break; 610 } 611 612 dev_priv->ips.r_t = dev_priv->mem_freq; 613 614 switch (csipll & 0x3ff) { 615 case 0x00c: 616 dev_priv->fsb_freq = 3200; 617 break; 618 case 0x00e: 619 dev_priv->fsb_freq = 3733; 620 break; 621 case 0x010: 622 dev_priv->fsb_freq = 4266; 623 break; 624 case 0x012: 625 dev_priv->fsb_freq = 4800; 626 break; 627 case 0x014: 628 dev_priv->fsb_freq = 5333; 629 break; 630 case 0x016: 631 dev_priv->fsb_freq = 5866; 632 break; 633 case 0x018: 634 dev_priv->fsb_freq = 6400; 635 break; 636 default: 637 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 638 csipll & 0x3ff); 639 dev_priv->fsb_freq = 0; 640 break; 641 } 642 643 if (dev_priv->fsb_freq == 3200) { 644 dev_priv->ips.c_m = 0; 645 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 646 dev_priv->ips.c_m = 1; 647 } else { 648 dev_priv->ips.c_m = 2; 649 } 650 } 651 652 static const struct cxsr_latency cxsr_latency_table[] = { 653 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 654 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 655 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 656 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 657 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 658 659 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 660 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 661 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 662 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 663 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 664 665 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 666 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 667 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 668 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 669 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 670 671 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 672 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 673 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 674 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 675 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 676 677 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 678 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 679 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 680 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 681 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 682 683 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 684 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 685 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 686 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 687 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 688 }; 689 690 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 691 int is_ddr3, 692 int fsb, 693 int mem) 694 { 695 const struct cxsr_latency *latency; 696 int i; 697 698 if (fsb == 0 || mem == 0) 699 return NULL; 700 701 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 702 latency = &cxsr_latency_table[i]; 703 if (is_desktop == latency->is_desktop && 704 is_ddr3 == latency->is_ddr3 && 705 fsb == latency->fsb_freq && mem == latency->mem_freq) 706 return latency; 707 } 708 709 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 710 711 return NULL; 712 } 713 714 static void pineview_disable_cxsr(struct drm_device *dev) 715 { 716 struct drm_i915_private *dev_priv = dev->dev_private; 717 718 /* deactivate cxsr */ 719 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 720 } 721 722 /* 723 * Latency for FIFO fetches is dependent on several factors: 724 * - memory configuration (speed, channels) 725 * - chipset 726 * - current MCH state 727 * It can be fairly high in some situations, so here we assume a fairly 728 * pessimal value. It's a tradeoff between extra memory fetches (if we 729 * set this value too high, the FIFO will fetch frequently to stay full) 730 * and power consumption (set it too low to save power and we might see 731 * FIFO underruns and display "flicker"). 732 * 733 * A value of 5us seems to be a good balance; safe for very low end 734 * platforms but not overly aggressive on lower latency configs. 735 */ 736 static const int latency_ns = 5000; 737 738 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 739 { 740 struct drm_i915_private *dev_priv = dev->dev_private; 741 uint32_t dsparb = I915_READ(DSPARB); 742 int size; 743 744 size = dsparb & 0x7f; 745 if (plane) 746 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 747 748 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 749 plane ? "B" : "A", size); 750 751 return size; 752 } 753 754 static int i85x_get_fifo_size(struct drm_device *dev, int plane) 755 { 756 struct drm_i915_private *dev_priv = dev->dev_private; 757 uint32_t dsparb = I915_READ(DSPARB); 758 int size; 759 760 size = dsparb & 0x1ff; 761 if (plane) 762 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 763 size >>= 1; /* Convert to cachelines */ 764 765 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 766 plane ? "B" : "A", size); 767 768 return size; 769 } 770 771 static int i845_get_fifo_size(struct drm_device *dev, int plane) 772 { 773 struct drm_i915_private *dev_priv = dev->dev_private; 774 uint32_t dsparb = I915_READ(DSPARB); 775 int size; 776 777 size = dsparb & 0x7f; 778 size >>= 2; /* Convert to cachelines */ 779 780 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 781 plane ? "B" : "A", 782 size); 783 784 return size; 785 } 786 787 static int i830_get_fifo_size(struct drm_device *dev, int plane) 788 { 789 struct drm_i915_private *dev_priv = dev->dev_private; 790 uint32_t dsparb = I915_READ(DSPARB); 791 int size; 792 793 size = dsparb & 0x7f; 794 size >>= 1; /* Convert to cachelines */ 795 796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 797 plane ? "B" : "A", size); 798 799 return size; 800 } 801 802 /* Pineview has different values for various configs */ 803 static const struct intel_watermark_params pineview_display_wm = { 804 PINEVIEW_DISPLAY_FIFO, 805 PINEVIEW_MAX_WM, 806 PINEVIEW_DFT_WM, 807 PINEVIEW_GUARD_WM, 808 PINEVIEW_FIFO_LINE_SIZE 809 }; 810 static const struct intel_watermark_params pineview_display_hplloff_wm = { 811 PINEVIEW_DISPLAY_FIFO, 812 PINEVIEW_MAX_WM, 813 PINEVIEW_DFT_HPLLOFF_WM, 814 PINEVIEW_GUARD_WM, 815 PINEVIEW_FIFO_LINE_SIZE 816 }; 817 static const struct intel_watermark_params pineview_cursor_wm = { 818 PINEVIEW_CURSOR_FIFO, 819 PINEVIEW_CURSOR_MAX_WM, 820 PINEVIEW_CURSOR_DFT_WM, 821 PINEVIEW_CURSOR_GUARD_WM, 822 PINEVIEW_FIFO_LINE_SIZE, 823 }; 824 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 825 PINEVIEW_CURSOR_FIFO, 826 PINEVIEW_CURSOR_MAX_WM, 827 PINEVIEW_CURSOR_DFT_WM, 828 PINEVIEW_CURSOR_GUARD_WM, 829 PINEVIEW_FIFO_LINE_SIZE 830 }; 831 static const struct intel_watermark_params g4x_wm_info = { 832 G4X_FIFO_SIZE, 833 G4X_MAX_WM, 834 G4X_MAX_WM, 835 2, 836 G4X_FIFO_LINE_SIZE, 837 }; 838 static const struct intel_watermark_params g4x_cursor_wm_info = { 839 I965_CURSOR_FIFO, 840 I965_CURSOR_MAX_WM, 841 I965_CURSOR_DFT_WM, 842 2, 843 G4X_FIFO_LINE_SIZE, 844 }; 845 static const struct intel_watermark_params valleyview_wm_info = { 846 VALLEYVIEW_FIFO_SIZE, 847 VALLEYVIEW_MAX_WM, 848 VALLEYVIEW_MAX_WM, 849 2, 850 G4X_FIFO_LINE_SIZE, 851 }; 852 static const struct intel_watermark_params valleyview_cursor_wm_info = { 853 I965_CURSOR_FIFO, 854 VALLEYVIEW_CURSOR_MAX_WM, 855 I965_CURSOR_DFT_WM, 856 2, 857 G4X_FIFO_LINE_SIZE, 858 }; 859 static const struct intel_watermark_params i965_cursor_wm_info = { 860 I965_CURSOR_FIFO, 861 I965_CURSOR_MAX_WM, 862 I965_CURSOR_DFT_WM, 863 2, 864 I915_FIFO_LINE_SIZE, 865 }; 866 static const struct intel_watermark_params i945_wm_info = { 867 I945_FIFO_SIZE, 868 I915_MAX_WM, 869 1, 870 2, 871 I915_FIFO_LINE_SIZE 872 }; 873 static const struct intel_watermark_params i915_wm_info = { 874 I915_FIFO_SIZE, 875 I915_MAX_WM, 876 1, 877 2, 878 I915_FIFO_LINE_SIZE 879 }; 880 static const struct intel_watermark_params i855_wm_info = { 881 I855GM_FIFO_SIZE, 882 I915_MAX_WM, 883 1, 884 2, 885 I830_FIFO_LINE_SIZE 886 }; 887 static const struct intel_watermark_params i830_wm_info = { 888 I830_FIFO_SIZE, 889 I915_MAX_WM, 890 1, 891 2, 892 I830_FIFO_LINE_SIZE 893 }; 894 895 static const struct intel_watermark_params ironlake_display_wm_info = { 896 ILK_DISPLAY_FIFO, 897 ILK_DISPLAY_MAXWM, 898 ILK_DISPLAY_DFTWM, 899 2, 900 ILK_FIFO_LINE_SIZE 901 }; 902 static const struct intel_watermark_params ironlake_cursor_wm_info = { 903 ILK_CURSOR_FIFO, 904 ILK_CURSOR_MAXWM, 905 ILK_CURSOR_DFTWM, 906 2, 907 ILK_FIFO_LINE_SIZE 908 }; 909 static const struct intel_watermark_params ironlake_display_srwm_info = { 910 ILK_DISPLAY_SR_FIFO, 911 ILK_DISPLAY_MAX_SRWM, 912 ILK_DISPLAY_DFT_SRWM, 913 2, 914 ILK_FIFO_LINE_SIZE 915 }; 916 static const struct intel_watermark_params ironlake_cursor_srwm_info = { 917 ILK_CURSOR_SR_FIFO, 918 ILK_CURSOR_MAX_SRWM, 919 ILK_CURSOR_DFT_SRWM, 920 2, 921 ILK_FIFO_LINE_SIZE 922 }; 923 924 static const struct intel_watermark_params sandybridge_display_wm_info = { 925 SNB_DISPLAY_FIFO, 926 SNB_DISPLAY_MAXWM, 927 SNB_DISPLAY_DFTWM, 928 2, 929 SNB_FIFO_LINE_SIZE 930 }; 931 static const struct intel_watermark_params sandybridge_cursor_wm_info = { 932 SNB_CURSOR_FIFO, 933 SNB_CURSOR_MAXWM, 934 SNB_CURSOR_DFTWM, 935 2, 936 SNB_FIFO_LINE_SIZE 937 }; 938 static const struct intel_watermark_params sandybridge_display_srwm_info = { 939 SNB_DISPLAY_SR_FIFO, 940 SNB_DISPLAY_MAX_SRWM, 941 SNB_DISPLAY_DFT_SRWM, 942 2, 943 SNB_FIFO_LINE_SIZE 944 }; 945 static const struct intel_watermark_params sandybridge_cursor_srwm_info = { 946 SNB_CURSOR_SR_FIFO, 947 SNB_CURSOR_MAX_SRWM, 948 SNB_CURSOR_DFT_SRWM, 949 2, 950 SNB_FIFO_LINE_SIZE 951 }; 952 953 954 /** 955 * intel_calculate_wm - calculate watermark level 956 * @clock_in_khz: pixel clock 957 * @wm: chip FIFO params 958 * @pixel_size: display pixel size 959 * @latency_ns: memory latency for the platform 960 * 961 * Calculate the watermark level (the level at which the display plane will 962 * start fetching from memory again). Each chip has a different display 963 * FIFO size and allocation, so the caller needs to figure that out and pass 964 * in the correct intel_watermark_params structure. 965 * 966 * As the pixel clock runs, the FIFO will be drained at a rate that depends 967 * on the pixel size. When it reaches the watermark level, it'll start 968 * fetching FIFO line sized based chunks from memory until the FIFO fills 969 * past the watermark point. If the FIFO drains completely, a FIFO underrun 970 * will occur, and a display engine hang could result. 971 */ 972 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 973 const struct intel_watermark_params *wm, 974 int fifo_size, 975 int pixel_size, 976 unsigned long latency_ns) 977 { 978 long entries_required, wm_size; 979 980 /* 981 * Note: we need to make sure we don't overflow for various clock & 982 * latency values. 983 * clocks go from a few thousand to several hundred thousand. 984 * latency is usually a few thousand 985 */ 986 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 987 1000; 988 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 989 990 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 991 992 wm_size = fifo_size - (entries_required + wm->guard_size); 993 994 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 995 996 /* Don't promote wm_size to unsigned... */ 997 if (wm_size > (long)wm->max_wm) 998 wm_size = wm->max_wm; 999 if (wm_size <= 0) 1000 wm_size = wm->default_wm; 1001 return wm_size; 1002 } 1003 1004 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 1005 { 1006 struct drm_crtc *crtc, *enabled = NULL; 1007 1008 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1009 if (intel_crtc_active(crtc)) { 1010 if (enabled) 1011 return NULL; 1012 enabled = crtc; 1013 } 1014 } 1015 1016 return enabled; 1017 } 1018 1019 static void pineview_update_wm(struct drm_device *dev) 1020 { 1021 struct drm_i915_private *dev_priv = dev->dev_private; 1022 struct drm_crtc *crtc; 1023 const struct cxsr_latency *latency; 1024 u32 reg; 1025 unsigned long wm; 1026 1027 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 1028 dev_priv->fsb_freq, dev_priv->mem_freq); 1029 if (!latency) { 1030 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 1031 pineview_disable_cxsr(dev); 1032 return; 1033 } 1034 1035 crtc = single_enabled_crtc(dev); 1036 if (crtc) { 1037 int clock = crtc->mode.clock; 1038 int pixel_size = crtc->fb->bits_per_pixel / 8; 1039 1040 /* Display SR */ 1041 wm = intel_calculate_wm(clock, &pineview_display_wm, 1042 pineview_display_wm.fifo_size, 1043 pixel_size, latency->display_sr); 1044 reg = I915_READ(DSPFW1); 1045 reg &= ~DSPFW_SR_MASK; 1046 reg |= wm << DSPFW_SR_SHIFT; 1047 I915_WRITE(DSPFW1, reg); 1048 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1049 1050 /* cursor SR */ 1051 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1052 pineview_display_wm.fifo_size, 1053 pixel_size, latency->cursor_sr); 1054 reg = I915_READ(DSPFW3); 1055 reg &= ~DSPFW_CURSOR_SR_MASK; 1056 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1057 I915_WRITE(DSPFW3, reg); 1058 1059 /* Display HPLL off SR */ 1060 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1061 pineview_display_hplloff_wm.fifo_size, 1062 pixel_size, latency->display_hpll_disable); 1063 reg = I915_READ(DSPFW3); 1064 reg &= ~DSPFW_HPLL_SR_MASK; 1065 reg |= wm & DSPFW_HPLL_SR_MASK; 1066 I915_WRITE(DSPFW3, reg); 1067 1068 /* cursor HPLL off SR */ 1069 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1070 pineview_display_hplloff_wm.fifo_size, 1071 pixel_size, latency->cursor_hpll_disable); 1072 reg = I915_READ(DSPFW3); 1073 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1074 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1075 I915_WRITE(DSPFW3, reg); 1076 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1077 1078 /* activate cxsr */ 1079 I915_WRITE(DSPFW3, 1080 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1081 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1082 } else { 1083 pineview_disable_cxsr(dev); 1084 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1085 } 1086 } 1087 1088 static bool g4x_compute_wm0(struct drm_device *dev, 1089 int plane, 1090 const struct intel_watermark_params *display, 1091 int display_latency_ns, 1092 const struct intel_watermark_params *cursor, 1093 int cursor_latency_ns, 1094 int *plane_wm, 1095 int *cursor_wm) 1096 { 1097 struct drm_crtc *crtc; 1098 int htotal, hdisplay, clock, pixel_size; 1099 int line_time_us, line_count; 1100 int entries, tlb_miss; 1101 1102 crtc = intel_get_crtc_for_plane(dev, plane); 1103 if (!intel_crtc_active(crtc)) { 1104 *cursor_wm = cursor->guard_size; 1105 *plane_wm = display->guard_size; 1106 return false; 1107 } 1108 1109 htotal = crtc->mode.htotal; 1110 hdisplay = crtc->mode.hdisplay; 1111 clock = crtc->mode.clock; 1112 pixel_size = crtc->fb->bits_per_pixel / 8; 1113 1114 /* Use the small buffer method to calculate plane watermark */ 1115 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1116 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1117 if (tlb_miss > 0) 1118 entries += tlb_miss; 1119 entries = DIV_ROUND_UP(entries, display->cacheline_size); 1120 *plane_wm = entries + display->guard_size; 1121 if (*plane_wm > (int)display->max_wm) 1122 *plane_wm = display->max_wm; 1123 1124 /* Use the large buffer method to calculate cursor watermark */ 1125 line_time_us = ((htotal * 1000) / clock); 1126 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1127 entries = line_count * 64 * pixel_size; 1128 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1129 if (tlb_miss > 0) 1130 entries += tlb_miss; 1131 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1132 *cursor_wm = entries + cursor->guard_size; 1133 if (*cursor_wm > (int)cursor->max_wm) 1134 *cursor_wm = (int)cursor->max_wm; 1135 1136 return true; 1137 } 1138 1139 /* 1140 * Check the wm result. 1141 * 1142 * If any calculated watermark values is larger than the maximum value that 1143 * can be programmed into the associated watermark register, that watermark 1144 * must be disabled. 1145 */ 1146 static bool g4x_check_srwm(struct drm_device *dev, 1147 int display_wm, int cursor_wm, 1148 const struct intel_watermark_params *display, 1149 const struct intel_watermark_params *cursor) 1150 { 1151 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1152 display_wm, cursor_wm); 1153 1154 if (display_wm > display->max_wm) { 1155 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1156 display_wm, display->max_wm); 1157 return false; 1158 } 1159 1160 if (cursor_wm > cursor->max_wm) { 1161 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1162 cursor_wm, cursor->max_wm); 1163 return false; 1164 } 1165 1166 if (!(display_wm || cursor_wm)) { 1167 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1168 return false; 1169 } 1170 1171 return true; 1172 } 1173 1174 static bool g4x_compute_srwm(struct drm_device *dev, 1175 int plane, 1176 int latency_ns, 1177 const struct intel_watermark_params *display, 1178 const struct intel_watermark_params *cursor, 1179 int *display_wm, int *cursor_wm) 1180 { 1181 struct drm_crtc *crtc; 1182 int hdisplay, htotal, pixel_size, clock; 1183 unsigned long line_time_us; 1184 int line_count, line_size; 1185 int small, large; 1186 int entries; 1187 1188 if (!latency_ns) { 1189 *display_wm = *cursor_wm = 0; 1190 return false; 1191 } 1192 1193 crtc = intel_get_crtc_for_plane(dev, plane); 1194 hdisplay = crtc->mode.hdisplay; 1195 htotal = crtc->mode.htotal; 1196 clock = crtc->mode.clock; 1197 pixel_size = crtc->fb->bits_per_pixel / 8; 1198 1199 line_time_us = (htotal * 1000) / clock; 1200 line_count = (latency_ns / line_time_us + 1000) / 1000; 1201 line_size = hdisplay * pixel_size; 1202 1203 /* Use the minimum of the small and large buffer method for primary */ 1204 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1205 large = line_count * line_size; 1206 1207 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1208 *display_wm = entries + display->guard_size; 1209 1210 /* calculate the self-refresh watermark for display cursor */ 1211 entries = line_count * pixel_size * 64; 1212 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1213 *cursor_wm = entries + cursor->guard_size; 1214 1215 return g4x_check_srwm(dev, 1216 *display_wm, *cursor_wm, 1217 display, cursor); 1218 } 1219 1220 static bool vlv_compute_drain_latency(struct drm_device *dev, 1221 int plane, 1222 int *plane_prec_mult, 1223 int *plane_dl, 1224 int *cursor_prec_mult, 1225 int *cursor_dl) 1226 { 1227 struct drm_crtc *crtc; 1228 int clock, pixel_size; 1229 int entries; 1230 1231 crtc = intel_get_crtc_for_plane(dev, plane); 1232 if (!intel_crtc_active(crtc)) 1233 return false; 1234 1235 clock = crtc->mode.clock; /* VESA DOT Clock */ 1236 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ 1237 1238 entries = (clock / 1000) * pixel_size; 1239 *plane_prec_mult = (entries > 256) ? 1240 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1241 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * 1242 pixel_size); 1243 1244 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1245 *cursor_prec_mult = (entries > 256) ? 1246 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1247 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); 1248 1249 return true; 1250 } 1251 1252 /* 1253 * Update drain latency registers of memory arbiter 1254 * 1255 * Valleyview SoC has a new memory arbiter and needs drain latency registers 1256 * to be programmed. Each plane has a drain latency multiplier and a drain 1257 * latency value. 1258 */ 1259 1260 static void vlv_update_drain_latency(struct drm_device *dev) 1261 { 1262 struct drm_i915_private *dev_priv = dev->dev_private; 1263 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1264 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1265 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1266 either 16 or 32 */ 1267 1268 /* For plane A, Cursor A */ 1269 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1270 &cursor_prec_mult, &cursora_dl)) { 1271 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1272 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; 1273 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1274 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; 1275 1276 I915_WRITE(VLV_DDL1, cursora_prec | 1277 (cursora_dl << DDL_CURSORA_SHIFT) | 1278 planea_prec | planea_dl); 1279 } 1280 1281 /* For plane B, Cursor B */ 1282 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1283 &cursor_prec_mult, &cursorb_dl)) { 1284 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1285 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; 1286 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1287 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; 1288 1289 I915_WRITE(VLV_DDL2, cursorb_prec | 1290 (cursorb_dl << DDL_CURSORB_SHIFT) | 1291 planeb_prec | planeb_dl); 1292 } 1293 } 1294 1295 #define single_plane_enabled(mask) is_power_of_2(mask) 1296 1297 static void valleyview_update_wm(struct drm_device *dev) 1298 { 1299 static const int sr_latency_ns = 12000; 1300 struct drm_i915_private *dev_priv = dev->dev_private; 1301 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1302 int plane_sr, cursor_sr; 1303 int ignore_plane_sr, ignore_cursor_sr; 1304 unsigned int enabled = 0; 1305 1306 vlv_update_drain_latency(dev); 1307 1308 if (g4x_compute_wm0(dev, 0, 1309 &valleyview_wm_info, latency_ns, 1310 &valleyview_cursor_wm_info, latency_ns, 1311 &planea_wm, &cursora_wm)) 1312 enabled |= 1; 1313 1314 if (g4x_compute_wm0(dev, 1, 1315 &valleyview_wm_info, latency_ns, 1316 &valleyview_cursor_wm_info, latency_ns, 1317 &planeb_wm, &cursorb_wm)) 1318 enabled |= 2; 1319 1320 if (single_plane_enabled(enabled) && 1321 g4x_compute_srwm(dev, ffs(enabled) - 1, 1322 sr_latency_ns, 1323 &valleyview_wm_info, 1324 &valleyview_cursor_wm_info, 1325 &plane_sr, &ignore_cursor_sr) && 1326 g4x_compute_srwm(dev, ffs(enabled) - 1, 1327 2*sr_latency_ns, 1328 &valleyview_wm_info, 1329 &valleyview_cursor_wm_info, 1330 &ignore_plane_sr, &cursor_sr)) { 1331 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1332 } else { 1333 I915_WRITE(FW_BLC_SELF_VLV, 1334 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1335 plane_sr = cursor_sr = 0; 1336 } 1337 1338 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1339 planea_wm, cursora_wm, 1340 planeb_wm, cursorb_wm, 1341 plane_sr, cursor_sr); 1342 1343 I915_WRITE(DSPFW1, 1344 (plane_sr << DSPFW_SR_SHIFT) | 1345 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1346 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1347 planea_wm); 1348 I915_WRITE(DSPFW2, 1349 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1350 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1351 I915_WRITE(DSPFW3, 1352 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | 1353 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1354 } 1355 1356 static void g4x_update_wm(struct drm_device *dev) 1357 { 1358 static const int sr_latency_ns = 12000; 1359 struct drm_i915_private *dev_priv = dev->dev_private; 1360 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1361 int plane_sr, cursor_sr; 1362 unsigned int enabled = 0; 1363 1364 if (g4x_compute_wm0(dev, 0, 1365 &g4x_wm_info, latency_ns, 1366 &g4x_cursor_wm_info, latency_ns, 1367 &planea_wm, &cursora_wm)) 1368 enabled |= 1; 1369 1370 if (g4x_compute_wm0(dev, 1, 1371 &g4x_wm_info, latency_ns, 1372 &g4x_cursor_wm_info, latency_ns, 1373 &planeb_wm, &cursorb_wm)) 1374 enabled |= 2; 1375 1376 if (single_plane_enabled(enabled) && 1377 g4x_compute_srwm(dev, ffs(enabled) - 1, 1378 sr_latency_ns, 1379 &g4x_wm_info, 1380 &g4x_cursor_wm_info, 1381 &plane_sr, &cursor_sr)) { 1382 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1383 } else { 1384 I915_WRITE(FW_BLC_SELF, 1385 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1386 plane_sr = cursor_sr = 0; 1387 } 1388 1389 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1390 planea_wm, cursora_wm, 1391 planeb_wm, cursorb_wm, 1392 plane_sr, cursor_sr); 1393 1394 I915_WRITE(DSPFW1, 1395 (plane_sr << DSPFW_SR_SHIFT) | 1396 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1397 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1398 planea_wm); 1399 I915_WRITE(DSPFW2, 1400 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1401 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1402 /* HPLL off in SR has some issues on G4x... disable it */ 1403 I915_WRITE(DSPFW3, 1404 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1405 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1406 } 1407 1408 static void i965_update_wm(struct drm_device *dev) 1409 { 1410 struct drm_i915_private *dev_priv = dev->dev_private; 1411 struct drm_crtc *crtc; 1412 int srwm = 1; 1413 int cursor_sr = 16; 1414 1415 /* Calc sr entries for one plane configs */ 1416 crtc = single_enabled_crtc(dev); 1417 if (crtc) { 1418 /* self-refresh has much higher latency */ 1419 static const int sr_latency_ns = 12000; 1420 int clock = crtc->mode.clock; 1421 int htotal = crtc->mode.htotal; 1422 int hdisplay = crtc->mode.hdisplay; 1423 int pixel_size = crtc->fb->bits_per_pixel / 8; 1424 unsigned long line_time_us; 1425 int entries; 1426 1427 line_time_us = ((htotal * 1000) / clock); 1428 1429 /* Use ns/us then divide to preserve precision */ 1430 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1431 pixel_size * hdisplay; 1432 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1433 srwm = I965_FIFO_SIZE - entries; 1434 if (srwm < 0) 1435 srwm = 1; 1436 srwm &= 0x1ff; 1437 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1438 entries, srwm); 1439 1440 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1441 pixel_size * 64; 1442 entries = DIV_ROUND_UP(entries, 1443 i965_cursor_wm_info.cacheline_size); 1444 cursor_sr = i965_cursor_wm_info.fifo_size - 1445 (entries + i965_cursor_wm_info.guard_size); 1446 1447 if (cursor_sr > i965_cursor_wm_info.max_wm) 1448 cursor_sr = i965_cursor_wm_info.max_wm; 1449 1450 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1451 "cursor %d\n", srwm, cursor_sr); 1452 1453 if (IS_CRESTLINE(dev)) 1454 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1455 } else { 1456 /* Turn off self refresh if both pipes are enabled */ 1457 if (IS_CRESTLINE(dev)) 1458 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1459 & ~FW_BLC_SELF_EN); 1460 } 1461 1462 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1463 srwm); 1464 1465 /* 965 has limitations... */ 1466 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1467 (8 << 16) | (8 << 8) | (8 << 0)); 1468 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1469 /* update cursor SR watermark */ 1470 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1471 } 1472 1473 static void i9xx_update_wm(struct drm_device *dev) 1474 { 1475 struct drm_i915_private *dev_priv = dev->dev_private; 1476 const struct intel_watermark_params *wm_info; 1477 uint32_t fwater_lo; 1478 uint32_t fwater_hi; 1479 int cwm, srwm = 1; 1480 int fifo_size; 1481 int planea_wm, planeb_wm; 1482 struct drm_crtc *crtc, *enabled = NULL; 1483 1484 if (IS_I945GM(dev)) 1485 wm_info = &i945_wm_info; 1486 else if (!IS_GEN2(dev)) 1487 wm_info = &i915_wm_info; 1488 else 1489 wm_info = &i855_wm_info; 1490 1491 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1492 crtc = intel_get_crtc_for_plane(dev, 0); 1493 if (intel_crtc_active(crtc)) { 1494 int cpp = crtc->fb->bits_per_pixel / 8; 1495 if (IS_GEN2(dev)) 1496 cpp = 4; 1497 1498 planea_wm = intel_calculate_wm(crtc->mode.clock, 1499 wm_info, fifo_size, cpp, 1500 latency_ns); 1501 enabled = crtc; 1502 } else 1503 planea_wm = fifo_size - wm_info->guard_size; 1504 1505 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1506 crtc = intel_get_crtc_for_plane(dev, 1); 1507 if (intel_crtc_active(crtc)) { 1508 int cpp = crtc->fb->bits_per_pixel / 8; 1509 if (IS_GEN2(dev)) 1510 cpp = 4; 1511 1512 planeb_wm = intel_calculate_wm(crtc->mode.clock, 1513 wm_info, fifo_size, cpp, 1514 latency_ns); 1515 if (enabled == NULL) 1516 enabled = crtc; 1517 else 1518 enabled = NULL; 1519 } else 1520 planeb_wm = fifo_size - wm_info->guard_size; 1521 1522 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1523 1524 /* 1525 * Overlay gets an aggressive default since video jitter is bad. 1526 */ 1527 cwm = 2; 1528 1529 /* Play safe and disable self-refresh before adjusting watermarks. */ 1530 if (IS_I945G(dev) || IS_I945GM(dev)) 1531 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1532 else if (IS_I915GM(dev)) 1533 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); 1534 1535 /* Calc sr entries for one plane configs */ 1536 if (HAS_FW_BLC(dev) && enabled) { 1537 /* self-refresh has much higher latency */ 1538 static const int sr_latency_ns = 6000; 1539 int clock = enabled->mode.clock; 1540 int htotal = enabled->mode.htotal; 1541 int hdisplay = enabled->mode.hdisplay; 1542 int pixel_size = enabled->fb->bits_per_pixel / 8; 1543 unsigned long line_time_us; 1544 int entries; 1545 1546 line_time_us = (htotal * 1000) / clock; 1547 1548 /* Use ns/us then divide to preserve precision */ 1549 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1550 pixel_size * hdisplay; 1551 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1552 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1553 srwm = wm_info->fifo_size - entries; 1554 if (srwm < 0) 1555 srwm = 1; 1556 1557 if (IS_I945G(dev) || IS_I945GM(dev)) 1558 I915_WRITE(FW_BLC_SELF, 1559 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1560 else if (IS_I915GM(dev)) 1561 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1562 } 1563 1564 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1565 planea_wm, planeb_wm, cwm, srwm); 1566 1567 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1568 fwater_hi = (cwm & 0x1f); 1569 1570 /* Set request length to 8 cachelines per fetch */ 1571 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1572 fwater_hi = fwater_hi | (1 << 8); 1573 1574 I915_WRITE(FW_BLC, fwater_lo); 1575 I915_WRITE(FW_BLC2, fwater_hi); 1576 1577 if (HAS_FW_BLC(dev)) { 1578 if (enabled) { 1579 if (IS_I945G(dev) || IS_I945GM(dev)) 1580 I915_WRITE(FW_BLC_SELF, 1581 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1582 else if (IS_I915GM(dev)) 1583 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); 1584 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1585 } else 1586 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1587 } 1588 } 1589 1590 static void i830_update_wm(struct drm_device *dev) 1591 { 1592 struct drm_i915_private *dev_priv = dev->dev_private; 1593 struct drm_crtc *crtc; 1594 uint32_t fwater_lo; 1595 int planea_wm; 1596 1597 crtc = single_enabled_crtc(dev); 1598 if (crtc == NULL) 1599 return; 1600 1601 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, 1602 dev_priv->display.get_fifo_size(dev, 0), 1603 4, latency_ns); 1604 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1605 fwater_lo |= (3<<8) | planea_wm; 1606 1607 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1608 1609 I915_WRITE(FW_BLC, fwater_lo); 1610 } 1611 1612 #define ILK_LP0_PLANE_LATENCY 700 1613 #define ILK_LP0_CURSOR_LATENCY 1300 1614 1615 /* 1616 * Check the wm result. 1617 * 1618 * If any calculated watermark values is larger than the maximum value that 1619 * can be programmed into the associated watermark register, that watermark 1620 * must be disabled. 1621 */ 1622 static bool ironlake_check_srwm(struct drm_device *dev, int level, 1623 int fbc_wm, int display_wm, int cursor_wm, 1624 const struct intel_watermark_params *display, 1625 const struct intel_watermark_params *cursor) 1626 { 1627 struct drm_i915_private *dev_priv = dev->dev_private; 1628 1629 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," 1630 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); 1631 1632 if (fbc_wm > SNB_FBC_MAX_SRWM) { 1633 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", 1634 fbc_wm, SNB_FBC_MAX_SRWM, level); 1635 1636 /* fbc has it's own way to disable FBC WM */ 1637 I915_WRITE(DISP_ARB_CTL, 1638 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); 1639 return false; 1640 } 1641 1642 if (display_wm > display->max_wm) { 1643 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", 1644 display_wm, SNB_DISPLAY_MAX_SRWM, level); 1645 return false; 1646 } 1647 1648 if (cursor_wm > cursor->max_wm) { 1649 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", 1650 cursor_wm, SNB_CURSOR_MAX_SRWM, level); 1651 return false; 1652 } 1653 1654 if (!(fbc_wm || display_wm || cursor_wm)) { 1655 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); 1656 return false; 1657 } 1658 1659 return true; 1660 } 1661 1662 /* 1663 * Compute watermark values of WM[1-3], 1664 */ 1665 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, 1666 int latency_ns, 1667 const struct intel_watermark_params *display, 1668 const struct intel_watermark_params *cursor, 1669 int *fbc_wm, int *display_wm, int *cursor_wm) 1670 { 1671 struct drm_crtc *crtc; 1672 unsigned long line_time_us; 1673 int hdisplay, htotal, pixel_size, clock; 1674 int line_count, line_size; 1675 int small, large; 1676 int entries; 1677 1678 if (!latency_ns) { 1679 *fbc_wm = *display_wm = *cursor_wm = 0; 1680 return false; 1681 } 1682 1683 crtc = intel_get_crtc_for_plane(dev, plane); 1684 hdisplay = crtc->mode.hdisplay; 1685 htotal = crtc->mode.htotal; 1686 clock = crtc->mode.clock; 1687 pixel_size = crtc->fb->bits_per_pixel / 8; 1688 1689 line_time_us = (htotal * 1000) / clock; 1690 line_count = (latency_ns / line_time_us + 1000) / 1000; 1691 line_size = hdisplay * pixel_size; 1692 1693 /* Use the minimum of the small and large buffer method for primary */ 1694 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1695 large = line_count * line_size; 1696 1697 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1698 *display_wm = entries + display->guard_size; 1699 1700 /* 1701 * Spec says: 1702 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 1703 */ 1704 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; 1705 1706 /* calculate the self-refresh watermark for display cursor */ 1707 entries = line_count * pixel_size * 64; 1708 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1709 *cursor_wm = entries + cursor->guard_size; 1710 1711 return ironlake_check_srwm(dev, level, 1712 *fbc_wm, *display_wm, *cursor_wm, 1713 display, cursor); 1714 } 1715 1716 static void ironlake_update_wm(struct drm_device *dev) 1717 { 1718 struct drm_i915_private *dev_priv = dev->dev_private; 1719 int fbc_wm, plane_wm, cursor_wm; 1720 unsigned int enabled; 1721 1722 enabled = 0; 1723 if (g4x_compute_wm0(dev, 0, 1724 &ironlake_display_wm_info, 1725 ILK_LP0_PLANE_LATENCY, 1726 &ironlake_cursor_wm_info, 1727 ILK_LP0_CURSOR_LATENCY, 1728 &plane_wm, &cursor_wm)) { 1729 I915_WRITE(WM0_PIPEA_ILK, 1730 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1731 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1732 " plane %d, " "cursor: %d\n", 1733 plane_wm, cursor_wm); 1734 enabled |= 1; 1735 } 1736 1737 if (g4x_compute_wm0(dev, 1, 1738 &ironlake_display_wm_info, 1739 ILK_LP0_PLANE_LATENCY, 1740 &ironlake_cursor_wm_info, 1741 ILK_LP0_CURSOR_LATENCY, 1742 &plane_wm, &cursor_wm)) { 1743 I915_WRITE(WM0_PIPEB_ILK, 1744 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1745 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1746 " plane %d, cursor: %d\n", 1747 plane_wm, cursor_wm); 1748 enabled |= 2; 1749 } 1750 1751 /* 1752 * Calculate and update the self-refresh watermark only when one 1753 * display plane is used. 1754 */ 1755 I915_WRITE(WM3_LP_ILK, 0); 1756 I915_WRITE(WM2_LP_ILK, 0); 1757 I915_WRITE(WM1_LP_ILK, 0); 1758 1759 if (!single_plane_enabled(enabled)) 1760 return; 1761 enabled = ffs(enabled) - 1; 1762 1763 /* WM1 */ 1764 if (!ironlake_compute_srwm(dev, 1, enabled, 1765 ILK_READ_WM1_LATENCY() * 500, 1766 &ironlake_display_srwm_info, 1767 &ironlake_cursor_srwm_info, 1768 &fbc_wm, &plane_wm, &cursor_wm)) 1769 return; 1770 1771 I915_WRITE(WM1_LP_ILK, 1772 WM1_LP_SR_EN | 1773 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1774 (fbc_wm << WM1_LP_FBC_SHIFT) | 1775 (plane_wm << WM1_LP_SR_SHIFT) | 1776 cursor_wm); 1777 1778 /* WM2 */ 1779 if (!ironlake_compute_srwm(dev, 2, enabled, 1780 ILK_READ_WM2_LATENCY() * 500, 1781 &ironlake_display_srwm_info, 1782 &ironlake_cursor_srwm_info, 1783 &fbc_wm, &plane_wm, &cursor_wm)) 1784 return; 1785 1786 I915_WRITE(WM2_LP_ILK, 1787 WM2_LP_EN | 1788 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1789 (fbc_wm << WM1_LP_FBC_SHIFT) | 1790 (plane_wm << WM1_LP_SR_SHIFT) | 1791 cursor_wm); 1792 1793 /* 1794 * WM3 is unsupported on ILK, probably because we don't have latency 1795 * data for that power state 1796 */ 1797 } 1798 1799 static void sandybridge_update_wm(struct drm_device *dev) 1800 { 1801 struct drm_i915_private *dev_priv = dev->dev_private; 1802 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1803 u32 val; 1804 int fbc_wm, plane_wm, cursor_wm; 1805 unsigned int enabled; 1806 1807 enabled = 0; 1808 if (g4x_compute_wm0(dev, 0, 1809 &sandybridge_display_wm_info, latency, 1810 &sandybridge_cursor_wm_info, latency, 1811 &plane_wm, &cursor_wm)) { 1812 val = I915_READ(WM0_PIPEA_ILK); 1813 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1814 I915_WRITE(WM0_PIPEA_ILK, val | 1815 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1816 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1817 " plane %d, " "cursor: %d\n", 1818 plane_wm, cursor_wm); 1819 enabled |= 1; 1820 } 1821 1822 if (g4x_compute_wm0(dev, 1, 1823 &sandybridge_display_wm_info, latency, 1824 &sandybridge_cursor_wm_info, latency, 1825 &plane_wm, &cursor_wm)) { 1826 val = I915_READ(WM0_PIPEB_ILK); 1827 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1828 I915_WRITE(WM0_PIPEB_ILK, val | 1829 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1830 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1831 " plane %d, cursor: %d\n", 1832 plane_wm, cursor_wm); 1833 enabled |= 2; 1834 } 1835 1836 /* 1837 * Calculate and update the self-refresh watermark only when one 1838 * display plane is used. 1839 * 1840 * SNB support 3 levels of watermark. 1841 * 1842 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1843 * and disabled in the descending order 1844 * 1845 */ 1846 I915_WRITE(WM3_LP_ILK, 0); 1847 I915_WRITE(WM2_LP_ILK, 0); 1848 I915_WRITE(WM1_LP_ILK, 0); 1849 1850 if (!single_plane_enabled(enabled) || 1851 dev_priv->sprite_scaling_enabled) 1852 return; 1853 enabled = ffs(enabled) - 1; 1854 1855 /* WM1 */ 1856 if (!ironlake_compute_srwm(dev, 1, enabled, 1857 SNB_READ_WM1_LATENCY() * 500, 1858 &sandybridge_display_srwm_info, 1859 &sandybridge_cursor_srwm_info, 1860 &fbc_wm, &plane_wm, &cursor_wm)) 1861 return; 1862 1863 I915_WRITE(WM1_LP_ILK, 1864 WM1_LP_SR_EN | 1865 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1866 (fbc_wm << WM1_LP_FBC_SHIFT) | 1867 (plane_wm << WM1_LP_SR_SHIFT) | 1868 cursor_wm); 1869 1870 /* WM2 */ 1871 if (!ironlake_compute_srwm(dev, 2, enabled, 1872 SNB_READ_WM2_LATENCY() * 500, 1873 &sandybridge_display_srwm_info, 1874 &sandybridge_cursor_srwm_info, 1875 &fbc_wm, &plane_wm, &cursor_wm)) 1876 return; 1877 1878 I915_WRITE(WM2_LP_ILK, 1879 WM2_LP_EN | 1880 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1881 (fbc_wm << WM1_LP_FBC_SHIFT) | 1882 (plane_wm << WM1_LP_SR_SHIFT) | 1883 cursor_wm); 1884 1885 /* WM3 */ 1886 if (!ironlake_compute_srwm(dev, 3, enabled, 1887 SNB_READ_WM3_LATENCY() * 500, 1888 &sandybridge_display_srwm_info, 1889 &sandybridge_cursor_srwm_info, 1890 &fbc_wm, &plane_wm, &cursor_wm)) 1891 return; 1892 1893 I915_WRITE(WM3_LP_ILK, 1894 WM3_LP_EN | 1895 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1896 (fbc_wm << WM1_LP_FBC_SHIFT) | 1897 (plane_wm << WM1_LP_SR_SHIFT) | 1898 cursor_wm); 1899 } 1900 1901 static void ivybridge_update_wm(struct drm_device *dev) 1902 { 1903 struct drm_i915_private *dev_priv = dev->dev_private; 1904 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1905 u32 val; 1906 int fbc_wm, plane_wm, cursor_wm; 1907 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; 1908 unsigned int enabled; 1909 1910 enabled = 0; 1911 if (g4x_compute_wm0(dev, 0, 1912 &sandybridge_display_wm_info, latency, 1913 &sandybridge_cursor_wm_info, latency, 1914 &plane_wm, &cursor_wm)) { 1915 val = I915_READ(WM0_PIPEA_ILK); 1916 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1917 I915_WRITE(WM0_PIPEA_ILK, val | 1918 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1919 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1920 " plane %d, " "cursor: %d\n", 1921 plane_wm, cursor_wm); 1922 enabled |= 1; 1923 } 1924 1925 if (g4x_compute_wm0(dev, 1, 1926 &sandybridge_display_wm_info, latency, 1927 &sandybridge_cursor_wm_info, latency, 1928 &plane_wm, &cursor_wm)) { 1929 val = I915_READ(WM0_PIPEB_ILK); 1930 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1931 I915_WRITE(WM0_PIPEB_ILK, val | 1932 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1933 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1934 " plane %d, cursor: %d\n", 1935 plane_wm, cursor_wm); 1936 enabled |= 2; 1937 } 1938 1939 if (g4x_compute_wm0(dev, 2, 1940 &sandybridge_display_wm_info, latency, 1941 &sandybridge_cursor_wm_info, latency, 1942 &plane_wm, &cursor_wm)) { 1943 val = I915_READ(WM0_PIPEC_IVB); 1944 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1945 I915_WRITE(WM0_PIPEC_IVB, val | 1946 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1947 DRM_DEBUG_KMS("FIFO watermarks For pipe C -" 1948 " plane %d, cursor: %d\n", 1949 plane_wm, cursor_wm); 1950 enabled |= 3; 1951 } 1952 1953 /* 1954 * Calculate and update the self-refresh watermark only when one 1955 * display plane is used. 1956 * 1957 * SNB support 3 levels of watermark. 1958 * 1959 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1960 * and disabled in the descending order 1961 * 1962 */ 1963 I915_WRITE(WM3_LP_ILK, 0); 1964 I915_WRITE(WM2_LP_ILK, 0); 1965 I915_WRITE(WM1_LP_ILK, 0); 1966 1967 if (!single_plane_enabled(enabled) || 1968 dev_priv->sprite_scaling_enabled) 1969 return; 1970 enabled = ffs(enabled) - 1; 1971 1972 /* WM1 */ 1973 if (!ironlake_compute_srwm(dev, 1, enabled, 1974 SNB_READ_WM1_LATENCY() * 500, 1975 &sandybridge_display_srwm_info, 1976 &sandybridge_cursor_srwm_info, 1977 &fbc_wm, &plane_wm, &cursor_wm)) 1978 return; 1979 1980 I915_WRITE(WM1_LP_ILK, 1981 WM1_LP_SR_EN | 1982 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1983 (fbc_wm << WM1_LP_FBC_SHIFT) | 1984 (plane_wm << WM1_LP_SR_SHIFT) | 1985 cursor_wm); 1986 1987 /* WM2 */ 1988 if (!ironlake_compute_srwm(dev, 2, enabled, 1989 SNB_READ_WM2_LATENCY() * 500, 1990 &sandybridge_display_srwm_info, 1991 &sandybridge_cursor_srwm_info, 1992 &fbc_wm, &plane_wm, &cursor_wm)) 1993 return; 1994 1995 I915_WRITE(WM2_LP_ILK, 1996 WM2_LP_EN | 1997 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1998 (fbc_wm << WM1_LP_FBC_SHIFT) | 1999 (plane_wm << WM1_LP_SR_SHIFT) | 2000 cursor_wm); 2001 2002 /* WM3, note we have to correct the cursor latency */ 2003 if (!ironlake_compute_srwm(dev, 3, enabled, 2004 SNB_READ_WM3_LATENCY() * 500, 2005 &sandybridge_display_srwm_info, 2006 &sandybridge_cursor_srwm_info, 2007 &fbc_wm, &plane_wm, &ignore_cursor_wm) || 2008 !ironlake_compute_srwm(dev, 3, enabled, 2009 2 * SNB_READ_WM3_LATENCY() * 500, 2010 &sandybridge_display_srwm_info, 2011 &sandybridge_cursor_srwm_info, 2012 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) 2013 return; 2014 2015 I915_WRITE(WM3_LP_ILK, 2016 WM3_LP_EN | 2017 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 2018 (fbc_wm << WM1_LP_FBC_SHIFT) | 2019 (plane_wm << WM1_LP_SR_SHIFT) | 2020 cursor_wm); 2021 } 2022 2023 static void 2024 haswell_update_linetime_wm(struct drm_device *dev, int pipe, 2025 struct drm_display_mode *mode) 2026 { 2027 struct drm_i915_private *dev_priv = dev->dev_private; 2028 u32 temp; 2029 2030 temp = I915_READ(PIPE_WM_LINETIME(pipe)); 2031 temp &= ~PIPE_WM_LINETIME_MASK; 2032 2033 /* The WM are computed with base on how long it takes to fill a single 2034 * row at the given clock rate, multiplied by 8. 2035 * */ 2036 temp |= PIPE_WM_LINETIME_TIME( 2037 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); 2038 2039 /* IPS watermarks are only used by pipe A, and are ignored by 2040 * pipes B and C. They are calculated similarly to the common 2041 * linetime values, except that we are using CD clock frequency 2042 * in MHz instead of pixel rate for the division. 2043 * 2044 * This is a placeholder for the IPS watermark calculation code. 2045 */ 2046 2047 I915_WRITE(PIPE_WM_LINETIME(pipe), temp); 2048 } 2049 2050 static bool 2051 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, 2052 uint32_t sprite_width, int pixel_size, 2053 const struct intel_watermark_params *display, 2054 int display_latency_ns, int *sprite_wm) 2055 { 2056 struct drm_crtc *crtc; 2057 int clock; 2058 int entries, tlb_miss; 2059 2060 crtc = intel_get_crtc_for_plane(dev, plane); 2061 if (!intel_crtc_active(crtc)) { 2062 *sprite_wm = display->guard_size; 2063 return false; 2064 } 2065 2066 clock = crtc->mode.clock; 2067 2068 /* Use the small buffer method to calculate the sprite watermark */ 2069 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 2070 tlb_miss = display->fifo_size*display->cacheline_size - 2071 sprite_width * 8; 2072 if (tlb_miss > 0) 2073 entries += tlb_miss; 2074 entries = DIV_ROUND_UP(entries, display->cacheline_size); 2075 *sprite_wm = entries + display->guard_size; 2076 if (*sprite_wm > (int)display->max_wm) 2077 *sprite_wm = display->max_wm; 2078 2079 return true; 2080 } 2081 2082 static bool 2083 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 2084 uint32_t sprite_width, int pixel_size, 2085 const struct intel_watermark_params *display, 2086 int latency_ns, int *sprite_wm) 2087 { 2088 struct drm_crtc *crtc; 2089 unsigned long line_time_us; 2090 int clock; 2091 int line_count, line_size; 2092 int small, large; 2093 int entries; 2094 2095 if (!latency_ns) { 2096 *sprite_wm = 0; 2097 return false; 2098 } 2099 2100 crtc = intel_get_crtc_for_plane(dev, plane); 2101 clock = crtc->mode.clock; 2102 if (!clock) { 2103 *sprite_wm = 0; 2104 return false; 2105 } 2106 2107 line_time_us = (sprite_width * 1000) / clock; 2108 if (!line_time_us) { 2109 *sprite_wm = 0; 2110 return false; 2111 } 2112 2113 line_count = (latency_ns / line_time_us + 1000) / 1000; 2114 line_size = sprite_width * pixel_size; 2115 2116 /* Use the minimum of the small and large buffer method for primary */ 2117 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 2118 large = line_count * line_size; 2119 2120 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 2121 *sprite_wm = entries + display->guard_size; 2122 2123 return *sprite_wm > 0x3ff ? false : true; 2124 } 2125 2126 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 2127 uint32_t sprite_width, int pixel_size) 2128 { 2129 struct drm_i915_private *dev_priv = dev->dev_private; 2130 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 2131 u32 val; 2132 int sprite_wm, reg; 2133 int ret; 2134 2135 switch (pipe) { 2136 case 0: 2137 reg = WM0_PIPEA_ILK; 2138 break; 2139 case 1: 2140 reg = WM0_PIPEB_ILK; 2141 break; 2142 case 2: 2143 reg = WM0_PIPEC_IVB; 2144 break; 2145 default: 2146 return; /* bad pipe */ 2147 } 2148 2149 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, 2150 &sandybridge_display_wm_info, 2151 latency, &sprite_wm); 2152 if (!ret) { 2153 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 2154 pipe); 2155 return; 2156 } 2157 2158 val = I915_READ(reg); 2159 val &= ~WM0_PIPE_SPRITE_MASK; 2160 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 2161 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 2162 2163 2164 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2165 pixel_size, 2166 &sandybridge_display_srwm_info, 2167 SNB_READ_WM1_LATENCY() * 500, 2168 &sprite_wm); 2169 if (!ret) { 2170 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 2171 pipe); 2172 return; 2173 } 2174 I915_WRITE(WM1S_LP_ILK, sprite_wm); 2175 2176 /* Only IVB has two more LP watermarks for sprite */ 2177 if (!IS_IVYBRIDGE(dev)) 2178 return; 2179 2180 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2181 pixel_size, 2182 &sandybridge_display_srwm_info, 2183 SNB_READ_WM2_LATENCY() * 500, 2184 &sprite_wm); 2185 if (!ret) { 2186 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 2187 pipe); 2188 return; 2189 } 2190 I915_WRITE(WM2S_LP_IVB, sprite_wm); 2191 2192 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2193 pixel_size, 2194 &sandybridge_display_srwm_info, 2195 SNB_READ_WM3_LATENCY() * 500, 2196 &sprite_wm); 2197 if (!ret) { 2198 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 2199 pipe); 2200 return; 2201 } 2202 I915_WRITE(WM3S_LP_IVB, sprite_wm); 2203 } 2204 2205 /** 2206 * intel_update_watermarks - update FIFO watermark values based on current modes 2207 * 2208 * Calculate watermark values for the various WM regs based on current mode 2209 * and plane configuration. 2210 * 2211 * There are several cases to deal with here: 2212 * - normal (i.e. non-self-refresh) 2213 * - self-refresh (SR) mode 2214 * - lines are large relative to FIFO size (buffer can hold up to 2) 2215 * - lines are small relative to FIFO size (buffer can hold more than 2 2216 * lines), so need to account for TLB latency 2217 * 2218 * The normal calculation is: 2219 * watermark = dotclock * bytes per pixel * latency 2220 * where latency is platform & configuration dependent (we assume pessimal 2221 * values here). 2222 * 2223 * The SR calculation is: 2224 * watermark = (trunc(latency/line time)+1) * surface width * 2225 * bytes per pixel 2226 * where 2227 * line time = htotal / dotclock 2228 * surface width = hdisplay for normal plane and 64 for cursor 2229 * and latency is assumed to be high, as above. 2230 * 2231 * The final value programmed to the register should always be rounded up, 2232 * and include an extra 2 entries to account for clock crossings. 2233 * 2234 * We don't use the sprite, so we can ignore that. And on Crestline we have 2235 * to set the non-SR watermarks to 8. 2236 */ 2237 void intel_update_watermarks(struct drm_device *dev) 2238 { 2239 struct drm_i915_private *dev_priv = dev->dev_private; 2240 2241 if (dev_priv->display.update_wm) 2242 dev_priv->display.update_wm(dev); 2243 } 2244 2245 void intel_update_linetime_watermarks(struct drm_device *dev, 2246 int pipe, struct drm_display_mode *mode) 2247 { 2248 struct drm_i915_private *dev_priv = dev->dev_private; 2249 2250 if (dev_priv->display.update_linetime_wm) 2251 dev_priv->display.update_linetime_wm(dev, pipe, mode); 2252 } 2253 2254 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 2255 uint32_t sprite_width, int pixel_size) 2256 { 2257 struct drm_i915_private *dev_priv = dev->dev_private; 2258 2259 if (dev_priv->display.update_sprite_wm) 2260 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, 2261 pixel_size); 2262 } 2263 2264 static struct drm_i915_gem_object * 2265 intel_alloc_context_page(struct drm_device *dev) 2266 { 2267 struct drm_i915_gem_object *ctx; 2268 int ret; 2269 2270 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2271 2272 ctx = i915_gem_alloc_object(dev, 4096); 2273 if (!ctx) { 2274 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 2275 return NULL; 2276 } 2277 2278 ret = i915_gem_object_pin(ctx, 4096, true, false); 2279 if (ret) { 2280 DRM_ERROR("failed to pin power context: %d\n", ret); 2281 goto err_unref; 2282 } 2283 2284 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 2285 if (ret) { 2286 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 2287 goto err_unpin; 2288 } 2289 2290 return ctx; 2291 2292 err_unpin: 2293 i915_gem_object_unpin(ctx); 2294 err_unref: 2295 drm_gem_object_unreference(&ctx->base); 2296 mutex_unlock(&dev->struct_mutex); 2297 return NULL; 2298 } 2299 2300 /** 2301 * Lock protecting IPS related data structures 2302 */ 2303 #ifdef __NetBSD__ 2304 spinlock_t mchdev_lock; 2305 #else 2306 DEFINE_SPINLOCK(mchdev_lock); 2307 #endif 2308 2309 /* Global for IPS driver to get at the current i915 device. Protected by 2310 * mchdev_lock. */ 2311 static struct drm_i915_private *i915_mch_dev; 2312 2313 bool ironlake_set_drps(struct drm_device *dev, u8 val) 2314 { 2315 struct drm_i915_private *dev_priv = dev->dev_private; 2316 u16 rgvswctl; 2317 2318 assert_spin_locked(&mchdev_lock); 2319 2320 rgvswctl = I915_READ16(MEMSWCTL); 2321 if (rgvswctl & MEMCTL_CMD_STS) { 2322 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2323 return false; /* still busy with another command */ 2324 } 2325 2326 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2327 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2328 I915_WRITE16(MEMSWCTL, rgvswctl); 2329 POSTING_READ16(MEMSWCTL); 2330 2331 rgvswctl |= MEMCTL_CMD_STS; 2332 I915_WRITE16(MEMSWCTL, rgvswctl); 2333 2334 return true; 2335 } 2336 2337 static void ironlake_enable_drps(struct drm_device *dev) 2338 { 2339 struct drm_i915_private *dev_priv = dev->dev_private; 2340 u32 rgvmodectl = I915_READ(MEMMODECTL); 2341 u8 fmax, fmin, fstart, vstart; 2342 2343 spin_lock_irq(&mchdev_lock); 2344 2345 /* Enable temp reporting */ 2346 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2347 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2348 2349 /* 100ms RC evaluation intervals */ 2350 I915_WRITE(RCUPEI, 100000); 2351 I915_WRITE(RCDNEI, 100000); 2352 2353 /* Set max/min thresholds to 90ms and 80ms respectively */ 2354 I915_WRITE(RCBMAXAVG, 90000); 2355 I915_WRITE(RCBMINAVG, 80000); 2356 2357 I915_WRITE(MEMIHYST, 1); 2358 2359 /* Set up min, max, and cur for interrupt handling */ 2360 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2361 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2362 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2363 MEMMODE_FSTART_SHIFT; 2364 2365 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2366 PXVFREQ_PX_SHIFT; 2367 2368 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 2369 dev_priv->ips.fstart = fstart; 2370 2371 dev_priv->ips.max_delay = fstart; 2372 dev_priv->ips.min_delay = fmin; 2373 dev_priv->ips.cur_delay = fstart; 2374 2375 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 2376 fmax, fmin, fstart); 2377 2378 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2379 2380 /* 2381 * Interrupts will be enabled in ironlake_irq_postinstall 2382 */ 2383 2384 I915_WRITE(VIDSTART, vstart); 2385 POSTING_READ(VIDSTART); 2386 2387 rgvmodectl |= MEMMODE_SWMODE_EN; 2388 I915_WRITE(MEMMODECTL, rgvmodectl); 2389 2390 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 2391 DRM_ERROR("stuck trying to change perf mode\n"); 2392 mdelay(1); 2393 2394 ironlake_set_drps(dev, fstart); 2395 2396 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2397 I915_READ(0x112e0); 2398 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 2399 dev_priv->ips.last_count2 = I915_READ(0x112f4); 2400 getrawmonotonic(&dev_priv->ips.last_time2); 2401 2402 spin_unlock_irq(&mchdev_lock); 2403 } 2404 2405 static void ironlake_disable_drps(struct drm_device *dev) 2406 { 2407 struct drm_i915_private *dev_priv = dev->dev_private; 2408 u16 rgvswctl; 2409 2410 spin_lock_irq(&mchdev_lock); 2411 2412 rgvswctl = I915_READ16(MEMSWCTL); 2413 2414 /* Ack interrupts, disable EFC interrupt */ 2415 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2416 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2417 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2418 I915_WRITE(DEIIR, DE_PCU_EVENT); 2419 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2420 2421 /* Go back to the starting frequency */ 2422 ironlake_set_drps(dev, dev_priv->ips.fstart); 2423 mdelay(1); 2424 rgvswctl |= MEMCTL_CMD_STS; 2425 I915_WRITE(MEMSWCTL, rgvswctl); 2426 mdelay(1); 2427 2428 spin_unlock_irq(&mchdev_lock); 2429 } 2430 2431 /* There's a funny hw issue where the hw returns all 0 when reading from 2432 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 2433 * ourselves, instead of doing a rmw cycle (which might result in us clearing 2434 * all limits and the gpu stuck at whatever frequency it is at atm). 2435 */ 2436 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) 2437 { 2438 u32 limits; 2439 2440 limits = 0; 2441 2442 if (*val >= dev_priv->rps.max_delay) 2443 *val = dev_priv->rps.max_delay; 2444 limits |= dev_priv->rps.max_delay << 24; 2445 2446 /* Only set the down limit when we've reached the lowest level to avoid 2447 * getting more interrupts, otherwise leave this clear. This prevents a 2448 * race in the hw when coming out of rc6: There's a tiny window where 2449 * the hw runs at the minimal clock before selecting the desired 2450 * frequency, if the down threshold expires in that window we will not 2451 * receive a down interrupt. */ 2452 if (*val <= dev_priv->rps.min_delay) { 2453 *val = dev_priv->rps.min_delay; 2454 limits |= dev_priv->rps.min_delay << 16; 2455 } 2456 2457 return limits; 2458 } 2459 2460 void gen6_set_rps(struct drm_device *dev, u8 val) 2461 { 2462 struct drm_i915_private *dev_priv = dev->dev_private; 2463 u32 limits = gen6_rps_limits(dev_priv, &val); 2464 2465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2466 WARN_ON(val > dev_priv->rps.max_delay); 2467 WARN_ON(val < dev_priv->rps.min_delay); 2468 2469 if (val == dev_priv->rps.cur_delay) 2470 return; 2471 2472 I915_WRITE(GEN6_RPNSWREQ, 2473 GEN6_FREQUENCY(val) | 2474 GEN6_OFFSET(0) | 2475 GEN6_AGGRESSIVE_TURBO); 2476 2477 /* Make sure we continue to get interrupts 2478 * until we hit the minimum or maximum frequencies. 2479 */ 2480 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); 2481 2482 POSTING_READ(GEN6_RPNSWREQ); 2483 2484 dev_priv->rps.cur_delay = val; 2485 2486 trace_intel_gpu_freq_change(val * 50); 2487 } 2488 2489 static void gen6_disable_rps(struct drm_device *dev) 2490 { 2491 struct drm_i915_private *dev_priv = dev->dev_private; 2492 2493 I915_WRITE(GEN6_RC_CONTROL, 0); 2494 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 2495 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 2496 I915_WRITE(GEN6_PMIER, 0); 2497 /* Complete PM interrupt masking here doesn't race with the rps work 2498 * item again unmasking PM interrupts because that is using a different 2499 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 2500 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 2501 2502 spin_lock_irq(&dev_priv->rps.lock); 2503 dev_priv->rps.pm_iir = 0; 2504 spin_unlock_irq(&dev_priv->rps.lock); 2505 2506 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2507 } 2508 2509 int intel_enable_rc6(const struct drm_device *dev) 2510 { 2511 /* Respect the kernel parameter if it is set */ 2512 if (i915_enable_rc6 >= 0) 2513 return i915_enable_rc6; 2514 2515 /* Disable RC6 on Ironlake */ 2516 if (INTEL_INFO(dev)->gen == 5) 2517 return 0; 2518 2519 if (IS_HASWELL(dev)) { 2520 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); 2521 return INTEL_RC6_ENABLE; 2522 } 2523 2524 /* snb/ivb have more than one rc6 state. */ 2525 if (INTEL_INFO(dev)->gen == 6) { 2526 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); 2527 return INTEL_RC6_ENABLE; 2528 } 2529 2530 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); 2531 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 2532 } 2533 2534 static void gen6_enable_rps(struct drm_device *dev) 2535 { 2536 struct drm_i915_private *dev_priv = dev->dev_private; 2537 struct intel_ring_buffer *ring; 2538 u32 rp_state_cap; 2539 u32 gt_perf_status; 2540 u32 rc6vids, pcu_mbox, rc6_mask = 0; 2541 u32 gtfifodbg; 2542 int rc6_mode; 2543 int i, ret; 2544 2545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2546 2547 /* Here begins a magic sequence of register writes to enable 2548 * auto-downclocking. 2549 * 2550 * Perhaps there might be some value in exposing these to 2551 * userspace... 2552 */ 2553 I915_WRITE(GEN6_RC_STATE, 0); 2554 2555 /* Clear the DBG now so we don't confuse earlier errors */ 2556 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 2557 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 2558 I915_WRITE(GTFIFODBG, gtfifodbg); 2559 } 2560 2561 gen6_gt_force_wake_get(dev_priv); 2562 2563 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 2564 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 2565 2566 /* In units of 100MHz */ 2567 dev_priv->rps.max_delay = rp_state_cap & 0xff; 2568 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; 2569 dev_priv->rps.cur_delay = 0; 2570 2571 /* disable the counters and set deterministic thresholds */ 2572 I915_WRITE(GEN6_RC_CONTROL, 0); 2573 2574 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 2575 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 2576 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 2577 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 2578 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 2579 2580 for_each_ring(ring, dev_priv, i) 2581 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 2582 2583 I915_WRITE(GEN6_RC_SLEEP, 0); 2584 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2585 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2586 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 2587 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2588 2589 /* Check if we are enabling RC6 */ 2590 rc6_mode = intel_enable_rc6(dev_priv->dev); 2591 if (rc6_mode & INTEL_RC6_ENABLE) 2592 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 2593 2594 /* We don't use those on Haswell */ 2595 if (!IS_HASWELL(dev)) { 2596 if (rc6_mode & INTEL_RC6p_ENABLE) 2597 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 2598 2599 if (rc6_mode & INTEL_RC6pp_ENABLE) 2600 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 2601 } 2602 2603 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 2604 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 2605 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 2606 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 2607 2608 I915_WRITE(GEN6_RC_CONTROL, 2609 rc6_mask | 2610 GEN6_RC_CTL_EI_MODE(1) | 2611 GEN6_RC_CTL_HW_ENABLE); 2612 2613 I915_WRITE(GEN6_RPNSWREQ, 2614 GEN6_FREQUENCY(10) | 2615 GEN6_OFFSET(0) | 2616 GEN6_AGGRESSIVE_TURBO); 2617 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2618 GEN6_FREQUENCY(12)); 2619 2620 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2621 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2622 dev_priv->rps.max_delay << 24 | 2623 dev_priv->rps.min_delay << 16); 2624 2625 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 2626 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 2627 I915_WRITE(GEN6_RP_UP_EI, 66000); 2628 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 2629 2630 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2631 I915_WRITE(GEN6_RP_CONTROL, 2632 GEN6_RP_MEDIA_TURBO | 2633 GEN6_RP_MEDIA_HW_NORMAL_MODE | 2634 GEN6_RP_MEDIA_IS_GFX | 2635 GEN6_RP_ENABLE | 2636 GEN6_RP_UP_BUSY_AVG | 2637 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); 2638 2639 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 2640 if (!ret) { 2641 pcu_mbox = 0; 2642 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 2643 if (ret && pcu_mbox & (1<<31)) { /* OC supported */ 2644 dev_priv->rps.max_delay = pcu_mbox & 0xff; 2645 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); 2646 } 2647 } else { 2648 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 2649 } 2650 2651 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); 2652 2653 /* requires MSI enabled */ 2654 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); 2655 spin_lock_irq(&dev_priv->rps.lock); 2656 WARN_ON(dev_priv->rps.pm_iir != 0); 2657 I915_WRITE(GEN6_PMIMR, 0); 2658 spin_unlock_irq(&dev_priv->rps.lock); 2659 /* enable all PM interrupts */ 2660 I915_WRITE(GEN6_PMINTRMSK, 0); 2661 2662 rc6vids = 0; 2663 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 2664 if (IS_GEN6(dev) && ret) { 2665 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 2666 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 2667 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 2668 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 2669 rc6vids &= 0xffff00; 2670 rc6vids |= GEN6_ENCODE_RC6_VID(450); 2671 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 2672 if (ret) 2673 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 2674 } 2675 2676 gen6_gt_force_wake_put(dev_priv); 2677 } 2678 2679 static void gen6_update_ring_freq(struct drm_device *dev) 2680 { 2681 struct drm_i915_private *dev_priv = dev->dev_private; 2682 int min_freq = 15; 2683 int gpu_freq; 2684 unsigned int ia_freq, max_ia_freq; 2685 int scaling_factor = 180; 2686 2687 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2688 2689 #ifdef __NetBSD__ /* XXX cpufreq */ 2690 { 2691 extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */ 2692 max_ia_freq = (tsc_freq / 1000); 2693 } 2694 #else 2695 max_ia_freq = cpufreq_quick_get_max(0); 2696 /* 2697 * Default to measured freq if none found, PCU will ensure we don't go 2698 * over 2699 */ 2700 if (!max_ia_freq) 2701 max_ia_freq = tsc_khz; 2702 #endif 2703 2704 /* Convert from kHz to MHz */ 2705 max_ia_freq /= 1000; 2706 2707 /* 2708 * For each potential GPU frequency, load a ring frequency we'd like 2709 * to use for memory access. We do this by specifying the IA frequency 2710 * the PCU should use as a reference to determine the ring frequency. 2711 */ 2712 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 2713 gpu_freq--) { 2714 int diff = dev_priv->rps.max_delay - gpu_freq; 2715 2716 /* 2717 * For GPU frequencies less than 750MHz, just use the lowest 2718 * ring freq. 2719 */ 2720 if (gpu_freq < min_freq) 2721 ia_freq = 800; 2722 else 2723 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 2724 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 2725 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; 2726 2727 sandybridge_pcode_write(dev_priv, 2728 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 2729 ia_freq | gpu_freq); 2730 } 2731 } 2732 2733 void ironlake_teardown_rc6(struct drm_device *dev) 2734 { 2735 struct drm_i915_private *dev_priv = dev->dev_private; 2736 2737 if (dev_priv->ips.renderctx) { 2738 i915_gem_object_unpin(dev_priv->ips.renderctx); 2739 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 2740 dev_priv->ips.renderctx = NULL; 2741 } 2742 2743 if (dev_priv->ips.pwrctx) { 2744 i915_gem_object_unpin(dev_priv->ips.pwrctx); 2745 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 2746 dev_priv->ips.pwrctx = NULL; 2747 } 2748 } 2749 2750 static void ironlake_disable_rc6(struct drm_device *dev) 2751 { 2752 struct drm_i915_private *dev_priv = dev->dev_private; 2753 2754 if (I915_READ(PWRCTXA)) { 2755 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 2756 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 2757 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 2758 50); 2759 2760 I915_WRITE(PWRCTXA, 0); 2761 POSTING_READ(PWRCTXA); 2762 2763 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2764 POSTING_READ(RSTDBYCTL); 2765 } 2766 } 2767 2768 static int ironlake_setup_rc6(struct drm_device *dev) 2769 { 2770 struct drm_i915_private *dev_priv = dev->dev_private; 2771 2772 if (dev_priv->ips.renderctx == NULL) 2773 dev_priv->ips.renderctx = intel_alloc_context_page(dev); 2774 if (!dev_priv->ips.renderctx) 2775 return -ENOMEM; 2776 2777 if (dev_priv->ips.pwrctx == NULL) 2778 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); 2779 if (!dev_priv->ips.pwrctx) { 2780 ironlake_teardown_rc6(dev); 2781 return -ENOMEM; 2782 } 2783 2784 return 0; 2785 } 2786 2787 static void ironlake_enable_rc6(struct drm_device *dev) 2788 { 2789 struct drm_i915_private *dev_priv = dev->dev_private; 2790 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 2791 bool was_interruptible; 2792 int ret; 2793 2794 /* rc6 disabled by default due to repeated reports of hanging during 2795 * boot and resume. 2796 */ 2797 if (!intel_enable_rc6(dev)) 2798 return; 2799 2800 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2801 2802 ret = ironlake_setup_rc6(dev); 2803 if (ret) 2804 return; 2805 2806 was_interruptible = dev_priv->mm.interruptible; 2807 dev_priv->mm.interruptible = false; 2808 2809 /* 2810 * GPU can automatically power down the render unit if given a page 2811 * to save state. 2812 */ 2813 ret = intel_ring_begin(ring, 6); 2814 if (ret) { 2815 ironlake_teardown_rc6(dev); 2816 dev_priv->mm.interruptible = was_interruptible; 2817 return; 2818 } 2819 2820 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 2821 intel_ring_emit(ring, MI_SET_CONTEXT); 2822 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | 2823 MI_MM_SPACE_GTT | 2824 MI_SAVE_EXT_STATE_EN | 2825 MI_RESTORE_EXT_STATE_EN | 2826 MI_RESTORE_INHIBIT); 2827 intel_ring_emit(ring, MI_SUSPEND_FLUSH); 2828 intel_ring_emit(ring, MI_NOOP); 2829 intel_ring_emit(ring, MI_FLUSH); 2830 intel_ring_advance(ring); 2831 2832 /* 2833 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 2834 * does an implicit flush, combined with MI_FLUSH above, it should be 2835 * safe to assume that renderctx is valid 2836 */ 2837 ret = intel_ring_idle(ring); 2838 dev_priv->mm.interruptible = was_interruptible; 2839 if (ret) { 2840 DRM_ERROR("failed to enable ironlake power power savings\n"); 2841 ironlake_teardown_rc6(dev); 2842 return; 2843 } 2844 2845 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); 2846 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2847 } 2848 2849 static unsigned long intel_pxfreq(u32 vidfreq) 2850 { 2851 unsigned long freq; 2852 int div = (vidfreq & 0x3f0000) >> 16; 2853 int post = (vidfreq & 0x3000) >> 12; 2854 int pre = (vidfreq & 0x7); 2855 2856 if (!pre) 2857 return 0; 2858 2859 freq = ((div * 133333) / ((1<<post) * pre)); 2860 2861 return freq; 2862 } 2863 2864 static const struct cparams { 2865 u16 i; 2866 u16 t; 2867 u16 m; 2868 u16 c; 2869 } cparams[] = { 2870 { 1, 1333, 301, 28664 }, 2871 { 1, 1066, 294, 24460 }, 2872 { 1, 800, 294, 25192 }, 2873 { 0, 1333, 276, 27605 }, 2874 { 0, 1066, 276, 27605 }, 2875 { 0, 800, 231, 23784 }, 2876 }; 2877 2878 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 2879 { 2880 u64 total_count, diff, ret; 2881 u32 count1, count2, count3, m = 0, c = 0; 2882 unsigned long now = jiffies_to_msecs(jiffies), diff1; 2883 int i; 2884 2885 assert_spin_locked(&mchdev_lock); 2886 2887 diff1 = now - dev_priv->ips.last_time1; 2888 2889 /* Prevent division-by-zero if we are asking too fast. 2890 * Also, we don't get interesting results if we are polling 2891 * faster than once in 10ms, so just return the saved value 2892 * in such cases. 2893 */ 2894 if (diff1 <= 10) 2895 return dev_priv->ips.chipset_power; 2896 2897 count1 = I915_READ(DMIEC); 2898 count2 = I915_READ(DDREC); 2899 count3 = I915_READ(CSIEC); 2900 2901 total_count = count1 + count2 + count3; 2902 2903 /* FIXME: handle per-counter overflow */ 2904 if (total_count < dev_priv->ips.last_count1) { 2905 diff = ~0UL - dev_priv->ips.last_count1; 2906 diff += total_count; 2907 } else { 2908 diff = total_count - dev_priv->ips.last_count1; 2909 } 2910 2911 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 2912 if (cparams[i].i == dev_priv->ips.c_m && 2913 cparams[i].t == dev_priv->ips.r_t) { 2914 m = cparams[i].m; 2915 c = cparams[i].c; 2916 break; 2917 } 2918 } 2919 2920 diff = div_u64(diff, diff1); 2921 ret = ((m * diff) + c); 2922 ret = div_u64(ret, 10); 2923 2924 dev_priv->ips.last_count1 = total_count; 2925 dev_priv->ips.last_time1 = now; 2926 2927 dev_priv->ips.chipset_power = ret; 2928 2929 return ret; 2930 } 2931 2932 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 2933 { 2934 unsigned long val; 2935 2936 if (dev_priv->info->gen != 5) 2937 return 0; 2938 2939 spin_lock_irq(&mchdev_lock); 2940 2941 val = __i915_chipset_val(dev_priv); 2942 2943 spin_unlock_irq(&mchdev_lock); 2944 2945 return val; 2946 } 2947 2948 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 2949 { 2950 unsigned long m, x, b; 2951 u32 tsfs; 2952 2953 tsfs = I915_READ(TSFS); 2954 2955 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 2956 x = I915_READ8(TR1); 2957 2958 b = tsfs & TSFS_INTR_MASK; 2959 2960 return ((m * x) / 127) - b; 2961 } 2962 2963 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 2964 { 2965 static const struct v_table { 2966 u16 vd; /* in .1 mil */ 2967 u16 vm; /* in .1 mil */ 2968 } v_table[] = { 2969 { 0, 0, }, 2970 { 375, 0, }, 2971 { 500, 0, }, 2972 { 625, 0, }, 2973 { 750, 0, }, 2974 { 875, 0, }, 2975 { 1000, 0, }, 2976 { 1125, 0, }, 2977 { 4125, 3000, }, 2978 { 4125, 3000, }, 2979 { 4125, 3000, }, 2980 { 4125, 3000, }, 2981 { 4125, 3000, }, 2982 { 4125, 3000, }, 2983 { 4125, 3000, }, 2984 { 4125, 3000, }, 2985 { 4125, 3000, }, 2986 { 4125, 3000, }, 2987 { 4125, 3000, }, 2988 { 4125, 3000, }, 2989 { 4125, 3000, }, 2990 { 4125, 3000, }, 2991 { 4125, 3000, }, 2992 { 4125, 3000, }, 2993 { 4125, 3000, }, 2994 { 4125, 3000, }, 2995 { 4125, 3000, }, 2996 { 4125, 3000, }, 2997 { 4125, 3000, }, 2998 { 4125, 3000, }, 2999 { 4125, 3000, }, 3000 { 4125, 3000, }, 3001 { 4250, 3125, }, 3002 { 4375, 3250, }, 3003 { 4500, 3375, }, 3004 { 4625, 3500, }, 3005 { 4750, 3625, }, 3006 { 4875, 3750, }, 3007 { 5000, 3875, }, 3008 { 5125, 4000, }, 3009 { 5250, 4125, }, 3010 { 5375, 4250, }, 3011 { 5500, 4375, }, 3012 { 5625, 4500, }, 3013 { 5750, 4625, }, 3014 { 5875, 4750, }, 3015 { 6000, 4875, }, 3016 { 6125, 5000, }, 3017 { 6250, 5125, }, 3018 { 6375, 5250, }, 3019 { 6500, 5375, }, 3020 { 6625, 5500, }, 3021 { 6750, 5625, }, 3022 { 6875, 5750, }, 3023 { 7000, 5875, }, 3024 { 7125, 6000, }, 3025 { 7250, 6125, }, 3026 { 7375, 6250, }, 3027 { 7500, 6375, }, 3028 { 7625, 6500, }, 3029 { 7750, 6625, }, 3030 { 7875, 6750, }, 3031 { 8000, 6875, }, 3032 { 8125, 7000, }, 3033 { 8250, 7125, }, 3034 { 8375, 7250, }, 3035 { 8500, 7375, }, 3036 { 8625, 7500, }, 3037 { 8750, 7625, }, 3038 { 8875, 7750, }, 3039 { 9000, 7875, }, 3040 { 9125, 8000, }, 3041 { 9250, 8125, }, 3042 { 9375, 8250, }, 3043 { 9500, 8375, }, 3044 { 9625, 8500, }, 3045 { 9750, 8625, }, 3046 { 9875, 8750, }, 3047 { 10000, 8875, }, 3048 { 10125, 9000, }, 3049 { 10250, 9125, }, 3050 { 10375, 9250, }, 3051 { 10500, 9375, }, 3052 { 10625, 9500, }, 3053 { 10750, 9625, }, 3054 { 10875, 9750, }, 3055 { 11000, 9875, }, 3056 { 11125, 10000, }, 3057 { 11250, 10125, }, 3058 { 11375, 10250, }, 3059 { 11500, 10375, }, 3060 { 11625, 10500, }, 3061 { 11750, 10625, }, 3062 { 11875, 10750, }, 3063 { 12000, 10875, }, 3064 { 12125, 11000, }, 3065 { 12250, 11125, }, 3066 { 12375, 11250, }, 3067 { 12500, 11375, }, 3068 { 12625, 11500, }, 3069 { 12750, 11625, }, 3070 { 12875, 11750, }, 3071 { 13000, 11875, }, 3072 { 13125, 12000, }, 3073 { 13250, 12125, }, 3074 { 13375, 12250, }, 3075 { 13500, 12375, }, 3076 { 13625, 12500, }, 3077 { 13750, 12625, }, 3078 { 13875, 12750, }, 3079 { 14000, 12875, }, 3080 { 14125, 13000, }, 3081 { 14250, 13125, }, 3082 { 14375, 13250, }, 3083 { 14500, 13375, }, 3084 { 14625, 13500, }, 3085 { 14750, 13625, }, 3086 { 14875, 13750, }, 3087 { 15000, 13875, }, 3088 { 15125, 14000, }, 3089 { 15250, 14125, }, 3090 { 15375, 14250, }, 3091 { 15500, 14375, }, 3092 { 15625, 14500, }, 3093 { 15750, 14625, }, 3094 { 15875, 14750, }, 3095 { 16000, 14875, }, 3096 { 16125, 15000, }, 3097 }; 3098 if (dev_priv->info->is_mobile) 3099 return v_table[pxvid].vm; 3100 else 3101 return v_table[pxvid].vd; 3102 } 3103 3104 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 3105 { 3106 struct timespec now, diff1; 3107 u64 diff; 3108 unsigned long diffms; 3109 u32 count; 3110 3111 assert_spin_locked(&mchdev_lock); 3112 3113 getrawmonotonic(&now); 3114 diff1 = timespec_sub(now, dev_priv->ips.last_time2); 3115 3116 /* Don't divide by 0 */ 3117 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 3118 if (!diffms) 3119 return; 3120 3121 count = I915_READ(GFXEC); 3122 3123 if (count < dev_priv->ips.last_count2) { 3124 diff = ~0UL - dev_priv->ips.last_count2; 3125 diff += count; 3126 } else { 3127 diff = count - dev_priv->ips.last_count2; 3128 } 3129 3130 dev_priv->ips.last_count2 = count; 3131 dev_priv->ips.last_time2 = now; 3132 3133 /* More magic constants... */ 3134 diff = diff * 1181; 3135 diff = div_u64(diff, diffms * 10); 3136 dev_priv->ips.gfx_power = diff; 3137 } 3138 3139 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 3140 { 3141 if (dev_priv->info->gen != 5) 3142 return; 3143 3144 spin_lock_irq(&mchdev_lock); 3145 3146 __i915_update_gfx_val(dev_priv); 3147 3148 spin_unlock_irq(&mchdev_lock); 3149 } 3150 3151 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 3152 { 3153 unsigned long t, corr, state1, corr2, state2; 3154 u32 pxvid, ext_v; 3155 3156 assert_spin_locked(&mchdev_lock); 3157 3158 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 3159 pxvid = (pxvid >> 24) & 0x7f; 3160 ext_v = pvid_to_extvid(dev_priv, pxvid); 3161 3162 state1 = ext_v; 3163 3164 t = i915_mch_val(dev_priv); 3165 3166 /* Revel in the empirically derived constants */ 3167 3168 /* Correction factor in 1/100000 units */ 3169 if (t > 80) 3170 corr = ((t * 2349) + 135940); 3171 else if (t >= 50) 3172 corr = ((t * 964) + 29317); 3173 else /* < 50 */ 3174 corr = ((t * 301) + 1004); 3175 3176 corr = corr * ((150142 * state1) / 10000 - 78642); 3177 corr /= 100000; 3178 corr2 = (corr * dev_priv->ips.corr); 3179 3180 state2 = (corr2 * state1) / 10000; 3181 state2 /= 100; /* convert to mW */ 3182 3183 __i915_update_gfx_val(dev_priv); 3184 3185 return dev_priv->ips.gfx_power + state2; 3186 } 3187 3188 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 3189 { 3190 unsigned long val; 3191 3192 if (dev_priv->info->gen != 5) 3193 return 0; 3194 3195 spin_lock_irq(&mchdev_lock); 3196 3197 val = __i915_gfx_val(dev_priv); 3198 3199 spin_unlock_irq(&mchdev_lock); 3200 3201 return val; 3202 } 3203 3204 #ifndef __NetBSD__ /* XXX IPS */ 3205 /** 3206 * i915_read_mch_val - return value for IPS use 3207 * 3208 * Calculate and return a value for the IPS driver to use when deciding whether 3209 * we have thermal and power headroom to increase CPU or GPU power budget. 3210 */ 3211 unsigned long i915_read_mch_val(void) 3212 { 3213 struct drm_i915_private *dev_priv; 3214 unsigned long chipset_val, graphics_val, ret = 0; 3215 3216 spin_lock_irq(&mchdev_lock); 3217 if (!i915_mch_dev) 3218 goto out_unlock; 3219 dev_priv = i915_mch_dev; 3220 3221 chipset_val = __i915_chipset_val(dev_priv); 3222 graphics_val = __i915_gfx_val(dev_priv); 3223 3224 ret = chipset_val + graphics_val; 3225 3226 out_unlock: 3227 spin_unlock_irq(&mchdev_lock); 3228 3229 return ret; 3230 } 3231 EXPORT_SYMBOL_GPL(i915_read_mch_val); 3232 3233 /** 3234 * i915_gpu_raise - raise GPU frequency limit 3235 * 3236 * Raise the limit; IPS indicates we have thermal headroom. 3237 */ 3238 bool i915_gpu_raise(void) 3239 { 3240 struct drm_i915_private *dev_priv; 3241 bool ret = true; 3242 3243 spin_lock_irq(&mchdev_lock); 3244 if (!i915_mch_dev) { 3245 ret = false; 3246 goto out_unlock; 3247 } 3248 dev_priv = i915_mch_dev; 3249 3250 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 3251 dev_priv->ips.max_delay--; 3252 3253 out_unlock: 3254 spin_unlock_irq(&mchdev_lock); 3255 3256 return ret; 3257 } 3258 EXPORT_SYMBOL_GPL(i915_gpu_raise); 3259 3260 /** 3261 * i915_gpu_lower - lower GPU frequency limit 3262 * 3263 * IPS indicates we're close to a thermal limit, so throttle back the GPU 3264 * frequency maximum. 3265 */ 3266 bool i915_gpu_lower(void) 3267 { 3268 struct drm_i915_private *dev_priv; 3269 bool ret = true; 3270 3271 spin_lock_irq(&mchdev_lock); 3272 if (!i915_mch_dev) { 3273 ret = false; 3274 goto out_unlock; 3275 } 3276 dev_priv = i915_mch_dev; 3277 3278 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 3279 dev_priv->ips.max_delay++; 3280 3281 out_unlock: 3282 spin_unlock_irq(&mchdev_lock); 3283 3284 return ret; 3285 } 3286 EXPORT_SYMBOL_GPL(i915_gpu_lower); 3287 3288 /** 3289 * i915_gpu_busy - indicate GPU business to IPS 3290 * 3291 * Tell the IPS driver whether or not the GPU is busy. 3292 */ 3293 bool i915_gpu_busy(void) 3294 { 3295 struct drm_i915_private *dev_priv; 3296 struct intel_ring_buffer *ring; 3297 bool ret = false; 3298 int i; 3299 3300 spin_lock_irq(&mchdev_lock); 3301 if (!i915_mch_dev) 3302 goto out_unlock; 3303 dev_priv = i915_mch_dev; 3304 3305 for_each_ring(ring, dev_priv, i) 3306 ret |= !list_empty(&ring->request_list); 3307 3308 out_unlock: 3309 spin_unlock_irq(&mchdev_lock); 3310 3311 return ret; 3312 } 3313 EXPORT_SYMBOL_GPL(i915_gpu_busy); 3314 3315 /** 3316 * i915_gpu_turbo_disable - disable graphics turbo 3317 * 3318 * Disable graphics turbo by resetting the max frequency and setting the 3319 * current frequency to the default. 3320 */ 3321 bool i915_gpu_turbo_disable(void) 3322 { 3323 struct drm_i915_private *dev_priv; 3324 bool ret = true; 3325 3326 spin_lock_irq(&mchdev_lock); 3327 if (!i915_mch_dev) { 3328 ret = false; 3329 goto out_unlock; 3330 } 3331 dev_priv = i915_mch_dev; 3332 3333 dev_priv->ips.max_delay = dev_priv->ips.fstart; 3334 3335 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 3336 ret = false; 3337 3338 out_unlock: 3339 spin_unlock_irq(&mchdev_lock); 3340 3341 return ret; 3342 } 3343 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 3344 #endif 3345 3346 /** 3347 * Tells the intel_ips driver that the i915 driver is now loaded, if 3348 * IPS got loaded first. 3349 * 3350 * This awkward dance is so that neither module has to depend on the 3351 * other in order for IPS to do the appropriate communication of 3352 * GPU turbo limits to i915. 3353 */ 3354 static void 3355 ips_ping_for_i915_load(void) 3356 { 3357 #ifndef __NetBSD__ /* XXX whattakludge for Linux module mania */ 3358 void (*link)(void); 3359 3360 link = symbol_get(ips_link_to_i915_driver); 3361 if (link) { 3362 link(); 3363 symbol_put(ips_link_to_i915_driver); 3364 } 3365 #endif 3366 } 3367 3368 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 3369 { 3370 #ifdef __NetBSD__ /* XXX */ 3371 /* 3372 * This seems as good a place as any to initialize mchdev_lock. 3373 * Taking the lock in the rest of this routine is silly, but... 3374 */ 3375 spin_lock_init(&mchdev_lock); 3376 #endif 3377 3378 /* We only register the i915 ips part with intel-ips once everything is 3379 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 3380 spin_lock_irq(&mchdev_lock); 3381 i915_mch_dev = dev_priv; 3382 spin_unlock_irq(&mchdev_lock); 3383 3384 ips_ping_for_i915_load(); 3385 } 3386 3387 void intel_gpu_ips_teardown(void) 3388 { 3389 #ifdef __NetBSD__ 3390 if (i915_mch_dev == NULL) 3391 return; 3392 #endif 3393 spin_lock_irq(&mchdev_lock); 3394 i915_mch_dev = NULL; 3395 spin_unlock_irq(&mchdev_lock); 3396 #ifdef __NetBSD__ 3397 spin_lock_destroy(&mchdev_lock); 3398 #endif 3399 } 3400 static void intel_init_emon(struct drm_device *dev) 3401 { 3402 struct drm_i915_private *dev_priv = dev->dev_private; 3403 u32 lcfuse; 3404 u8 pxw[16]; 3405 int i; 3406 3407 /* Disable to program */ 3408 I915_WRITE(ECR, 0); 3409 POSTING_READ(ECR); 3410 3411 /* Program energy weights for various events */ 3412 I915_WRITE(SDEW, 0x15040d00); 3413 I915_WRITE(CSIEW0, 0x007f0000); 3414 I915_WRITE(CSIEW1, 0x1e220004); 3415 I915_WRITE(CSIEW2, 0x04000004); 3416 3417 for (i = 0; i < 5; i++) 3418 I915_WRITE(PEW + (i * 4), 0); 3419 for (i = 0; i < 3; i++) 3420 I915_WRITE(DEW + (i * 4), 0); 3421 3422 /* Program P-state weights to account for frequency power adjustment */ 3423 for (i = 0; i < 16; i++) { 3424 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 3425 unsigned long freq = intel_pxfreq(pxvidfreq); 3426 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 3427 PXVFREQ_PX_SHIFT; 3428 unsigned long val; 3429 3430 val = vid * vid; 3431 val *= (freq / 1000); 3432 val *= 255; 3433 val /= (127*127*900); 3434 if (val > 0xff) 3435 DRM_ERROR("bad pxval: %ld\n", val); 3436 pxw[i] = val; 3437 } 3438 /* Render standby states get 0 weight */ 3439 pxw[14] = 0; 3440 pxw[15] = 0; 3441 3442 for (i = 0; i < 4; i++) { 3443 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 3444 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 3445 I915_WRITE(PXW + (i * 4), val); 3446 } 3447 3448 /* Adjust magic regs to magic values (more experimental results) */ 3449 I915_WRITE(OGW0, 0); 3450 I915_WRITE(OGW1, 0); 3451 I915_WRITE(EG0, 0x00007f00); 3452 I915_WRITE(EG1, 0x0000000e); 3453 I915_WRITE(EG2, 0x000e0000); 3454 I915_WRITE(EG3, 0x68000300); 3455 I915_WRITE(EG4, 0x42000000); 3456 I915_WRITE(EG5, 0x00140031); 3457 I915_WRITE(EG6, 0); 3458 I915_WRITE(EG7, 0); 3459 3460 for (i = 0; i < 8; i++) 3461 I915_WRITE(PXWL + (i * 4), 0); 3462 3463 /* Enable PMON + select events */ 3464 I915_WRITE(ECR, 0x80000019); 3465 3466 lcfuse = I915_READ(LCFUSE02); 3467 3468 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 3469 } 3470 3471 void intel_disable_gt_powersave(struct drm_device *dev) 3472 { 3473 struct drm_i915_private *dev_priv = dev->dev_private; 3474 3475 if (IS_IRONLAKE_M(dev)) { 3476 ironlake_disable_drps(dev); 3477 ironlake_disable_rc6(dev); 3478 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { 3479 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 3480 mutex_lock(&dev_priv->rps.hw_lock); 3481 gen6_disable_rps(dev); 3482 mutex_unlock(&dev_priv->rps.hw_lock); 3483 } 3484 } 3485 3486 static void intel_gen6_powersave_work(struct work_struct *work) 3487 { 3488 struct drm_i915_private *dev_priv = 3489 container_of(work, struct drm_i915_private, 3490 rps.delayed_resume_work.work); 3491 struct drm_device *dev = dev_priv->dev; 3492 3493 mutex_lock(&dev_priv->rps.hw_lock); 3494 gen6_enable_rps(dev); 3495 gen6_update_ring_freq(dev); 3496 mutex_unlock(&dev_priv->rps.hw_lock); 3497 } 3498 3499 void intel_enable_gt_powersave(struct drm_device *dev) 3500 { 3501 struct drm_i915_private *dev_priv = dev->dev_private; 3502 3503 if (IS_IRONLAKE_M(dev)) { 3504 ironlake_enable_drps(dev); 3505 ironlake_enable_rc6(dev); 3506 intel_init_emon(dev); 3507 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { 3508 /* 3509 * PCU communication is slow and this doesn't need to be 3510 * done at any specific time, so do this out of our fast path 3511 * to make resume and init faster. 3512 */ 3513 schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 3514 round_jiffies_up_relative(HZ)); 3515 } 3516 } 3517 3518 static void ibx_init_clock_gating(struct drm_device *dev) 3519 { 3520 struct drm_i915_private *dev_priv = dev->dev_private; 3521 3522 /* 3523 * On Ibex Peak and Cougar Point, we need to disable clock 3524 * gating for the panel power sequencer or it will fail to 3525 * start up when no ports are active. 3526 */ 3527 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3528 } 3529 3530 static void ironlake_init_clock_gating(struct drm_device *dev) 3531 { 3532 struct drm_i915_private *dev_priv = dev->dev_private; 3533 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3534 3535 /* Required for FBC */ 3536 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 3537 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 3538 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 3539 3540 I915_WRITE(PCH_3DCGDIS0, 3541 MARIUNIT_CLOCK_GATE_DISABLE | 3542 SVSMUNIT_CLOCK_GATE_DISABLE); 3543 I915_WRITE(PCH_3DCGDIS1, 3544 VFMUNIT_CLOCK_GATE_DISABLE); 3545 3546 /* 3547 * According to the spec the following bits should be set in 3548 * order to enable memory self-refresh 3549 * The bit 22/21 of 0x42004 3550 * The bit 5 of 0x42020 3551 * The bit 15 of 0x45000 3552 */ 3553 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3554 (I915_READ(ILK_DISPLAY_CHICKEN2) | 3555 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 3556 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 3557 I915_WRITE(DISP_ARB_CTL, 3558 (I915_READ(DISP_ARB_CTL) | 3559 DISP_FBC_WM_DIS)); 3560 I915_WRITE(WM3_LP_ILK, 0); 3561 I915_WRITE(WM2_LP_ILK, 0); 3562 I915_WRITE(WM1_LP_ILK, 0); 3563 3564 /* 3565 * Based on the document from hardware guys the following bits 3566 * should be set unconditionally in order to enable FBC. 3567 * The bit 22 of 0x42000 3568 * The bit 22 of 0x42004 3569 * The bit 7,8,9 of 0x42020. 3570 */ 3571 if (IS_IRONLAKE_M(dev)) { 3572 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3573 I915_READ(ILK_DISPLAY_CHICKEN1) | 3574 ILK_FBCQ_DIS); 3575 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3576 I915_READ(ILK_DISPLAY_CHICKEN2) | 3577 ILK_DPARB_GATE); 3578 } 3579 3580 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3581 3582 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3583 I915_READ(ILK_DISPLAY_CHICKEN2) | 3584 ILK_ELPIN_409_SELECT); 3585 I915_WRITE(_3D_CHICKEN2, 3586 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 3587 _3D_CHICKEN2_WM_READ_PIPELINED); 3588 3589 /* WaDisableRenderCachePipelinedFlush */ 3590 I915_WRITE(CACHE_MODE_0, 3591 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 3592 3593 ibx_init_clock_gating(dev); 3594 } 3595 3596 static void cpt_init_clock_gating(struct drm_device *dev) 3597 { 3598 struct drm_i915_private *dev_priv = dev->dev_private; 3599 int pipe; 3600 3601 /* 3602 * On Ibex Peak and Cougar Point, we need to disable clock 3603 * gating for the panel power sequencer or it will fail to 3604 * start up when no ports are active. 3605 */ 3606 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3607 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 3608 DPLS_EDP_PPS_FIX_DIS); 3609 /* The below fixes the weird display corruption, a few pixels shifted 3610 * downward, on (only) LVDS of some HP laptops with IVY. 3611 */ 3612 for_each_pipe(pipe) 3613 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); 3614 /* WADP0ClockGatingDisable */ 3615 for_each_pipe(pipe) { 3616 I915_WRITE(TRANS_CHICKEN1(pipe), 3617 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 3618 } 3619 } 3620 3621 static void gen6_init_clock_gating(struct drm_device *dev) 3622 { 3623 struct drm_i915_private *dev_priv = dev->dev_private; 3624 int pipe; 3625 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3626 3627 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3628 3629 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3630 I915_READ(ILK_DISPLAY_CHICKEN2) | 3631 ILK_ELPIN_409_SELECT); 3632 3633 /* WaDisableHiZPlanesWhenMSAAEnabled */ 3634 I915_WRITE(_3D_CHICKEN, 3635 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 3636 3637 /* WaSetupGtModeTdRowDispatch */ 3638 if (IS_SNB_GT1(dev)) 3639 I915_WRITE(GEN6_GT_MODE, 3640 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 3641 3642 I915_WRITE(WM3_LP_ILK, 0); 3643 I915_WRITE(WM2_LP_ILK, 0); 3644 I915_WRITE(WM1_LP_ILK, 0); 3645 3646 I915_WRITE(CACHE_MODE_0, 3647 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 3648 3649 I915_WRITE(GEN6_UCGCTL1, 3650 I915_READ(GEN6_UCGCTL1) | 3651 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 3652 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 3653 3654 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3655 * gating disable must be set. Failure to set it results in 3656 * flickering pixels due to Z write ordering failures after 3657 * some amount of runtime in the Mesa "fire" demo, and Unigine 3658 * Sanctuary and Tropics, and apparently anything else with 3659 * alpha test or pixel discard. 3660 * 3661 * According to the spec, bit 11 (RCCUNIT) must also be set, 3662 * but we didn't debug actual testcases to find it out. 3663 * 3664 * Also apply WaDisableVDSUnitClockGating and 3665 * WaDisableRCPBUnitClockGating. 3666 */ 3667 I915_WRITE(GEN6_UCGCTL2, 3668 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3669 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3670 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3671 3672 /* Bspec says we need to always set all mask bits. */ 3673 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 3674 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 3675 3676 /* 3677 * According to the spec the following bits should be 3678 * set in order to enable memory self-refresh and fbc: 3679 * The bit21 and bit22 of 0x42000 3680 * The bit21 and bit22 of 0x42004 3681 * The bit5 and bit7 of 0x42020 3682 * The bit14 of 0x70180 3683 * The bit14 of 0x71180 3684 */ 3685 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3686 I915_READ(ILK_DISPLAY_CHICKEN1) | 3687 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 3688 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3689 I915_READ(ILK_DISPLAY_CHICKEN2) | 3690 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 3691 I915_WRITE(ILK_DSPCLK_GATE_D, 3692 I915_READ(ILK_DSPCLK_GATE_D) | 3693 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 3694 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 3695 3696 /* WaMbcDriverBootEnable */ 3697 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3698 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3699 3700 for_each_pipe(pipe) { 3701 I915_WRITE(DSPCNTR(pipe), 3702 I915_READ(DSPCNTR(pipe)) | 3703 DISPPLANE_TRICKLE_FEED_DISABLE); 3704 intel_flush_display_plane(dev_priv, pipe); 3705 } 3706 3707 /* The default value should be 0x200 according to docs, but the two 3708 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 3709 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); 3710 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); 3711 3712 cpt_init_clock_gating(dev); 3713 } 3714 3715 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 3716 { 3717 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 3718 3719 reg &= ~GEN7_FF_SCHED_MASK; 3720 reg |= GEN7_FF_TS_SCHED_HW; 3721 reg |= GEN7_FF_VS_SCHED_HW; 3722 reg |= GEN7_FF_DS_SCHED_HW; 3723 3724 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 3725 } 3726 3727 static void lpt_init_clock_gating(struct drm_device *dev) 3728 { 3729 struct drm_i915_private *dev_priv = dev->dev_private; 3730 3731 /* 3732 * TODO: this bit should only be enabled when really needed, then 3733 * disabled when not needed anymore in order to save power. 3734 */ 3735 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 3736 I915_WRITE(SOUTH_DSPCLK_GATE_D, 3737 I915_READ(SOUTH_DSPCLK_GATE_D) | 3738 PCH_LP_PARTITION_LEVEL_DISABLE); 3739 } 3740 3741 static void haswell_init_clock_gating(struct drm_device *dev) 3742 { 3743 struct drm_i915_private *dev_priv = dev->dev_private; 3744 int pipe; 3745 3746 I915_WRITE(WM3_LP_ILK, 0); 3747 I915_WRITE(WM2_LP_ILK, 0); 3748 I915_WRITE(WM1_LP_ILK, 0); 3749 3750 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3751 * This implements the WaDisableRCZUnitClockGating workaround. 3752 */ 3753 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 3754 3755 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3756 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3757 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3758 3759 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3760 I915_WRITE(GEN7_L3CNTLREG1, 3761 GEN7_WA_FOR_GEN7_L3_CONTROL); 3762 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3763 GEN7_WA_L3_CHICKEN_MODE); 3764 3765 /* This is required by WaCatErrorRejectionIssue */ 3766 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3767 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3768 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3769 3770 for_each_pipe(pipe) { 3771 I915_WRITE(DSPCNTR(pipe), 3772 I915_READ(DSPCNTR(pipe)) | 3773 DISPPLANE_TRICKLE_FEED_DISABLE); 3774 intel_flush_display_plane(dev_priv, pipe); 3775 } 3776 3777 gen7_setup_fixed_func_scheduler(dev_priv); 3778 3779 /* WaDisable4x2SubspanOptimization */ 3780 I915_WRITE(CACHE_MODE_1, 3781 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3782 3783 /* WaMbcDriverBootEnable */ 3784 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3785 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3786 3787 /* XXX: This is a workaround for early silicon revisions and should be 3788 * removed later. 3789 */ 3790 I915_WRITE(WM_DBG, 3791 I915_READ(WM_DBG) | 3792 WM_DBG_DISALLOW_MULTIPLE_LP | 3793 WM_DBG_DISALLOW_SPRITE | 3794 WM_DBG_DISALLOW_MAXFIFO); 3795 3796 lpt_init_clock_gating(dev); 3797 } 3798 3799 static void ivybridge_init_clock_gating(struct drm_device *dev) 3800 { 3801 struct drm_i915_private *dev_priv = dev->dev_private; 3802 int pipe; 3803 uint32_t snpcr; 3804 3805 I915_WRITE(WM3_LP_ILK, 0); 3806 I915_WRITE(WM2_LP_ILK, 0); 3807 I915_WRITE(WM1_LP_ILK, 0); 3808 3809 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3810 3811 /* WaDisableEarlyCull */ 3812 I915_WRITE(_3D_CHICKEN3, 3813 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3814 3815 /* WaDisableBackToBackFlipFix */ 3816 I915_WRITE(IVB_CHICKEN3, 3817 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3818 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3819 3820 /* WaDisablePSDDualDispatchEnable */ 3821 if (IS_IVB_GT1(dev)) 3822 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3823 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3824 else 3825 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, 3826 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3827 3828 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3829 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3830 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3831 3832 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3833 I915_WRITE(GEN7_L3CNTLREG1, 3834 GEN7_WA_FOR_GEN7_L3_CONTROL); 3835 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3836 GEN7_WA_L3_CHICKEN_MODE); 3837 if (IS_IVB_GT1(dev)) 3838 I915_WRITE(GEN7_ROW_CHICKEN2, 3839 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3840 else 3841 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 3842 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3843 3844 3845 /* WaForceL3Serialization */ 3846 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3847 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3848 3849 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3850 * gating disable must be set. Failure to set it results in 3851 * flickering pixels due to Z write ordering failures after 3852 * some amount of runtime in the Mesa "fire" demo, and Unigine 3853 * Sanctuary and Tropics, and apparently anything else with 3854 * alpha test or pixel discard. 3855 * 3856 * According to the spec, bit 11 (RCCUNIT) must also be set, 3857 * but we didn't debug actual testcases to find it out. 3858 * 3859 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3860 * This implements the WaDisableRCZUnitClockGating workaround. 3861 */ 3862 I915_WRITE(GEN6_UCGCTL2, 3863 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3864 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3865 3866 /* This is required by WaCatErrorRejectionIssue */ 3867 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3868 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3869 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3870 3871 for_each_pipe(pipe) { 3872 I915_WRITE(DSPCNTR(pipe), 3873 I915_READ(DSPCNTR(pipe)) | 3874 DISPPLANE_TRICKLE_FEED_DISABLE); 3875 intel_flush_display_plane(dev_priv, pipe); 3876 } 3877 3878 /* WaMbcDriverBootEnable */ 3879 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3880 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3881 3882 gen7_setup_fixed_func_scheduler(dev_priv); 3883 3884 /* WaDisable4x2SubspanOptimization */ 3885 I915_WRITE(CACHE_MODE_1, 3886 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3887 3888 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 3889 snpcr &= ~GEN6_MBC_SNPCR_MASK; 3890 snpcr |= GEN6_MBC_SNPCR_MED; 3891 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 3892 3893 cpt_init_clock_gating(dev); 3894 } 3895 3896 static void valleyview_init_clock_gating(struct drm_device *dev) 3897 { 3898 struct drm_i915_private *dev_priv = dev->dev_private; 3899 int pipe; 3900 3901 I915_WRITE(WM3_LP_ILK, 0); 3902 I915_WRITE(WM2_LP_ILK, 0); 3903 I915_WRITE(WM1_LP_ILK, 0); 3904 3905 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3906 3907 /* WaDisableEarlyCull */ 3908 I915_WRITE(_3D_CHICKEN3, 3909 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3910 3911 /* WaDisableBackToBackFlipFix */ 3912 I915_WRITE(IVB_CHICKEN3, 3913 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3914 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3915 3916 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3917 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3918 3919 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3920 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3921 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3922 3923 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3924 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); 3925 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 3926 3927 /* WaForceL3Serialization */ 3928 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3929 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3930 3931 /* WaDisableDopClockGating */ 3932 I915_WRITE(GEN7_ROW_CHICKEN2, 3933 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3934 3935 /* WaForceL3Serialization */ 3936 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3937 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3938 3939 /* This is required by WaCatErrorRejectionIssue */ 3940 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3941 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3942 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3943 3944 /* WaMbcDriverBootEnable */ 3945 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3946 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3947 3948 3949 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3950 * gating disable must be set. Failure to set it results in 3951 * flickering pixels due to Z write ordering failures after 3952 * some amount of runtime in the Mesa "fire" demo, and Unigine 3953 * Sanctuary and Tropics, and apparently anything else with 3954 * alpha test or pixel discard. 3955 * 3956 * According to the spec, bit 11 (RCCUNIT) must also be set, 3957 * but we didn't debug actual testcases to find it out. 3958 * 3959 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3960 * This implements the WaDisableRCZUnitClockGating workaround. 3961 * 3962 * Also apply WaDisableVDSUnitClockGating and 3963 * WaDisableRCPBUnitClockGating. 3964 */ 3965 I915_WRITE(GEN6_UCGCTL2, 3966 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3967 GEN7_TDLUNIT_CLOCK_GATE_DISABLE | 3968 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3969 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3970 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3971 3972 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 3973 3974 for_each_pipe(pipe) { 3975 I915_WRITE(DSPCNTR(pipe), 3976 I915_READ(DSPCNTR(pipe)) | 3977 DISPPLANE_TRICKLE_FEED_DISABLE); 3978 intel_flush_display_plane(dev_priv, pipe); 3979 } 3980 3981 I915_WRITE(CACHE_MODE_1, 3982 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3983 3984 /* 3985 * On ValleyView, the GUnit needs to signal the GT 3986 * when flip and other events complete. So enable 3987 * all the GUnit->GT interrupts here 3988 */ 3989 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | 3990 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | 3991 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | 3992 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | 3993 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | 3994 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | 3995 PLANEA_FLIPDONE_INT_EN); 3996 3997 /* 3998 * WaDisableVLVClockGating_VBIIssue 3999 * Disable clock gating on th GCFG unit to prevent a delay 4000 * in the reporting of vblank events. 4001 */ 4002 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 4003 } 4004 4005 static void g4x_init_clock_gating(struct drm_device *dev) 4006 { 4007 struct drm_i915_private *dev_priv = dev->dev_private; 4008 uint32_t dspclk_gate; 4009 4010 I915_WRITE(RENCLK_GATE_D1, 0); 4011 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 4012 GS_UNIT_CLOCK_GATE_DISABLE | 4013 CL_UNIT_CLOCK_GATE_DISABLE); 4014 I915_WRITE(RAMCLK_GATE_D, 0); 4015 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 4016 OVRUNIT_CLOCK_GATE_DISABLE | 4017 OVCUNIT_CLOCK_GATE_DISABLE; 4018 if (IS_GM45(dev)) 4019 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 4020 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 4021 4022 /* WaDisableRenderCachePipelinedFlush */ 4023 I915_WRITE(CACHE_MODE_0, 4024 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4025 } 4026 4027 static void crestline_init_clock_gating(struct drm_device *dev) 4028 { 4029 struct drm_i915_private *dev_priv = dev->dev_private; 4030 4031 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 4032 I915_WRITE(RENCLK_GATE_D2, 0); 4033 I915_WRITE(DSPCLK_GATE_D, 0); 4034 I915_WRITE(RAMCLK_GATE_D, 0); 4035 I915_WRITE16(DEUC, 0); 4036 } 4037 4038 static void broadwater_init_clock_gating(struct drm_device *dev) 4039 { 4040 struct drm_i915_private *dev_priv = dev->dev_private; 4041 4042 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 4043 I965_RCC_CLOCK_GATE_DISABLE | 4044 I965_RCPB_CLOCK_GATE_DISABLE | 4045 I965_ISC_CLOCK_GATE_DISABLE | 4046 I965_FBC_CLOCK_GATE_DISABLE); 4047 I915_WRITE(RENCLK_GATE_D2, 0); 4048 } 4049 4050 static void gen3_init_clock_gating(struct drm_device *dev) 4051 { 4052 struct drm_i915_private *dev_priv = dev->dev_private; 4053 u32 dstate = I915_READ(D_STATE); 4054 4055 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4056 DSTATE_DOT_CLOCK_GATING; 4057 I915_WRITE(D_STATE, dstate); 4058 4059 if (IS_PINEVIEW(dev)) 4060 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 4061 4062 /* IIR "flip pending" means done if this bit is set */ 4063 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 4064 } 4065 4066 static void i85x_init_clock_gating(struct drm_device *dev) 4067 { 4068 struct drm_i915_private *dev_priv = dev->dev_private; 4069 4070 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4071 } 4072 4073 static void i830_init_clock_gating(struct drm_device *dev) 4074 { 4075 struct drm_i915_private *dev_priv = dev->dev_private; 4076 4077 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4078 } 4079 4080 void intel_init_clock_gating(struct drm_device *dev) 4081 { 4082 struct drm_i915_private *dev_priv = dev->dev_private; 4083 4084 dev_priv->display.init_clock_gating(dev); 4085 } 4086 4087 /* Starting with Haswell, we have different power wells for 4088 * different parts of the GPU. This attempts to enable them all. 4089 */ 4090 void intel_init_power_wells(struct drm_device *dev) 4091 { 4092 struct drm_i915_private *dev_priv = dev->dev_private; 4093 unsigned long power_wells[] = { 4094 HSW_PWR_WELL_CTL1, 4095 HSW_PWR_WELL_CTL2, 4096 HSW_PWR_WELL_CTL4 4097 }; 4098 int i; 4099 4100 if (!IS_HASWELL(dev)) 4101 return; 4102 4103 mutex_lock(&dev->struct_mutex); 4104 4105 for (i = 0; i < ARRAY_SIZE(power_wells); i++) { 4106 int well = I915_READ(power_wells[i]); 4107 4108 if ((well & HSW_PWR_WELL_STATE) == 0) { 4109 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); 4110 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) 4111 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); 4112 } 4113 } 4114 4115 mutex_unlock(&dev->struct_mutex); 4116 } 4117 4118 /* Set up chip specific power management-related functions */ 4119 void intel_init_pm(struct drm_device *dev) 4120 { 4121 struct drm_i915_private *dev_priv = dev->dev_private; 4122 4123 if (I915_HAS_FBC(dev)) { 4124 if (HAS_PCH_SPLIT(dev)) { 4125 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 4126 dev_priv->display.enable_fbc = ironlake_enable_fbc; 4127 dev_priv->display.disable_fbc = ironlake_disable_fbc; 4128 } else if (IS_GM45(dev)) { 4129 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4130 dev_priv->display.enable_fbc = g4x_enable_fbc; 4131 dev_priv->display.disable_fbc = g4x_disable_fbc; 4132 } else if (IS_CRESTLINE(dev)) { 4133 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4134 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4135 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4136 } 4137 /* 855GM needs testing */ 4138 } 4139 4140 /* For cxsr */ 4141 if (IS_PINEVIEW(dev)) 4142 i915_pineview_get_mem_freq(dev); 4143 else if (IS_GEN5(dev)) 4144 i915_ironlake_get_mem_freq(dev); 4145 4146 /* For FIFO watermark updates */ 4147 if (HAS_PCH_SPLIT(dev)) { 4148 if (IS_GEN5(dev)) { 4149 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) 4150 dev_priv->display.update_wm = ironlake_update_wm; 4151 else { 4152 DRM_DEBUG_KMS("Failed to get proper latency. " 4153 "Disable CxSR\n"); 4154 dev_priv->display.update_wm = NULL; 4155 } 4156 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 4157 } else if (IS_GEN6(dev)) { 4158 if (SNB_READ_WM0_LATENCY()) { 4159 dev_priv->display.update_wm = sandybridge_update_wm; 4160 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4161 } else { 4162 DRM_DEBUG_KMS("Failed to read display plane latency. " 4163 "Disable CxSR\n"); 4164 dev_priv->display.update_wm = NULL; 4165 } 4166 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 4167 } else if (IS_IVYBRIDGE(dev)) { 4168 /* FIXME: detect B0+ stepping and use auto training */ 4169 if (SNB_READ_WM0_LATENCY()) { 4170 dev_priv->display.update_wm = ivybridge_update_wm; 4171 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4172 } else { 4173 DRM_DEBUG_KMS("Failed to read display plane latency. " 4174 "Disable CxSR\n"); 4175 dev_priv->display.update_wm = NULL; 4176 } 4177 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 4178 } else if (IS_HASWELL(dev)) { 4179 if (SNB_READ_WM0_LATENCY()) { 4180 dev_priv->display.update_wm = sandybridge_update_wm; 4181 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4182 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; 4183 } else { 4184 DRM_DEBUG_KMS("Failed to read display plane latency. " 4185 "Disable CxSR\n"); 4186 dev_priv->display.update_wm = NULL; 4187 } 4188 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 4189 } else 4190 dev_priv->display.update_wm = NULL; 4191 } else if (IS_VALLEYVIEW(dev)) { 4192 dev_priv->display.update_wm = valleyview_update_wm; 4193 dev_priv->display.init_clock_gating = 4194 valleyview_init_clock_gating; 4195 } else if (IS_PINEVIEW(dev)) { 4196 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 4197 dev_priv->is_ddr3, 4198 dev_priv->fsb_freq, 4199 dev_priv->mem_freq)) { 4200 DRM_INFO("failed to find known CxSR latency " 4201 "(found ddr%s fsb freq %d, mem freq %d), " 4202 "disabling CxSR\n", 4203 (dev_priv->is_ddr3 == 1) ? "3" : "2", 4204 dev_priv->fsb_freq, dev_priv->mem_freq); 4205 /* Disable CxSR and never update its watermark again */ 4206 pineview_disable_cxsr(dev); 4207 dev_priv->display.update_wm = NULL; 4208 } else 4209 dev_priv->display.update_wm = pineview_update_wm; 4210 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4211 } else if (IS_G4X(dev)) { 4212 dev_priv->display.update_wm = g4x_update_wm; 4213 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 4214 } else if (IS_GEN4(dev)) { 4215 dev_priv->display.update_wm = i965_update_wm; 4216 if (IS_CRESTLINE(dev)) 4217 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 4218 else if (IS_BROADWATER(dev)) 4219 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 4220 } else if (IS_GEN3(dev)) { 4221 dev_priv->display.update_wm = i9xx_update_wm; 4222 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4223 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4224 } else if (IS_I865G(dev)) { 4225 dev_priv->display.update_wm = i830_update_wm; 4226 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4227 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4228 } else if (IS_I85X(dev)) { 4229 dev_priv->display.update_wm = i9xx_update_wm; 4230 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4231 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4232 } else { 4233 dev_priv->display.update_wm = i830_update_wm; 4234 dev_priv->display.init_clock_gating = i830_init_clock_gating; 4235 if (IS_845G(dev)) 4236 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4237 else 4238 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4239 } 4240 } 4241 4242 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 4243 { 4244 u32 gt_thread_status_mask; 4245 4246 if (IS_HASWELL(dev_priv->dev)) 4247 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 4248 else 4249 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 4250 4251 /* w/a for a sporadic read returning 0 by waiting for the GT 4252 * thread to wake up. 4253 */ 4254 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 4255 DRM_ERROR("GT thread status wait timed out\n"); 4256 } 4257 4258 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 4259 { 4260 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4261 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4262 } 4263 4264 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4265 { 4266 u32 forcewake_ack; 4267 4268 if (IS_HASWELL(dev_priv->dev)) 4269 forcewake_ack = FORCEWAKE_ACK_HSW; 4270 else 4271 forcewake_ack = FORCEWAKE_ACK; 4272 4273 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4274 FORCEWAKE_ACK_TIMEOUT_MS)) 4275 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4276 4277 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); 4278 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4279 4280 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4281 FORCEWAKE_ACK_TIMEOUT_MS)) 4282 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4283 4284 __gen6_gt_wait_for_thread_c0(dev_priv); 4285 } 4286 4287 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 4288 { 4289 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 4290 /* something from same cacheline, but !FORCEWAKE_MT */ 4291 POSTING_READ(ECOBUS); 4292 } 4293 4294 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 4295 { 4296 u32 forcewake_ack; 4297 4298 if (IS_HASWELL(dev_priv->dev)) 4299 forcewake_ack = FORCEWAKE_ACK_HSW; 4300 else 4301 forcewake_ack = FORCEWAKE_MT_ACK; 4302 4303 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4304 FORCEWAKE_ACK_TIMEOUT_MS)) 4305 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4306 4307 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4308 /* something from same cacheline, but !FORCEWAKE_MT */ 4309 POSTING_READ(ECOBUS); 4310 4311 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4312 FORCEWAKE_ACK_TIMEOUT_MS)) 4313 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4314 4315 __gen6_gt_wait_for_thread_c0(dev_priv); 4316 } 4317 4318 /* 4319 * Generally this is called implicitly by the register read function. However, 4320 * if some sequence requires the GT to not power down then this function should 4321 * be called at the beginning of the sequence followed by a call to 4322 * gen6_gt_force_wake_put() at the end of the sequence. 4323 */ 4324 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4325 { 4326 unsigned long irqflags; 4327 4328 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); 4329 if (dev_priv->forcewake_count++ == 0) 4330 dev_priv->gt.force_wake_get(dev_priv); 4331 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); 4332 } 4333 4334 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 4335 { 4336 u32 gtfifodbg; 4337 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 4338 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 4339 "MMIO read or write has been dropped %x\n", gtfifodbg)) 4340 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 4341 } 4342 4343 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4344 { 4345 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4346 /* something from same cacheline, but !FORCEWAKE */ 4347 POSTING_READ(ECOBUS); 4348 gen6_gt_check_fifodbg(dev_priv); 4349 } 4350 4351 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4352 { 4353 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4354 /* something from same cacheline, but !FORCEWAKE_MT */ 4355 POSTING_READ(ECOBUS); 4356 gen6_gt_check_fifodbg(dev_priv); 4357 } 4358 4359 /* 4360 * see gen6_gt_force_wake_get() 4361 */ 4362 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4363 { 4364 unsigned long irqflags; 4365 4366 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); 4367 if (--dev_priv->forcewake_count == 0) 4368 dev_priv->gt.force_wake_put(dev_priv); 4369 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); 4370 } 4371 4372 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 4373 { 4374 int ret = 0; 4375 4376 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 4377 int loop = 500; 4378 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4379 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 4380 udelay(10); 4381 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4382 } 4383 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 4384 ++ret; 4385 dev_priv->gt_fifo_count = fifo; 4386 } 4387 dev_priv->gt_fifo_count--; 4388 4389 return ret; 4390 } 4391 4392 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 4393 { 4394 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); 4395 /* something from same cacheline, but !FORCEWAKE_VLV */ 4396 POSTING_READ(FORCEWAKE_ACK_VLV); 4397 } 4398 4399 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 4400 { 4401 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, 4402 FORCEWAKE_ACK_TIMEOUT_MS)) 4403 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4404 4405 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4406 4407 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 4408 FORCEWAKE_ACK_TIMEOUT_MS)) 4409 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4410 4411 __gen6_gt_wait_for_thread_c0(dev_priv); 4412 } 4413 4414 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 4415 { 4416 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4417 /* something from same cacheline, but !FORCEWAKE_VLV */ 4418 POSTING_READ(FORCEWAKE_ACK_VLV); 4419 gen6_gt_check_fifodbg(dev_priv); 4420 } 4421 4422 void intel_gt_reset(struct drm_device *dev) 4423 { 4424 struct drm_i915_private *dev_priv = dev->dev_private; 4425 4426 if (IS_VALLEYVIEW(dev)) { 4427 vlv_force_wake_reset(dev_priv); 4428 } else if (INTEL_INFO(dev)->gen >= 6) { 4429 __gen6_gt_force_wake_reset(dev_priv); 4430 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 4431 __gen6_gt_force_wake_mt_reset(dev_priv); 4432 } 4433 } 4434 4435 void intel_gt_init(struct drm_device *dev) 4436 { 4437 struct drm_i915_private *dev_priv = dev->dev_private; 4438 4439 spin_lock_init(&dev_priv->gt_lock); 4440 4441 intel_gt_reset(dev); 4442 4443 if (IS_VALLEYVIEW(dev)) { 4444 dev_priv->gt.force_wake_get = vlv_force_wake_get; 4445 dev_priv->gt.force_wake_put = vlv_force_wake_put; 4446 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 4447 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; 4448 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; 4449 } else if (IS_GEN6(dev)) { 4450 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; 4451 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; 4452 } 4453 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 4454 intel_gen6_powersave_work); 4455 } 4456 4457 #ifdef __NetBSD__ /* XXX gt fini */ 4458 void 4459 intel_gt_fini(struct drm_device *dev) 4460 { 4461 struct drm_i915_private *dev_priv = dev->dev_private; 4462 4463 spin_lock_destroy(&dev_priv->gt_lock); 4464 } 4465 #endif 4466 4467 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 4468 { 4469 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4470 4471 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4472 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 4473 return -EAGAIN; 4474 } 4475 4476 I915_WRITE(GEN6_PCODE_DATA, *val); 4477 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4478 4479 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4480 500)) { 4481 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 4482 return -ETIMEDOUT; 4483 } 4484 4485 *val = I915_READ(GEN6_PCODE_DATA); 4486 I915_WRITE(GEN6_PCODE_DATA, 0); 4487 4488 return 0; 4489 } 4490 4491 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 4492 { 4493 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4494 4495 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4496 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 4497 return -EAGAIN; 4498 } 4499 4500 I915_WRITE(GEN6_PCODE_DATA, val); 4501 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4502 4503 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4504 500)) { 4505 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 4506 return -ETIMEDOUT; 4507 } 4508 4509 I915_WRITE(GEN6_PCODE_DATA, 0); 4510 4511 return 0; 4512 } 4513
Indexes created Sat Oct 11 19:10:01 GMT 2025