intel_pm.c revision 1.23
1 /* $NetBSD: intel_pm.c,v 1.23 2020/02/14 09:39:37 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.23 2020/02/14 09:39:37 riastradh Exp $"); 32 33 #include <linux/bitops.h> 34 #include <linux/cpufreq.h> 35 #include <linux/export.h> 36 #include "i915_drv.h" 37 #include "i915_trace.h" 38 #include "intel_drv.h" 39 #ifndef __NetBSD__ 40 #include "../../../platform/x86/intel_ips.h" 41 #endif 42 #include <linux/module.h> 43 #include <linux/log2.h> 44 #include <linux/math64.h> 45 #include <linux/time.h> 46 47 #include <linux/nbsd-namespace.h> 48 49 /** 50 * RC6 is a special power stage which allows the GPU to enter an very 51 * low-voltage mode when idle, using down to 0V while at this stage. This 52 * stage is entered automatically when the GPU is idle when RC6 support is 53 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 54 * 55 * There are different RC6 modes available in Intel GPU, which differentiate 56 * among each other with the latency required to enter and leave RC6 and 57 * voltage consumed by the GPU in different states. 58 * 59 * The combination of the following flags define which states GPU is allowed 60 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 61 * RC6pp is deepest RC6. Their support by hardware varies according to the 62 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 63 * which brings the most power savings; deeper states save more power, but 64 * require higher latency to switch to and wake up. 65 */ 66 #define INTEL_RC6_ENABLE (1<<0) 67 #define INTEL_RC6p_ENABLE (1<<1) 68 #define INTEL_RC6pp_ENABLE (1<<2) 69 70 static void bxt_init_clock_gating(struct drm_device *dev) 71 { 72 struct drm_i915_private *dev_priv = dev->dev_private; 73 74 /* WaDisableSDEUnitClockGating:bxt */ 75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 76 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 77 78 /* 79 * FIXME: 80 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 81 */ 82 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 83 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 84 85 /* 86 * Lower the display internal timeout. 87 * This is needed to avoid any hard hangs when DSI port PLL 88 * is off and a MMIO access is attempted by any privilege 89 * application, using batch buffers or any other means. 90 */ 91 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 92 } 93 94 static void i915_pineview_get_mem_freq(struct drm_device *dev) 95 { 96 struct drm_i915_private *dev_priv = dev->dev_private; 97 u32 tmp; 98 99 tmp = I915_READ(CLKCFG); 100 101 switch (tmp & CLKCFG_FSB_MASK) { 102 case CLKCFG_FSB_533: 103 dev_priv->fsb_freq = 533; /* 133*4 */ 104 break; 105 case CLKCFG_FSB_800: 106 dev_priv->fsb_freq = 800; /* 200*4 */ 107 break; 108 case CLKCFG_FSB_667: 109 dev_priv->fsb_freq = 667; /* 167*4 */ 110 break; 111 case CLKCFG_FSB_400: 112 dev_priv->fsb_freq = 400; /* 100*4 */ 113 break; 114 } 115 116 switch (tmp & CLKCFG_MEM_MASK) { 117 case CLKCFG_MEM_533: 118 dev_priv->mem_freq = 533; 119 break; 120 case CLKCFG_MEM_667: 121 dev_priv->mem_freq = 667; 122 break; 123 case CLKCFG_MEM_800: 124 dev_priv->mem_freq = 800; 125 break; 126 } 127 128 /* detect pineview DDR3 setting */ 129 tmp = I915_READ(CSHRDDR3CTL); 130 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 131 } 132 133 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 134 { 135 struct drm_i915_private *dev_priv = dev->dev_private; 136 u16 ddrpll, csipll; 137 138 ddrpll = I915_READ16(DDRMPLL1); 139 csipll = I915_READ16(CSIPLL0); 140 141 switch (ddrpll & 0xff) { 142 case 0xc: 143 dev_priv->mem_freq = 800; 144 break; 145 case 0x10: 146 dev_priv->mem_freq = 1066; 147 break; 148 case 0x14: 149 dev_priv->mem_freq = 1333; 150 break; 151 case 0x18: 152 dev_priv->mem_freq = 1600; 153 break; 154 default: 155 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 156 ddrpll & 0xff); 157 dev_priv->mem_freq = 0; 158 break; 159 } 160 161 dev_priv->ips.r_t = dev_priv->mem_freq; 162 163 switch (csipll & 0x3ff) { 164 case 0x00c: 165 dev_priv->fsb_freq = 3200; 166 break; 167 case 0x00e: 168 dev_priv->fsb_freq = 3733; 169 break; 170 case 0x010: 171 dev_priv->fsb_freq = 4266; 172 break; 173 case 0x012: 174 dev_priv->fsb_freq = 4800; 175 break; 176 case 0x014: 177 dev_priv->fsb_freq = 5333; 178 break; 179 case 0x016: 180 dev_priv->fsb_freq = 5866; 181 break; 182 case 0x018: 183 dev_priv->fsb_freq = 6400; 184 break; 185 default: 186 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 187 csipll & 0x3ff); 188 dev_priv->fsb_freq = 0; 189 break; 190 } 191 192 if (dev_priv->fsb_freq == 3200) { 193 dev_priv->ips.c_m = 0; 194 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 195 dev_priv->ips.c_m = 1; 196 } else { 197 dev_priv->ips.c_m = 2; 198 } 199 } 200 201 static const struct cxsr_latency cxsr_latency_table[] = { 202 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 203 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 204 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 205 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 206 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 207 208 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 209 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 210 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 211 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 212 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 213 214 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 215 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 216 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 217 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 218 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 219 220 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 221 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 222 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 223 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 224 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 225 226 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 227 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 228 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 229 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 230 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 231 232 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 233 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 234 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 235 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 236 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 237 }; 238 239 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 240 int is_ddr3, 241 int fsb, 242 int mem) 243 { 244 const struct cxsr_latency *latency; 245 int i; 246 247 if (fsb == 0 || mem == 0) 248 return NULL; 249 250 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 251 latency = &cxsr_latency_table[i]; 252 if (is_desktop == latency->is_desktop && 253 is_ddr3 == latency->is_ddr3 && 254 fsb == latency->fsb_freq && mem == latency->mem_freq) 255 return latency; 256 } 257 258 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 259 260 return NULL; 261 } 262 263 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 264 { 265 u32 val; 266 267 mutex_lock(&dev_priv->rps.hw_lock); 268 269 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 270 if (enable) 271 val &= ~FORCE_DDR_HIGH_FREQ; 272 else 273 val |= FORCE_DDR_HIGH_FREQ; 274 val &= ~FORCE_DDR_LOW_FREQ; 275 val |= FORCE_DDR_FREQ_REQ_ACK; 276 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 277 278 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 279 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 280 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 281 282 mutex_unlock(&dev_priv->rps.hw_lock); 283 } 284 285 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 286 { 287 u32 val; 288 289 mutex_lock(&dev_priv->rps.hw_lock); 290 291 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 292 if (enable) 293 val |= DSP_MAXFIFO_PM5_ENABLE; 294 else 295 val &= ~DSP_MAXFIFO_PM5_ENABLE; 296 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 297 298 mutex_unlock(&dev_priv->rps.hw_lock); 299 } 300 301 #define FW_WM(value, plane) \ 302 (((u32)(value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 303 304 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 305 { 306 struct drm_device *dev = dev_priv->dev; 307 u32 val; 308 309 if (IS_VALLEYVIEW(dev)) { 310 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 311 POSTING_READ(FW_BLC_SELF_VLV); 312 dev_priv->wm.vlv.cxsr = enable; 313 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 314 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 315 POSTING_READ(FW_BLC_SELF); 316 } else if (IS_PINEVIEW(dev)) { 317 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 318 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 319 I915_WRITE(DSPFW3, val); 320 POSTING_READ(DSPFW3); 321 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 322 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 323 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 324 I915_WRITE(FW_BLC_SELF, val); 325 POSTING_READ(FW_BLC_SELF); 326 } else if (IS_I915GM(dev)) { 327 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 328 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 329 I915_WRITE(INSTPM, val); 330 POSTING_READ(INSTPM); 331 } else { 332 return; 333 } 334 335 DRM_DEBUG_KMS("memory self-refresh is %s\n", 336 enable ? "enabled" : "disabled"); 337 } 338 339 340 /* 341 * Latency for FIFO fetches is dependent on several factors: 342 * - memory configuration (speed, channels) 343 * - chipset 344 * - current MCH state 345 * It can be fairly high in some situations, so here we assume a fairly 346 * pessimal value. It's a tradeoff between extra memory fetches (if we 347 * set this value too high, the FIFO will fetch frequently to stay full) 348 * and power consumption (set it too low to save power and we might see 349 * FIFO underruns and display "flicker"). 350 * 351 * A value of 5us seems to be a good balance; safe for very low end 352 * platforms but not overly aggressive on lower latency configs. 353 */ 354 static const int pessimal_latency_ns = 5000; 355 356 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 357 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 358 359 static int vlv_get_fifo_size(struct drm_device *dev, 360 enum pipe pipe, int plane) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 int sprite0_start, sprite1_start, size; 364 365 switch (pipe) { 366 uint32_t dsparb, dsparb2, dsparb3; 367 case PIPE_A: 368 dsparb = I915_READ(DSPARB); 369 dsparb2 = I915_READ(DSPARB2); 370 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 371 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 372 break; 373 case PIPE_B: 374 dsparb = I915_READ(DSPARB); 375 dsparb2 = I915_READ(DSPARB2); 376 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 377 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 378 break; 379 case PIPE_C: 380 dsparb2 = I915_READ(DSPARB2); 381 dsparb3 = I915_READ(DSPARB3); 382 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 383 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 384 break; 385 default: 386 return 0; 387 } 388 389 switch (plane) { 390 case 0: 391 size = sprite0_start; 392 break; 393 case 1: 394 size = sprite1_start - sprite0_start; 395 break; 396 case 2: 397 size = 512 - 1 - sprite1_start; 398 break; 399 default: 400 return 0; 401 } 402 403 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 404 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 405 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 406 size); 407 408 return size; 409 } 410 411 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 412 { 413 struct drm_i915_private *dev_priv = dev->dev_private; 414 uint32_t dsparb = I915_READ(DSPARB); 415 int size; 416 417 size = dsparb & 0x7f; 418 if (plane) 419 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 420 421 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 422 plane ? "B" : "A", size); 423 424 return size; 425 } 426 427 static int i830_get_fifo_size(struct drm_device *dev, int plane) 428 { 429 struct drm_i915_private *dev_priv = dev->dev_private; 430 uint32_t dsparb = I915_READ(DSPARB); 431 int size; 432 433 size = dsparb & 0x1ff; 434 if (plane) 435 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 436 size >>= 1; /* Convert to cachelines */ 437 438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 439 plane ? "B" : "A", size); 440 441 return size; 442 } 443 444 static int i845_get_fifo_size(struct drm_device *dev, int plane) 445 { 446 struct drm_i915_private *dev_priv = dev->dev_private; 447 uint32_t dsparb = I915_READ(DSPARB); 448 int size; 449 450 size = dsparb & 0x7f; 451 size >>= 2; /* Convert to cachelines */ 452 453 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 454 plane ? "B" : "A", 455 size); 456 457 return size; 458 } 459 460 /* Pineview has different values for various configs */ 461 static const struct intel_watermark_params pineview_display_wm = { 462 .fifo_size = PINEVIEW_DISPLAY_FIFO, 463 .max_wm = PINEVIEW_MAX_WM, 464 .default_wm = PINEVIEW_DFT_WM, 465 .guard_size = PINEVIEW_GUARD_WM, 466 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 467 }; 468 static const struct intel_watermark_params pineview_display_hplloff_wm = { 469 .fifo_size = PINEVIEW_DISPLAY_FIFO, 470 .max_wm = PINEVIEW_MAX_WM, 471 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 472 .guard_size = PINEVIEW_GUARD_WM, 473 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 474 }; 475 static const struct intel_watermark_params pineview_cursor_wm = { 476 .fifo_size = PINEVIEW_CURSOR_FIFO, 477 .max_wm = PINEVIEW_CURSOR_MAX_WM, 478 .default_wm = PINEVIEW_CURSOR_DFT_WM, 479 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 480 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 481 }; 482 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 483 .fifo_size = PINEVIEW_CURSOR_FIFO, 484 .max_wm = PINEVIEW_CURSOR_MAX_WM, 485 .default_wm = PINEVIEW_CURSOR_DFT_WM, 486 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 488 }; 489 static const struct intel_watermark_params g4x_wm_info = { 490 .fifo_size = G4X_FIFO_SIZE, 491 .max_wm = G4X_MAX_WM, 492 .default_wm = G4X_MAX_WM, 493 .guard_size = 2, 494 .cacheline_size = G4X_FIFO_LINE_SIZE, 495 }; 496 static const struct intel_watermark_params g4x_cursor_wm_info = { 497 .fifo_size = I965_CURSOR_FIFO, 498 .max_wm = I965_CURSOR_MAX_WM, 499 .default_wm = I965_CURSOR_DFT_WM, 500 .guard_size = 2, 501 .cacheline_size = G4X_FIFO_LINE_SIZE, 502 }; 503 static const struct intel_watermark_params valleyview_wm_info __unused = { 504 .fifo_size = VALLEYVIEW_FIFO_SIZE, 505 .max_wm = VALLEYVIEW_MAX_WM, 506 .default_wm = VALLEYVIEW_MAX_WM, 507 .guard_size = 2, 508 .cacheline_size = G4X_FIFO_LINE_SIZE, 509 }; 510 static const struct intel_watermark_params valleyview_cursor_wm_info __unused = { 511 .fifo_size = I965_CURSOR_FIFO, 512 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 513 .default_wm = I965_CURSOR_DFT_WM, 514 .guard_size = 2, 515 .cacheline_size = G4X_FIFO_LINE_SIZE, 516 }; 517 static const struct intel_watermark_params i965_cursor_wm_info = { 518 .fifo_size = I965_CURSOR_FIFO, 519 .max_wm = I965_CURSOR_MAX_WM, 520 .default_wm = I965_CURSOR_DFT_WM, 521 .guard_size = 2, 522 .cacheline_size = I915_FIFO_LINE_SIZE, 523 }; 524 static const struct intel_watermark_params i945_wm_info = { 525 .fifo_size = I945_FIFO_SIZE, 526 .max_wm = I915_MAX_WM, 527 .default_wm = 1, 528 .guard_size = 2, 529 .cacheline_size = I915_FIFO_LINE_SIZE, 530 }; 531 static const struct intel_watermark_params i915_wm_info = { 532 .fifo_size = I915_FIFO_SIZE, 533 .max_wm = I915_MAX_WM, 534 .default_wm = 1, 535 .guard_size = 2, 536 .cacheline_size = I915_FIFO_LINE_SIZE, 537 }; 538 static const struct intel_watermark_params i830_a_wm_info = { 539 .fifo_size = I855GM_FIFO_SIZE, 540 .max_wm = I915_MAX_WM, 541 .default_wm = 1, 542 .guard_size = 2, 543 .cacheline_size = I830_FIFO_LINE_SIZE, 544 }; 545 static const struct intel_watermark_params i830_bc_wm_info = { 546 .fifo_size = I855GM_FIFO_SIZE, 547 .max_wm = I915_MAX_WM/2, 548 .default_wm = 1, 549 .guard_size = 2, 550 .cacheline_size = I830_FIFO_LINE_SIZE, 551 }; 552 static const struct intel_watermark_params i845_wm_info = { 553 .fifo_size = I830_FIFO_SIZE, 554 .max_wm = I915_MAX_WM, 555 .default_wm = 1, 556 .guard_size = 2, 557 .cacheline_size = I830_FIFO_LINE_SIZE, 558 }; 559 560 /** 561 * intel_calculate_wm - calculate watermark level 562 * @clock_in_khz: pixel clock 563 * @wm: chip FIFO params 564 * @pixel_size: display pixel size 565 * @latency_ns: memory latency for the platform 566 * 567 * Calculate the watermark level (the level at which the display plane will 568 * start fetching from memory again). Each chip has a different display 569 * FIFO size and allocation, so the caller needs to figure that out and pass 570 * in the correct intel_watermark_params structure. 571 * 572 * As the pixel clock runs, the FIFO will be drained at a rate that depends 573 * on the pixel size. When it reaches the watermark level, it'll start 574 * fetching FIFO line sized based chunks from memory until the FIFO fills 575 * past the watermark point. If the FIFO drains completely, a FIFO underrun 576 * will occur, and a display engine hang could result. 577 */ 578 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 579 const struct intel_watermark_params *wm, 580 int fifo_size, 581 int pixel_size, 582 unsigned long latency_ns) 583 { 584 long entries_required, wm_size; 585 586 /* 587 * Note: we need to make sure we don't overflow for various clock & 588 * latency values. 589 * clocks go from a few thousand to several hundred thousand. 590 * latency is usually a few thousand 591 */ 592 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 593 1000; 594 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 595 596 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 597 598 wm_size = fifo_size - (entries_required + wm->guard_size); 599 600 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 601 602 /* Don't promote wm_size to unsigned... */ 603 if (wm_size > (long)wm->max_wm) 604 wm_size = wm->max_wm; 605 if (wm_size <= 0) 606 wm_size = wm->default_wm; 607 608 /* 609 * Bspec seems to indicate that the value shouldn't be lower than 610 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 611 * Lets go for 8 which is the burst size since certain platforms 612 * already use a hardcoded 8 (which is what the spec says should be 613 * done). 614 */ 615 if (wm_size <= 8) 616 wm_size = 8; 617 618 return wm_size; 619 } 620 621 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 622 { 623 struct drm_crtc *crtc, *enabled = NULL; 624 625 for_each_crtc(dev, crtc) { 626 if (intel_crtc_active(crtc)) { 627 if (enabled) 628 return NULL; 629 enabled = crtc; 630 } 631 } 632 633 return enabled; 634 } 635 636 static void pineview_update_wm(struct drm_crtc *unused_crtc) 637 { 638 struct drm_device *dev = unused_crtc->dev; 639 struct drm_i915_private *dev_priv = dev->dev_private; 640 struct drm_crtc *crtc; 641 const struct cxsr_latency *latency; 642 u32 reg; 643 unsigned long wm; 644 645 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 646 dev_priv->fsb_freq, dev_priv->mem_freq); 647 if (!latency) { 648 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 649 intel_set_memory_cxsr(dev_priv, false); 650 return; 651 } 652 653 crtc = single_enabled_crtc(dev); 654 if (crtc) { 655 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 656 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 657 int clock = adjusted_mode->crtc_clock; 658 659 /* Display SR */ 660 wm = intel_calculate_wm(clock, &pineview_display_wm, 661 pineview_display_wm.fifo_size, 662 pixel_size, latency->display_sr); 663 reg = I915_READ(DSPFW1); 664 reg &= ~DSPFW_SR_MASK; 665 reg |= FW_WM(wm, SR); 666 I915_WRITE(DSPFW1, reg); 667 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 668 669 /* cursor SR */ 670 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 671 pineview_display_wm.fifo_size, 672 pixel_size, latency->cursor_sr); 673 reg = I915_READ(DSPFW3); 674 reg &= ~DSPFW_CURSOR_SR_MASK; 675 reg |= FW_WM(wm, CURSOR_SR); 676 I915_WRITE(DSPFW3, reg); 677 678 /* Display HPLL off SR */ 679 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 680 pineview_display_hplloff_wm.fifo_size, 681 pixel_size, latency->display_hpll_disable); 682 reg = I915_READ(DSPFW3); 683 reg &= ~DSPFW_HPLL_SR_MASK; 684 reg |= FW_WM(wm, HPLL_SR); 685 I915_WRITE(DSPFW3, reg); 686 687 /* cursor HPLL off SR */ 688 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 689 pineview_display_hplloff_wm.fifo_size, 690 pixel_size, latency->cursor_hpll_disable); 691 reg = I915_READ(DSPFW3); 692 reg &= ~DSPFW_HPLL_CURSOR_MASK; 693 reg |= FW_WM(wm, HPLL_CURSOR); 694 I915_WRITE(DSPFW3, reg); 695 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 696 697 intel_set_memory_cxsr(dev_priv, true); 698 } else { 699 intel_set_memory_cxsr(dev_priv, false); 700 } 701 } 702 703 static bool g4x_compute_wm0(struct drm_device *dev, 704 int plane, 705 const struct intel_watermark_params *display, 706 int display_latency_ns, 707 const struct intel_watermark_params *cursor, 708 int cursor_latency_ns, 709 int *plane_wm, 710 int *cursor_wm) 711 { 712 struct drm_crtc *crtc; 713 const struct drm_display_mode *adjusted_mode; 714 int htotal, hdisplay, clock, pixel_size; 715 int line_time_us, line_count; 716 int entries, tlb_miss; 717 718 crtc = intel_get_crtc_for_plane(dev, plane); 719 if (!intel_crtc_active(crtc)) { 720 *cursor_wm = cursor->guard_size; 721 *plane_wm = display->guard_size; 722 return false; 723 } 724 725 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 726 clock = adjusted_mode->crtc_clock; 727 htotal = adjusted_mode->crtc_htotal; 728 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 729 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 730 731 /* Use the small buffer method to calculate plane watermark */ 732 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 733 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 734 if (tlb_miss > 0) 735 entries += tlb_miss; 736 entries = DIV_ROUND_UP(entries, display->cacheline_size); 737 *plane_wm = entries + display->guard_size; 738 if (*plane_wm > (int)display->max_wm) 739 *plane_wm = display->max_wm; 740 741 /* Use the large buffer method to calculate cursor watermark */ 742 line_time_us = max(htotal * 1000 / clock, 1); 743 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 744 entries = line_count * crtc->cursor->state->crtc_w * pixel_size; 745 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 746 if (tlb_miss > 0) 747 entries += tlb_miss; 748 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 749 *cursor_wm = entries + cursor->guard_size; 750 if (*cursor_wm > (int)cursor->max_wm) 751 *cursor_wm = (int)cursor->max_wm; 752 753 return true; 754 } 755 756 /* 757 * Check the wm result. 758 * 759 * If any calculated watermark values is larger than the maximum value that 760 * can be programmed into the associated watermark register, that watermark 761 * must be disabled. 762 */ 763 static bool g4x_check_srwm(struct drm_device *dev, 764 int display_wm, int cursor_wm, 765 const struct intel_watermark_params *display, 766 const struct intel_watermark_params *cursor) 767 { 768 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 769 display_wm, cursor_wm); 770 771 if (display_wm > display->max_wm) { 772 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 773 display_wm, display->max_wm); 774 return false; 775 } 776 777 if (cursor_wm > cursor->max_wm) { 778 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 779 cursor_wm, cursor->max_wm); 780 return false; 781 } 782 783 if (!(display_wm || cursor_wm)) { 784 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 785 return false; 786 } 787 788 return true; 789 } 790 791 static bool g4x_compute_srwm(struct drm_device *dev, 792 int plane, 793 int latency_ns, 794 const struct intel_watermark_params *display, 795 const struct intel_watermark_params *cursor, 796 int *display_wm, int *cursor_wm) 797 { 798 struct drm_crtc *crtc; 799 const struct drm_display_mode *adjusted_mode; 800 int hdisplay, htotal, pixel_size, clock; 801 unsigned long line_time_us; 802 int line_count, line_size; 803 int small, large; 804 int entries; 805 806 if (!latency_ns) { 807 *display_wm = *cursor_wm = 0; 808 return false; 809 } 810 811 crtc = intel_get_crtc_for_plane(dev, plane); 812 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 813 clock = adjusted_mode->crtc_clock; 814 htotal = adjusted_mode->crtc_htotal; 815 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 816 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 817 818 line_time_us = max(htotal * 1000 / clock, 1); 819 line_count = (latency_ns / line_time_us + 1000) / 1000; 820 line_size = hdisplay * pixel_size; 821 822 /* Use the minimum of the small and large buffer method for primary */ 823 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 824 large = line_count * line_size; 825 826 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 827 *display_wm = entries + display->guard_size; 828 829 /* calculate the self-refresh watermark for display cursor */ 830 entries = line_count * pixel_size * crtc->cursor->state->crtc_w; 831 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 832 *cursor_wm = entries + cursor->guard_size; 833 834 return g4x_check_srwm(dev, 835 *display_wm, *cursor_wm, 836 display, cursor); 837 } 838 839 #define FW_WM_VLV(value, plane) \ 840 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 841 842 static void vlv_write_wm_values(struct intel_crtc *crtc, 843 const struct vlv_wm_values *wm) 844 { 845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 846 enum pipe pipe = crtc->pipe; 847 848 I915_WRITE(VLV_DDL(pipe), 849 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 850 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 851 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 852 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 853 854 I915_WRITE(DSPFW1, 855 FW_WM(wm->sr.plane, SR) | 856 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 857 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 858 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 859 I915_WRITE(DSPFW2, 860 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 861 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 862 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 863 I915_WRITE(DSPFW3, 864 FW_WM(wm->sr.cursor, CURSOR_SR)); 865 866 if (IS_CHERRYVIEW(dev_priv)) { 867 I915_WRITE(DSPFW7_CHV, 868 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 869 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 870 I915_WRITE(DSPFW8_CHV, 871 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 872 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 873 I915_WRITE(DSPFW9_CHV, 874 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 875 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 876 I915_WRITE(DSPHOWM, 877 FW_WM(wm->sr.plane >> 9, SR_HI) | 878 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 879 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 880 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 881 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 882 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 883 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 884 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 885 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 886 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 887 } else { 888 I915_WRITE(DSPFW7, 889 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 890 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 891 I915_WRITE(DSPHOWM, 892 FW_WM(wm->sr.plane >> 9, SR_HI) | 893 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 894 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 895 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 896 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 897 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 898 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 899 } 900 901 /* zero (unused) WM1 watermarks */ 902 I915_WRITE(DSPFW4, 0); 903 I915_WRITE(DSPFW5, 0); 904 I915_WRITE(DSPFW6, 0); 905 I915_WRITE(DSPHOWM1, 0); 906 907 POSTING_READ(DSPFW1); 908 } 909 910 #undef FW_WM_VLV 911 912 enum vlv_wm_level { 913 VLV_WM_LEVEL_PM2, 914 VLV_WM_LEVEL_PM5, 915 VLV_WM_LEVEL_DDR_DVFS, 916 }; 917 918 /* latency must be in 0.1us units. */ 919 static unsigned int vlv_wm_method2(unsigned int pixel_rate, 920 unsigned int pipe_htotal, 921 unsigned int horiz_pixels, 922 unsigned int bytes_per_pixel, 923 unsigned int latency) 924 { 925 unsigned int ret; 926 927 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 928 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 929 ret = DIV_ROUND_UP(ret, 64); 930 931 return ret; 932 } 933 934 static void vlv_setup_wm_latency(struct drm_device *dev) 935 { 936 struct drm_i915_private *dev_priv = dev->dev_private; 937 938 /* all latencies in usec */ 939 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 940 941 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 942 943 if (IS_CHERRYVIEW(dev_priv)) { 944 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 946 947 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 948 } 949 } 950 951 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 952 struct intel_crtc *crtc, 953 const struct intel_plane_state *state, 954 int level) 955 { 956 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 957 int clock, htotal, pixel_size, width, wm; 958 959 if (dev_priv->wm.pri_latency[level] == 0) 960 return USHRT_MAX; 961 962 if (!state->visible) 963 return 0; 964 965 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 966 clock = crtc->config->base.adjusted_mode.crtc_clock; 967 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 968 width = crtc->config->pipe_src_w; 969 if (WARN_ON(htotal == 0)) 970 htotal = 1; 971 972 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 973 /* 974 * FIXME the formula gives values that are 975 * too big for the cursor FIFO, and hence we 976 * would never be able to use cursors. For 977 * now just hardcode the watermark. 978 */ 979 wm = 63; 980 } else { 981 wm = vlv_wm_method2(clock, htotal, width, pixel_size, 982 dev_priv->wm.pri_latency[level] * 10); 983 } 984 985 return min_t(int, wm, USHRT_MAX); 986 } 987 988 static void vlv_compute_fifo(struct intel_crtc *crtc) 989 { 990 struct drm_device *dev = crtc->base.dev; 991 struct vlv_wm_state *wm_state = &crtc->wm_state; 992 struct intel_plane *plane; 993 unsigned int total_rate = 0; 994 const int fifo_size = 512 - 1; 995 int fifo_extra, fifo_left = fifo_size; 996 997 for_each_intel_plane_on_crtc(dev, crtc, plane) { 998 struct intel_plane_state *state = 999 to_intel_plane_state(plane->base.state); 1000 1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1002 continue; 1003 1004 if (state->visible) { 1005 wm_state->num_active_planes++; 1006 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1007 } 1008 } 1009 1010 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1011 struct intel_plane_state *state = 1012 to_intel_plane_state(plane->base.state); 1013 unsigned int rate; 1014 1015 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1016 plane->wm.fifo_size = 63; 1017 continue; 1018 } 1019 1020 if (!state->visible) { 1021 plane->wm.fifo_size = 0; 1022 continue; 1023 } 1024 1025 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1026 plane->wm.fifo_size = fifo_size * rate / total_rate; 1027 fifo_left -= plane->wm.fifo_size; 1028 } 1029 1030 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1031 1032 /* spread the remainder evenly */ 1033 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1034 int plane_extra; 1035 1036 if (fifo_left == 0) 1037 break; 1038 1039 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1040 continue; 1041 1042 /* give it all to the first plane if none are active */ 1043 if (plane->wm.fifo_size == 0 && 1044 wm_state->num_active_planes) 1045 continue; 1046 1047 plane_extra = min(fifo_extra, fifo_left); 1048 plane->wm.fifo_size += plane_extra; 1049 fifo_left -= plane_extra; 1050 } 1051 1052 WARN_ON(fifo_left != 0); 1053 } 1054 1055 static void vlv_invert_wms(struct intel_crtc *crtc) 1056 { 1057 struct vlv_wm_state *wm_state = &crtc->wm_state; 1058 int level; 1059 1060 for (level = 0; level < wm_state->num_levels; level++) { 1061 struct drm_device *dev = crtc->base.dev; 1062 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1063 struct intel_plane *plane; 1064 1065 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1066 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1067 1068 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1069 switch (plane->base.type) { 1070 int sprite; 1071 case DRM_PLANE_TYPE_CURSOR: 1072 wm_state->wm[level].cursor = plane->wm.fifo_size - 1073 wm_state->wm[level].cursor; 1074 break; 1075 case DRM_PLANE_TYPE_PRIMARY: 1076 wm_state->wm[level].primary = plane->wm.fifo_size - 1077 wm_state->wm[level].primary; 1078 break; 1079 case DRM_PLANE_TYPE_OVERLAY: 1080 sprite = plane->plane; 1081 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1082 wm_state->wm[level].sprite[sprite]; 1083 break; 1084 } 1085 } 1086 } 1087 } 1088 1089 static void vlv_compute_wm(struct intel_crtc *crtc) 1090 { 1091 struct drm_device *dev = crtc->base.dev; 1092 struct vlv_wm_state *wm_state = &crtc->wm_state; 1093 struct intel_plane *plane; 1094 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1095 int level; 1096 1097 memset(wm_state, 0, sizeof(*wm_state)); 1098 1099 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1100 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1101 1102 wm_state->num_active_planes = 0; 1103 1104 vlv_compute_fifo(crtc); 1105 1106 if (wm_state->num_active_planes != 1) 1107 wm_state->cxsr = false; 1108 1109 if (wm_state->cxsr) { 1110 for (level = 0; level < wm_state->num_levels; level++) { 1111 wm_state->sr[level].plane = sr_fifo_size; 1112 wm_state->sr[level].cursor = 63; 1113 } 1114 } 1115 1116 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1117 struct intel_plane_state *state = 1118 to_intel_plane_state(plane->base.state); 1119 1120 if (!state->visible) 1121 continue; 1122 1123 /* normal watermarks */ 1124 for (level = 0; level < wm_state->num_levels; level++) { 1125 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1126 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1127 1128 /* hack */ 1129 if (WARN_ON(level == 0 && wm > max_wm)) 1130 wm = max_wm; 1131 1132 if (wm > plane->wm.fifo_size) 1133 break; 1134 1135 switch (plane->base.type) { 1136 int sprite; 1137 case DRM_PLANE_TYPE_CURSOR: 1138 wm_state->wm[level].cursor = wm; 1139 break; 1140 case DRM_PLANE_TYPE_PRIMARY: 1141 wm_state->wm[level].primary = wm; 1142 break; 1143 case DRM_PLANE_TYPE_OVERLAY: 1144 sprite = plane->plane; 1145 wm_state->wm[level].sprite[sprite] = wm; 1146 break; 1147 } 1148 } 1149 1150 wm_state->num_levels = level; 1151 1152 if (!wm_state->cxsr) 1153 continue; 1154 1155 /* maxfifo watermarks */ 1156 switch (plane->base.type) { 1157 int sprite, level; 1158 case DRM_PLANE_TYPE_CURSOR: 1159 for (level = 0; level < wm_state->num_levels; level++) 1160 wm_state->sr[level].cursor = 1161 wm_state->wm[level].cursor; 1162 break; 1163 case DRM_PLANE_TYPE_PRIMARY: 1164 for (level = 0; level < wm_state->num_levels; level++) 1165 wm_state->sr[level].plane = 1166 min(wm_state->sr[level].plane, 1167 wm_state->wm[level].primary); 1168 break; 1169 case DRM_PLANE_TYPE_OVERLAY: 1170 sprite = plane->plane; 1171 for (level = 0; level < wm_state->num_levels; level++) 1172 wm_state->sr[level].plane = 1173 min(wm_state->sr[level].plane, 1174 wm_state->wm[level].sprite[sprite]); 1175 break; 1176 } 1177 } 1178 1179 /* clear any (partially) filled invalid levels */ 1180 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1181 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1182 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1183 } 1184 1185 vlv_invert_wms(crtc); 1186 } 1187 1188 #define VLV_FIFO(plane, value) \ 1189 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1190 1191 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1192 { 1193 struct drm_device *dev = crtc->base.dev; 1194 struct drm_i915_private *dev_priv = to_i915(dev); 1195 struct intel_plane *plane; 1196 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1197 1198 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1199 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1200 WARN_ON(plane->wm.fifo_size != 63); 1201 continue; 1202 } 1203 1204 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1205 sprite0_start = plane->wm.fifo_size; 1206 else if (plane->plane == 0) 1207 sprite1_start = sprite0_start + plane->wm.fifo_size; 1208 else 1209 fifo_size = sprite1_start + plane->wm.fifo_size; 1210 } 1211 1212 WARN_ON(fifo_size != 512 - 1); 1213 1214 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1215 pipe_name(crtc->pipe), sprite0_start, 1216 sprite1_start, fifo_size); 1217 1218 switch (crtc->pipe) { 1219 uint32_t dsparb, dsparb2, dsparb3; 1220 case PIPE_A: 1221 dsparb = I915_READ(DSPARB); 1222 dsparb2 = I915_READ(DSPARB2); 1223 1224 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1225 VLV_FIFO(SPRITEB, 0xff)); 1226 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1227 VLV_FIFO(SPRITEB, sprite1_start)); 1228 1229 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1230 VLV_FIFO(SPRITEB_HI, 0x1)); 1231 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1232 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1233 1234 I915_WRITE(DSPARB, dsparb); 1235 I915_WRITE(DSPARB2, dsparb2); 1236 break; 1237 case PIPE_B: 1238 dsparb = I915_READ(DSPARB); 1239 dsparb2 = I915_READ(DSPARB2); 1240 1241 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1242 VLV_FIFO(SPRITED, 0xff)); 1243 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1244 VLV_FIFO(SPRITED, sprite1_start)); 1245 1246 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1247 VLV_FIFO(SPRITED_HI, 0xff)); 1248 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1249 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1250 1251 I915_WRITE(DSPARB, dsparb); 1252 I915_WRITE(DSPARB2, dsparb2); 1253 break; 1254 case PIPE_C: 1255 dsparb3 = I915_READ(DSPARB3); 1256 dsparb2 = I915_READ(DSPARB2); 1257 1258 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1259 VLV_FIFO(SPRITEF, 0xff)); 1260 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1261 VLV_FIFO(SPRITEF, sprite1_start)); 1262 1263 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1264 VLV_FIFO(SPRITEF_HI, 0xff)); 1265 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1266 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1267 1268 I915_WRITE(DSPARB3, dsparb3); 1269 I915_WRITE(DSPARB2, dsparb2); 1270 break; 1271 default: 1272 break; 1273 } 1274 } 1275 1276 #undef VLV_FIFO 1277 1278 static void vlv_merge_wm(struct drm_device *dev, 1279 struct vlv_wm_values *wm) 1280 { 1281 struct intel_crtc *crtc; 1282 int num_active_crtcs = 0; 1283 1284 wm->level = to_i915(dev)->wm.max_level; 1285 wm->cxsr = true; 1286 1287 for_each_intel_crtc(dev, crtc) { 1288 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1289 1290 if (!crtc->active) 1291 continue; 1292 1293 if (!wm_state->cxsr) 1294 wm->cxsr = false; 1295 1296 num_active_crtcs++; 1297 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1298 } 1299 1300 if (num_active_crtcs != 1) 1301 wm->cxsr = false; 1302 1303 if (num_active_crtcs > 1) 1304 wm->level = VLV_WM_LEVEL_PM2; 1305 1306 for_each_intel_crtc(dev, crtc) { 1307 struct vlv_wm_state *wm_state = &crtc->wm_state; 1308 enum pipe pipe = crtc->pipe; 1309 1310 if (!crtc->active) 1311 continue; 1312 1313 wm->pipe[pipe] = wm_state->wm[wm->level]; 1314 if (wm->cxsr) 1315 wm->sr = wm_state->sr[wm->level]; 1316 1317 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1318 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1319 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1320 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1321 } 1322 } 1323 1324 static void vlv_update_wm(struct drm_crtc *crtc) 1325 { 1326 struct drm_device *dev = crtc->dev; 1327 struct drm_i915_private *dev_priv = dev->dev_private; 1328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1329 enum pipe pipe = intel_crtc->pipe; 1330 struct vlv_wm_values wm = {}; 1331 1332 vlv_compute_wm(intel_crtc); 1333 vlv_merge_wm(dev, &wm); 1334 1335 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1336 /* FIXME should be part of crtc atomic commit */ 1337 vlv_pipe_set_fifo_size(intel_crtc); 1338 return; 1339 } 1340 1341 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1342 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1343 chv_set_memory_dvfs(dev_priv, false); 1344 1345 if (wm.level < VLV_WM_LEVEL_PM5 && 1346 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1347 chv_set_memory_pm5(dev_priv, false); 1348 1349 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1350 intel_set_memory_cxsr(dev_priv, false); 1351 1352 /* FIXME should be part of crtc atomic commit */ 1353 vlv_pipe_set_fifo_size(intel_crtc); 1354 1355 vlv_write_wm_values(intel_crtc, &wm); 1356 1357 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1358 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1359 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1360 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1361 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1362 1363 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1364 intel_set_memory_cxsr(dev_priv, true); 1365 1366 if (wm.level >= VLV_WM_LEVEL_PM5 && 1367 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1368 chv_set_memory_pm5(dev_priv, true); 1369 1370 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1371 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1372 chv_set_memory_dvfs(dev_priv, true); 1373 1374 dev_priv->wm.vlv = wm; 1375 } 1376 1377 #define single_plane_enabled(mask) is_power_of_2(mask) 1378 1379 static void g4x_update_wm(struct drm_crtc *crtc) 1380 { 1381 struct drm_device *dev = crtc->dev; 1382 static const int sr_latency_ns = 12000; 1383 struct drm_i915_private *dev_priv = dev->dev_private; 1384 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1385 int plane_sr, cursor_sr; 1386 unsigned int enabled = 0; 1387 bool cxsr_enabled; 1388 1389 if (g4x_compute_wm0(dev, PIPE_A, 1390 &g4x_wm_info, pessimal_latency_ns, 1391 &g4x_cursor_wm_info, pessimal_latency_ns, 1392 &planea_wm, &cursora_wm)) 1393 enabled |= 1 << PIPE_A; 1394 1395 if (g4x_compute_wm0(dev, PIPE_B, 1396 &g4x_wm_info, pessimal_latency_ns, 1397 &g4x_cursor_wm_info, pessimal_latency_ns, 1398 &planeb_wm, &cursorb_wm)) 1399 enabled |= 1 << PIPE_B; 1400 1401 if (single_plane_enabled(enabled) && 1402 g4x_compute_srwm(dev, ffs(enabled) - 1, 1403 sr_latency_ns, 1404 &g4x_wm_info, 1405 &g4x_cursor_wm_info, 1406 &plane_sr, &cursor_sr)) { 1407 cxsr_enabled = true; 1408 } else { 1409 cxsr_enabled = false; 1410 intel_set_memory_cxsr(dev_priv, false); 1411 plane_sr = cursor_sr = 0; 1412 } 1413 1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1415 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1416 planea_wm, cursora_wm, 1417 planeb_wm, cursorb_wm, 1418 plane_sr, cursor_sr); 1419 1420 I915_WRITE(DSPFW1, 1421 FW_WM(plane_sr, SR) | 1422 FW_WM(cursorb_wm, CURSORB) | 1423 FW_WM(planeb_wm, PLANEB) | 1424 FW_WM(planea_wm, PLANEA)); 1425 I915_WRITE(DSPFW2, 1426 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1427 FW_WM(cursora_wm, CURSORA)); 1428 /* HPLL off in SR has some issues on G4x... disable it */ 1429 I915_WRITE(DSPFW3, 1430 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1431 FW_WM(cursor_sr, CURSOR_SR)); 1432 1433 if (cxsr_enabled) 1434 intel_set_memory_cxsr(dev_priv, true); 1435 } 1436 1437 static void i965_update_wm(struct drm_crtc *unused_crtc) 1438 { 1439 struct drm_device *dev = unused_crtc->dev; 1440 struct drm_i915_private *dev_priv = dev->dev_private; 1441 struct drm_crtc *crtc; 1442 int srwm = 1; 1443 int cursor_sr = 16; 1444 bool cxsr_enabled; 1445 1446 /* Calc sr entries for one plane configs */ 1447 crtc = single_enabled_crtc(dev); 1448 if (crtc) { 1449 /* self-refresh has much higher latency */ 1450 static const int sr_latency_ns = 12000; 1451 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1452 int clock = adjusted_mode->crtc_clock; 1453 int htotal = adjusted_mode->crtc_htotal; 1454 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1455 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 1456 unsigned long line_time_us; 1457 int entries; 1458 1459 line_time_us = max(htotal * 1000 / clock, 1); 1460 1461 /* Use ns/us then divide to preserve precision */ 1462 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1463 pixel_size * hdisplay; 1464 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1465 srwm = I965_FIFO_SIZE - entries; 1466 if (srwm < 0) 1467 srwm = 1; 1468 srwm &= 0x1ff; 1469 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1470 entries, srwm); 1471 1472 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1473 pixel_size * crtc->cursor->state->crtc_w; 1474 entries = DIV_ROUND_UP(entries, 1475 i965_cursor_wm_info.cacheline_size); 1476 cursor_sr = i965_cursor_wm_info.fifo_size - 1477 (entries + i965_cursor_wm_info.guard_size); 1478 1479 if (cursor_sr > i965_cursor_wm_info.max_wm) 1480 cursor_sr = i965_cursor_wm_info.max_wm; 1481 1482 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1483 "cursor %d\n", srwm, cursor_sr); 1484 1485 cxsr_enabled = true; 1486 } else { 1487 cxsr_enabled = false; 1488 /* Turn off self refresh if both pipes are enabled */ 1489 intel_set_memory_cxsr(dev_priv, false); 1490 } 1491 1492 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1493 srwm); 1494 1495 /* 965 has limitations... */ 1496 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1497 FW_WM(8, CURSORB) | 1498 FW_WM(8, PLANEB) | 1499 FW_WM(8, PLANEA)); 1500 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1501 FW_WM(8, PLANEC_OLD)); 1502 /* update cursor SR watermark */ 1503 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1504 1505 if (cxsr_enabled) 1506 intel_set_memory_cxsr(dev_priv, true); 1507 } 1508 1509 #undef FW_WM 1510 1511 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1512 { 1513 struct drm_device *dev = unused_crtc->dev; 1514 struct drm_i915_private *dev_priv = dev->dev_private; 1515 const struct intel_watermark_params *wm_info; 1516 uint32_t fwater_lo; 1517 uint32_t fwater_hi; 1518 int cwm, srwm = 1; 1519 int fifo_size; 1520 int planea_wm, planeb_wm; 1521 struct drm_crtc *crtc, *enabled = NULL; 1522 1523 if (IS_I945GM(dev)) 1524 wm_info = &i945_wm_info; 1525 else if (!IS_GEN2(dev)) 1526 wm_info = &i915_wm_info; 1527 else 1528 wm_info = &i830_a_wm_info; 1529 1530 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1531 crtc = intel_get_crtc_for_plane(dev, 0); 1532 if (intel_crtc_active(crtc)) { 1533 const struct drm_display_mode *adjusted_mode; 1534 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1535 if (IS_GEN2(dev)) 1536 cpp = 4; 1537 1538 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1539 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1540 wm_info, fifo_size, cpp, 1541 pessimal_latency_ns); 1542 enabled = crtc; 1543 } else { 1544 planea_wm = fifo_size - wm_info->guard_size; 1545 if (planea_wm > (long)wm_info->max_wm) 1546 planea_wm = wm_info->max_wm; 1547 } 1548 1549 if (IS_GEN2(dev)) 1550 wm_info = &i830_bc_wm_info; 1551 1552 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1553 crtc = intel_get_crtc_for_plane(dev, 1); 1554 if (intel_crtc_active(crtc)) { 1555 const struct drm_display_mode *adjusted_mode; 1556 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1557 if (IS_GEN2(dev)) 1558 cpp = 4; 1559 1560 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1561 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1562 wm_info, fifo_size, cpp, 1563 pessimal_latency_ns); 1564 if (enabled == NULL) 1565 enabled = crtc; 1566 else 1567 enabled = NULL; 1568 } else { 1569 planeb_wm = fifo_size - wm_info->guard_size; 1570 if (planeb_wm > (long)wm_info->max_wm) 1571 planeb_wm = wm_info->max_wm; 1572 } 1573 1574 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1575 1576 if (IS_I915GM(dev) && enabled) { 1577 struct drm_i915_gem_object *obj; 1578 1579 obj = intel_fb_obj(enabled->primary->state->fb); 1580 1581 /* self-refresh seems busted with untiled */ 1582 if (obj->tiling_mode == I915_TILING_NONE) 1583 enabled = NULL; 1584 } 1585 1586 /* 1587 * Overlay gets an aggressive default since video jitter is bad. 1588 */ 1589 cwm = 2; 1590 1591 /* Play safe and disable self-refresh before adjusting watermarks. */ 1592 intel_set_memory_cxsr(dev_priv, false); 1593 1594 /* Calc sr entries for one plane configs */ 1595 if (HAS_FW_BLC(dev) && enabled) { 1596 /* self-refresh has much higher latency */ 1597 static const int sr_latency_ns = 6000; 1598 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; 1599 int clock = adjusted_mode->crtc_clock; 1600 int htotal = adjusted_mode->crtc_htotal; 1601 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1602 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; 1603 unsigned long line_time_us; 1604 int entries; 1605 1606 line_time_us = max(htotal * 1000 / clock, 1); 1607 1608 /* Use ns/us then divide to preserve precision */ 1609 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1610 pixel_size * hdisplay; 1611 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1612 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1613 srwm = wm_info->fifo_size - entries; 1614 if (srwm < 0) 1615 srwm = 1; 1616 1617 if (IS_I945G(dev) || IS_I945GM(dev)) 1618 I915_WRITE(FW_BLC_SELF, 1619 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1620 else if (IS_I915GM(dev)) 1621 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1622 } 1623 1624 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1625 planea_wm, planeb_wm, cwm, srwm); 1626 1627 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1628 fwater_hi = (cwm & 0x1f); 1629 1630 /* Set request length to 8 cachelines per fetch */ 1631 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1632 fwater_hi = fwater_hi | (1 << 8); 1633 1634 I915_WRITE(FW_BLC, fwater_lo); 1635 I915_WRITE(FW_BLC2, fwater_hi); 1636 1637 if (enabled) 1638 intel_set_memory_cxsr(dev_priv, true); 1639 } 1640 1641 static void i845_update_wm(struct drm_crtc *unused_crtc) 1642 { 1643 struct drm_device *dev = unused_crtc->dev; 1644 struct drm_i915_private *dev_priv = dev->dev_private; 1645 struct drm_crtc *crtc; 1646 const struct drm_display_mode *adjusted_mode; 1647 uint32_t fwater_lo; 1648 int planea_wm; 1649 1650 crtc = single_enabled_crtc(dev); 1651 if (crtc == NULL) 1652 return; 1653 1654 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1655 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1656 &i845_wm_info, 1657 dev_priv->display.get_fifo_size(dev, 0), 1658 4, pessimal_latency_ns); 1659 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1660 fwater_lo |= (3<<8) | planea_wm; 1661 1662 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1663 1664 I915_WRITE(FW_BLC, fwater_lo); 1665 } 1666 1667 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1668 { 1669 uint32_t pixel_rate; 1670 1671 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1672 1673 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1674 * adjust the pixel_rate here. */ 1675 1676 if (pipe_config->pch_pfit.enabled) { 1677 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1678 uint32_t pfit_size = pipe_config->pch_pfit.size; 1679 1680 pipe_w = pipe_config->pipe_src_w; 1681 pipe_h = pipe_config->pipe_src_h; 1682 1683 pfit_w = (pfit_size >> 16) & 0xFFFF; 1684 pfit_h = pfit_size & 0xFFFF; 1685 if (pipe_w < pfit_w) 1686 pipe_w = pfit_w; 1687 if (pipe_h < pfit_h) 1688 pipe_h = pfit_h; 1689 1690 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1691 pfit_w * pfit_h); 1692 } 1693 1694 return pixel_rate; 1695 } 1696 1697 /* latency must be in 0.1us units. */ 1698 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1699 uint32_t latency) 1700 { 1701 uint64_t ret; 1702 1703 if (WARN(latency == 0, "Latency value missing\n")) 1704 return UINT_MAX; 1705 1706 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1707 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1708 1709 return ret; 1710 } 1711 1712 /* latency must be in 0.1us units. */ 1713 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1714 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1715 uint32_t latency) 1716 { 1717 uint32_t ret; 1718 1719 if (WARN(latency == 0, "Latency value missing\n")) 1720 return UINT_MAX; 1721 1722 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1723 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1724 ret = DIV_ROUND_UP(ret, 64) + 2; 1725 return ret; 1726 } 1727 1728 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1729 uint8_t bytes_per_pixel) 1730 { 1731 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1732 } 1733 1734 struct skl_pipe_wm_parameters { 1735 bool active; 1736 uint32_t pipe_htotal; 1737 uint32_t pixel_rate; /* in KHz */ 1738 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; 1739 }; 1740 1741 struct ilk_wm_maximums { 1742 uint16_t pri; 1743 uint16_t spr; 1744 uint16_t cur; 1745 uint16_t fbc; 1746 }; 1747 1748 /* used in computing the new watermarks state */ 1749 struct intel_wm_config { 1750 unsigned int num_pipes_active; 1751 bool sprites_enabled; 1752 bool sprites_scaled; 1753 }; 1754 1755 /* 1756 * For both WM_PIPE and WM_LP. 1757 * mem_value must be in 0.1us units. 1758 */ 1759 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 1760 const struct intel_plane_state *pstate, 1761 uint32_t mem_value, 1762 bool is_lp) 1763 { 1764 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1765 uint32_t method1, method2; 1766 1767 if (!cstate->base.active || !pstate->visible) 1768 return 0; 1769 1770 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1771 1772 if (!is_lp) 1773 return method1; 1774 1775 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1776 cstate->base.adjusted_mode.crtc_htotal, 1777 drm_rect_width(&pstate->dst), 1778 bpp, 1779 mem_value); 1780 1781 return min(method1, method2); 1782 } 1783 1784 /* 1785 * For both WM_PIPE and WM_LP. 1786 * mem_value must be in 0.1us units. 1787 */ 1788 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 1789 const struct intel_plane_state *pstate, 1790 uint32_t mem_value) 1791 { 1792 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1793 uint32_t method1, method2; 1794 1795 if (!cstate->base.active || !pstate->visible) 1796 return 0; 1797 1798 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1799 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1800 cstate->base.adjusted_mode.crtc_htotal, 1801 drm_rect_width(&pstate->dst), 1802 bpp, 1803 mem_value); 1804 return min(method1, method2); 1805 } 1806 1807 /* 1808 * For both WM_PIPE and WM_LP. 1809 * mem_value must be in 0.1us units. 1810 */ 1811 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 1812 const struct intel_plane_state *pstate, 1813 uint32_t mem_value) 1814 { 1815 /* 1816 * We treat the cursor plane as always-on for the purposes of watermark 1817 * calculation. Until we have two-stage watermark programming merged, 1818 * this is necessary to avoid flickering. 1819 */ 1820 int cpp = 4; 1821 int width = pstate->visible ? pstate->base.crtc_w : 64; 1822 1823 if (!cstate->base.active) 1824 return 0; 1825 1826 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1827 cstate->base.adjusted_mode.crtc_htotal, 1828 width, cpp, mem_value); 1829 } 1830 1831 /* Only for WM_LP. */ 1832 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 1833 const struct intel_plane_state *pstate, 1834 uint32_t pri_val) 1835 { 1836 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1837 1838 if (!cstate->base.active || !pstate->visible) 1839 return 0; 1840 1841 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); 1842 } 1843 1844 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1845 { 1846 if (INTEL_INFO(dev)->gen >= 8) 1847 return 3072; 1848 else if (INTEL_INFO(dev)->gen >= 7) 1849 return 768; 1850 else 1851 return 512; 1852 } 1853 1854 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1855 int level, bool is_sprite) 1856 { 1857 if (INTEL_INFO(dev)->gen >= 8) 1858 /* BDW primary/sprite plane watermarks */ 1859 return level == 0 ? 255 : 2047; 1860 else if (INTEL_INFO(dev)->gen >= 7) 1861 /* IVB/HSW primary/sprite plane watermarks */ 1862 return level == 0 ? 127 : 1023; 1863 else if (!is_sprite) 1864 /* ILK/SNB primary plane watermarks */ 1865 return level == 0 ? 127 : 511; 1866 else 1867 /* ILK/SNB sprite plane watermarks */ 1868 return level == 0 ? 63 : 255; 1869 } 1870 1871 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1872 int level) 1873 { 1874 if (INTEL_INFO(dev)->gen >= 7) 1875 return level == 0 ? 63 : 255; 1876 else 1877 return level == 0 ? 31 : 63; 1878 } 1879 1880 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1881 { 1882 if (INTEL_INFO(dev)->gen >= 8) 1883 return 31; 1884 else 1885 return 15; 1886 } 1887 1888 /* Calculate the maximum primary/sprite plane watermark */ 1889 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1890 int level, 1891 const struct intel_wm_config *config, 1892 enum intel_ddb_partitioning ddb_partitioning, 1893 bool is_sprite) 1894 { 1895 unsigned int fifo_size = ilk_display_fifo_size(dev); 1896 1897 /* if sprites aren't enabled, sprites get nothing */ 1898 if (is_sprite && !config->sprites_enabled) 1899 return 0; 1900 1901 /* HSW allows LP1+ watermarks even with multiple pipes */ 1902 if (level == 0 || config->num_pipes_active > 1) { 1903 fifo_size /= INTEL_INFO(dev)->num_pipes; 1904 1905 /* 1906 * For some reason the non self refresh 1907 * FIFO size is only half of the self 1908 * refresh FIFO size on ILK/SNB. 1909 */ 1910 if (INTEL_INFO(dev)->gen <= 6) 1911 fifo_size /= 2; 1912 } 1913 1914 if (config->sprites_enabled) { 1915 /* level 0 is always calculated with 1:1 split */ 1916 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1917 if (is_sprite) 1918 fifo_size *= 5; 1919 fifo_size /= 6; 1920 } else { 1921 fifo_size /= 2; 1922 } 1923 } 1924 1925 /* clamp to max that the registers can hold */ 1926 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1927 } 1928 1929 /* Calculate the maximum cursor plane watermark */ 1930 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1931 int level, 1932 const struct intel_wm_config *config) 1933 { 1934 /* HSW LP1+ watermarks w/ multiple pipes */ 1935 if (level > 0 && config->num_pipes_active > 1) 1936 return 64; 1937 1938 /* otherwise just report max that registers can hold */ 1939 return ilk_cursor_wm_reg_max(dev, level); 1940 } 1941 1942 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1943 int level, 1944 const struct intel_wm_config *config, 1945 enum intel_ddb_partitioning ddb_partitioning, 1946 struct ilk_wm_maximums *max) 1947 { 1948 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1949 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1950 max->cur = ilk_cursor_wm_max(dev, level, config); 1951 max->fbc = ilk_fbc_wm_reg_max(dev); 1952 } 1953 1954 static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 1955 int level, 1956 struct ilk_wm_maximums *max) 1957 { 1958 max->pri = ilk_plane_wm_reg_max(dev, level, false); 1959 max->spr = ilk_plane_wm_reg_max(dev, level, true); 1960 max->cur = ilk_cursor_wm_reg_max(dev, level); 1961 max->fbc = ilk_fbc_wm_reg_max(dev); 1962 } 1963 1964 static bool ilk_validate_wm_level(int level, 1965 const struct ilk_wm_maximums *max, 1966 struct intel_wm_level *result) 1967 { 1968 bool ret; 1969 1970 /* already determined to be invalid? */ 1971 if (!result->enable) 1972 return false; 1973 1974 result->enable = result->pri_val <= max->pri && 1975 result->spr_val <= max->spr && 1976 result->cur_val <= max->cur; 1977 1978 ret = result->enable; 1979 1980 /* 1981 * HACK until we can pre-compute everything, 1982 * and thus fail gracefully if LP0 watermarks 1983 * are exceeded... 1984 */ 1985 if (level == 0 && !result->enable) { 1986 if (result->pri_val > max->pri) 1987 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1988 level, result->pri_val, max->pri); 1989 if (result->spr_val > max->spr) 1990 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1991 level, result->spr_val, max->spr); 1992 if (result->cur_val > max->cur) 1993 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1994 level, result->cur_val, max->cur); 1995 1996 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1997 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1998 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1999 result->enable = true; 2000 } 2001 2002 return ret; 2003 } 2004 2005 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 2006 const struct intel_crtc *intel_crtc, 2007 int level, 2008 struct intel_crtc_state *cstate, 2009 struct intel_wm_level *result) 2010 { 2011 struct intel_plane *intel_plane; 2012 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 2013 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 2014 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 2015 2016 /* WM1+ latency values stored in 0.5us units */ 2017 if (level > 0) { 2018 pri_latency *= 5; 2019 spr_latency *= 5; 2020 cur_latency *= 5; 2021 } 2022 2023 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { 2024 struct intel_plane_state *pstate = 2025 to_intel_plane_state(intel_plane->base.state); 2026 2027 switch (intel_plane->base.type) { 2028 case DRM_PLANE_TYPE_PRIMARY: 2029 result->pri_val = ilk_compute_pri_wm(cstate, pstate, 2030 pri_latency, 2031 level); 2032 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, 2033 result->pri_val); 2034 break; 2035 case DRM_PLANE_TYPE_OVERLAY: 2036 result->spr_val = ilk_compute_spr_wm(cstate, pstate, 2037 spr_latency); 2038 break; 2039 case DRM_PLANE_TYPE_CURSOR: 2040 result->cur_val = ilk_compute_cur_wm(cstate, pstate, 2041 cur_latency); 2042 break; 2043 } 2044 } 2045 2046 result->enable = true; 2047 } 2048 2049 static uint32_t 2050 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 2051 { 2052 struct drm_i915_private *dev_priv = dev->dev_private; 2053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2054 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 2055 u32 linetime, ips_linetime; 2056 2057 if (!intel_crtc->active) 2058 return 0; 2059 2060 /* The WM are computed with base on how long it takes to fill a single 2061 * row at the given clock rate, multiplied by 8. 2062 * */ 2063 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2064 adjusted_mode->crtc_clock); 2065 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2066 dev_priv->cdclk_freq); 2067 2068 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2069 PIPE_WM_LINETIME_TIME(linetime); 2070 } 2071 2072 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2073 { 2074 struct drm_i915_private *dev_priv = dev->dev_private; 2075 2076 if (IS_GEN9(dev)) { 2077 uint32_t val; 2078 int ret, i; 2079 int level, max_level = ilk_wm_max_level(dev); 2080 2081 /* read the first set of memory latencies[0:3] */ 2082 val = 0; /* data0 to be programmed to 0 for first set */ 2083 mutex_lock(&dev_priv->rps.hw_lock); 2084 ret = sandybridge_pcode_read(dev_priv, 2085 GEN9_PCODE_READ_MEM_LATENCY, 2086 &val); 2087 mutex_unlock(&dev_priv->rps.hw_lock); 2088 2089 if (ret) { 2090 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2091 return; 2092 } 2093 2094 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2095 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2096 GEN9_MEM_LATENCY_LEVEL_MASK; 2097 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2098 GEN9_MEM_LATENCY_LEVEL_MASK; 2099 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2100 GEN9_MEM_LATENCY_LEVEL_MASK; 2101 2102 /* read the second set of memory latencies[4:7] */ 2103 val = 1; /* data0 to be programmed to 1 for second set */ 2104 mutex_lock(&dev_priv->rps.hw_lock); 2105 ret = sandybridge_pcode_read(dev_priv, 2106 GEN9_PCODE_READ_MEM_LATENCY, 2107 &val); 2108 mutex_unlock(&dev_priv->rps.hw_lock); 2109 if (ret) { 2110 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2111 return; 2112 } 2113 2114 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2115 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2116 GEN9_MEM_LATENCY_LEVEL_MASK; 2117 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2118 GEN9_MEM_LATENCY_LEVEL_MASK; 2119 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2120 GEN9_MEM_LATENCY_LEVEL_MASK; 2121 2122 /* 2123 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 2124 * need to be disabled. We make sure to sanitize the values out 2125 * of the punit to satisfy this requirement. 2126 */ 2127 for (level = 1; level <= max_level; level++) { 2128 if (wm[level] == 0) { 2129 for (i = level + 1; i <= max_level; i++) 2130 wm[i] = 0; 2131 break; 2132 } 2133 } 2134 2135 /* 2136 * WaWmMemoryReadLatency:skl 2137 * 2138 * punit doesn't take into account the read latency so we need 2139 * to add 2us to the various latency levels we retrieve from the 2140 * punit when level 0 response data us 0us. 2141 */ 2142 if (wm[0] == 0) { 2143 wm[0] += 2; 2144 for (level = 1; level <= max_level; level++) { 2145 if (wm[level] == 0) 2146 break; 2147 wm[level] += 2; 2148 } 2149 } 2150 2151 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2152 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2153 2154 wm[0] = (sskpd >> 56) & 0xFF; 2155 if (wm[0] == 0) 2156 wm[0] = sskpd & 0xF; 2157 wm[1] = (sskpd >> 4) & 0xFF; 2158 wm[2] = (sskpd >> 12) & 0xFF; 2159 wm[3] = (sskpd >> 20) & 0x1FF; 2160 wm[4] = (sskpd >> 32) & 0x1FF; 2161 } else if (INTEL_INFO(dev)->gen >= 6) { 2162 uint32_t sskpd = I915_READ(MCH_SSKPD); 2163 2164 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2165 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2166 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2167 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2168 } else if (INTEL_INFO(dev)->gen >= 5) { 2169 uint32_t mltr = I915_READ(MLTR_ILK); 2170 2171 /* ILK primary LP0 latency is 700 ns */ 2172 wm[0] = 7; 2173 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2174 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2175 } 2176 } 2177 2178 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2179 { 2180 /* ILK sprite LP0 latency is 1300 ns */ 2181 if (INTEL_INFO(dev)->gen == 5) 2182 wm[0] = 13; 2183 } 2184 2185 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2186 { 2187 /* ILK cursor LP0 latency is 1300 ns */ 2188 if (INTEL_INFO(dev)->gen == 5) 2189 wm[0] = 13; 2190 2191 /* WaDoubleCursorLP3Latency:ivb */ 2192 if (IS_IVYBRIDGE(dev)) 2193 wm[3] *= 2; 2194 } 2195 2196 int ilk_wm_max_level(const struct drm_device *dev) 2197 { 2198 /* how many WM levels are we expecting */ 2199 if (INTEL_INFO(dev)->gen >= 9) 2200 return 7; 2201 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2202 return 4; 2203 else if (INTEL_INFO(dev)->gen >= 6) 2204 return 3; 2205 else 2206 return 2; 2207 } 2208 2209 static void intel_print_wm_latency(struct drm_device *dev, 2210 const char *name, 2211 const uint16_t wm[8]) 2212 { 2213 int level, max_level = ilk_wm_max_level(dev); 2214 2215 for (level = 0; level <= max_level; level++) { 2216 unsigned int latency = wm[level]; 2217 2218 if (latency == 0) { 2219 DRM_ERROR("%s WM%d latency not provided\n", 2220 name, level); 2221 continue; 2222 } 2223 2224 /* 2225 * - latencies are in us on gen9. 2226 * - before then, WM1+ latency values are in 0.5us units 2227 */ 2228 if (IS_GEN9(dev)) 2229 latency *= 10; 2230 else if (level > 0) 2231 latency *= 5; 2232 2233 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2234 name, level, wm[level], 2235 latency / 10, latency % 10); 2236 } 2237 } 2238 2239 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2240 uint16_t wm[5], uint16_t min) 2241 { 2242 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2243 2244 if (wm[0] >= min) 2245 return false; 2246 2247 wm[0] = max(wm[0], min); 2248 for (level = 1; level <= max_level; level++) 2249 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2250 2251 return true; 2252 } 2253 2254 static void snb_wm_latency_quirk(struct drm_device *dev) 2255 { 2256 struct drm_i915_private *dev_priv = dev->dev_private; 2257 bool changed; 2258 2259 /* 2260 * The BIOS provided WM memory latency values are often 2261 * inadequate for high resolution displays. Adjust them. 2262 */ 2263 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2264 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2265 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2266 2267 if (!changed) 2268 return; 2269 2270 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2271 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2272 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2273 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2274 } 2275 2276 static void ilk_setup_wm_latency(struct drm_device *dev) 2277 { 2278 struct drm_i915_private *dev_priv = dev->dev_private; 2279 2280 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2281 2282 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2283 sizeof(dev_priv->wm.pri_latency)); 2284 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2285 sizeof(dev_priv->wm.pri_latency)); 2286 2287 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2288 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2289 2290 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2291 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2292 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2293 2294 if (IS_GEN6(dev)) 2295 snb_wm_latency_quirk(dev); 2296 } 2297 2298 static void skl_setup_wm_latency(struct drm_device *dev) 2299 { 2300 struct drm_i915_private *dev_priv = dev->dev_private; 2301 2302 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2303 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2304 } 2305 2306 static void ilk_compute_wm_config(struct drm_device *dev, 2307 struct intel_wm_config *config) 2308 { 2309 struct intel_crtc *intel_crtc; 2310 2311 /* Compute the currently _active_ config */ 2312 for_each_intel_crtc(dev, intel_crtc) { 2313 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; 2314 2315 if (!wm->pipe_enabled) 2316 continue; 2317 2318 config->sprites_enabled |= wm->sprites_enabled; 2319 config->sprites_scaled |= wm->sprites_scaled; 2320 config->num_pipes_active++; 2321 } 2322 } 2323 2324 /* Compute new watermarks for the pipe */ 2325 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, 2326 struct intel_pipe_wm *pipe_wm) 2327 { 2328 struct drm_crtc *crtc = cstate->base.crtc; 2329 struct drm_device *dev = crtc->dev; 2330 const struct drm_i915_private *dev_priv = dev->dev_private; 2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2332 struct intel_plane *intel_plane; 2333 struct intel_plane_state *sprstate = NULL; 2334 int level, max_level = ilk_wm_max_level(dev); 2335 /* LP0 watermark maximums depend on this pipe alone */ 2336 struct intel_wm_config config = { 2337 .num_pipes_active = 1, 2338 }; 2339 struct ilk_wm_maximums max; 2340 2341 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2342 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { 2343 sprstate = to_intel_plane_state(intel_plane->base.state); 2344 break; 2345 } 2346 } 2347 2348 config.sprites_enabled = sprstate->visible; 2349 config.sprites_scaled = sprstate->visible && 2350 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || 2351 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); 2352 2353 pipe_wm->pipe_enabled = cstate->base.active; 2354 pipe_wm->sprites_enabled = sprstate->visible; 2355 pipe_wm->sprites_scaled = config.sprites_scaled; 2356 2357 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2358 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) 2359 max_level = 1; 2360 2361 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2362 if (config.sprites_scaled) 2363 max_level = 0; 2364 2365 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); 2366 2367 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2368 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2369 2370 /* LP0 watermarks always use 1/2 DDB partitioning */ 2371 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2372 2373 /* At least LP0 must be valid */ 2374 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2375 return false; 2376 2377 ilk_compute_wm_reg_maximums(dev, 1, &max); 2378 2379 for (level = 1; level <= max_level; level++) { 2380 struct intel_wm_level wm = {}; 2381 2382 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); 2383 2384 /* 2385 * Disable any watermark level that exceeds the 2386 * register maximums since such watermarks are 2387 * always invalid. 2388 */ 2389 if (!ilk_validate_wm_level(level, &max, &wm)) 2390 break; 2391 2392 pipe_wm->wm[level] = wm; 2393 } 2394 2395 return true; 2396 } 2397 2398 /* 2399 * Merge the watermarks from all active pipes for a specific level. 2400 */ 2401 static void ilk_merge_wm_level(struct drm_device *dev, 2402 int level, 2403 struct intel_wm_level *ret_wm) 2404 { 2405 const struct intel_crtc *intel_crtc; 2406 2407 ret_wm->enable = true; 2408 2409 for_each_intel_crtc(dev, intel_crtc) { 2410 const struct intel_pipe_wm *active = &intel_crtc->wm.active; 2411 const struct intel_wm_level *wm = &active->wm[level]; 2412 2413 if (!active->pipe_enabled) 2414 continue; 2415 2416 /* 2417 * The watermark values may have been used in the past, 2418 * so we must maintain them in the registers for some 2419 * time even if the level is now disabled. 2420 */ 2421 if (!wm->enable) 2422 ret_wm->enable = false; 2423 2424 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2425 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2426 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2427 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2428 } 2429 } 2430 2431 /* 2432 * Merge all low power watermarks for all active pipes. 2433 */ 2434 static void ilk_wm_merge(struct drm_device *dev, 2435 const struct intel_wm_config *config, 2436 const struct ilk_wm_maximums *max, 2437 struct intel_pipe_wm *merged) 2438 { 2439 struct drm_i915_private *dev_priv = dev->dev_private; 2440 int level, max_level = ilk_wm_max_level(dev); 2441 int last_enabled_level = max_level; 2442 2443 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2444 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2445 config->num_pipes_active > 1) 2446 return; 2447 2448 /* ILK: FBC WM must be disabled always */ 2449 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2450 2451 /* merge each WM1+ level */ 2452 for (level = 1; level <= max_level; level++) { 2453 struct intel_wm_level *wm = &merged->wm[level]; 2454 2455 ilk_merge_wm_level(dev, level, wm); 2456 2457 if (level > last_enabled_level) 2458 wm->enable = false; 2459 else if (!ilk_validate_wm_level(level, max, wm)) 2460 /* make sure all following levels get disabled */ 2461 last_enabled_level = level - 1; 2462 2463 /* 2464 * The spec says it is preferred to disable 2465 * FBC WMs instead of disabling a WM level. 2466 */ 2467 if (wm->fbc_val > max->fbc) { 2468 if (wm->enable) 2469 merged->fbc_wm_enabled = false; 2470 wm->fbc_val = 0; 2471 } 2472 } 2473 2474 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2475 /* 2476 * FIXME this is racy. FBC might get enabled later. 2477 * What we should check here is whether FBC can be 2478 * enabled sometime later. 2479 */ 2480 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2481 intel_fbc_enabled(dev_priv)) { 2482 for (level = 2; level <= max_level; level++) { 2483 struct intel_wm_level *wm = &merged->wm[level]; 2484 2485 wm->enable = false; 2486 } 2487 } 2488 } 2489 2490 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2491 { 2492 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2493 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2494 } 2495 2496 /* The value we need to program into the WM_LPx latency field */ 2497 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2498 { 2499 struct drm_i915_private *dev_priv = dev->dev_private; 2500 2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2502 return 2 * level; 2503 else 2504 return dev_priv->wm.pri_latency[level]; 2505 } 2506 2507 static void ilk_compute_wm_results(struct drm_device *dev, 2508 const struct intel_pipe_wm *merged, 2509 enum intel_ddb_partitioning partitioning, 2510 struct ilk_wm_values *results) 2511 { 2512 struct intel_crtc *intel_crtc; 2513 int level, wm_lp; 2514 2515 results->enable_fbc_wm = merged->fbc_wm_enabled; 2516 results->partitioning = partitioning; 2517 2518 /* LP1+ register values */ 2519 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2520 const struct intel_wm_level *r; 2521 2522 level = ilk_wm_lp_to_level(wm_lp, merged); 2523 2524 r = &merged->wm[level]; 2525 2526 /* 2527 * Maintain the watermark values even if the level is 2528 * disabled. Doing otherwise could cause underruns. 2529 */ 2530 results->wm_lp[wm_lp - 1] = 2531 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2532 (r->pri_val << WM1_LP_SR_SHIFT) | 2533 r->cur_val; 2534 2535 if (r->enable) 2536 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2537 2538 if (INTEL_INFO(dev)->gen >= 8) 2539 results->wm_lp[wm_lp - 1] |= 2540 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2541 else 2542 results->wm_lp[wm_lp - 1] |= 2543 r->fbc_val << WM1_LP_FBC_SHIFT; 2544 2545 /* 2546 * Always set WM1S_LP_EN when spr_val != 0, even if the 2547 * level is disabled. Doing otherwise could cause underruns. 2548 */ 2549 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2550 WARN_ON(wm_lp != 1); 2551 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2552 } else 2553 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2554 } 2555 2556 /* LP0 register values */ 2557 for_each_intel_crtc(dev, intel_crtc) { 2558 enum pipe pipe = intel_crtc->pipe; 2559 const struct intel_wm_level *r = 2560 &intel_crtc->wm.active.wm[0]; 2561 2562 if (WARN_ON(!r->enable)) 2563 continue; 2564 2565 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2566 2567 results->wm_pipe[pipe] = 2568 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2569 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2570 r->cur_val; 2571 } 2572 } 2573 2574 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2575 * case both are at the same level. Prefer r1 in case they're the same. */ 2576 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2577 struct intel_pipe_wm *r1, 2578 struct intel_pipe_wm *r2) 2579 { 2580 int level, max_level = ilk_wm_max_level(dev); 2581 int level1 = 0, level2 = 0; 2582 2583 for (level = 1; level <= max_level; level++) { 2584 if (r1->wm[level].enable) 2585 level1 = level; 2586 if (r2->wm[level].enable) 2587 level2 = level; 2588 } 2589 2590 if (level1 == level2) { 2591 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2592 return r2; 2593 else 2594 return r1; 2595 } else if (level1 > level2) { 2596 return r1; 2597 } else { 2598 return r2; 2599 } 2600 } 2601 2602 /* dirty bits used to track which watermarks need changes */ 2603 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2604 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2605 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2606 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2607 #define WM_DIRTY_FBC (1 << 24) 2608 #define WM_DIRTY_DDB (1 << 25) 2609 2610 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2611 const struct ilk_wm_values *old, 2612 const struct ilk_wm_values *new) 2613 { 2614 unsigned int dirty = 0; 2615 enum pipe pipe; 2616 int wm_lp; 2617 2618 for_each_pipe(dev_priv, pipe) { 2619 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2620 dirty |= WM_DIRTY_LINETIME(pipe); 2621 /* Must disable LP1+ watermarks too */ 2622 dirty |= WM_DIRTY_LP_ALL; 2623 } 2624 2625 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2626 dirty |= WM_DIRTY_PIPE(pipe); 2627 /* Must disable LP1+ watermarks too */ 2628 dirty |= WM_DIRTY_LP_ALL; 2629 } 2630 } 2631 2632 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2633 dirty |= WM_DIRTY_FBC; 2634 /* Must disable LP1+ watermarks too */ 2635 dirty |= WM_DIRTY_LP_ALL; 2636 } 2637 2638 if (old->partitioning != new->partitioning) { 2639 dirty |= WM_DIRTY_DDB; 2640 /* Must disable LP1+ watermarks too */ 2641 dirty |= WM_DIRTY_LP_ALL; 2642 } 2643 2644 /* LP1+ watermarks already deemed dirty, no need to continue */ 2645 if (dirty & WM_DIRTY_LP_ALL) 2646 return dirty; 2647 2648 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2649 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2650 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2651 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2652 break; 2653 } 2654 2655 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2656 for (; wm_lp <= 3; wm_lp++) 2657 dirty |= WM_DIRTY_LP(wm_lp); 2658 2659 return dirty; 2660 } 2661 2662 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2663 unsigned int dirty) 2664 { 2665 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2666 bool changed = false; 2667 2668 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2669 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2670 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2671 changed = true; 2672 } 2673 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2674 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2675 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2676 changed = true; 2677 } 2678 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2679 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2680 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2681 changed = true; 2682 } 2683 2684 /* 2685 * Don't touch WM1S_LP_EN here. 2686 * Doing so could cause underruns. 2687 */ 2688 2689 return changed; 2690 } 2691 2692 /* 2693 * The spec says we shouldn't write when we don't need, because every write 2694 * causes WMs to be re-evaluated, expending some power. 2695 */ 2696 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2697 struct ilk_wm_values *results) 2698 { 2699 struct drm_device *dev = dev_priv->dev; 2700 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2701 unsigned int dirty; 2702 uint32_t val; 2703 2704 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2705 if (!dirty) 2706 return; 2707 2708 _ilk_disable_lp_wm(dev_priv, dirty); 2709 2710 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2711 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2712 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2713 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2714 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2715 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2716 2717 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2718 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2719 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2720 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2721 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2722 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2723 2724 if (dirty & WM_DIRTY_DDB) { 2725 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2726 val = I915_READ(WM_MISC); 2727 if (results->partitioning == INTEL_DDB_PART_1_2) 2728 val &= ~WM_MISC_DATA_PARTITION_5_6; 2729 else 2730 val |= WM_MISC_DATA_PARTITION_5_6; 2731 I915_WRITE(WM_MISC, val); 2732 } else { 2733 val = I915_READ(DISP_ARB_CTL2); 2734 if (results->partitioning == INTEL_DDB_PART_1_2) 2735 val &= ~DISP_DATA_PARTITION_5_6; 2736 else 2737 val |= DISP_DATA_PARTITION_5_6; 2738 I915_WRITE(DISP_ARB_CTL2, val); 2739 } 2740 } 2741 2742 if (dirty & WM_DIRTY_FBC) { 2743 val = I915_READ(DISP_ARB_CTL); 2744 if (results->enable_fbc_wm) 2745 val &= ~DISP_FBC_WM_DIS; 2746 else 2747 val |= DISP_FBC_WM_DIS; 2748 I915_WRITE(DISP_ARB_CTL, val); 2749 } 2750 2751 if (dirty & WM_DIRTY_LP(1) && 2752 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2753 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2754 2755 if (INTEL_INFO(dev)->gen >= 7) { 2756 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2757 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2758 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2759 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2760 } 2761 2762 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2763 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2764 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2765 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2766 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2767 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2768 2769 dev_priv->wm.hw = *results; 2770 } 2771 2772 static bool ilk_disable_lp_wm(struct drm_device *dev) 2773 { 2774 struct drm_i915_private *dev_priv = dev->dev_private; 2775 2776 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2777 } 2778 2779 /* 2780 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2781 * different active planes. 2782 */ 2783 2784 #define SKL_DDB_SIZE 896 /* in blocks */ 2785 #define BXT_DDB_SIZE 512 2786 2787 static void 2788 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2789 struct drm_crtc *for_crtc, 2790 const struct intel_wm_config *config, 2791 const struct skl_pipe_wm_parameters *params, 2792 struct skl_ddb_entry *alloc /* out */) 2793 { 2794 struct drm_crtc *crtc; 2795 unsigned int pipe_size, ddb_size; 2796 int nth_active_pipe; 2797 2798 if (!params->active) { 2799 alloc->start = 0; 2800 alloc->end = 0; 2801 return; 2802 } 2803 2804 if (IS_BROXTON(dev)) 2805 ddb_size = BXT_DDB_SIZE; 2806 else 2807 ddb_size = SKL_DDB_SIZE; 2808 2809 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2810 2811 nth_active_pipe = 0; 2812 for_each_crtc(dev, crtc) { 2813 if (!to_intel_crtc(crtc)->active) 2814 continue; 2815 2816 if (crtc == for_crtc) 2817 break; 2818 2819 nth_active_pipe++; 2820 } 2821 2822 pipe_size = ddb_size / config->num_pipes_active; 2823 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2824 alloc->end = alloc->start + pipe_size; 2825 } 2826 2827 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2828 { 2829 if (config->num_pipes_active == 1) 2830 return 32; 2831 2832 return 8; 2833 } 2834 2835 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2836 { 2837 entry->start = reg & 0x3ff; 2838 entry->end = (reg >> 16) & 0x3ff; 2839 if (entry->end) 2840 entry->end += 1; 2841 } 2842 2843 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2844 struct skl_ddb_allocation *ddb /* out */) 2845 { 2846 enum pipe pipe; 2847 int plane; 2848 u32 val; 2849 2850 memset(ddb, 0, sizeof(*ddb)); 2851 2852 for_each_pipe(dev_priv, pipe) { 2853 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) 2854 continue; 2855 2856 for_each_plane(dev_priv, pipe, plane) { 2857 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2858 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2859 val); 2860 } 2861 2862 val = I915_READ(CUR_BUF_CFG(pipe)); 2863 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], 2864 val); 2865 } 2866 } 2867 2868 static unsigned int 2869 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) 2870 { 2871 2872 /* for planar format */ 2873 if (p->y_bytes_per_pixel) { 2874 if (y) /* y-plane data rate */ 2875 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; 2876 else /* uv-plane data rate */ 2877 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; 2878 } 2879 2880 /* for packed formats */ 2881 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; 2882 } 2883 2884 /* 2885 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2886 * a 8192x4096@32bpp framebuffer: 2887 * 3 * 4096 * 8192 * 4 < 2^32 2888 */ 2889 static unsigned int 2890 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, 2891 const struct skl_pipe_wm_parameters *params) 2892 { 2893 unsigned int total_data_rate = 0; 2894 int plane; 2895 2896 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2897 const struct intel_plane_wm_parameters *p; 2898 2899 p = ¶ms->plane[plane]; 2900 if (!p->enabled) 2901 continue; 2902 2903 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ 2904 if (p->y_bytes_per_pixel) { 2905 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ 2906 } 2907 } 2908 2909 return total_data_rate; 2910 } 2911 2912 static void 2913 skl_allocate_pipe_ddb(struct drm_crtc *crtc, 2914 const struct intel_wm_config *config, 2915 const struct skl_pipe_wm_parameters *params, 2916 struct skl_ddb_allocation *ddb /* out */) 2917 { 2918 struct drm_device *dev = crtc->dev; 2919 struct drm_i915_private *dev_priv = dev->dev_private; 2920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2921 enum pipe pipe = intel_crtc->pipe; 2922 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2923 uint16_t alloc_size, start, cursor_blocks; 2924 uint16_t minimum[I915_MAX_PLANES]; 2925 uint16_t y_minimum[I915_MAX_PLANES]; 2926 unsigned int total_data_rate; 2927 int plane; 2928 2929 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); 2930 alloc_size = skl_ddb_entry_size(alloc); 2931 if (alloc_size == 0) { 2932 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2933 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, 2934 sizeof(ddb->plane[pipe][PLANE_CURSOR])); 2935 return; 2936 } 2937 2938 cursor_blocks = skl_cursor_allocation(config); 2939 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; 2940 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; 2941 2942 alloc_size -= cursor_blocks; 2943 alloc->end -= cursor_blocks; 2944 2945 /* 1. Allocate the mininum required blocks for each active plane */ 2946 for_each_plane(dev_priv, pipe, plane) { 2947 const struct intel_plane_wm_parameters *p; 2948 2949 p = ¶ms->plane[plane]; 2950 if (!p->enabled) 2951 continue; 2952 2953 minimum[plane] = 8; 2954 alloc_size -= minimum[plane]; 2955 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; 2956 alloc_size -= y_minimum[plane]; 2957 } 2958 2959 /* 2960 * 2. Distribute the remaining space in proportion to the amount of 2961 * data each plane needs to fetch from memory. 2962 * 2963 * FIXME: we may not allocate every single block here. 2964 */ 2965 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); 2966 2967 start = alloc->start; 2968 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2969 const struct intel_plane_wm_parameters *p; 2970 unsigned int data_rate, y_data_rate; 2971 uint16_t plane_blocks, y_plane_blocks = 0; 2972 2973 p = ¶ms->plane[plane]; 2974 if (!p->enabled) 2975 continue; 2976 2977 data_rate = skl_plane_relative_data_rate(p, 0); 2978 2979 /* 2980 * allocation for (packed formats) or (uv-plane part of planar format): 2981 * promote the expression to 64 bits to avoid overflowing, the 2982 * result is < available as data_rate / total_data_rate < 1 2983 */ 2984 plane_blocks = minimum[plane]; 2985 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 2986 total_data_rate); 2987 2988 ddb->plane[pipe][plane].start = start; 2989 ddb->plane[pipe][plane].end = start + plane_blocks; 2990 2991 start += plane_blocks; 2992 2993 /* 2994 * allocation for y_plane part of planar format: 2995 */ 2996 if (p->y_bytes_per_pixel) { 2997 y_data_rate = skl_plane_relative_data_rate(p, 1); 2998 y_plane_blocks = y_minimum[plane]; 2999 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 3000 total_data_rate); 3001 3002 ddb->y_plane[pipe][plane].start = start; 3003 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; 3004 3005 start += y_plane_blocks; 3006 } 3007 3008 } 3009 3010 } 3011 3012 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3013 { 3014 /* TODO: Take into account the scalers once we support them */ 3015 return config->base.adjusted_mode.crtc_clock; 3016 } 3017 3018 /* 3019 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3020 * for the read latency) and bytes_per_pixel should always be <= 8, so that 3021 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 3022 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 3023 */ 3024 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 3025 uint32_t latency) 3026 { 3027 uint32_t wm_intermediate_val, ret; 3028 3029 if (latency == 0) 3030 return UINT_MAX; 3031 3032 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; 3033 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3034 3035 return ret; 3036 } 3037 3038 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3039 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 3040 uint64_t tiling, uint32_t latency) 3041 { 3042 uint32_t ret; 3043 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3044 uint32_t wm_intermediate_val; 3045 3046 if (latency == 0) 3047 return UINT_MAX; 3048 3049 plane_bytes_per_line = horiz_pixels * bytes_per_pixel; 3050 3051 if (tiling == I915_FORMAT_MOD_Y_TILED || 3052 tiling == I915_FORMAT_MOD_Yf_TILED) { 3053 plane_bytes_per_line *= 4; 3054 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3055 plane_blocks_per_line /= 4; 3056 } else { 3057 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3058 } 3059 3060 wm_intermediate_val = latency * pixel_rate; 3061 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3062 plane_blocks_per_line; 3063 3064 return ret; 3065 } 3066 3067 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3068 const struct intel_crtc *intel_crtc) 3069 { 3070 struct drm_device *dev = intel_crtc->base.dev; 3071 struct drm_i915_private *dev_priv = dev->dev_private; 3072 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3073 enum pipe pipe = intel_crtc->pipe; 3074 3075 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], 3076 sizeof(new_ddb->plane[pipe]))) 3077 return true; 3078 3079 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], 3080 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) 3081 return true; 3082 3083 return false; 3084 } 3085 3086 static void skl_compute_wm_global_parameters(struct drm_device *dev, 3087 struct intel_wm_config *config) 3088 { 3089 struct drm_crtc *crtc; 3090 struct drm_plane *plane; 3091 3092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3093 config->num_pipes_active += to_intel_crtc(crtc)->active; 3094 3095 /* FIXME: I don't think we need those two global parameters on SKL */ 3096 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3097 struct intel_plane *intel_plane = to_intel_plane(plane); 3098 3099 config->sprites_enabled |= intel_plane->wm.enabled; 3100 config->sprites_scaled |= intel_plane->wm.scaled; 3101 } 3102 } 3103 3104 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, 3105 struct skl_pipe_wm_parameters *p) 3106 { 3107 struct drm_device *dev = crtc->dev; 3108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3109 enum pipe pipe = intel_crtc->pipe; 3110 struct drm_plane *plane; 3111 struct drm_framebuffer *fb; 3112 int i = 1; /* Index for sprite planes start */ 3113 3114 p->active = intel_crtc->active; 3115 if (p->active) { 3116 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 3117 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); 3118 3119 fb = crtc->primary->state->fb; 3120 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ 3121 if (fb) { 3122 p->plane[0].enabled = true; 3123 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3124 drm_format_plane_cpp(fb->pixel_format, 1) : 3125 drm_format_plane_cpp(fb->pixel_format, 0); 3126 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3127 drm_format_plane_cpp(fb->pixel_format, 0) : 0; 3128 p->plane[0].tiling = fb->modifier[0]; 3129 } else { 3130 p->plane[0].enabled = false; 3131 p->plane[0].bytes_per_pixel = 0; 3132 p->plane[0].y_bytes_per_pixel = 0; 3133 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; 3134 } 3135 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; 3136 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; 3137 p->plane[0].rotation = crtc->primary->state->rotation; 3138 3139 fb = crtc->cursor->state->fb; 3140 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; 3141 if (fb) { 3142 p->plane[PLANE_CURSOR].enabled = true; 3143 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; 3144 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; 3145 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; 3146 } else { 3147 p->plane[PLANE_CURSOR].enabled = false; 3148 p->plane[PLANE_CURSOR].bytes_per_pixel = 0; 3149 p->plane[PLANE_CURSOR].horiz_pixels = 64; 3150 p->plane[PLANE_CURSOR].vert_pixels = 64; 3151 } 3152 } 3153 3154 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3155 struct intel_plane *intel_plane = to_intel_plane(plane); 3156 3157 if (intel_plane->pipe == pipe && 3158 plane->type == DRM_PLANE_TYPE_OVERLAY) 3159 p->plane[i++] = intel_plane->wm; 3160 } 3161 } 3162 3163 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3164 struct skl_pipe_wm_parameters *p, 3165 struct intel_plane_wm_parameters *p_params, 3166 uint16_t ddb_allocation, 3167 int level, 3168 uint16_t *out_blocks, /* out */ 3169 uint8_t *out_lines /* out */) 3170 { 3171 uint32_t latency = dev_priv->wm.skl_latency[level]; 3172 uint32_t method1, method2; 3173 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3174 uint32_t res_blocks, res_lines; 3175 uint32_t selected_result; 3176 uint8_t bytes_per_pixel; 3177 3178 if (latency == 0 || !p->active || !p_params->enabled) 3179 return false; 3180 3181 bytes_per_pixel = p_params->y_bytes_per_pixel ? 3182 p_params->y_bytes_per_pixel : 3183 p_params->bytes_per_pixel; 3184 method1 = skl_wm_method1(p->pixel_rate, 3185 bytes_per_pixel, 3186 latency); 3187 method2 = skl_wm_method2(p->pixel_rate, 3188 p->pipe_htotal, 3189 p_params->horiz_pixels, 3190 bytes_per_pixel, 3191 p_params->tiling, 3192 latency); 3193 3194 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; 3195 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3196 3197 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3198 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { 3199 uint32_t min_scanlines = 4; 3200 uint32_t y_tile_minimum; 3201 if (intel_rotation_90_or_270(p_params->rotation)) { 3202 switch (p_params->bytes_per_pixel) { 3203 case 1: 3204 min_scanlines = 16; 3205 break; 3206 case 2: 3207 min_scanlines = 8; 3208 break; 3209 case 8: 3210 WARN(1, "Unsupported pixel depth for rotation"); 3211 } 3212 } 3213 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3214 selected_result = max(method2, y_tile_minimum); 3215 } else { 3216 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3217 selected_result = min(method1, method2); 3218 else 3219 selected_result = method1; 3220 } 3221 3222 res_blocks = selected_result + 1; 3223 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3224 3225 if (level >= 1 && level <= 7) { 3226 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3227 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) 3228 res_lines += 4; 3229 else 3230 res_blocks++; 3231 } 3232 3233 if (res_blocks >= ddb_allocation || res_lines > 31) 3234 return false; 3235 3236 *out_blocks = res_blocks; 3237 *out_lines = res_lines; 3238 3239 return true; 3240 } 3241 3242 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3243 struct skl_ddb_allocation *ddb, 3244 struct skl_pipe_wm_parameters *p, 3245 enum pipe pipe, 3246 int level, 3247 int num_planes, 3248 struct skl_wm_level *result) 3249 { 3250 uint16_t ddb_blocks; 3251 int i; 3252 3253 for (i = 0; i < num_planes; i++) { 3254 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3255 3256 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3257 p, &p->plane[i], 3258 ddb_blocks, 3259 level, 3260 &result->plane_res_b[i], 3261 &result->plane_res_l[i]); 3262 } 3263 3264 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); 3265 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, 3266 &p->plane[PLANE_CURSOR], 3267 ddb_blocks, level, 3268 &result->plane_res_b[PLANE_CURSOR], 3269 &result->plane_res_l[PLANE_CURSOR]); 3270 } 3271 3272 static uint32_t 3273 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) 3274 { 3275 if (!to_intel_crtc(crtc)->active) 3276 return 0; 3277 3278 if (WARN_ON(p->pixel_rate == 0)) 3279 return 0; 3280 3281 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); 3282 } 3283 3284 static void skl_compute_transition_wm(struct drm_crtc *crtc, 3285 struct skl_pipe_wm_parameters *params, 3286 struct skl_wm_level *trans_wm /* out */) 3287 { 3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3289 int i; 3290 3291 if (!params->active) 3292 return; 3293 3294 /* Until we know more, just disable transition WMs */ 3295 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3296 trans_wm->plane_en[i] = false; 3297 trans_wm->plane_en[PLANE_CURSOR] = false; 3298 } 3299 3300 static void skl_compute_pipe_wm(struct drm_crtc *crtc, 3301 struct skl_ddb_allocation *ddb, 3302 struct skl_pipe_wm_parameters *params, 3303 struct skl_pipe_wm *pipe_wm) 3304 { 3305 struct drm_device *dev = crtc->dev; 3306 const struct drm_i915_private *dev_priv = dev->dev_private; 3307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3308 int level, max_level = ilk_wm_max_level(dev); 3309 3310 for (level = 0; level <= max_level; level++) { 3311 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, 3312 level, intel_num_planes(intel_crtc), 3313 &pipe_wm->wm[level]); 3314 } 3315 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); 3316 3317 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); 3318 } 3319 3320 static void skl_compute_wm_results(struct drm_device *dev, 3321 struct skl_pipe_wm_parameters *p, 3322 struct skl_pipe_wm *p_wm, 3323 struct skl_wm_values *r, 3324 struct intel_crtc *intel_crtc) 3325 { 3326 int level, max_level = ilk_wm_max_level(dev); 3327 enum pipe pipe = intel_crtc->pipe; 3328 uint32_t temp; 3329 int i; 3330 3331 for (level = 0; level <= max_level; level++) { 3332 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3333 temp = 0; 3334 3335 temp |= p_wm->wm[level].plane_res_l[i] << 3336 PLANE_WM_LINES_SHIFT; 3337 temp |= p_wm->wm[level].plane_res_b[i]; 3338 if (p_wm->wm[level].plane_en[i]) 3339 temp |= PLANE_WM_EN; 3340 3341 r->plane[pipe][i][level] = temp; 3342 } 3343 3344 temp = 0; 3345 3346 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3347 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; 3348 3349 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) 3350 temp |= PLANE_WM_EN; 3351 3352 r->plane[pipe][PLANE_CURSOR][level] = temp; 3353 3354 } 3355 3356 /* transition WMs */ 3357 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3358 temp = 0; 3359 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3360 temp |= p_wm->trans_wm.plane_res_b[i]; 3361 if (p_wm->trans_wm.plane_en[i]) 3362 temp |= PLANE_WM_EN; 3363 3364 r->plane_trans[pipe][i] = temp; 3365 } 3366 3367 temp = 0; 3368 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3369 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; 3370 if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) 3371 temp |= PLANE_WM_EN; 3372 3373 r->plane_trans[pipe][PLANE_CURSOR] = temp; 3374 3375 r->wm_linetime[pipe] = p_wm->linetime; 3376 } 3377 3378 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, 3379 const struct skl_ddb_entry *entry) 3380 { 3381 if (entry->end) 3382 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3383 else 3384 I915_WRITE(reg, 0); 3385 } 3386 3387 static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3388 const struct skl_wm_values *new) 3389 { 3390 struct drm_device *dev = dev_priv->dev; 3391 struct intel_crtc *crtc; 3392 3393 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 3394 int i, level, max_level = ilk_wm_max_level(dev); 3395 enum pipe pipe = crtc->pipe; 3396 3397 if (!new->dirty[pipe]) 3398 continue; 3399 3400 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3401 3402 for (level = 0; level <= max_level; level++) { 3403 for (i = 0; i < intel_num_planes(crtc); i++) 3404 I915_WRITE(PLANE_WM(pipe, i, level), 3405 new->plane[pipe][i][level]); 3406 I915_WRITE(CUR_WM(pipe, level), 3407 new->plane[pipe][PLANE_CURSOR][level]); 3408 } 3409 for (i = 0; i < intel_num_planes(crtc); i++) 3410 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3411 new->plane_trans[pipe][i]); 3412 I915_WRITE(CUR_WM_TRANS(pipe), 3413 new->plane_trans[pipe][PLANE_CURSOR]); 3414 3415 for (i = 0; i < intel_num_planes(crtc); i++) { 3416 skl_ddb_entry_write(dev_priv, 3417 PLANE_BUF_CFG(pipe, i), 3418 &new->ddb.plane[pipe][i]); 3419 skl_ddb_entry_write(dev_priv, 3420 PLANE_NV12_BUF_CFG(pipe, i), 3421 &new->ddb.y_plane[pipe][i]); 3422 } 3423 3424 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3425 &new->ddb.plane[pipe][PLANE_CURSOR]); 3426 } 3427 } 3428 3429 /* 3430 * When setting up a new DDB allocation arrangement, we need to correctly 3431 * sequence the times at which the new allocations for the pipes are taken into 3432 * account or we'll have pipes fetching from space previously allocated to 3433 * another pipe. 3434 * 3435 * Roughly the sequence looks like: 3436 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3437 * overlapping with a previous light-up pipe (another way to put it is: 3438 * pipes with their new allocation strickly included into their old ones). 3439 * 2. re-allocate the other pipes that get their allocation reduced 3440 * 3. allocate the pipes having their allocation increased 3441 * 3442 * Steps 1. and 2. are here to take care of the following case: 3443 * - Initially DDB looks like this: 3444 * | B | C | 3445 * - enable pipe A. 3446 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3447 * allocation 3448 * | A | B | C | 3449 * 3450 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3451 */ 3452 3453 static void 3454 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) 3455 { 3456 int plane; 3457 3458 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3459 3460 for_each_plane(dev_priv, pipe, plane) { 3461 I915_WRITE(PLANE_SURF(pipe, plane), 3462 I915_READ(PLANE_SURF(pipe, plane))); 3463 } 3464 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3465 } 3466 3467 static bool 3468 skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3469 const struct skl_ddb_allocation *new, 3470 enum pipe pipe) 3471 { 3472 uint16_t old_size, new_size; 3473 3474 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3475 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3476 3477 return old_size != new_size && 3478 new->pipe[pipe].start >= old->pipe[pipe].start && 3479 new->pipe[pipe].end <= old->pipe[pipe].end; 3480 } 3481 3482 static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3483 struct skl_wm_values *new_values) 3484 { 3485 struct drm_device *dev = dev_priv->dev; 3486 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3487 bool reallocated[I915_MAX_PIPES] = {}; 3488 struct intel_crtc *crtc; 3489 enum pipe pipe; 3490 3491 new_ddb = &new_values->ddb; 3492 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3493 3494 /* 3495 * First pass: flush the pipes with the new allocation contained into 3496 * the old space. 3497 * 3498 * We'll wait for the vblank on those pipes to ensure we can safely 3499 * re-allocate the freed space without this pipe fetching from it. 3500 */ 3501 for_each_intel_crtc(dev, crtc) { 3502 if (!crtc->active) 3503 continue; 3504 3505 pipe = crtc->pipe; 3506 3507 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3508 continue; 3509 3510 skl_wm_flush_pipe(dev_priv, pipe, 1); 3511 intel_wait_for_vblank(dev, pipe); 3512 3513 reallocated[pipe] = true; 3514 } 3515 3516 3517 /* 3518 * Second pass: flush the pipes that are having their allocation 3519 * reduced, but overlapping with a previous allocation. 3520 * 3521 * Here as well we need to wait for the vblank to make sure the freed 3522 * space is not used anymore. 3523 */ 3524 for_each_intel_crtc(dev, crtc) { 3525 if (!crtc->active) 3526 continue; 3527 3528 pipe = crtc->pipe; 3529 3530 if (reallocated[pipe]) 3531 continue; 3532 3533 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3534 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3535 skl_wm_flush_pipe(dev_priv, pipe, 2); 3536 intel_wait_for_vblank(dev, pipe); 3537 reallocated[pipe] = true; 3538 } 3539 } 3540 3541 /* 3542 * Third pass: flush the pipes that got more space allocated. 3543 * 3544 * We don't need to actively wait for the update here, next vblank 3545 * will just get more DDB space with the correct WM values. 3546 */ 3547 for_each_intel_crtc(dev, crtc) { 3548 if (!crtc->active) 3549 continue; 3550 3551 pipe = crtc->pipe; 3552 3553 /* 3554 * At this point, only the pipes more space than before are 3555 * left to re-allocate. 3556 */ 3557 if (reallocated[pipe]) 3558 continue; 3559 3560 skl_wm_flush_pipe(dev_priv, pipe, 3); 3561 } 3562 } 3563 3564 static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3565 struct skl_pipe_wm_parameters *params, 3566 struct intel_wm_config *config, 3567 struct skl_ddb_allocation *ddb, /* out */ 3568 struct skl_pipe_wm *pipe_wm /* out */) 3569 { 3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3571 3572 skl_compute_wm_pipe_parameters(crtc, params); 3573 skl_allocate_pipe_ddb(crtc, config, params, ddb); 3574 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); 3575 3576 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) 3577 return false; 3578 3579 intel_crtc->wm.skl_active = *pipe_wm; 3580 3581 return true; 3582 } 3583 3584 static void skl_update_other_pipe_wm(struct drm_device *dev, 3585 struct drm_crtc *crtc, 3586 struct intel_wm_config *config, 3587 struct skl_wm_values *r) 3588 { 3589 struct intel_crtc *intel_crtc; 3590 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3591 3592 /* 3593 * If the WM update hasn't changed the allocation for this_crtc (the 3594 * crtc we are currently computing the new WM values for), other 3595 * enabled crtcs will keep the same allocation and we don't need to 3596 * recompute anything for them. 3597 */ 3598 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3599 return; 3600 3601 /* 3602 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3603 * other active pipes need new DDB allocation and WM values. 3604 */ 3605 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 3606 base.head) { 3607 struct skl_pipe_wm_parameters params = {}; 3608 struct skl_pipe_wm pipe_wm = {}; 3609 bool wm_changed; 3610 3611 if (this_crtc->pipe == intel_crtc->pipe) 3612 continue; 3613 3614 if (!intel_crtc->active) 3615 continue; 3616 3617 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3618 ¶ms, config, 3619 &r->ddb, &pipe_wm); 3620 3621 /* 3622 * If we end up re-computing the other pipe WM values, it's 3623 * because it was really needed, so we expect the WM values to 3624 * be different. 3625 */ 3626 WARN_ON(!wm_changed); 3627 3628 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); 3629 r->dirty[intel_crtc->pipe] = true; 3630 } 3631 } 3632 3633 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) 3634 { 3635 watermarks->wm_linetime[pipe] = 0; 3636 memset(watermarks->plane[pipe], 0, 3637 sizeof(uint32_t) * 8 * I915_MAX_PLANES); 3638 memset(watermarks->plane_trans[pipe], 3639 0, sizeof(uint32_t) * I915_MAX_PLANES); 3640 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; 3641 3642 /* Clear ddb entries for pipe */ 3643 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); 3644 memset(&watermarks->ddb.plane[pipe], 0, 3645 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3646 memset(&watermarks->ddb.y_plane[pipe], 0, 3647 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3648 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, 3649 sizeof(struct skl_ddb_entry)); 3650 3651 } 3652 3653 static void skl_update_wm(struct drm_crtc *crtc) 3654 { 3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3656 struct drm_device *dev = crtc->dev; 3657 struct drm_i915_private *dev_priv = dev->dev_private; 3658 struct skl_pipe_wm_parameters params = {}; 3659 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3660 struct skl_pipe_wm pipe_wm = {}; 3661 struct intel_wm_config config = {}; 3662 3663 3664 /* Clear all dirty flags */ 3665 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); 3666 3667 skl_clear_wm(results, intel_crtc->pipe); 3668 3669 skl_compute_wm_global_parameters(dev, &config); 3670 3671 if (!skl_update_pipe_wm(crtc, ¶ms, &config, 3672 &results->ddb, &pipe_wm)) 3673 return; 3674 3675 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); 3676 results->dirty[intel_crtc->pipe] = true; 3677 3678 skl_update_other_pipe_wm(dev, crtc, &config, results); 3679 skl_write_wm_values(dev_priv, results); 3680 skl_flush_wm_values(dev_priv, results); 3681 3682 /* store the new configuration */ 3683 dev_priv->wm.skl_hw = *results; 3684 } 3685 3686 static void 3687 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, 3688 uint32_t sprite_width, uint32_t sprite_height, 3689 int pixel_size, bool enabled, bool scaled) 3690 { 3691 struct intel_plane *intel_plane = to_intel_plane(plane); 3692 struct drm_framebuffer *fb = plane->state->fb; 3693 3694 intel_plane->wm.enabled = enabled; 3695 intel_plane->wm.scaled = scaled; 3696 intel_plane->wm.horiz_pixels = sprite_width; 3697 intel_plane->wm.vert_pixels = sprite_height; 3698 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; 3699 3700 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ 3701 intel_plane->wm.bytes_per_pixel = 3702 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3703 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; 3704 intel_plane->wm.y_bytes_per_pixel = 3705 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3706 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; 3707 3708 /* 3709 * Framebuffer can be NULL on plane disable, but it does not 3710 * matter for watermarks if we assume no tiling in that case. 3711 */ 3712 if (fb) 3713 intel_plane->wm.tiling = fb->modifier[0]; 3714 intel_plane->wm.rotation = plane->state->rotation; 3715 3716 skl_update_wm(crtc); 3717 } 3718 3719 static void ilk_update_wm(struct drm_crtc *crtc) 3720 { 3721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3722 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3723 struct drm_device *dev = crtc->dev; 3724 struct drm_i915_private *dev_priv = dev->dev_private; 3725 struct ilk_wm_maximums max; 3726 struct ilk_wm_values results = {}; 3727 enum intel_ddb_partitioning partitioning; 3728 struct intel_pipe_wm pipe_wm = {}; 3729 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; 3730 struct intel_wm_config config = {}; 3731 3732 WARN_ON(cstate->base.active != intel_crtc->active); 3733 3734 intel_compute_pipe_wm(cstate, &pipe_wm); 3735 3736 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 3737 return; 3738 3739 intel_crtc->wm.active = pipe_wm; 3740 3741 ilk_compute_wm_config(dev, &config); 3742 3743 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3744 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3745 3746 /* 5/6 split only in single pipe config on IVB+ */ 3747 if (INTEL_INFO(dev)->gen >= 7 && 3748 config.num_pipes_active == 1 && config.sprites_enabled) { 3749 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3750 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3751 3752 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3753 } else { 3754 best_lp_wm = &lp_wm_1_2; 3755 } 3756 3757 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3758 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3759 3760 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3761 3762 ilk_write_wm_values(dev_priv, &results); 3763 } 3764 3765 static void 3766 ilk_update_sprite_wm(struct drm_plane *plane, 3767 struct drm_crtc *crtc, 3768 uint32_t sprite_width, uint32_t sprite_height, 3769 int pixel_size, bool enabled, bool scaled) 3770 { 3771 struct drm_device *dev = plane->dev; 3772 struct intel_plane *intel_plane = to_intel_plane(plane); 3773 3774 /* 3775 * IVB workaround: must disable low power watermarks for at least 3776 * one frame before enabling scaling. LP watermarks can be re-enabled 3777 * when scaling is disabled. 3778 * 3779 * WaCxSRDisabledForSpriteScaling:ivb 3780 */ 3781 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 3782 intel_wait_for_vblank(dev, intel_plane->pipe); 3783 3784 ilk_update_wm(crtc); 3785 } 3786 3787 static void skl_pipe_wm_active_state(uint32_t val, 3788 struct skl_pipe_wm *active, 3789 bool is_transwm, 3790 bool is_cursor, 3791 int i, 3792 int level) 3793 { 3794 bool is_enabled = (val & PLANE_WM_EN) != 0; 3795 3796 if (!is_transwm) { 3797 if (!is_cursor) { 3798 active->wm[level].plane_en[i] = is_enabled; 3799 active->wm[level].plane_res_b[i] = 3800 val & PLANE_WM_BLOCKS_MASK; 3801 active->wm[level].plane_res_l[i] = 3802 (val >> PLANE_WM_LINES_SHIFT) & 3803 PLANE_WM_LINES_MASK; 3804 } else { 3805 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; 3806 active->wm[level].plane_res_b[PLANE_CURSOR] = 3807 val & PLANE_WM_BLOCKS_MASK; 3808 active->wm[level].plane_res_l[PLANE_CURSOR] = 3809 (val >> PLANE_WM_LINES_SHIFT) & 3810 PLANE_WM_LINES_MASK; 3811 } 3812 } else { 3813 if (!is_cursor) { 3814 active->trans_wm.plane_en[i] = is_enabled; 3815 active->trans_wm.plane_res_b[i] = 3816 val & PLANE_WM_BLOCKS_MASK; 3817 active->trans_wm.plane_res_l[i] = 3818 (val >> PLANE_WM_LINES_SHIFT) & 3819 PLANE_WM_LINES_MASK; 3820 } else { 3821 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; 3822 active->trans_wm.plane_res_b[PLANE_CURSOR] = 3823 val & PLANE_WM_BLOCKS_MASK; 3824 active->trans_wm.plane_res_l[PLANE_CURSOR] = 3825 (val >> PLANE_WM_LINES_SHIFT) & 3826 PLANE_WM_LINES_MASK; 3827 } 3828 } 3829 } 3830 3831 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3832 { 3833 struct drm_device *dev = crtc->dev; 3834 struct drm_i915_private *dev_priv = dev->dev_private; 3835 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3837 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; 3838 enum pipe pipe = intel_crtc->pipe; 3839 int level, i, max_level; 3840 uint32_t temp; 3841 3842 max_level = ilk_wm_max_level(dev); 3843 3844 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3845 3846 for (level = 0; level <= max_level; level++) { 3847 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3848 hw->plane[pipe][i][level] = 3849 I915_READ(PLANE_WM(pipe, i, level)); 3850 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); 3851 } 3852 3853 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3854 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3855 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); 3856 3857 if (!intel_crtc->active) 3858 return; 3859 3860 hw->dirty[pipe] = true; 3861 3862 active->linetime = hw->wm_linetime[pipe]; 3863 3864 for (level = 0; level <= max_level; level++) { 3865 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3866 temp = hw->plane[pipe][i][level]; 3867 skl_pipe_wm_active_state(temp, active, false, 3868 false, i, level); 3869 } 3870 temp = hw->plane[pipe][PLANE_CURSOR][level]; 3871 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3872 } 3873 3874 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3875 temp = hw->plane_trans[pipe][i]; 3876 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3877 } 3878 3879 temp = hw->plane_trans[pipe][PLANE_CURSOR]; 3880 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3881 } 3882 3883 void skl_wm_get_hw_state(struct drm_device *dev) 3884 { 3885 struct drm_i915_private *dev_priv = dev->dev_private; 3886 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3887 struct drm_crtc *crtc; 3888 3889 skl_ddb_get_hw_state(dev_priv, ddb); 3890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3891 skl_pipe_wm_get_hw_state(crtc); 3892 } 3893 3894 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3895 { 3896 struct drm_device *dev = crtc->dev; 3897 struct drm_i915_private *dev_priv = dev->dev_private; 3898 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3900 struct intel_pipe_wm *active = &intel_crtc->wm.active; 3901 enum pipe pipe = intel_crtc->pipe; 3902 static const unsigned int wm0_pipe_reg[] = { 3903 [PIPE_A] = WM0_PIPEA_ILK, 3904 [PIPE_B] = WM0_PIPEB_ILK, 3905 [PIPE_C] = WM0_PIPEC_IVB, 3906 }; 3907 3908 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3909 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3910 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3911 3912 memset(active, 0, sizeof(*active)); 3913 3914 active->pipe_enabled = intel_crtc->active; 3915 3916 if (active->pipe_enabled) { 3917 u32 tmp = hw->wm_pipe[pipe]; 3918 3919 /* 3920 * For active pipes LP0 watermark is marked as 3921 * enabled, and LP1+ watermaks as disabled since 3922 * we can't really reverse compute them in case 3923 * multiple pipes are active. 3924 */ 3925 active->wm[0].enable = true; 3926 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3927 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3928 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3929 active->linetime = hw->wm_linetime[pipe]; 3930 } else { 3931 int level, max_level = ilk_wm_max_level(dev); 3932 3933 /* 3934 * For inactive pipes, all watermark levels 3935 * should be marked as enabled but zeroed, 3936 * which is what we'd compute them to. 3937 */ 3938 for (level = 0; level <= max_level; level++) 3939 active->wm[level].enable = true; 3940 } 3941 } 3942 3943 #define _FW_WM(value, plane) \ 3944 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3945 #define _FW_WM_VLV(value, plane) \ 3946 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3947 3948 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3949 struct vlv_wm_values *wm) 3950 { 3951 enum pipe pipe; 3952 uint32_t tmp; 3953 3954 for_each_pipe(dev_priv, pipe) { 3955 tmp = I915_READ(VLV_DDL(pipe)); 3956 3957 wm->ddl[pipe].primary = 3958 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3959 wm->ddl[pipe].cursor = 3960 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3961 wm->ddl[pipe].sprite[0] = 3962 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3963 wm->ddl[pipe].sprite[1] = 3964 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3965 } 3966 3967 tmp = I915_READ(DSPFW1); 3968 wm->sr.plane = _FW_WM(tmp, SR); 3969 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3970 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3971 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3972 3973 tmp = I915_READ(DSPFW2); 3974 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3975 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3976 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3977 3978 tmp = I915_READ(DSPFW3); 3979 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 3980 3981 if (IS_CHERRYVIEW(dev_priv)) { 3982 tmp = I915_READ(DSPFW7_CHV); 3983 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3984 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3985 3986 tmp = I915_READ(DSPFW8_CHV); 3987 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 3988 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 3989 3990 tmp = I915_READ(DSPFW9_CHV); 3991 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 3992 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 3993 3994 tmp = I915_READ(DSPHOWM); 3995 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3996 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 3997 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 3998 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 3999 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4000 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4001 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4002 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4003 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4004 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4005 } else { 4006 tmp = I915_READ(DSPFW7); 4007 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 4008 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 4009 4010 tmp = I915_READ(DSPHOWM); 4011 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 4012 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4013 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4014 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4015 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4016 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4017 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4018 } 4019 } 4020 4021 #undef _FW_WM 4022 #undef _FW_WM_VLV 4023 4024 void vlv_wm_get_hw_state(struct drm_device *dev) 4025 { 4026 struct drm_i915_private *dev_priv = to_i915(dev); 4027 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 4028 struct intel_plane *plane; 4029 enum pipe pipe; 4030 u32 val; 4031 4032 vlv_read_wm_values(dev_priv, wm); 4033 4034 for_each_intel_plane(dev, plane) { 4035 switch (plane->base.type) { 4036 int sprite; 4037 case DRM_PLANE_TYPE_CURSOR: 4038 plane->wm.fifo_size = 63; 4039 break; 4040 case DRM_PLANE_TYPE_PRIMARY: 4041 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 4042 break; 4043 case DRM_PLANE_TYPE_OVERLAY: 4044 sprite = plane->plane; 4045 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 4046 break; 4047 } 4048 } 4049 4050 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 4051 wm->level = VLV_WM_LEVEL_PM2; 4052 4053 if (IS_CHERRYVIEW(dev_priv)) { 4054 mutex_lock(&dev_priv->rps.hw_lock); 4055 4056 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 4057 if (val & DSP_MAXFIFO_PM5_ENABLE) 4058 wm->level = VLV_WM_LEVEL_PM5; 4059 4060 /* 4061 * If DDR DVFS is disabled in the BIOS, Punit 4062 * will never ack the request. So if that happens 4063 * assume we don't have to enable/disable DDR DVFS 4064 * dynamically. To test that just set the REQ_ACK 4065 * bit to poke the Punit, but don't change the 4066 * HIGH/LOW bits so that we don't actually change 4067 * the current state. 4068 */ 4069 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4070 val |= FORCE_DDR_FREQ_REQ_ACK; 4071 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4072 4073 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4074 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4075 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4076 "assuming DDR DVFS is disabled\n"); 4077 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4078 } else { 4079 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4080 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4081 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4082 } 4083 4084 mutex_unlock(&dev_priv->rps.hw_lock); 4085 } 4086 4087 for_each_pipe(dev_priv, pipe) 4088 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4089 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4090 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4091 4092 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4093 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4094 } 4095 4096 void ilk_wm_get_hw_state(struct drm_device *dev) 4097 { 4098 struct drm_i915_private *dev_priv = dev->dev_private; 4099 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4100 struct drm_crtc *crtc; 4101 4102 for_each_crtc(dev, crtc) 4103 ilk_pipe_wm_get_hw_state(crtc); 4104 4105 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4106 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4107 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4108 4109 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4110 if (INTEL_INFO(dev)->gen >= 7) { 4111 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4112 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4113 } 4114 4115 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4116 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4117 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4118 else if (IS_IVYBRIDGE(dev)) 4119 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4120 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4121 4122 hw->enable_fbc_wm = 4123 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4124 } 4125 4126 /** 4127 * intel_update_watermarks - update FIFO watermark values based on current modes 4128 * 4129 * Calculate watermark values for the various WM regs based on current mode 4130 * and plane configuration. 4131 * 4132 * There are several cases to deal with here: 4133 * - normal (i.e. non-self-refresh) 4134 * - self-refresh (SR) mode 4135 * - lines are large relative to FIFO size (buffer can hold up to 2) 4136 * - lines are small relative to FIFO size (buffer can hold more than 2 4137 * lines), so need to account for TLB latency 4138 * 4139 * The normal calculation is: 4140 * watermark = dotclock * bytes per pixel * latency 4141 * where latency is platform & configuration dependent (we assume pessimal 4142 * values here). 4143 * 4144 * The SR calculation is: 4145 * watermark = (trunc(latency/line time)+1) * surface width * 4146 * bytes per pixel 4147 * where 4148 * line time = htotal / dotclock 4149 * surface width = hdisplay for normal plane and 64 for cursor 4150 * and latency is assumed to be high, as above. 4151 * 4152 * The final value programmed to the register should always be rounded up, 4153 * and include an extra 2 entries to account for clock crossings. 4154 * 4155 * We don't use the sprite, so we can ignore that. And on Crestline we have 4156 * to set the non-SR watermarks to 8. 4157 */ 4158 void intel_update_watermarks(struct drm_crtc *crtc) 4159 { 4160 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4161 4162 if (dev_priv->display.update_wm) 4163 dev_priv->display.update_wm(crtc); 4164 } 4165 4166 void intel_update_sprite_watermarks(struct drm_plane *plane, 4167 struct drm_crtc *crtc, 4168 uint32_t sprite_width, 4169 uint32_t sprite_height, 4170 int pixel_size, 4171 bool enabled, bool scaled) 4172 { 4173 struct drm_i915_private *dev_priv = plane->dev->dev_private; 4174 4175 if (dev_priv->display.update_sprite_wm) 4176 dev_priv->display.update_sprite_wm(plane, crtc, 4177 sprite_width, sprite_height, 4178 pixel_size, enabled, scaled); 4179 } 4180 4181 /** 4182 * Lock protecting IPS related data structures 4183 */ 4184 #ifdef __NetBSD__ 4185 spinlock_t mchdev_lock; 4186 #else 4187 DEFINE_SPINLOCK(mchdev_lock); 4188 #endif 4189 4190 /* Global for IPS driver to get at the current i915 device. Protected by 4191 * mchdev_lock. */ 4192 static struct drm_i915_private *i915_mch_dev; 4193 4194 bool ironlake_set_drps(struct drm_device *dev, u8 val) 4195 { 4196 struct drm_i915_private *dev_priv = dev->dev_private; 4197 u16 rgvswctl; 4198 4199 assert_spin_locked(&mchdev_lock); 4200 4201 rgvswctl = I915_READ16(MEMSWCTL); 4202 if (rgvswctl & MEMCTL_CMD_STS) { 4203 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4204 return false; /* still busy with another command */ 4205 } 4206 4207 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4208 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4209 I915_WRITE16(MEMSWCTL, rgvswctl); 4210 POSTING_READ16(MEMSWCTL); 4211 4212 rgvswctl |= MEMCTL_CMD_STS; 4213 I915_WRITE16(MEMSWCTL, rgvswctl); 4214 4215 return true; 4216 } 4217 4218 static void ironlake_enable_drps(struct drm_device *dev) 4219 { 4220 struct drm_i915_private *dev_priv = dev->dev_private; 4221 u32 rgvmodectl = I915_READ(MEMMODECTL); 4222 u8 fmax, fmin, fstart, vstart; 4223 4224 spin_lock_irq(&mchdev_lock); 4225 4226 /* Enable temp reporting */ 4227 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4228 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4229 4230 /* 100ms RC evaluation intervals */ 4231 I915_WRITE(RCUPEI, 100000); 4232 I915_WRITE(RCDNEI, 100000); 4233 4234 /* Set max/min thresholds to 90ms and 80ms respectively */ 4235 I915_WRITE(RCBMAXAVG, 90000); 4236 I915_WRITE(RCBMINAVG, 80000); 4237 4238 I915_WRITE(MEMIHYST, 1); 4239 4240 /* Set up min, max, and cur for interrupt handling */ 4241 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4242 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4243 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4244 MEMMODE_FSTART_SHIFT; 4245 4246 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> 4247 PXVFREQ_PX_SHIFT; 4248 4249 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4250 dev_priv->ips.fstart = fstart; 4251 4252 dev_priv->ips.max_delay = fstart; 4253 dev_priv->ips.min_delay = fmin; 4254 dev_priv->ips.cur_delay = fstart; 4255 4256 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4257 fmax, fmin, fstart); 4258 4259 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4260 4261 /* 4262 * Interrupts will be enabled in ironlake_irq_postinstall 4263 */ 4264 4265 I915_WRITE(VIDSTART, vstart); 4266 POSTING_READ(VIDSTART); 4267 4268 rgvmodectl |= MEMMODE_SWMODE_EN; 4269 I915_WRITE(MEMMODECTL, rgvmodectl); 4270 4271 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4272 DRM_ERROR("stuck trying to change perf mode\n"); 4273 mdelay(1); 4274 4275 ironlake_set_drps(dev, fstart); 4276 4277 dev_priv->ips.last_count1 = I915_READ(DMIEC) + 4278 I915_READ(DDREC) + I915_READ(CSIEC); 4279 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4280 dev_priv->ips.last_count2 = I915_READ(GFXEC); 4281 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4282 4283 spin_unlock_irq(&mchdev_lock); 4284 } 4285 4286 static void ironlake_disable_drps(struct drm_device *dev) 4287 { 4288 struct drm_i915_private *dev_priv = dev->dev_private; 4289 u16 rgvswctl; 4290 4291 spin_lock_irq(&mchdev_lock); 4292 4293 rgvswctl = I915_READ16(MEMSWCTL); 4294 4295 /* Ack interrupts, disable EFC interrupt */ 4296 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4297 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4298 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4299 I915_WRITE(DEIIR, DE_PCU_EVENT); 4300 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4301 4302 /* Go back to the starting frequency */ 4303 ironlake_set_drps(dev, dev_priv->ips.fstart); 4304 mdelay(1); 4305 rgvswctl |= MEMCTL_CMD_STS; 4306 I915_WRITE(MEMSWCTL, rgvswctl); 4307 mdelay(1); 4308 4309 spin_unlock_irq(&mchdev_lock); 4310 } 4311 4312 /* There's a funny hw issue where the hw returns all 0 when reading from 4313 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4314 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4315 * all limits and the gpu stuck at whatever frequency it is at atm). 4316 */ 4317 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4318 { 4319 u32 limits; 4320 4321 /* Only set the down limit when we've reached the lowest level to avoid 4322 * getting more interrupts, otherwise leave this clear. This prevents a 4323 * race in the hw when coming out of rc6: There's a tiny window where 4324 * the hw runs at the minimal clock before selecting the desired 4325 * frequency, if the down threshold expires in that window we will not 4326 * receive a down interrupt. */ 4327 if (IS_GEN9(dev_priv->dev)) { 4328 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4329 if (val <= dev_priv->rps.min_freq_softlimit) 4330 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4331 } else { 4332 limits = dev_priv->rps.max_freq_softlimit << 24; 4333 if (val <= dev_priv->rps.min_freq_softlimit) 4334 limits |= dev_priv->rps.min_freq_softlimit << 16; 4335 } 4336 4337 return limits; 4338 } 4339 4340 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4341 { 4342 int new_power; 4343 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4344 u32 ei_up = 0, ei_down = 0; 4345 4346 new_power = dev_priv->rps.power; 4347 switch (dev_priv->rps.power) { 4348 case LOW_POWER: 4349 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4350 new_power = BETWEEN; 4351 break; 4352 4353 case BETWEEN: 4354 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4355 new_power = LOW_POWER; 4356 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4357 new_power = HIGH_POWER; 4358 break; 4359 4360 case HIGH_POWER: 4361 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4362 new_power = BETWEEN; 4363 break; 4364 } 4365 /* Max/min bins are special */ 4366 if (val <= dev_priv->rps.min_freq_softlimit) 4367 new_power = LOW_POWER; 4368 if (val >= dev_priv->rps.max_freq_softlimit) 4369 new_power = HIGH_POWER; 4370 if (new_power == dev_priv->rps.power) 4371 return; 4372 4373 /* Note the units here are not exactly 1us, but 1280ns. */ 4374 switch (new_power) { 4375 case LOW_POWER: 4376 /* Upclock if more than 95% busy over 16ms */ 4377 ei_up = 16000; 4378 threshold_up = 95; 4379 4380 /* Downclock if less than 85% busy over 32ms */ 4381 ei_down = 32000; 4382 threshold_down = 85; 4383 break; 4384 4385 case BETWEEN: 4386 /* Upclock if more than 90% busy over 13ms */ 4387 ei_up = 13000; 4388 threshold_up = 90; 4389 4390 /* Downclock if less than 75% busy over 32ms */ 4391 ei_down = 32000; 4392 threshold_down = 75; 4393 break; 4394 4395 case HIGH_POWER: 4396 /* Upclock if more than 85% busy over 10ms */ 4397 ei_up = 10000; 4398 threshold_up = 85; 4399 4400 /* Downclock if less than 60% busy over 32ms */ 4401 ei_down = 32000; 4402 threshold_down = 60; 4403 break; 4404 } 4405 4406 /* When byt can survive without system hang with dynamic 4407 * sw freq adjustments, this restriction can be lifted. 4408 */ 4409 if (IS_VALLEYVIEW(dev_priv)) 4410 goto skip_hw_write; 4411 4412 I915_WRITE(GEN6_RP_UP_EI, 4413 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4414 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4415 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4416 4417 I915_WRITE(GEN6_RP_DOWN_EI, 4418 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4419 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4420 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4421 4422 I915_WRITE(GEN6_RP_CONTROL, 4423 GEN6_RP_MEDIA_TURBO | 4424 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4425 GEN6_RP_MEDIA_IS_GFX | 4426 GEN6_RP_ENABLE | 4427 GEN6_RP_UP_BUSY_AVG | 4428 GEN6_RP_DOWN_IDLE_AVG); 4429 4430 skip_hw_write: 4431 dev_priv->rps.power = new_power; 4432 dev_priv->rps.up_threshold = threshold_up; 4433 dev_priv->rps.down_threshold = threshold_down; 4434 dev_priv->rps.last_adj = 0; 4435 } 4436 4437 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4438 { 4439 u32 mask = 0; 4440 4441 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ 4442 if (val > dev_priv->rps.min_freq_softlimit) 4443 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4444 if (val < dev_priv->rps.max_freq_softlimit) 4445 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4446 4447 mask &= dev_priv->pm_rps_events; 4448 4449 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4450 } 4451 4452 /* gen6_set_rps is called to update the frequency request, but should also be 4453 * called when the range (min_delay and max_delay) is modified so that we can 4454 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4455 static void gen6_set_rps(struct drm_device *dev, u8 val) 4456 { 4457 struct drm_i915_private *dev_priv = dev->dev_private; 4458 4459 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4460 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) 4461 return; 4462 4463 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4464 WARN_ON(val > dev_priv->rps.max_freq); 4465 WARN_ON(val < dev_priv->rps.min_freq); 4466 4467 /* min/max delay may still have been modified so be sure to 4468 * write the limits value. 4469 */ 4470 if (val != dev_priv->rps.cur_freq) { 4471 gen6_set_rps_thresholds(dev_priv, val); 4472 4473 if (IS_GEN9(dev)) 4474 I915_WRITE(GEN6_RPNSWREQ, 4475 GEN9_FREQUENCY(val)); 4476 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4477 I915_WRITE(GEN6_RPNSWREQ, 4478 HSW_FREQUENCY(val)); 4479 else 4480 I915_WRITE(GEN6_RPNSWREQ, 4481 GEN6_FREQUENCY(val) | 4482 GEN6_OFFSET(0) | 4483 GEN6_AGGRESSIVE_TURBO); 4484 } 4485 4486 /* Make sure we continue to get interrupts 4487 * until we hit the minimum or maximum frequencies. 4488 */ 4489 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4490 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4491 4492 POSTING_READ(GEN6_RPNSWREQ); 4493 4494 dev_priv->rps.cur_freq = val; 4495 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4496 } 4497 4498 static void valleyview_set_rps(struct drm_device *dev, u8 val) 4499 { 4500 struct drm_i915_private *dev_priv = dev->dev_private; 4501 4502 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4503 WARN_ON(val > dev_priv->rps.max_freq); 4504 WARN_ON(val < dev_priv->rps.min_freq); 4505 4506 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4507 "Odd GPU freq value\n")) 4508 val &= ~1; 4509 4510 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4511 4512 if (val != dev_priv->rps.cur_freq) { 4513 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4514 if (!IS_CHERRYVIEW(dev_priv)) 4515 gen6_set_rps_thresholds(dev_priv, val); 4516 } 4517 4518 dev_priv->rps.cur_freq = val; 4519 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4520 } 4521 4522 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4523 * 4524 * * If Gfx is Idle, then 4525 * 1. Forcewake Media well. 4526 * 2. Request idle freq. 4527 * 3. Release Forcewake of Media well. 4528 */ 4529 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4530 { 4531 u32 val = dev_priv->rps.idle_freq; 4532 4533 if (dev_priv->rps.cur_freq <= val) 4534 return; 4535 4536 /* Wake up the media well, as that takes a lot less 4537 * power than the Render well. */ 4538 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4539 valleyview_set_rps(dev_priv->dev, val); 4540 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4541 } 4542 4543 void gen6_rps_busy(struct drm_i915_private *dev_priv) 4544 { 4545 mutex_lock(&dev_priv->rps.hw_lock); 4546 if (dev_priv->rps.enabled) { 4547 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) 4548 gen6_rps_reset_ei(dev_priv); 4549 I915_WRITE(GEN6_PMINTRMSK, 4550 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4551 } 4552 mutex_unlock(&dev_priv->rps.hw_lock); 4553 } 4554 4555 void gen6_rps_idle(struct drm_i915_private *dev_priv) 4556 { 4557 struct drm_device *dev = dev_priv->dev; 4558 4559 mutex_lock(&dev_priv->rps.hw_lock); 4560 if (dev_priv->rps.enabled) { 4561 if (IS_VALLEYVIEW(dev)) 4562 vlv_set_rps_idle(dev_priv); 4563 else 4564 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4565 dev_priv->rps.last_adj = 0; 4566 I915_WRITE(GEN6_PMINTRMSK, 4567 gen6_sanitize_rps_pm_mask(dev_priv, ~0)); 4568 } 4569 mutex_unlock(&dev_priv->rps.hw_lock); 4570 4571 spin_lock(&dev_priv->rps.client_lock); 4572 while (!list_empty(&dev_priv->rps.clients)) 4573 list_del_init(dev_priv->rps.clients.next); 4574 spin_unlock(&dev_priv->rps.client_lock); 4575 } 4576 4577 void gen6_rps_boost(struct drm_i915_private *dev_priv, 4578 struct intel_rps_client *rps, 4579 unsigned long submitted) 4580 { 4581 /* This is intentionally racy! We peek at the state here, then 4582 * validate inside the RPS worker. 4583 */ 4584 if (!(dev_priv->mm.busy && 4585 dev_priv->rps.enabled && 4586 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4587 return; 4588 4589 /* Force a RPS boost (and don't count it against the client) if 4590 * the GPU is severely congested. 4591 */ 4592 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4593 rps = NULL; 4594 4595 spin_lock(&dev_priv->rps.client_lock); 4596 if (rps == NULL || list_empty(&rps->link)) { 4597 spin_lock_irq(&dev_priv->irq_lock); 4598 if (dev_priv->rps.interrupts_enabled) { 4599 dev_priv->rps.client_boost = true; 4600 queue_work(dev_priv->wq, &dev_priv->rps.work); 4601 } 4602 spin_unlock_irq(&dev_priv->irq_lock); 4603 4604 if (rps != NULL) { 4605 list_add(&rps->link, &dev_priv->rps.clients); 4606 rps->boosts++; 4607 } else 4608 dev_priv->rps.boosts++; 4609 } 4610 spin_unlock(&dev_priv->rps.client_lock); 4611 } 4612 4613 void intel_set_rps(struct drm_device *dev, u8 val) 4614 { 4615 if (IS_VALLEYVIEW(dev)) 4616 valleyview_set_rps(dev, val); 4617 else 4618 gen6_set_rps(dev, val); 4619 } 4620 4621 static void gen9_disable_rc6(struct drm_device *dev) 4622 { 4623 struct drm_i915_private *dev_priv = dev->dev_private; 4624 4625 I915_WRITE(GEN6_RC_CONTROL, 0); 4626 } 4627 4628 static void gen9_disable_rps(struct drm_device *dev) 4629 { 4630 struct drm_i915_private *dev_priv = dev->dev_private; 4631 4632 I915_WRITE(GEN9_PG_ENABLE, 0); 4633 } 4634 4635 static void gen6_disable_rc6(struct drm_device *dev) 4636 { 4637 struct drm_i915_private *dev_priv = dev->dev_private; 4638 4639 I915_WRITE(GEN6_RC_CONTROL, 0); 4640 } 4641 4642 static void gen6_disable_rps(struct drm_device *dev) 4643 { 4644 struct drm_i915_private *dev_priv = dev->dev_private; 4645 4646 I915_WRITE(GEN6_RPNSWREQ, 1UL << 31); 4647 } 4648 4649 static void cherryview_disable_rc6(struct drm_device *dev) 4650 { 4651 struct drm_i915_private *dev_priv = dev->dev_private; 4652 4653 I915_WRITE(GEN6_RC_CONTROL, 0); 4654 } 4655 4656 static void valleyview_disable_rc6(struct drm_device *dev) 4657 { 4658 struct drm_i915_private *dev_priv = dev->dev_private; 4659 4660 /* we're doing forcewake before Disabling RC6, 4661 * This what the BIOS expects when going into suspend */ 4662 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4663 4664 I915_WRITE(GEN6_RC_CONTROL, 0); 4665 4666 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4667 } 4668 4669 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4670 { 4671 if (IS_VALLEYVIEW(dev)) { 4672 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4673 mode = GEN6_RC_CTL_RC6_ENABLE; 4674 else 4675 mode = 0; 4676 } 4677 if (HAS_RC6p(dev)) 4678 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4679 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 4680 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 4681 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 4682 4683 else 4684 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4685 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 4686 } 4687 4688 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4689 { 4690 /* No RC6 before Ironlake and code is gone for ilk. */ 4691 if (INTEL_INFO(dev)->gen < 6) 4692 return 0; 4693 4694 /* Respect the kernel parameter if it is set */ 4695 if (enable_rc6 >= 0) { 4696 int mask; 4697 4698 if (HAS_RC6p(dev)) 4699 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4700 INTEL_RC6pp_ENABLE; 4701 else 4702 mask = INTEL_RC6_ENABLE; 4703 4704 if ((enable_rc6 & mask) != enable_rc6) 4705 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4706 enable_rc6 & mask, enable_rc6, mask); 4707 4708 return enable_rc6 & mask; 4709 } 4710 4711 if (IS_IVYBRIDGE(dev)) 4712 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4713 4714 return INTEL_RC6_ENABLE; 4715 } 4716 4717 int intel_enable_rc6(const struct drm_device *dev) 4718 { 4719 return i915.enable_rc6; 4720 } 4721 4722 static void gen6_init_rps_frequencies(struct drm_device *dev) 4723 { 4724 struct drm_i915_private *dev_priv = dev->dev_private; 4725 uint32_t rp_state_cap; 4726 u32 ddcc_status = 0; 4727 int ret; 4728 4729 /* All of these values are in units of 50MHz */ 4730 dev_priv->rps.cur_freq = 0; 4731 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4732 if (IS_BROXTON(dev)) { 4733 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4734 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4735 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4736 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4737 } else { 4738 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4739 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4740 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4741 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4742 } 4743 4744 /* hw_max = RP0 until we check for overclocking */ 4745 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4746 4747 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4748 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || 4749 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4750 ret = sandybridge_pcode_read(dev_priv, 4751 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4752 &ddcc_status); 4753 if (0 == ret) 4754 dev_priv->rps.efficient_freq = 4755 clamp_t(u8, 4756 ((ddcc_status >> 8) & 0xff), 4757 dev_priv->rps.min_freq, 4758 dev_priv->rps.max_freq); 4759 } 4760 4761 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4762 /* Store the frequency values in 16.66 MHZ units, which is 4763 the natural hardware unit for SKL */ 4764 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4765 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4766 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4767 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4768 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4769 } 4770 4771 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4772 4773 /* Preserve min/max settings in case of re-init */ 4774 if (dev_priv->rps.max_freq_softlimit == 0) 4775 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4776 4777 if (dev_priv->rps.min_freq_softlimit == 0) { 4778 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4779 dev_priv->rps.min_freq_softlimit = 4780 max_t(int, dev_priv->rps.efficient_freq, 4781 intel_freq_opcode(dev_priv, 450)); 4782 else 4783 dev_priv->rps.min_freq_softlimit = 4784 dev_priv->rps.min_freq; 4785 } 4786 } 4787 4788 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4789 static void gen9_enable_rps(struct drm_device *dev) 4790 { 4791 struct drm_i915_private *dev_priv = dev->dev_private; 4792 4793 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4794 4795 gen6_init_rps_frequencies(dev); 4796 4797 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4798 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { 4799 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4800 return; 4801 } 4802 4803 /* Program defaults and thresholds for RPS*/ 4804 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4805 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4806 4807 /* 1 second timeout*/ 4808 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4809 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4810 4811 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4812 4813 /* Leaning on the below call to gen6_set_rps to program/setup the 4814 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4815 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4816 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4817 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4818 4819 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4820 } 4821 4822 static void gen9_enable_rc6(struct drm_device *dev) 4823 { 4824 struct drm_i915_private *dev_priv = dev->dev_private; 4825 struct intel_engine_cs *ring; 4826 uint32_t rc6_mask = 0; 4827 int unused; 4828 4829 /* 1a: Software RC state - RC0 */ 4830 I915_WRITE(GEN6_RC_STATE, 0); 4831 4832 /* 1b: Get forcewake during program sequence. Although the driver 4833 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4834 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4835 4836 /* 2a: Disable RC states. */ 4837 I915_WRITE(GEN6_RC_CONTROL, 0); 4838 4839 /* 2b: Program RC6 thresholds.*/ 4840 4841 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4842 if (IS_SKYLAKE(dev)) 4843 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4844 else 4845 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4846 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4847 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4848 for_each_ring(ring, dev_priv, unused) 4849 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4850 4851 if (HAS_GUC_UCODE(dev)) 4852 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); 4853 4854 I915_WRITE(GEN6_RC_SLEEP, 0); 4855 4856 /* 2c: Program Coarse Power Gating Policies. */ 4857 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4858 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4859 4860 /* 3a: Enable RC6 */ 4861 if (!dev_priv->rps.ctx_corrupted && 4862 intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4863 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4864 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4865 "on" : "off"); 4866 /* WaRsUseTimeoutMode */ 4867 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || 4868 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { 4869 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ 4870 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4871 GEN7_RC_CTL_TO_MODE | 4872 rc6_mask); 4873 } else { 4874 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4875 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4876 GEN6_RC_CTL_EI_MODE(1) | 4877 rc6_mask); 4878 } 4879 4880 /* 4881 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4882 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4883 */ 4884 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || 4885 INTEL_INFO(dev)->gen == 9) 4886 I915_WRITE(GEN9_PG_ENABLE, 0); 4887 else 4888 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4889 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); 4890 4891 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4892 4893 } 4894 4895 static void gen8_enable_rps(struct drm_device *dev) 4896 { 4897 struct drm_i915_private *dev_priv = dev->dev_private; 4898 struct intel_engine_cs *ring; 4899 uint32_t rc6_mask = 0; 4900 int unused; 4901 4902 /* 1a: Software RC state - RC0 */ 4903 I915_WRITE(GEN6_RC_STATE, 0); 4904 4905 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4906 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4907 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4908 4909 /* 2a: Disable RC states. */ 4910 I915_WRITE(GEN6_RC_CONTROL, 0); 4911 4912 /* Initialize rps frequencies */ 4913 gen6_init_rps_frequencies(dev); 4914 4915 /* 2b: Program RC6 thresholds.*/ 4916 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4917 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4918 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4919 for_each_ring(ring, dev_priv, unused) 4920 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4921 I915_WRITE(GEN6_RC_SLEEP, 0); 4922 if (IS_BROADWELL(dev)) 4923 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4924 else 4925 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4926 4927 /* 3: Enable RC6 */ 4928 if (!dev_priv->rps.ctx_corrupted && 4929 intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4930 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4931 intel_print_rc6_info(dev, rc6_mask); 4932 if (IS_BROADWELL(dev)) 4933 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4934 GEN7_RC_CTL_TO_MODE | 4935 rc6_mask); 4936 else 4937 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4938 GEN6_RC_CTL_EI_MODE(1) | 4939 rc6_mask); 4940 4941 /* 4 Program defaults and thresholds for RPS*/ 4942 I915_WRITE(GEN6_RPNSWREQ, 4943 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4944 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4945 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4946 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4947 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4948 4949 /* Docs recommend 900MHz, and 300 MHz respectively */ 4950 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4951 dev_priv->rps.max_freq_softlimit << 24 | 4952 dev_priv->rps.min_freq_softlimit << 16); 4953 4954 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4955 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4956 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4957 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4958 4959 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4960 4961 /* 5: Enable RPS */ 4962 I915_WRITE(GEN6_RP_CONTROL, 4963 GEN6_RP_MEDIA_TURBO | 4964 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4965 GEN6_RP_MEDIA_IS_GFX | 4966 GEN6_RP_ENABLE | 4967 GEN6_RP_UP_BUSY_AVG | 4968 GEN6_RP_DOWN_IDLE_AVG); 4969 4970 /* 6: Ring frequency + overclocking (our driver does this later */ 4971 4972 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4973 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4974 4975 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4976 } 4977 4978 static void gen6_enable_rps(struct drm_device *dev) 4979 { 4980 struct drm_i915_private *dev_priv = dev->dev_private; 4981 struct intel_engine_cs *ring; 4982 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4983 u32 gtfifodbg; 4984 int rc6_mode; 4985 int i, ret; 4986 4987 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4988 4989 /* Here begins a magic sequence of register writes to enable 4990 * auto-downclocking. 4991 * 4992 * Perhaps there might be some value in exposing these to 4993 * userspace... 4994 */ 4995 I915_WRITE(GEN6_RC_STATE, 0); 4996 4997 /* Clear the DBG now so we don't confuse earlier errors */ 4998 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 4999 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 5000 I915_WRITE(GTFIFODBG, gtfifodbg); 5001 } 5002 5003 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5004 5005 /* Initialize rps frequencies */ 5006 gen6_init_rps_frequencies(dev); 5007 5008 /* disable the counters and set deterministic thresholds */ 5009 I915_WRITE(GEN6_RC_CONTROL, 0); 5010 5011 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 5012 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 5013 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 5014 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5015 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5016 5017 for_each_ring(ring, dev_priv, i) 5018 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5019 5020 I915_WRITE(GEN6_RC_SLEEP, 0); 5021 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 5022 if (IS_IVYBRIDGE(dev)) 5023 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 5024 else 5025 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 5026 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 5027 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 5028 5029 /* Check if we are enabling RC6 */ 5030 rc6_mode = intel_enable_rc6(dev_priv->dev); 5031 if (rc6_mode & INTEL_RC6_ENABLE) 5032 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 5033 5034 /* We don't use those on Haswell */ 5035 if (!IS_HASWELL(dev)) { 5036 if (rc6_mode & INTEL_RC6p_ENABLE) 5037 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 5038 5039 if (rc6_mode & INTEL_RC6pp_ENABLE) 5040 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 5041 } 5042 5043 intel_print_rc6_info(dev, rc6_mask); 5044 5045 I915_WRITE(GEN6_RC_CONTROL, 5046 rc6_mask | 5047 GEN6_RC_CTL_EI_MODE(1) | 5048 GEN6_RC_CTL_HW_ENABLE); 5049 5050 /* Power down if completely idle for over 50ms */ 5051 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 5052 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5053 5054 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 5055 if (ret) 5056 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5057 5058 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5059 if (!ret && (pcu_mbox & __BIT(31))) { /* OC supported */ 5060 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5061 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5062 (pcu_mbox & 0xff) * 50); 5063 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5064 } 5065 5066 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5067 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5068 5069 rc6vids = 0; 5070 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5071 if (IS_GEN6(dev) && ret) { 5072 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5073 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5074 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5075 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5076 rc6vids &= 0xffff00; 5077 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5078 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5079 if (ret) 5080 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5081 } 5082 5083 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5084 } 5085 5086 static void __gen6_update_ring_freq(struct drm_device *dev) 5087 { 5088 struct drm_i915_private *dev_priv = dev->dev_private; 5089 int min_freq = 15; 5090 unsigned int gpu_freq; 5091 unsigned int max_ia_freq, min_ring_freq; 5092 unsigned int max_gpu_freq, min_gpu_freq; 5093 int scaling_factor = 180; 5094 #ifndef __NetBSD__ 5095 struct cpufreq_policy *policy; 5096 #endif 5097 5098 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5099 5100 #ifdef __NetBSD__ 5101 { 5102 extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */ 5103 max_ia_freq = (tsc_freq / 1000); 5104 } 5105 #else 5106 policy = cpufreq_cpu_get(0); 5107 if (policy) { 5108 max_ia_freq = policy->cpuinfo.max_freq; 5109 cpufreq_cpu_put(policy); 5110 } else { 5111 /* 5112 * Default to measured freq if none found, PCU will ensure we 5113 * don't go over 5114 */ 5115 max_ia_freq = tsc_khz; 5116 } 5117 #endif 5118 5119 /* Convert from kHz to MHz */ 5120 max_ia_freq /= 1000; 5121 5122 min_ring_freq = I915_READ(DCLK) & 0xf; 5123 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5124 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5125 5126 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5127 /* Convert GT frequency to 50 HZ units */ 5128 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5129 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5130 } else { 5131 min_gpu_freq = dev_priv->rps.min_freq; 5132 max_gpu_freq = dev_priv->rps.max_freq; 5133 } 5134 5135 /* 5136 * For each potential GPU frequency, load a ring frequency we'd like 5137 * to use for memory access. We do this by specifying the IA frequency 5138 * the PCU should use as a reference to determine the ring frequency. 5139 */ 5140 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5141 int diff = max_gpu_freq - gpu_freq; 5142 unsigned int ia_freq = 0, ring_freq = 0; 5143 5144 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5145 /* 5146 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5147 * No floor required for ring frequency on SKL. 5148 */ 5149 ring_freq = gpu_freq; 5150 } else if (INTEL_INFO(dev)->gen >= 8) { 5151 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5152 ring_freq = max(min_ring_freq, gpu_freq); 5153 } else if (IS_HASWELL(dev)) { 5154 ring_freq = mult_frac(gpu_freq, 5, 4); 5155 ring_freq = max(min_ring_freq, ring_freq); 5156 /* leave ia_freq as the default, chosen by cpufreq */ 5157 } else { 5158 /* On older processors, there is no separate ring 5159 * clock domain, so in order to boost the bandwidth 5160 * of the ring, we need to upclock the CPU (ia_freq). 5161 * 5162 * For GPU frequencies less than 750MHz, 5163 * just use the lowest ring freq. 5164 */ 5165 if (gpu_freq < min_freq) 5166 ia_freq = 800; 5167 else 5168 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5169 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5170 } 5171 5172 sandybridge_pcode_write(dev_priv, 5173 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5174 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5175 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5176 gpu_freq); 5177 } 5178 } 5179 5180 void gen6_update_ring_freq(struct drm_device *dev) 5181 { 5182 struct drm_i915_private *dev_priv = dev->dev_private; 5183 5184 if (!HAS_CORE_RING_FREQ(dev)) 5185 return; 5186 5187 mutex_lock(&dev_priv->rps.hw_lock); 5188 __gen6_update_ring_freq(dev); 5189 mutex_unlock(&dev_priv->rps.hw_lock); 5190 } 5191 5192 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5193 { 5194 struct drm_device *dev = dev_priv->dev; 5195 u32 val, rp0; 5196 5197 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5198 5199 switch (INTEL_INFO(dev)->eu_total) { 5200 case 8: 5201 /* (2 * 4) config */ 5202 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5203 break; 5204 case 12: 5205 /* (2 * 6) config */ 5206 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5207 break; 5208 case 16: 5209 /* (2 * 8) config */ 5210 default: 5211 /* Setting (2 * 8) Min RP0 for any other combination */ 5212 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5213 break; 5214 } 5215 5216 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5217 5218 return rp0; 5219 } 5220 5221 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5222 { 5223 u32 val, rpe; 5224 5225 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5226 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5227 5228 return rpe; 5229 } 5230 5231 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5232 { 5233 u32 val, rp1; 5234 5235 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5236 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5237 5238 return rp1; 5239 } 5240 5241 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5242 { 5243 u32 val, rp1; 5244 5245 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5246 5247 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5248 5249 return rp1; 5250 } 5251 5252 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5253 { 5254 u32 val, rp0; 5255 5256 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5257 5258 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5259 /* Clamp to max */ 5260 rp0 = min_t(u32, rp0, 0xea); 5261 5262 return rp0; 5263 } 5264 5265 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5266 { 5267 u32 val, rpe; 5268 5269 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5270 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5271 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5272 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5273 5274 return rpe; 5275 } 5276 5277 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5278 { 5279 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5280 } 5281 5282 /* Check that the pctx buffer wasn't move under us. */ 5283 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5284 { 5285 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5286 5287 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5288 dev_priv->vlv_pctx->stolen->start); 5289 } 5290 5291 5292 /* Check that the pcbr address is not empty. */ 5293 static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5294 { 5295 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5296 5297 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5298 } 5299 5300 static void cherryview_setup_pctx(struct drm_device *dev) 5301 { 5302 struct drm_i915_private *dev_priv = dev->dev_private; 5303 unsigned long pctx_paddr, paddr; 5304 struct i915_gtt *gtt = &dev_priv->gtt; 5305 u32 pcbr; 5306 int pctx_size = 32*1024; 5307 5308 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5309 5310 pcbr = I915_READ(VLV_PCBR); 5311 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5312 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5313 paddr = (dev_priv->mm.stolen_base + 5314 (gtt->stolen_size - pctx_size)); 5315 5316 pctx_paddr = (paddr & (~4095)); 5317 I915_WRITE(VLV_PCBR, pctx_paddr); 5318 } 5319 5320 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5321 } 5322 5323 static void valleyview_setup_pctx(struct drm_device *dev) 5324 { 5325 struct drm_i915_private *dev_priv = dev->dev_private; 5326 struct drm_i915_gem_object *pctx; 5327 unsigned long pctx_paddr; 5328 u32 pcbr; 5329 int pctx_size = 24*1024; 5330 5331 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5332 5333 pcbr = I915_READ(VLV_PCBR); 5334 if (pcbr) { 5335 /* BIOS set it up already, grab the pre-alloc'd space */ 5336 int pcbr_offset; 5337 5338 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5339 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5340 pcbr_offset, 5341 I915_GTT_OFFSET_NONE, 5342 pctx_size); 5343 goto out; 5344 } 5345 5346 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5347 5348 /* 5349 * From the Gunit register HAS: 5350 * The Gfx driver is expected to program this register and ensure 5351 * proper allocation within Gfx stolen memory. For example, this 5352 * register should be programmed such than the PCBR range does not 5353 * overlap with other ranges, such as the frame buffer, protected 5354 * memory, or any other relevant ranges. 5355 */ 5356 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5357 if (!pctx) { 5358 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5359 return; 5360 } 5361 5362 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5363 I915_WRITE(VLV_PCBR, pctx_paddr); 5364 5365 out: 5366 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5367 dev_priv->vlv_pctx = pctx; 5368 } 5369 5370 static void valleyview_cleanup_pctx(struct drm_device *dev) 5371 { 5372 struct drm_i915_private *dev_priv = dev->dev_private; 5373 5374 if (WARN_ON(!dev_priv->vlv_pctx)) 5375 return; 5376 5377 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 5378 dev_priv->vlv_pctx = NULL; 5379 } 5380 5381 static void valleyview_init_gt_powersave(struct drm_device *dev) 5382 { 5383 struct drm_i915_private *dev_priv = dev->dev_private; 5384 u32 val; 5385 5386 valleyview_setup_pctx(dev); 5387 5388 mutex_lock(&dev_priv->rps.hw_lock); 5389 5390 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5391 switch ((val >> 6) & 3) { 5392 case 0: 5393 case 1: 5394 dev_priv->mem_freq = 800; 5395 break; 5396 case 2: 5397 dev_priv->mem_freq = 1066; 5398 break; 5399 case 3: 5400 dev_priv->mem_freq = 1333; 5401 break; 5402 } 5403 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5404 5405 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5406 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5407 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5408 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5409 dev_priv->rps.max_freq); 5410 5411 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5412 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5413 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5414 dev_priv->rps.efficient_freq); 5415 5416 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5417 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5418 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5419 dev_priv->rps.rp1_freq); 5420 5421 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5422 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5423 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5424 dev_priv->rps.min_freq); 5425 5426 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5427 5428 /* Preserve min/max settings in case of re-init */ 5429 if (dev_priv->rps.max_freq_softlimit == 0) 5430 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5431 5432 if (dev_priv->rps.min_freq_softlimit == 0) 5433 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5434 5435 mutex_unlock(&dev_priv->rps.hw_lock); 5436 } 5437 5438 static void cherryview_init_gt_powersave(struct drm_device *dev) 5439 { 5440 struct drm_i915_private *dev_priv = dev->dev_private; 5441 u32 val; 5442 5443 cherryview_setup_pctx(dev); 5444 5445 mutex_lock(&dev_priv->rps.hw_lock); 5446 5447 mutex_lock(&dev_priv->sb_lock); 5448 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5449 mutex_unlock(&dev_priv->sb_lock); 5450 5451 switch ((val >> 2) & 0x7) { 5452 case 3: 5453 dev_priv->mem_freq = 2000; 5454 break; 5455 default: 5456 dev_priv->mem_freq = 1600; 5457 break; 5458 } 5459 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5460 5461 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5462 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5463 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5464 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5465 dev_priv->rps.max_freq); 5466 5467 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5468 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5469 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5470 dev_priv->rps.efficient_freq); 5471 5472 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5473 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5474 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5475 dev_priv->rps.rp1_freq); 5476 5477 /* PUnit validated range is only [RPe, RP0] */ 5478 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5479 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5480 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5481 dev_priv->rps.min_freq); 5482 5483 WARN_ONCE((dev_priv->rps.max_freq | 5484 dev_priv->rps.efficient_freq | 5485 dev_priv->rps.rp1_freq | 5486 dev_priv->rps.min_freq) & 1, 5487 "Odd GPU freq values\n"); 5488 5489 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5490 5491 /* Preserve min/max settings in case of re-init */ 5492 if (dev_priv->rps.max_freq_softlimit == 0) 5493 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5494 5495 if (dev_priv->rps.min_freq_softlimit == 0) 5496 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5497 5498 mutex_unlock(&dev_priv->rps.hw_lock); 5499 } 5500 5501 static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5502 { 5503 valleyview_cleanup_pctx(dev); 5504 } 5505 5506 static void cherryview_enable_rps(struct drm_device *dev) 5507 { 5508 struct drm_i915_private *dev_priv = dev->dev_private; 5509 struct intel_engine_cs *ring; 5510 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5511 int i; 5512 5513 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5514 5515 gtfifodbg = I915_READ(GTFIFODBG); 5516 if (gtfifodbg) { 5517 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5518 gtfifodbg); 5519 I915_WRITE(GTFIFODBG, gtfifodbg); 5520 } 5521 5522 cherryview_check_pctx(dev_priv); 5523 5524 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5525 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5526 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5527 5528 /* Disable RC states. */ 5529 I915_WRITE(GEN6_RC_CONTROL, 0); 5530 5531 /* 2a: Program RC6 thresholds.*/ 5532 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5533 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5534 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5535 5536 for_each_ring(ring, dev_priv, i) 5537 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5538 I915_WRITE(GEN6_RC_SLEEP, 0); 5539 5540 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5541 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5542 5543 /* allows RC6 residency counter to work */ 5544 I915_WRITE(VLV_COUNTER_CONTROL, 5545 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5546 VLV_MEDIA_RC6_COUNT_EN | 5547 VLV_RENDER_RC6_COUNT_EN)); 5548 5549 /* For now we assume BIOS is allocating and populating the PCBR */ 5550 pcbr = I915_READ(VLV_PCBR); 5551 5552 /* 3: Enable RC6 */ 5553 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5554 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5555 rc6_mode = GEN7_RC_CTL_TO_MODE; 5556 5557 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5558 5559 /* 4 Program defaults and thresholds for RPS*/ 5560 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5561 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5562 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5563 I915_WRITE(GEN6_RP_UP_EI, 66000); 5564 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5565 5566 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5567 5568 /* 5: Enable RPS */ 5569 I915_WRITE(GEN6_RP_CONTROL, 5570 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5571 GEN6_RP_MEDIA_IS_GFX | 5572 GEN6_RP_ENABLE | 5573 GEN6_RP_UP_BUSY_AVG | 5574 GEN6_RP_DOWN_IDLE_AVG); 5575 5576 /* Setting Fixed Bias */ 5577 val = VLV_OVERRIDE_EN | 5578 VLV_SOC_TDP_EN | 5579 CHV_BIAS_CPU_50_SOC_50; 5580 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5581 5582 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5583 5584 /* RPS code assumes GPLL is used */ 5585 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5586 5587 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5588 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5589 5590 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5591 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5592 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5593 dev_priv->rps.cur_freq); 5594 5595 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5596 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5597 dev_priv->rps.efficient_freq); 5598 5599 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5600 5601 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5602 } 5603 5604 static void valleyview_enable_rps(struct drm_device *dev) 5605 { 5606 struct drm_i915_private *dev_priv = dev->dev_private; 5607 struct intel_engine_cs *ring; 5608 u32 gtfifodbg, val, rc6_mode = 0; 5609 int i; 5610 5611 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5612 5613 valleyview_check_pctx(dev_priv); 5614 5615 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5616 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5617 gtfifodbg); 5618 I915_WRITE(GTFIFODBG, gtfifodbg); 5619 } 5620 5621 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5622 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5623 5624 /* Disable RC states. */ 5625 I915_WRITE(GEN6_RC_CONTROL, 0); 5626 5627 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5628 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5629 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5630 I915_WRITE(GEN6_RP_UP_EI, 66000); 5631 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5632 5633 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5634 5635 I915_WRITE(GEN6_RP_CONTROL, 5636 GEN6_RP_MEDIA_TURBO | 5637 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5638 GEN6_RP_MEDIA_IS_GFX | 5639 GEN6_RP_ENABLE | 5640 GEN6_RP_UP_BUSY_AVG | 5641 GEN6_RP_DOWN_IDLE_CONT); 5642 5643 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5644 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5645 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5646 5647 for_each_ring(ring, dev_priv, i) 5648 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5649 5650 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5651 5652 /* allows RC6 residency counter to work */ 5653 I915_WRITE(VLV_COUNTER_CONTROL, 5654 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5655 VLV_RENDER_RC0_COUNT_EN | 5656 VLV_MEDIA_RC6_COUNT_EN | 5657 VLV_RENDER_RC6_COUNT_EN)); 5658 5659 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5660 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5661 5662 intel_print_rc6_info(dev, rc6_mode); 5663 5664 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5665 5666 /* Setting Fixed Bias */ 5667 val = VLV_OVERRIDE_EN | 5668 VLV_SOC_TDP_EN | 5669 VLV_BIAS_CPU_125_SOC_875; 5670 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5671 5672 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5673 5674 /* RPS code assumes GPLL is used */ 5675 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5676 5677 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5678 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5679 5680 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5681 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5682 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5683 dev_priv->rps.cur_freq); 5684 5685 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5686 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5687 dev_priv->rps.efficient_freq); 5688 5689 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5690 5691 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5692 } 5693 5694 static unsigned long intel_pxfreq(u32 vidfreq) 5695 { 5696 unsigned long freq; 5697 int div = (vidfreq & 0x3f0000) >> 16; 5698 int post = (vidfreq & 0x3000) >> 12; 5699 int pre = (vidfreq & 0x7); 5700 5701 if (!pre) 5702 return 0; 5703 5704 freq = ((div * 133333) / ((1<<post) * pre)); 5705 5706 return freq; 5707 } 5708 5709 static const struct cparams { 5710 u16 i; 5711 u16 t; 5712 u16 m; 5713 u16 c; 5714 } cparams[] = { 5715 { 1, 1333, 301, 28664 }, 5716 { 1, 1066, 294, 24460 }, 5717 { 1, 800, 294, 25192 }, 5718 { 0, 1333, 276, 27605 }, 5719 { 0, 1066, 276, 27605 }, 5720 { 0, 800, 231, 23784 }, 5721 }; 5722 5723 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5724 { 5725 u64 total_count, diff, ret; 5726 u32 count1, count2, count3, m = 0, c = 0; 5727 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5728 int i; 5729 5730 assert_spin_locked(&mchdev_lock); 5731 5732 diff1 = now - dev_priv->ips.last_time1; 5733 5734 /* Prevent division-by-zero if we are asking too fast. 5735 * Also, we don't get interesting results if we are polling 5736 * faster than once in 10ms, so just return the saved value 5737 * in such cases. 5738 */ 5739 if (diff1 <= 10) 5740 return dev_priv->ips.chipset_power; 5741 5742 count1 = I915_READ(DMIEC); 5743 count2 = I915_READ(DDREC); 5744 count3 = I915_READ(CSIEC); 5745 5746 total_count = count1 + count2 + count3; 5747 5748 /* FIXME: handle per-counter overflow */ 5749 if (total_count < dev_priv->ips.last_count1) { 5750 diff = ~0UL - dev_priv->ips.last_count1; 5751 diff += total_count; 5752 } else { 5753 diff = total_count - dev_priv->ips.last_count1; 5754 } 5755 5756 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5757 if (cparams[i].i == dev_priv->ips.c_m && 5758 cparams[i].t == dev_priv->ips.r_t) { 5759 m = cparams[i].m; 5760 c = cparams[i].c; 5761 break; 5762 } 5763 } 5764 5765 diff = div_u64(diff, diff1); 5766 ret = ((m * diff) + c); 5767 ret = div_u64(ret, 10); 5768 5769 dev_priv->ips.last_count1 = total_count; 5770 dev_priv->ips.last_time1 = now; 5771 5772 dev_priv->ips.chipset_power = ret; 5773 5774 return ret; 5775 } 5776 5777 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5778 { 5779 struct drm_device *dev = dev_priv->dev; 5780 unsigned long val; 5781 5782 if (INTEL_INFO(dev)->gen != 5) 5783 return 0; 5784 5785 spin_lock_irq(&mchdev_lock); 5786 5787 val = __i915_chipset_val(dev_priv); 5788 5789 spin_unlock_irq(&mchdev_lock); 5790 5791 return val; 5792 } 5793 5794 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5795 { 5796 unsigned long m, x, b; 5797 u32 tsfs; 5798 5799 tsfs = I915_READ(TSFS); 5800 5801 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5802 x = I915_READ8(TR1); 5803 5804 b = tsfs & TSFS_INTR_MASK; 5805 5806 return ((m * x) / 127) - b; 5807 } 5808 5809 static int _pxvid_to_vd(u8 pxvid) 5810 { 5811 if (pxvid == 0) 5812 return 0; 5813 5814 if (pxvid >= 8 && pxvid < 31) 5815 pxvid = 31; 5816 5817 return (pxvid + 2) * 125; 5818 } 5819 5820 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5821 { 5822 struct drm_device *dev = dev_priv->dev; 5823 const int vd = _pxvid_to_vd(pxvid); 5824 const int vm = vd - 1125; 5825 5826 if (INTEL_INFO(dev)->is_mobile) 5827 return vm > 0 ? vm : 0; 5828 5829 return vd; 5830 } 5831 5832 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5833 { 5834 u64 now, diff, diffms; 5835 u32 count; 5836 5837 assert_spin_locked(&mchdev_lock); 5838 5839 now = ktime_get_raw_ns(); 5840 diffms = now - dev_priv->ips.last_time2; 5841 do_div(diffms, NSEC_PER_MSEC); 5842 5843 /* Don't divide by 0 */ 5844 if (!diffms) 5845 return; 5846 5847 count = I915_READ(GFXEC); 5848 5849 if (count < dev_priv->ips.last_count2) { 5850 diff = ~0UL - dev_priv->ips.last_count2; 5851 diff += count; 5852 } else { 5853 diff = count - dev_priv->ips.last_count2; 5854 } 5855 5856 dev_priv->ips.last_count2 = count; 5857 dev_priv->ips.last_time2 = now; 5858 5859 /* More magic constants... */ 5860 diff = diff * 1181; 5861 diff = div_u64(diff, diffms * 10); 5862 dev_priv->ips.gfx_power = diff; 5863 } 5864 5865 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5866 { 5867 struct drm_device *dev = dev_priv->dev; 5868 5869 if (INTEL_INFO(dev)->gen != 5) 5870 return; 5871 5872 spin_lock_irq(&mchdev_lock); 5873 5874 __i915_update_gfx_val(dev_priv); 5875 5876 spin_unlock_irq(&mchdev_lock); 5877 } 5878 5879 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5880 { 5881 unsigned long t, corr, state1, corr2, state2; 5882 u32 pxvid, ext_v; 5883 5884 assert_spin_locked(&mchdev_lock); 5885 5886 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); 5887 pxvid = (pxvid >> 24) & 0x7f; 5888 ext_v = pvid_to_extvid(dev_priv, pxvid); 5889 5890 state1 = ext_v; 5891 5892 t = i915_mch_val(dev_priv); 5893 5894 /* Revel in the empirically derived constants */ 5895 5896 /* Correction factor in 1/100000 units */ 5897 if (t > 80) 5898 corr = ((t * 2349) + 135940); 5899 else if (t >= 50) 5900 corr = ((t * 964) + 29317); 5901 else /* < 50 */ 5902 corr = ((t * 301) + 1004); 5903 5904 corr = corr * ((150142 * state1) / 10000 - 78642); 5905 corr /= 100000; 5906 corr2 = (corr * dev_priv->ips.corr); 5907 5908 state2 = (corr2 * state1) / 10000; 5909 state2 /= 100; /* convert to mW */ 5910 5911 __i915_update_gfx_val(dev_priv); 5912 5913 return dev_priv->ips.gfx_power + state2; 5914 } 5915 5916 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5917 { 5918 struct drm_device *dev = dev_priv->dev; 5919 unsigned long val; 5920 5921 if (INTEL_INFO(dev)->gen != 5) 5922 return 0; 5923 5924 spin_lock_irq(&mchdev_lock); 5925 5926 val = __i915_gfx_val(dev_priv); 5927 5928 spin_unlock_irq(&mchdev_lock); 5929 5930 return val; 5931 } 5932 5933 /** 5934 * i915_read_mch_val - return value for IPS use 5935 * 5936 * Calculate and return a value for the IPS driver to use when deciding whether 5937 * we have thermal and power headroom to increase CPU or GPU power budget. 5938 */ 5939 unsigned long i915_read_mch_val(void) 5940 { 5941 struct drm_i915_private *dev_priv; 5942 unsigned long chipset_val, graphics_val, ret = 0; 5943 5944 spin_lock_irq(&mchdev_lock); 5945 if (!i915_mch_dev) 5946 goto out_unlock; 5947 dev_priv = i915_mch_dev; 5948 5949 chipset_val = __i915_chipset_val(dev_priv); 5950 graphics_val = __i915_gfx_val(dev_priv); 5951 5952 ret = chipset_val + graphics_val; 5953 5954 out_unlock: 5955 spin_unlock_irq(&mchdev_lock); 5956 5957 return ret; 5958 } 5959 EXPORT_SYMBOL_GPL(i915_read_mch_val); 5960 5961 /** 5962 * i915_gpu_raise - raise GPU frequency limit 5963 * 5964 * Raise the limit; IPS indicates we have thermal headroom. 5965 */ 5966 bool i915_gpu_raise(void) 5967 { 5968 struct drm_i915_private *dev_priv; 5969 bool ret = true; 5970 5971 spin_lock_irq(&mchdev_lock); 5972 if (!i915_mch_dev) { 5973 ret = false; 5974 goto out_unlock; 5975 } 5976 dev_priv = i915_mch_dev; 5977 5978 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5979 dev_priv->ips.max_delay--; 5980 5981 out_unlock: 5982 spin_unlock_irq(&mchdev_lock); 5983 5984 return ret; 5985 } 5986 EXPORT_SYMBOL_GPL(i915_gpu_raise); 5987 5988 /** 5989 * i915_gpu_lower - lower GPU frequency limit 5990 * 5991 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5992 * frequency maximum. 5993 */ 5994 bool i915_gpu_lower(void) 5995 { 5996 struct drm_i915_private *dev_priv; 5997 bool ret = true; 5998 5999 spin_lock_irq(&mchdev_lock); 6000 if (!i915_mch_dev) { 6001 ret = false; 6002 goto out_unlock; 6003 } 6004 dev_priv = i915_mch_dev; 6005 6006 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 6007 dev_priv->ips.max_delay++; 6008 6009 out_unlock: 6010 spin_unlock_irq(&mchdev_lock); 6011 6012 return ret; 6013 } 6014 EXPORT_SYMBOL_GPL(i915_gpu_lower); 6015 6016 /** 6017 * i915_gpu_busy - indicate GPU business to IPS 6018 * 6019 * Tell the IPS driver whether or not the GPU is busy. 6020 */ 6021 bool i915_gpu_busy(void) 6022 { 6023 struct drm_i915_private *dev_priv; 6024 struct intel_engine_cs *ring; 6025 bool ret = false; 6026 int i; 6027 6028 spin_lock_irq(&mchdev_lock); 6029 if (!i915_mch_dev) 6030 goto out_unlock; 6031 dev_priv = i915_mch_dev; 6032 6033 for_each_ring(ring, dev_priv, i) 6034 ret |= !list_empty(&ring->request_list); 6035 6036 out_unlock: 6037 spin_unlock_irq(&mchdev_lock); 6038 6039 return ret; 6040 } 6041 EXPORT_SYMBOL_GPL(i915_gpu_busy); 6042 6043 /** 6044 * i915_gpu_turbo_disable - disable graphics turbo 6045 * 6046 * Disable graphics turbo by resetting the max frequency and setting the 6047 * current frequency to the default. 6048 */ 6049 bool i915_gpu_turbo_disable(void) 6050 { 6051 struct drm_i915_private *dev_priv; 6052 bool ret = true; 6053 6054 spin_lock_irq(&mchdev_lock); 6055 if (!i915_mch_dev) { 6056 ret = false; 6057 goto out_unlock; 6058 } 6059 dev_priv = i915_mch_dev; 6060 6061 dev_priv->ips.max_delay = dev_priv->ips.fstart; 6062 6063 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 6064 ret = false; 6065 6066 out_unlock: 6067 spin_unlock_irq(&mchdev_lock); 6068 6069 return ret; 6070 } 6071 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 6072 6073 /** 6074 * Tells the intel_ips driver that the i915 driver is now loaded, if 6075 * IPS got loaded first. 6076 * 6077 * This awkward dance is so that neither module has to depend on the 6078 * other in order for IPS to do the appropriate communication of 6079 * GPU turbo limits to i915. 6080 */ 6081 static void 6082 ips_ping_for_i915_load(void) 6083 { 6084 #ifndef __NetBSD__ /* XXX IPS GPU turbo limits what? */ 6085 void (*link)(void); 6086 6087 link = symbol_get(ips_link_to_i915_driver); 6088 if (link) { 6089 link(); 6090 symbol_put(ips_link_to_i915_driver); 6091 } 6092 #endif 6093 } 6094 6095 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6096 { 6097 /* We only register the i915 ips part with intel-ips once everything is 6098 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6099 spin_lock_irq(&mchdev_lock); 6100 i915_mch_dev = dev_priv; 6101 spin_unlock_irq(&mchdev_lock); 6102 6103 ips_ping_for_i915_load(); 6104 } 6105 6106 void intel_gpu_ips_teardown(void) 6107 { 6108 spin_lock_irq(&mchdev_lock); 6109 i915_mch_dev = NULL; 6110 spin_unlock_irq(&mchdev_lock); 6111 } 6112 6113 static void intel_init_emon(struct drm_device *dev) 6114 { 6115 struct drm_i915_private *dev_priv = dev->dev_private; 6116 u32 lcfuse; 6117 u8 pxw[16]; 6118 int i; 6119 6120 /* Disable to program */ 6121 I915_WRITE(ECR, 0); 6122 POSTING_READ(ECR); 6123 6124 /* Program energy weights for various events */ 6125 I915_WRITE(SDEW, 0x15040d00); 6126 I915_WRITE(CSIEW0, 0x007f0000); 6127 I915_WRITE(CSIEW1, 0x1e220004); 6128 I915_WRITE(CSIEW2, 0x04000004); 6129 6130 for (i = 0; i < 5; i++) 6131 I915_WRITE(PEW(i), 0); 6132 for (i = 0; i < 3; i++) 6133 I915_WRITE(DEW(i), 0); 6134 6135 /* Program P-state weights to account for frequency power adjustment */ 6136 for (i = 0; i < 16; i++) { 6137 u32 pxvidfreq = I915_READ(PXVFREQ(i)); 6138 unsigned long freq = intel_pxfreq(pxvidfreq); 6139 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6140 PXVFREQ_PX_SHIFT; 6141 unsigned long val; 6142 6143 val = vid * vid; 6144 val *= (freq / 1000); 6145 val *= 255; 6146 val /= (127*127*900); 6147 if (val > 0xff) 6148 DRM_ERROR("bad pxval: %ld\n", val); 6149 pxw[i] = val; 6150 } 6151 /* Render standby states get 0 weight */ 6152 pxw[14] = 0; 6153 pxw[15] = 0; 6154 6155 for (i = 0; i < 4; i++) { 6156 u32 val = ((u32)pxw[i*4] << 24) | ((u32)pxw[(i*4)+1] << 16) | 6157 ((u32)pxw[(i*4)+2] << 8) | ((u32)pxw[(i*4)+3]); 6158 I915_WRITE(PXW(i), val); 6159 } 6160 6161 /* Adjust magic regs to magic values (more experimental results) */ 6162 I915_WRITE(OGW0, 0); 6163 I915_WRITE(OGW1, 0); 6164 I915_WRITE(EG0, 0x00007f00); 6165 I915_WRITE(EG1, 0x0000000e); 6166 I915_WRITE(EG2, 0x000e0000); 6167 I915_WRITE(EG3, 0x68000300); 6168 I915_WRITE(EG4, 0x42000000); 6169 I915_WRITE(EG5, 0x00140031); 6170 I915_WRITE(EG6, 0); 6171 I915_WRITE(EG7, 0); 6172 6173 for (i = 0; i < 8; i++) 6174 I915_WRITE(PXWL(i), 0); 6175 6176 /* Enable PMON + select events */ 6177 I915_WRITE(ECR, 0x80000019); 6178 6179 lcfuse = I915_READ(LCFUSE02); 6180 6181 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6182 } 6183 6184 static bool i915_rc6_ctx_corrupted(struct drm_i915_private *dev_priv) 6185 { 6186 return !I915_READ(GEN8_RC6_CTX_INFO); 6187 } 6188 6189 static void i915_rc6_ctx_wa_init(struct drm_i915_private *i915) 6190 { 6191 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 6192 return; 6193 6194 if (i915_rc6_ctx_corrupted(i915)) { 6195 DRM_INFO("RC6 context corrupted, disabling runtime power management\n"); 6196 i915->rps.ctx_corrupted = true; 6197 intel_runtime_pm_get(i915); 6198 } 6199 } 6200 6201 static void i915_rc6_ctx_wa_cleanup(struct drm_i915_private *i915) 6202 { 6203 if (i915->rps.ctx_corrupted) { 6204 intel_runtime_pm_put(i915); 6205 i915->rps.ctx_corrupted = false; 6206 } 6207 } 6208 6209 /** 6210 * i915_rc6_ctx_wa_suspend - system suspend sequence for the RC6 CTX WA 6211 * @i915: i915 device 6212 * 6213 * Perform any steps needed to clean up the RC6 CTX WA before system suspend. 6214 */ 6215 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915) 6216 { 6217 if (i915->rps.ctx_corrupted) 6218 intel_runtime_pm_put(i915); 6219 } 6220 6221 /** 6222 * i915_rc6_ctx_wa_resume - system resume sequence for the RC6 CTX WA 6223 * @i915: i915 device 6224 * 6225 * Perform any steps needed to re-init the RC6 CTX WA after system resume. 6226 */ 6227 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915) 6228 { 6229 if (!i915->rps.ctx_corrupted) 6230 return; 6231 6232 if (i915_rc6_ctx_corrupted(i915)) { 6233 intel_runtime_pm_get(i915); 6234 return; 6235 } 6236 6237 DRM_INFO("RC6 context restored, re-enabling runtime power management\n"); 6238 i915->rps.ctx_corrupted = false; 6239 } 6240 6241 static void intel_disable_rc6(struct drm_device *dev); 6242 6243 /** 6244 * i915_rc6_ctx_wa_check - check for a new RC6 CTX corruption 6245 * @i915: i915 device 6246 * 6247 * Check if an RC6 CTX corruption has happened since the last check and if so 6248 * disable RC6 and runtime power management. 6249 * 6250 * Return false if no context corruption has happened since the last call of 6251 * this function, true otherwise. 6252 */ 6253 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915) 6254 { 6255 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 6256 return false; 6257 6258 if (i915->rps.ctx_corrupted) 6259 return false; 6260 6261 if (!i915_rc6_ctx_corrupted(i915)) 6262 return false; 6263 6264 DRM_NOTE("RC6 context corruption, disabling runtime power management\n"); 6265 6266 intel_disable_rc6(i915->dev); 6267 i915->rps.ctx_corrupted = true; 6268 intel_runtime_pm_get_noresume(i915); 6269 6270 return true; 6271 } 6272 6273 void intel_init_gt_powersave(struct drm_device *dev) 6274 { 6275 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); 6276 6277 i915_rc6_ctx_wa_init(to_i915(dev)); 6278 6279 if (IS_CHERRYVIEW(dev)) 6280 cherryview_init_gt_powersave(dev); 6281 else if (IS_VALLEYVIEW(dev)) 6282 valleyview_init_gt_powersave(dev); 6283 } 6284 6285 void intel_cleanup_gt_powersave(struct drm_device *dev) 6286 { 6287 if (IS_CHERRYVIEW(dev)) 6288 return; 6289 else if (IS_VALLEYVIEW(dev)) 6290 valleyview_cleanup_gt_powersave(dev); 6291 6292 i915_rc6_ctx_wa_cleanup(to_i915(dev)); 6293 } 6294 6295 static void gen6_suspend_rps(struct drm_device *dev) 6296 { 6297 struct drm_i915_private *dev_priv = dev->dev_private; 6298 6299 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6300 6301 gen6_disable_rps_interrupts(dev); 6302 } 6303 6304 /** 6305 * intel_suspend_gt_powersave - suspend PM work and helper threads 6306 * @dev: drm device 6307 * 6308 * We don't want to disable RC6 or other features here, we just want 6309 * to make sure any work we've queued has finished and won't bother 6310 * us while we're suspended. 6311 */ 6312 void intel_suspend_gt_powersave(struct drm_device *dev) 6313 { 6314 struct drm_i915_private *dev_priv = dev->dev_private; 6315 6316 if (INTEL_INFO(dev)->gen < 6) 6317 return; 6318 6319 gen6_suspend_rps(dev); 6320 6321 /* Force GPU to min freq during suspend */ 6322 gen6_rps_idle(dev_priv); 6323 } 6324 6325 static void __intel_disable_rc6(struct drm_device *dev) 6326 { 6327 if (INTEL_INFO(dev)->gen >= 9) 6328 gen9_disable_rc6(dev); 6329 else if (IS_CHERRYVIEW(dev)) 6330 cherryview_disable_rc6(dev); 6331 else if (IS_VALLEYVIEW(dev)) 6332 valleyview_disable_rc6(dev); 6333 else 6334 gen6_disable_rc6(dev); 6335 } 6336 6337 static void intel_disable_rc6(struct drm_device *dev) 6338 { 6339 struct drm_i915_private *dev_priv = to_i915(dev); 6340 6341 mutex_lock(&dev_priv->rps.hw_lock); 6342 __intel_disable_rc6(dev); 6343 mutex_unlock(&dev_priv->rps.hw_lock); 6344 } 6345 6346 static void intel_disable_rps(struct drm_device *dev) 6347 { 6348 if (IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev)) 6349 return; 6350 6351 if (INTEL_INFO(dev)->gen >= 9) 6352 gen9_disable_rps(dev); 6353 else 6354 gen6_disable_rps(dev); 6355 } 6356 6357 void intel_disable_gt_powersave(struct drm_device *dev) 6358 { 6359 struct drm_i915_private *dev_priv = dev->dev_private; 6360 6361 if (IS_IRONLAKE_M(dev)) { 6362 ironlake_disable_drps(dev); 6363 } else if (INTEL_INFO(dev)->gen >= 6) { 6364 intel_suspend_gt_powersave(dev); 6365 6366 mutex_lock(&dev_priv->rps.hw_lock); 6367 6368 __intel_disable_rc6(dev); 6369 intel_disable_rps(dev); 6370 6371 dev_priv->rps.enabled = false; 6372 6373 mutex_unlock(&dev_priv->rps.hw_lock); 6374 } 6375 } 6376 6377 static void intel_gen6_powersave_work(struct work_struct *work) 6378 { 6379 struct drm_i915_private *dev_priv = 6380 container_of(work, struct drm_i915_private, 6381 rps.delayed_resume_work.work); 6382 struct drm_device *dev = dev_priv->dev; 6383 6384 mutex_lock(&dev_priv->rps.hw_lock); 6385 6386 gen6_reset_rps_interrupts(dev); 6387 6388 if (IS_CHERRYVIEW(dev)) { 6389 cherryview_enable_rps(dev); 6390 } else if (IS_VALLEYVIEW(dev)) { 6391 valleyview_enable_rps(dev); 6392 } else if (INTEL_INFO(dev)->gen >= 9) { 6393 gen9_enable_rc6(dev); 6394 gen9_enable_rps(dev); 6395 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 6396 __gen6_update_ring_freq(dev); 6397 } else if (IS_BROADWELL(dev)) { 6398 gen8_enable_rps(dev); 6399 __gen6_update_ring_freq(dev); 6400 } else { 6401 gen6_enable_rps(dev); 6402 __gen6_update_ring_freq(dev); 6403 } 6404 6405 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6406 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6407 6408 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6409 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6410 6411 dev_priv->rps.enabled = true; 6412 6413 gen6_enable_rps_interrupts(dev); 6414 6415 mutex_unlock(&dev_priv->rps.hw_lock); 6416 6417 intel_runtime_pm_put(dev_priv); 6418 } 6419 6420 void intel_enable_gt_powersave(struct drm_device *dev) 6421 { 6422 struct drm_i915_private *dev_priv = dev->dev_private; 6423 6424 /* Powersaving is controlled by the host when inside a VM */ 6425 if (intel_vgpu_active(dev)) 6426 return; 6427 6428 if (IS_IRONLAKE_M(dev)) { 6429 mutex_lock(&dev->struct_mutex); 6430 ironlake_enable_drps(dev); 6431 intel_init_emon(dev); 6432 mutex_unlock(&dev->struct_mutex); 6433 } else if (INTEL_INFO(dev)->gen >= 6) { 6434 /* 6435 * PCU communication is slow and this doesn't need to be 6436 * done at any specific time, so do this out of our fast path 6437 * to make resume and init faster. 6438 * 6439 * We depend on the HW RC6 power context save/restore 6440 * mechanism when entering D3 through runtime PM suspend. So 6441 * disable RPM until RPS/RC6 is properly setup. We can only 6442 * get here via the driver load/system resume/runtime resume 6443 * paths, so the _noresume version is enough (and in case of 6444 * runtime resume it's necessary). 6445 */ 6446 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6447 round_jiffies_up_relative(HZ))) 6448 intel_runtime_pm_get_noresume(dev_priv); 6449 } 6450 } 6451 6452 void intel_reset_gt_powersave(struct drm_device *dev) 6453 { 6454 struct drm_i915_private *dev_priv = dev->dev_private; 6455 6456 if (INTEL_INFO(dev)->gen < 6) 6457 return; 6458 6459 gen6_suspend_rps(dev); 6460 dev_priv->rps.enabled = false; 6461 } 6462 6463 static void ibx_init_clock_gating(struct drm_device *dev) 6464 { 6465 struct drm_i915_private *dev_priv = dev->dev_private; 6466 6467 /* 6468 * On Ibex Peak and Cougar Point, we need to disable clock 6469 * gating for the panel power sequencer or it will fail to 6470 * start up when no ports are active. 6471 */ 6472 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6473 } 6474 6475 static void g4x_disable_trickle_feed(struct drm_device *dev) 6476 { 6477 struct drm_i915_private *dev_priv = dev->dev_private; 6478 enum pipe pipe; 6479 6480 for_each_pipe(dev_priv, pipe) { 6481 I915_WRITE(DSPCNTR(pipe), 6482 I915_READ(DSPCNTR(pipe)) | 6483 DISPPLANE_TRICKLE_FEED_DISABLE); 6484 6485 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6486 POSTING_READ(DSPSURF(pipe)); 6487 } 6488 } 6489 6490 static void ilk_init_lp_watermarks(struct drm_device *dev) 6491 { 6492 struct drm_i915_private *dev_priv = dev->dev_private; 6493 6494 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6495 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6496 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6497 6498 /* 6499 * Don't touch WM1S_LP_EN here. 6500 * Doing so could cause underruns. 6501 */ 6502 } 6503 6504 static void ironlake_init_clock_gating(struct drm_device *dev) 6505 { 6506 struct drm_i915_private *dev_priv = dev->dev_private; 6507 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6508 6509 /* 6510 * Required for FBC 6511 * WaFbcDisableDpfcClockGating:ilk 6512 */ 6513 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6514 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6515 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6516 6517 I915_WRITE(PCH_3DCGDIS0, 6518 MARIUNIT_CLOCK_GATE_DISABLE | 6519 SVSMUNIT_CLOCK_GATE_DISABLE); 6520 I915_WRITE(PCH_3DCGDIS1, 6521 VFMUNIT_CLOCK_GATE_DISABLE); 6522 6523 /* 6524 * According to the spec the following bits should be set in 6525 * order to enable memory self-refresh 6526 * The bit 22/21 of 0x42004 6527 * The bit 5 of 0x42020 6528 * The bit 15 of 0x45000 6529 */ 6530 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6531 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6532 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6533 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6534 I915_WRITE(DISP_ARB_CTL, 6535 (I915_READ(DISP_ARB_CTL) | 6536 DISP_FBC_WM_DIS)); 6537 6538 ilk_init_lp_watermarks(dev); 6539 6540 /* 6541 * Based on the document from hardware guys the following bits 6542 * should be set unconditionally in order to enable FBC. 6543 * The bit 22 of 0x42000 6544 * The bit 22 of 0x42004 6545 * The bit 7,8,9 of 0x42020. 6546 */ 6547 if (IS_IRONLAKE_M(dev)) { 6548 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6549 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6550 I915_READ(ILK_DISPLAY_CHICKEN1) | 6551 ILK_FBCQ_DIS); 6552 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6553 I915_READ(ILK_DISPLAY_CHICKEN2) | 6554 ILK_DPARB_GATE); 6555 } 6556 6557 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6558 6559 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6560 I915_READ(ILK_DISPLAY_CHICKEN2) | 6561 ILK_ELPIN_409_SELECT); 6562 I915_WRITE(_3D_CHICKEN2, 6563 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6564 _3D_CHICKEN2_WM_READ_PIPELINED); 6565 6566 /* WaDisableRenderCachePipelinedFlush:ilk */ 6567 I915_WRITE(CACHE_MODE_0, 6568 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6569 6570 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6571 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6572 6573 g4x_disable_trickle_feed(dev); 6574 6575 ibx_init_clock_gating(dev); 6576 } 6577 6578 static void cpt_init_clock_gating(struct drm_device *dev) 6579 { 6580 struct drm_i915_private *dev_priv = dev->dev_private; 6581 int pipe; 6582 uint32_t val; 6583 6584 /* 6585 * On Ibex Peak and Cougar Point, we need to disable clock 6586 * gating for the panel power sequencer or it will fail to 6587 * start up when no ports are active. 6588 */ 6589 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6590 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6591 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6592 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6593 DPLS_EDP_PPS_FIX_DIS); 6594 /* The below fixes the weird display corruption, a few pixels shifted 6595 * downward, on (only) LVDS of some HP laptops with IVY. 6596 */ 6597 for_each_pipe(dev_priv, pipe) { 6598 val = I915_READ(TRANS_CHICKEN2(pipe)); 6599 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6600 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6601 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6602 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6603 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6604 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6605 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6606 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6607 } 6608 /* WADP0ClockGatingDisable */ 6609 for_each_pipe(dev_priv, pipe) { 6610 I915_WRITE(TRANS_CHICKEN1(pipe), 6611 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6612 } 6613 } 6614 6615 static void gen6_check_mch_setup(struct drm_device *dev) 6616 { 6617 struct drm_i915_private *dev_priv = dev->dev_private; 6618 uint32_t tmp; 6619 6620 tmp = I915_READ(MCH_SSKPD); 6621 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6622 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6623 tmp); 6624 } 6625 6626 static void gen6_init_clock_gating(struct drm_device *dev) 6627 { 6628 struct drm_i915_private *dev_priv = dev->dev_private; 6629 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6630 6631 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6632 6633 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6634 I915_READ(ILK_DISPLAY_CHICKEN2) | 6635 ILK_ELPIN_409_SELECT); 6636 6637 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6638 I915_WRITE(_3D_CHICKEN, 6639 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6640 6641 /* WaDisable_RenderCache_OperationalFlush:snb */ 6642 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6643 6644 /* 6645 * BSpec recoomends 8x4 when MSAA is used, 6646 * however in practice 16x4 seems fastest. 6647 * 6648 * Note that PS/WM thread counts depend on the WIZ hashing 6649 * disable bit, which we don't touch here, but it's good 6650 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6651 */ 6652 I915_WRITE(GEN6_GT_MODE, 6653 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6654 6655 ilk_init_lp_watermarks(dev); 6656 6657 I915_WRITE(CACHE_MODE_0, 6658 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6659 6660 I915_WRITE(GEN6_UCGCTL1, 6661 I915_READ(GEN6_UCGCTL1) | 6662 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6663 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6664 6665 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6666 * gating disable must be set. Failure to set it results in 6667 * flickering pixels due to Z write ordering failures after 6668 * some amount of runtime in the Mesa "fire" demo, and Unigine 6669 * Sanctuary and Tropics, and apparently anything else with 6670 * alpha test or pixel discard. 6671 * 6672 * According to the spec, bit 11 (RCCUNIT) must also be set, 6673 * but we didn't debug actual testcases to find it out. 6674 * 6675 * WaDisableRCCUnitClockGating:snb 6676 * WaDisableRCPBUnitClockGating:snb 6677 */ 6678 I915_WRITE(GEN6_UCGCTL2, 6679 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6680 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6681 6682 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6683 I915_WRITE(_3D_CHICKEN3, 6684 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6685 6686 /* 6687 * Bspec says: 6688 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6689 * 3DSTATE_SF number of SF output attributes is more than 16." 6690 */ 6691 I915_WRITE(_3D_CHICKEN3, 6692 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6693 6694 /* 6695 * According to the spec the following bits should be 6696 * set in order to enable memory self-refresh and fbc: 6697 * The bit21 and bit22 of 0x42000 6698 * The bit21 and bit22 of 0x42004 6699 * The bit5 and bit7 of 0x42020 6700 * The bit14 of 0x70180 6701 * The bit14 of 0x71180 6702 * 6703 * WaFbcAsynchFlipDisableFbcQueue:snb 6704 */ 6705 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6706 I915_READ(ILK_DISPLAY_CHICKEN1) | 6707 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6708 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6709 I915_READ(ILK_DISPLAY_CHICKEN2) | 6710 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6711 I915_WRITE(ILK_DSPCLK_GATE_D, 6712 I915_READ(ILK_DSPCLK_GATE_D) | 6713 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6714 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6715 6716 g4x_disable_trickle_feed(dev); 6717 6718 cpt_init_clock_gating(dev); 6719 6720 gen6_check_mch_setup(dev); 6721 } 6722 6723 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6724 { 6725 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6726 6727 /* 6728 * WaVSThreadDispatchOverride:ivb,vlv 6729 * 6730 * This actually overrides the dispatch 6731 * mode for all thread types. 6732 */ 6733 reg &= ~GEN7_FF_SCHED_MASK; 6734 reg |= GEN7_FF_TS_SCHED_HW; 6735 reg |= GEN7_FF_VS_SCHED_HW; 6736 reg |= GEN7_FF_DS_SCHED_HW; 6737 6738 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6739 } 6740 6741 static void lpt_init_clock_gating(struct drm_device *dev) 6742 { 6743 struct drm_i915_private *dev_priv = dev->dev_private; 6744 6745 /* 6746 * TODO: this bit should only be enabled when really needed, then 6747 * disabled when not needed anymore in order to save power. 6748 */ 6749 if (HAS_PCH_LPT_LP(dev)) 6750 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6751 I915_READ(SOUTH_DSPCLK_GATE_D) | 6752 PCH_LP_PARTITION_LEVEL_DISABLE); 6753 6754 /* WADPOClockGatingDisable:hsw */ 6755 I915_WRITE(TRANS_CHICKEN1(PIPE_A), 6756 I915_READ(TRANS_CHICKEN1(PIPE_A)) | 6757 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6758 } 6759 6760 static void lpt_suspend_hw(struct drm_device *dev) 6761 { 6762 struct drm_i915_private *dev_priv = dev->dev_private; 6763 6764 if (HAS_PCH_LPT_LP(dev)) { 6765 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6766 6767 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6768 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6769 } 6770 } 6771 6772 static void broadwell_init_clock_gating(struct drm_device *dev) 6773 { 6774 struct drm_i915_private *dev_priv = dev->dev_private; 6775 enum pipe pipe; 6776 uint32_t misccpctl; 6777 6778 ilk_init_lp_watermarks(dev); 6779 6780 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6781 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6782 6783 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6784 I915_WRITE(CHICKEN_PAR1_1, 6785 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6786 6787 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6788 for_each_pipe(dev_priv, pipe) { 6789 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6790 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6791 BDW_DPRS_MASK_VBLANK_SRD); 6792 } 6793 6794 /* WaVSRefCountFullforceMissDisable:bdw */ 6795 /* WaDSRefCountFullforceMissDisable:bdw */ 6796 I915_WRITE(GEN7_FF_THREAD_MODE, 6797 I915_READ(GEN7_FF_THREAD_MODE) & 6798 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6799 6800 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6801 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6802 6803 /* WaDisableSDEUnitClockGating:bdw */ 6804 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6805 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6806 6807 /* 6808 * WaProgramL3SqcReg1Default:bdw 6809 * WaTempDisableDOPClkGating:bdw 6810 */ 6811 misccpctl = I915_READ(GEN7_MISCCPCTL); 6812 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6813 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6814 /* 6815 * Wait at least 100 clocks before re-enabling clock gating. See 6816 * the definition of L3SQCREG1 in BSpec. 6817 */ 6818 POSTING_READ(GEN8_L3SQCREG1); 6819 udelay(1); 6820 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6821 6822 /* 6823 * WaGttCachingOffByDefault:bdw 6824 * GTT cache may not work with big pages, so if those 6825 * are ever enabled GTT cache may need to be disabled. 6826 */ 6827 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6828 6829 lpt_init_clock_gating(dev); 6830 } 6831 6832 static void haswell_init_clock_gating(struct drm_device *dev) 6833 { 6834 struct drm_i915_private *dev_priv = dev->dev_private; 6835 6836 ilk_init_lp_watermarks(dev); 6837 6838 /* L3 caching of data atomics doesn't work -- disable it. */ 6839 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6840 I915_WRITE(HSW_ROW_CHICKEN3, 6841 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6842 6843 /* This is required by WaCatErrorRejectionIssue:hsw */ 6844 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6845 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6846 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6847 6848 /* WaVSRefCountFullforceMissDisable:hsw */ 6849 I915_WRITE(GEN7_FF_THREAD_MODE, 6850 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6851 6852 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6853 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6854 6855 /* enable HiZ Raw Stall Optimization */ 6856 I915_WRITE(CACHE_MODE_0_GEN7, 6857 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6858 6859 /* WaDisable4x2SubspanOptimization:hsw */ 6860 I915_WRITE(CACHE_MODE_1, 6861 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6862 6863 /* 6864 * BSpec recommends 8x4 when MSAA is used, 6865 * however in practice 16x4 seems fastest. 6866 * 6867 * Note that PS/WM thread counts depend on the WIZ hashing 6868 * disable bit, which we don't touch here, but it's good 6869 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6870 */ 6871 I915_WRITE(GEN7_GT_MODE, 6872 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6873 6874 /* WaSampleCChickenBitEnable:hsw */ 6875 I915_WRITE(HALF_SLICE_CHICKEN3, 6876 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6877 6878 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6879 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6880 6881 /* WaRsPkgCStateDisplayPMReq:hsw */ 6882 I915_WRITE(CHICKEN_PAR1_1, 6883 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6884 6885 lpt_init_clock_gating(dev); 6886 } 6887 6888 static void ivybridge_init_clock_gating(struct drm_device *dev) 6889 { 6890 struct drm_i915_private *dev_priv = dev->dev_private; 6891 uint32_t snpcr; 6892 6893 ilk_init_lp_watermarks(dev); 6894 6895 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6896 6897 /* WaDisableEarlyCull:ivb */ 6898 I915_WRITE(_3D_CHICKEN3, 6899 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6900 6901 /* WaDisableBackToBackFlipFix:ivb */ 6902 I915_WRITE(IVB_CHICKEN3, 6903 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6904 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6905 6906 /* WaDisablePSDDualDispatchEnable:ivb */ 6907 if (IS_IVB_GT1(dev)) 6908 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6909 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6910 6911 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6912 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6913 6914 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6915 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6916 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6917 6918 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6919 I915_WRITE(GEN7_L3CNTLREG1, 6920 GEN7_WA_FOR_GEN7_L3_CONTROL); 6921 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6922 GEN7_WA_L3_CHICKEN_MODE); 6923 if (IS_IVB_GT1(dev)) 6924 I915_WRITE(GEN7_ROW_CHICKEN2, 6925 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6926 else { 6927 /* must write both registers */ 6928 I915_WRITE(GEN7_ROW_CHICKEN2, 6929 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6930 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6931 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6932 } 6933 6934 /* WaForceL3Serialization:ivb */ 6935 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6936 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6937 6938 /* 6939 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6940 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6941 */ 6942 I915_WRITE(GEN6_UCGCTL2, 6943 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6944 6945 /* This is required by WaCatErrorRejectionIssue:ivb */ 6946 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6947 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6948 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6949 6950 g4x_disable_trickle_feed(dev); 6951 6952 gen7_setup_fixed_func_scheduler(dev_priv); 6953 6954 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6955 /* enable HiZ Raw Stall Optimization */ 6956 I915_WRITE(CACHE_MODE_0_GEN7, 6957 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6958 } 6959 6960 /* WaDisable4x2SubspanOptimization:ivb */ 6961 I915_WRITE(CACHE_MODE_1, 6962 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6963 6964 /* 6965 * BSpec recommends 8x4 when MSAA is used, 6966 * however in practice 16x4 seems fastest. 6967 * 6968 * Note that PS/WM thread counts depend on the WIZ hashing 6969 * disable bit, which we don't touch here, but it's good 6970 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6971 */ 6972 I915_WRITE(GEN7_GT_MODE, 6973 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6974 6975 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6976 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6977 snpcr |= GEN6_MBC_SNPCR_MED; 6978 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6979 6980 if (!HAS_PCH_NOP(dev)) 6981 cpt_init_clock_gating(dev); 6982 6983 gen6_check_mch_setup(dev); 6984 } 6985 6986 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6987 { 6988 u32 val; 6989 6990 /* 6991 * On driver load, a pipe may be active and driving a DSI display. 6992 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 6993 * (and never recovering) in this case. intel_dsi_post_disable() will 6994 * clear it when we turn off the display. 6995 */ 6996 val = I915_READ(DSPCLK_GATE_D); 6997 val &= DPOUNIT_CLOCK_GATE_DISABLE; 6998 val |= VRHUNIT_CLOCK_GATE_DISABLE; 6999 I915_WRITE(DSPCLK_GATE_D, val); 7000 7001 /* 7002 * Disable trickle feed and enable pnd deadline calculation 7003 */ 7004 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 7005 I915_WRITE(CBR1_VLV, 0); 7006 } 7007 7008 static void valleyview_init_clock_gating(struct drm_device *dev) 7009 { 7010 struct drm_i915_private *dev_priv = dev->dev_private; 7011 7012 vlv_init_display_clock_gating(dev_priv); 7013 7014 /* WaDisableEarlyCull:vlv */ 7015 I915_WRITE(_3D_CHICKEN3, 7016 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 7017 7018 /* WaDisableBackToBackFlipFix:vlv */ 7019 I915_WRITE(IVB_CHICKEN3, 7020 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 7021 CHICKEN3_DGMG_DONE_FIX_DISABLE); 7022 7023 /* WaPsdDispatchEnable:vlv */ 7024 /* WaDisablePSDDualDispatchEnable:vlv */ 7025 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 7026 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 7027 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 7028 7029 /* WaDisable_RenderCache_OperationalFlush:vlv */ 7030 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7031 7032 /* WaForceL3Serialization:vlv */ 7033 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 7034 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 7035 7036 /* WaDisableDopClockGating:vlv */ 7037 I915_WRITE(GEN7_ROW_CHICKEN2, 7038 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 7039 7040 /* This is required by WaCatErrorRejectionIssue:vlv */ 7041 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 7042 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 7043 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 7044 7045 gen7_setup_fixed_func_scheduler(dev_priv); 7046 7047 /* 7048 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 7049 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 7050 */ 7051 I915_WRITE(GEN6_UCGCTL2, 7052 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 7053 7054 /* WaDisableL3Bank2xClockGate:vlv 7055 * Disabling L3 clock gating- MMIO 940c[25] = 1 7056 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 7057 I915_WRITE(GEN7_UCGCTL4, 7058 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 7059 7060 /* 7061 * BSpec says this must be set, even though 7062 * WaDisable4x2SubspanOptimization isn't listed for VLV. 7063 */ 7064 I915_WRITE(CACHE_MODE_1, 7065 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 7066 7067 /* 7068 * BSpec recommends 8x4 when MSAA is used, 7069 * however in practice 16x4 seems fastest. 7070 * 7071 * Note that PS/WM thread counts depend on the WIZ hashing 7072 * disable bit, which we don't touch here, but it's good 7073 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 7074 */ 7075 I915_WRITE(GEN7_GT_MODE, 7076 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 7077 7078 /* 7079 * WaIncreaseL3CreditsForVLVB0:vlv 7080 * This is the hardware default actually. 7081 */ 7082 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 7083 7084 /* 7085 * WaDisableVLVClockGating_VBIIssue:vlv 7086 * Disable clock gating on th GCFG unit to prevent a delay 7087 * in the reporting of vblank events. 7088 */ 7089 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 7090 } 7091 7092 static void cherryview_init_clock_gating(struct drm_device *dev) 7093 { 7094 struct drm_i915_private *dev_priv = dev->dev_private; 7095 7096 vlv_init_display_clock_gating(dev_priv); 7097 7098 /* WaVSRefCountFullforceMissDisable:chv */ 7099 /* WaDSRefCountFullforceMissDisable:chv */ 7100 I915_WRITE(GEN7_FF_THREAD_MODE, 7101 I915_READ(GEN7_FF_THREAD_MODE) & 7102 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 7103 7104 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 7105 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 7106 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 7107 7108 /* WaDisableCSUnitClockGating:chv */ 7109 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 7110 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 7111 7112 /* WaDisableSDEUnitClockGating:chv */ 7113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 7114 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 7115 7116 /* 7117 * GTT cache may not work with big pages, so if those 7118 * are ever enabled GTT cache may need to be disabled. 7119 */ 7120 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 7121 } 7122 7123 static void g4x_init_clock_gating(struct drm_device *dev) 7124 { 7125 struct drm_i915_private *dev_priv = dev->dev_private; 7126 uint32_t dspclk_gate; 7127 7128 I915_WRITE(RENCLK_GATE_D1, 0); 7129 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 7130 GS_UNIT_CLOCK_GATE_DISABLE | 7131 CL_UNIT_CLOCK_GATE_DISABLE); 7132 I915_WRITE(RAMCLK_GATE_D, 0); 7133 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 7134 OVRUNIT_CLOCK_GATE_DISABLE | 7135 OVCUNIT_CLOCK_GATE_DISABLE; 7136 if (IS_GM45(dev)) 7137 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 7138 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 7139 7140 /* WaDisableRenderCachePipelinedFlush */ 7141 I915_WRITE(CACHE_MODE_0, 7142 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 7143 7144 /* WaDisable_RenderCache_OperationalFlush:g4x */ 7145 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7146 7147 g4x_disable_trickle_feed(dev); 7148 } 7149 7150 static void crestline_init_clock_gating(struct drm_device *dev) 7151 { 7152 struct drm_i915_private *dev_priv = dev->dev_private; 7153 7154 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 7155 I915_WRITE(RENCLK_GATE_D2, 0); 7156 I915_WRITE(DSPCLK_GATE_D, 0); 7157 I915_WRITE(RAMCLK_GATE_D, 0); 7158 I915_WRITE16(DEUC, 0); 7159 I915_WRITE(MI_ARB_STATE, 7160 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7161 7162 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7163 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7164 } 7165 7166 static void broadwater_init_clock_gating(struct drm_device *dev) 7167 { 7168 struct drm_i915_private *dev_priv = dev->dev_private; 7169 7170 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 7171 I965_RCC_CLOCK_GATE_DISABLE | 7172 I965_RCPB_CLOCK_GATE_DISABLE | 7173 I965_ISC_CLOCK_GATE_DISABLE | 7174 I965_FBC_CLOCK_GATE_DISABLE); 7175 I915_WRITE(RENCLK_GATE_D2, 0); 7176 I915_WRITE(MI_ARB_STATE, 7177 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7178 7179 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7180 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7181 } 7182 7183 static void gen3_init_clock_gating(struct drm_device *dev) 7184 { 7185 struct drm_i915_private *dev_priv = dev->dev_private; 7186 u32 dstate = I915_READ(D_STATE); 7187 7188 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7189 DSTATE_DOT_CLOCK_GATING; 7190 I915_WRITE(D_STATE, dstate); 7191 7192 if (IS_PINEVIEW(dev)) 7193 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 7194 7195 /* IIR "flip pending" means done if this bit is set */ 7196 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 7197 7198 /* interrupts should cause a wake up from C3 */ 7199 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7200 7201 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7202 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7203 7204 I915_WRITE(MI_ARB_STATE, 7205 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7206 } 7207 7208 static void i85x_init_clock_gating(struct drm_device *dev) 7209 { 7210 struct drm_i915_private *dev_priv = dev->dev_private; 7211 7212 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7213 7214 /* interrupts should cause a wake up from C3 */ 7215 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7216 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7217 7218 I915_WRITE(MEM_MODE, 7219 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7220 } 7221 7222 static void i830_init_clock_gating(struct drm_device *dev) 7223 { 7224 struct drm_i915_private *dev_priv = dev->dev_private; 7225 7226 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7227 7228 I915_WRITE(MEM_MODE, 7229 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7230 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7231 } 7232 7233 void intel_init_clock_gating(struct drm_device *dev) 7234 { 7235 struct drm_i915_private *dev_priv = dev->dev_private; 7236 7237 if (dev_priv->display.init_clock_gating) 7238 dev_priv->display.init_clock_gating(dev); 7239 } 7240 7241 void intel_suspend_hw(struct drm_device *dev) 7242 { 7243 if (HAS_PCH_LPT(dev)) 7244 lpt_suspend_hw(dev); 7245 } 7246 7247 /* Set up chip specific power management-related functions */ 7248 void intel_init_pm(struct drm_device *dev) 7249 { 7250 struct drm_i915_private *dev_priv = dev->dev_private; 7251 7252 intel_fbc_init(dev_priv); 7253 7254 /* For cxsr */ 7255 if (IS_PINEVIEW(dev)) 7256 i915_pineview_get_mem_freq(dev); 7257 else if (IS_GEN5(dev)) 7258 i915_ironlake_get_mem_freq(dev); 7259 7260 /* For FIFO watermark updates */ 7261 if (INTEL_INFO(dev)->gen >= 9) { 7262 skl_setup_wm_latency(dev); 7263 7264 if (IS_BROXTON(dev)) 7265 dev_priv->display.init_clock_gating = 7266 bxt_init_clock_gating; 7267 dev_priv->display.update_wm = skl_update_wm; 7268 dev_priv->display.update_sprite_wm = skl_update_sprite_wm; 7269 } else if (HAS_PCH_SPLIT(dev)) { 7270 ilk_setup_wm_latency(dev); 7271 7272 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7273 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7274 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7275 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7276 dev_priv->display.update_wm = ilk_update_wm; 7277 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 7278 } else { 7279 DRM_DEBUG_KMS("Failed to read display plane latency. " 7280 "Disable CxSR\n"); 7281 } 7282 7283 if (IS_GEN5(dev)) 7284 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7285 else if (IS_GEN6(dev)) 7286 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7287 else if (IS_IVYBRIDGE(dev)) 7288 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7289 else if (IS_HASWELL(dev)) 7290 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7291 else if (INTEL_INFO(dev)->gen == 8) 7292 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7293 } else if (IS_CHERRYVIEW(dev)) { 7294 vlv_setup_wm_latency(dev); 7295 7296 dev_priv->display.update_wm = vlv_update_wm; 7297 dev_priv->display.init_clock_gating = 7298 cherryview_init_clock_gating; 7299 } else if (IS_VALLEYVIEW(dev)) { 7300 vlv_setup_wm_latency(dev); 7301 7302 dev_priv->display.update_wm = vlv_update_wm; 7303 dev_priv->display.init_clock_gating = 7304 valleyview_init_clock_gating; 7305 } else if (IS_PINEVIEW(dev)) { 7306 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7307 dev_priv->is_ddr3, 7308 dev_priv->fsb_freq, 7309 dev_priv->mem_freq)) { 7310 DRM_INFO("failed to find known CxSR latency " 7311 "(found ddr%s fsb freq %d, mem freq %d), " 7312 "disabling CxSR\n", 7313 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7314 dev_priv->fsb_freq, dev_priv->mem_freq); 7315 /* Disable CxSR and never update its watermark again */ 7316 intel_set_memory_cxsr(dev_priv, false); 7317 dev_priv->display.update_wm = NULL; 7318 } else 7319 dev_priv->display.update_wm = pineview_update_wm; 7320 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7321 } else if (IS_G4X(dev)) { 7322 dev_priv->display.update_wm = g4x_update_wm; 7323 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7324 } else if (IS_GEN4(dev)) { 7325 dev_priv->display.update_wm = i965_update_wm; 7326 if (IS_CRESTLINE(dev)) 7327 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7328 else if (IS_BROADWATER(dev)) 7329 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7330 } else if (IS_GEN3(dev)) { 7331 dev_priv->display.update_wm = i9xx_update_wm; 7332 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7333 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7334 } else if (IS_GEN2(dev)) { 7335 if (INTEL_INFO(dev)->num_pipes == 1) { 7336 dev_priv->display.update_wm = i845_update_wm; 7337 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7338 } else { 7339 dev_priv->display.update_wm = i9xx_update_wm; 7340 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7341 } 7342 7343 if (IS_I85X(dev) || IS_I865G(dev)) 7344 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7345 else 7346 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7347 } else { 7348 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7349 } 7350 } 7351 7352 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7353 { 7354 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7355 7356 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7357 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7358 return -EAGAIN; 7359 } 7360 7361 I915_WRITE(GEN6_PCODE_DATA, *val); 7362 I915_WRITE(GEN6_PCODE_DATA1, 0); 7363 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7364 7365 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7366 500)) { 7367 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7368 return -ETIMEDOUT; 7369 } 7370 7371 *val = I915_READ(GEN6_PCODE_DATA); 7372 I915_WRITE(GEN6_PCODE_DATA, 0); 7373 7374 return 0; 7375 } 7376 7377 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7378 { 7379 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7380 7381 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7382 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7383 return -EAGAIN; 7384 } 7385 7386 I915_WRITE(GEN6_PCODE_DATA, val); 7387 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7388 7389 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7390 500)) { 7391 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7392 return -ETIMEDOUT; 7393 } 7394 7395 I915_WRITE(GEN6_PCODE_DATA, 0); 7396 7397 return 0; 7398 } 7399 7400 static int vlv_gpu_freq_div(unsigned int czclk_freq) 7401 { 7402 switch (czclk_freq) { 7403 case 200: 7404 return 10; 7405 case 267: 7406 return 12; 7407 case 320: 7408 case 333: 7409 return 16; 7410 case 400: 7411 return 20; 7412 default: 7413 return -1; 7414 } 7415 } 7416 7417 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7418 { 7419 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7420 7421 div = vlv_gpu_freq_div(czclk_freq); 7422 if (div < 0) 7423 return div; 7424 7425 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7426 } 7427 7428 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7429 { 7430 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7431 7432 mul = vlv_gpu_freq_div(czclk_freq); 7433 if (mul < 0) 7434 return mul; 7435 7436 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7437 } 7438 7439 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7440 { 7441 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7442 7443 div = vlv_gpu_freq_div(czclk_freq) / 2; 7444 if (div < 0) 7445 return div; 7446 7447 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7448 } 7449 7450 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7451 { 7452 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7453 7454 mul = vlv_gpu_freq_div(czclk_freq) / 2; 7455 if (mul < 0) 7456 return mul; 7457 7458 /* CHV needs even values */ 7459 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7460 } 7461 7462 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7463 { 7464 if (IS_GEN9(dev_priv->dev)) 7465 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7466 GEN9_FREQ_SCALER); 7467 else if (IS_CHERRYVIEW(dev_priv->dev)) 7468 return chv_gpu_freq(dev_priv, val); 7469 else if (IS_VALLEYVIEW(dev_priv->dev)) 7470 return byt_gpu_freq(dev_priv, val); 7471 else 7472 return val * GT_FREQUENCY_MULTIPLIER; 7473 } 7474 7475 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7476 { 7477 if (IS_GEN9(dev_priv->dev)) 7478 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7479 GT_FREQUENCY_MULTIPLIER); 7480 else if (IS_CHERRYVIEW(dev_priv->dev)) 7481 return chv_freq_opcode(dev_priv, val); 7482 else if (IS_VALLEYVIEW(dev_priv->dev)) 7483 return byt_freq_opcode(dev_priv, val); 7484 else 7485 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7486 } 7487 7488 struct request_boost { 7489 struct work_struct work; 7490 struct drm_i915_gem_request *req; 7491 }; 7492 7493 static void __intel_rps_boost_work(struct work_struct *work) 7494 { 7495 struct request_boost *boost = container_of(work, struct request_boost, work); 7496 struct drm_i915_gem_request *req = boost->req; 7497 7498 if (!i915_gem_request_completed(req, true)) 7499 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7500 req->emitted_jiffies); 7501 7502 i915_gem_request_unreference__unlocked(req); 7503 kfree(boost); 7504 } 7505 7506 void intel_queue_rps_boost_for_request(struct drm_device *dev, 7507 struct drm_i915_gem_request *req) 7508 { 7509 struct request_boost *boost; 7510 7511 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7512 return; 7513 7514 if (i915_gem_request_completed(req, true)) 7515 return; 7516 7517 boost = kmalloc(sizeof(*boost), GFP_ATOMIC); 7518 if (boost == NULL) 7519 return; 7520 7521 i915_gem_request_reference(req); 7522 boost->req = req; 7523 7524 INIT_WORK(&boost->work, __intel_rps_boost_work); 7525 queue_work(to_i915(dev)->wq, &boost->work); 7526 } 7527 7528 void intel_pm_setup(struct drm_device *dev) 7529 { 7530 struct drm_i915_private *dev_priv = dev->dev_private; 7531 7532 mutex_init(&dev_priv->rps.hw_lock); 7533 spin_lock_init(&dev_priv->rps.client_lock); 7534 7535 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7536 intel_gen6_powersave_work); 7537 INIT_LIST_HEAD(&dev_priv->rps.clients); 7538 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7539 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7540 7541 dev_priv->pm.suspended = false; 7542 } 7543
Indexes created Sat Oct 11 19:10:01 GMT 2025