intel_pm.c revision 1.3
1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 25 * 26 */ 27 28 #include <linux/cpufreq.h> 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 #ifndef __NetBSD__ 32 #include "../../../platform/x86/intel_ips.h" 33 #endif 34 #include <linux/module.h> 35 #include <linux/kgdb.h> 36 #include <linux/log2.h> 37 #include <linux/math64.h> 38 #include <linux/time.h> 39 #include <asm/param.h> 40 #include <linux/vgaarb.h> 41 #include <drm/i915_powerwell.h> 42 #include <linux/pm_runtime.h> 43 44 /** 45 * RC6 is a special power stage which allows the GPU to enter an very 46 * low-voltage mode when idle, using down to 0V while at this stage. This 47 * stage is entered automatically when the GPU is idle when RC6 support is 48 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 49 * 50 * There are different RC6 modes available in Intel GPU, which differentiate 51 * among each other with the latency required to enter and leave RC6 and 52 * voltage consumed by the GPU in different states. 53 * 54 * The combination of the following flags define which states GPU is allowed 55 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 56 * RC6pp is deepest RC6. Their support by hardware varies according to the 57 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 58 * which brings the most power savings; deeper states save more power, but 59 * require higher latency to switch to and wake up. 60 */ 61 #define INTEL_RC6_ENABLE (1<<0) 62 #define INTEL_RC6p_ENABLE (1<<1) 63 #define INTEL_RC6pp_ENABLE (1<<2) 64 65 /* FBC, or Frame Buffer Compression, is a technique employed to compress the 66 * framebuffer contents in-memory, aiming at reducing the required bandwidth 67 * during in-memory transfers and, therefore, reduce the power packet. 68 * 69 * The benefits of FBC are mostly visible with solid backgrounds and 70 * variation-less patterns. 71 * 72 * FBC-related functionality can be enabled by the means of the 73 * i915.i915_enable_fbc parameter 74 */ 75 76 static void i8xx_disable_fbc(struct drm_device *dev) 77 { 78 struct drm_i915_private *dev_priv = dev->dev_private; 79 u32 fbc_ctl; 80 81 /* Disable compression */ 82 fbc_ctl = I915_READ(FBC_CONTROL); 83 if ((fbc_ctl & FBC_CTL_EN) == 0) 84 return; 85 86 fbc_ctl &= ~FBC_CTL_EN; 87 I915_WRITE(FBC_CONTROL, fbc_ctl); 88 89 /* Wait for compressing bit to clear */ 90 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 91 DRM_DEBUG_KMS("FBC idle timed out\n"); 92 return; 93 } 94 95 DRM_DEBUG_KMS("disabled FBC\n"); 96 } 97 98 static void i8xx_enable_fbc(struct drm_crtc *crtc) 99 { 100 struct drm_device *dev = crtc->dev; 101 struct drm_i915_private *dev_priv = dev->dev_private; 102 struct drm_framebuffer *fb = crtc->primary->fb; 103 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 104 struct drm_i915_gem_object *obj = intel_fb->obj; 105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 106 int cfb_pitch; 107 int i; 108 u32 fbc_ctl; 109 110 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; 111 if (fb->pitches[0] < cfb_pitch) 112 cfb_pitch = fb->pitches[0]; 113 114 /* FBC_CTL wants 32B or 64B units */ 115 if (IS_GEN2(dev)) 116 cfb_pitch = (cfb_pitch / 32) - 1; 117 else 118 cfb_pitch = (cfb_pitch / 64) - 1; 119 120 /* Clear old tags */ 121 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 122 I915_WRITE(FBC_TAG + (i * 4), 0); 123 124 if (IS_GEN4(dev)) { 125 u32 fbc_ctl2; 126 127 /* Set it up... */ 128 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 129 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); 130 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 131 I915_WRITE(FBC_FENCE_OFF, crtc->y); 132 } 133 134 /* enable it... */ 135 fbc_ctl = I915_READ(FBC_CONTROL); 136 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; 137 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; 138 if (IS_I945GM(dev)) 139 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 140 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 141 fbc_ctl |= obj->fence_reg; 142 I915_WRITE(FBC_CONTROL, fbc_ctl); 143 144 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", 145 cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); 146 } 147 148 static bool i8xx_fbc_enabled(struct drm_device *dev) 149 { 150 struct drm_i915_private *dev_priv = dev->dev_private; 151 152 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 153 } 154 155 static void g4x_enable_fbc(struct drm_crtc *crtc) 156 { 157 struct drm_device *dev = crtc->dev; 158 struct drm_i915_private *dev_priv = dev->dev_private; 159 struct drm_framebuffer *fb = crtc->primary->fb; 160 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 161 struct drm_i915_gem_object *obj = intel_fb->obj; 162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 163 u32 dpfc_ctl; 164 165 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; 166 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 167 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 168 else 169 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 170 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 171 172 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 173 174 /* enable it... */ 175 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 176 177 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 178 } 179 180 static void g4x_disable_fbc(struct drm_device *dev) 181 { 182 struct drm_i915_private *dev_priv = dev->dev_private; 183 u32 dpfc_ctl; 184 185 /* Disable compression */ 186 dpfc_ctl = I915_READ(DPFC_CONTROL); 187 if (dpfc_ctl & DPFC_CTL_EN) { 188 dpfc_ctl &= ~DPFC_CTL_EN; 189 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 190 191 DRM_DEBUG_KMS("disabled FBC\n"); 192 } 193 } 194 195 static bool g4x_fbc_enabled(struct drm_device *dev) 196 { 197 struct drm_i915_private *dev_priv = dev->dev_private; 198 199 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 200 } 201 202 static void sandybridge_blit_fbc_update(struct drm_device *dev) 203 { 204 struct drm_i915_private *dev_priv = dev->dev_private; 205 u32 blt_ecoskpd; 206 207 /* Make sure blitter notifies FBC of writes */ 208 209 /* Blitter is part of Media powerwell on VLV. No impact of 210 * his param in other platforms for now */ 211 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); 212 213 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 214 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 215 GEN6_BLITTER_LOCK_SHIFT; 216 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 217 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 218 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 219 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 220 GEN6_BLITTER_LOCK_SHIFT); 221 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 222 POSTING_READ(GEN6_BLITTER_ECOSKPD); 223 224 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); 225 } 226 227 static void ironlake_enable_fbc(struct drm_crtc *crtc) 228 { 229 struct drm_device *dev = crtc->dev; 230 struct drm_i915_private *dev_priv = dev->dev_private; 231 struct drm_framebuffer *fb = crtc->primary->fb; 232 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 233 struct drm_i915_gem_object *obj = intel_fb->obj; 234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 235 u32 dpfc_ctl; 236 237 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); 238 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 239 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 240 else 241 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 242 dpfc_ctl |= DPFC_CTL_FENCE_EN; 243 if (IS_GEN5(dev)) 244 dpfc_ctl |= obj->fence_reg; 245 246 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 247 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); 248 /* enable it... */ 249 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 250 251 if (IS_GEN6(dev)) { 252 I915_WRITE(SNB_DPFC_CTL_SA, 253 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 254 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 255 sandybridge_blit_fbc_update(dev); 256 } 257 258 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 259 } 260 261 static void ironlake_disable_fbc(struct drm_device *dev) 262 { 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 u32 dpfc_ctl; 265 266 /* Disable compression */ 267 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 268 if (dpfc_ctl & DPFC_CTL_EN) { 269 dpfc_ctl &= ~DPFC_CTL_EN; 270 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 271 272 DRM_DEBUG_KMS("disabled FBC\n"); 273 } 274 } 275 276 static bool ironlake_fbc_enabled(struct drm_device *dev) 277 { 278 struct drm_i915_private *dev_priv = dev->dev_private; 279 280 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 281 } 282 283 static void gen7_enable_fbc(struct drm_crtc *crtc) 284 { 285 struct drm_device *dev = crtc->dev; 286 struct drm_i915_private *dev_priv = dev->dev_private; 287 struct drm_framebuffer *fb = crtc->primary->fb; 288 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 289 struct drm_i915_gem_object *obj = intel_fb->obj; 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 291 u32 dpfc_ctl; 292 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); 294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) 295 dpfc_ctl |= DPFC_CTL_LIMIT_2X; 296 else 297 dpfc_ctl |= DPFC_CTL_LIMIT_1X; 298 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; 299 300 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 301 302 if (IS_IVYBRIDGE(dev)) { 303 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 304 I915_WRITE(ILK_DISPLAY_CHICKEN1, 305 I915_READ(ILK_DISPLAY_CHICKEN1) | 306 ILK_FBCQ_DIS); 307 } else { 308 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 309 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), 310 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | 311 HSW_FBCQ_DIS); 312 } 313 314 I915_WRITE(SNB_DPFC_CTL_SA, 315 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 316 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 317 318 sandybridge_blit_fbc_update(dev); 319 320 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 321 } 322 323 bool intel_fbc_enabled(struct drm_device *dev) 324 { 325 struct drm_i915_private *dev_priv = dev->dev_private; 326 327 if (!dev_priv->display.fbc_enabled) 328 return false; 329 330 return dev_priv->display.fbc_enabled(dev); 331 } 332 333 static void intel_fbc_work_fn(struct work_struct *__work) 334 { 335 struct intel_fbc_work *work = 336 container_of(to_delayed_work(__work), 337 struct intel_fbc_work, work); 338 struct drm_device *dev = work->crtc->dev; 339 struct drm_i915_private *dev_priv = dev->dev_private; 340 341 mutex_lock(&dev->struct_mutex); 342 if (work == dev_priv->fbc.fbc_work) { 343 /* Double check that we haven't switched fb without cancelling 344 * the prior work. 345 */ 346 if (work->crtc->primary->fb == work->fb) { 347 dev_priv->display.enable_fbc(work->crtc); 348 349 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; 350 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; 351 dev_priv->fbc.y = work->crtc->y; 352 } 353 354 dev_priv->fbc.fbc_work = NULL; 355 } 356 mutex_unlock(&dev->struct_mutex); 357 358 kfree(work); 359 } 360 361 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 362 { 363 if (dev_priv->fbc.fbc_work == NULL) 364 return; 365 366 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 367 368 /* Synchronisation is provided by struct_mutex and checking of 369 * dev_priv->fbc.fbc_work, so we can perform the cancellation 370 * entirely asynchronously. 371 */ 372 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) 373 /* tasklet was killed before being run, clean up */ 374 kfree(dev_priv->fbc.fbc_work); 375 376 /* Mark the work as no longer wanted so that if it does 377 * wake-up (because the work was already running and waiting 378 * for our mutex), it will discover that is no longer 379 * necessary to run. 380 */ 381 dev_priv->fbc.fbc_work = NULL; 382 } 383 384 static void intel_enable_fbc(struct drm_crtc *crtc) 385 { 386 struct intel_fbc_work *work; 387 struct drm_device *dev = crtc->dev; 388 struct drm_i915_private *dev_priv = dev->dev_private; 389 390 if (!dev_priv->display.enable_fbc) 391 return; 392 393 intel_cancel_fbc_work(dev_priv); 394 395 work = kzalloc(sizeof(*work), GFP_KERNEL); 396 if (work == NULL) { 397 DRM_ERROR("Failed to allocate FBC work structure\n"); 398 dev_priv->display.enable_fbc(crtc); 399 return; 400 } 401 402 work->crtc = crtc; 403 work->fb = crtc->primary->fb; 404 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 405 406 dev_priv->fbc.fbc_work = work; 407 408 /* Delay the actual enabling to let pageflipping cease and the 409 * display to settle before starting the compression. Note that 410 * this delay also serves a second purpose: it allows for a 411 * vblank to pass after disabling the FBC before we attempt 412 * to modify the control registers. 413 * 414 * A more complicated solution would involve tracking vblanks 415 * following the termination of the page-flipping sequence 416 * and indeed performing the enable as a co-routine and not 417 * waiting synchronously upon the vblank. 418 * 419 * WaFbcWaitForVBlankBeforeEnable:ilk,snb 420 */ 421 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 422 } 423 424 void intel_disable_fbc(struct drm_device *dev) 425 { 426 struct drm_i915_private *dev_priv = dev->dev_private; 427 428 intel_cancel_fbc_work(dev_priv); 429 430 if (!dev_priv->display.disable_fbc) 431 return; 432 433 dev_priv->display.disable_fbc(dev); 434 dev_priv->fbc.plane = -1; 435 } 436 437 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, 438 enum no_fbc_reason reason) 439 { 440 if (dev_priv->fbc.no_fbc_reason == reason) 441 return false; 442 443 dev_priv->fbc.no_fbc_reason = reason; 444 return true; 445 } 446 447 /** 448 * intel_update_fbc - enable/disable FBC as needed 449 * @dev: the drm_device 450 * 451 * Set up the framebuffer compression hardware at mode set time. We 452 * enable it if possible: 453 * - plane A only (on pre-965) 454 * - no pixel mulitply/line duplication 455 * - no alpha buffer discard 456 * - no dual wide 457 * - framebuffer <= max_hdisplay in width, max_vdisplay in height 458 * 459 * We can't assume that any compression will take place (worst case), 460 * so the compressed buffer has to be the same size as the uncompressed 461 * one. It also must reside (along with the line length buffer) in 462 * stolen memory. 463 * 464 * We need to enable/disable FBC on a global basis. 465 */ 466 void intel_update_fbc(struct drm_device *dev) 467 { 468 struct drm_i915_private *dev_priv = dev->dev_private; 469 struct drm_crtc *crtc = NULL, *tmp_crtc; 470 struct intel_crtc *intel_crtc; 471 struct drm_framebuffer *fb; 472 struct intel_framebuffer *intel_fb; 473 struct drm_i915_gem_object *obj; 474 const struct drm_display_mode *adjusted_mode; 475 unsigned int max_width, max_height; 476 477 if (!HAS_FBC(dev)) { 478 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); 479 return; 480 } 481 482 if (!i915.powersave) { 483 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) 484 DRM_DEBUG_KMS("fbc disabled per module param\n"); 485 return; 486 } 487 488 /* 489 * If FBC is already on, we just have to verify that we can 490 * keep it that way... 491 * Need to disable if: 492 * - more than one pipe is active 493 * - changing FBC params (stride, fence, mode) 494 * - new fb is too large to fit in compressed buffer 495 * - going to an unsupported config (interlace, pixel multiply, etc.) 496 */ 497 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 498 if (intel_crtc_active(tmp_crtc) && 499 to_intel_crtc(tmp_crtc)->primary_enabled) { 500 if (crtc) { 501 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) 502 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 503 goto out_disable; 504 } 505 crtc = tmp_crtc; 506 } 507 } 508 509 if (!crtc || crtc->primary->fb == NULL) { 510 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) 511 DRM_DEBUG_KMS("no output, disabling\n"); 512 goto out_disable; 513 } 514 515 intel_crtc = to_intel_crtc(crtc); 516 fb = crtc->primary->fb; 517 intel_fb = to_intel_framebuffer(fb); 518 obj = intel_fb->obj; 519 adjusted_mode = &intel_crtc->config.adjusted_mode; 520 521 if (i915.enable_fbc < 0 && 522 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { 523 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 524 DRM_DEBUG_KMS("disabled per chip default\n"); 525 goto out_disable; 526 } 527 if (!i915.enable_fbc) { 528 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) 529 DRM_DEBUG_KMS("fbc disabled per module param\n"); 530 goto out_disable; 531 } 532 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || 533 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 534 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) 535 DRM_DEBUG_KMS("mode incompatible with compression, " 536 "disabling\n"); 537 goto out_disable; 538 } 539 540 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 541 max_width = 4096; 542 max_height = 2048; 543 } else { 544 max_width = 2048; 545 max_height = 1536; 546 } 547 if (intel_crtc->config.pipe_src_w > max_width || 548 intel_crtc->config.pipe_src_h > max_height) { 549 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) 550 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 551 goto out_disable; 552 } 553 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && 554 intel_crtc->plane != PLANE_A) { 555 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) 556 DRM_DEBUG_KMS("plane not A, disabling compression\n"); 557 goto out_disable; 558 } 559 560 /* The use of a CPU fence is mandatory in order to detect writes 561 * by the CPU to the scanout and trigger updates to the FBC. 562 */ 563 if (obj->tiling_mode != I915_TILING_X || 564 obj->fence_reg == I915_FENCE_REG_NONE) { 565 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) 566 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 567 goto out_disable; 568 } 569 570 /* If the kernel debugger is active, always disable compression */ 571 if (in_dbg_master()) 572 goto out_disable; 573 574 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { 575 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) 576 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); 577 goto out_disable; 578 } 579 580 /* If the scanout has not changed, don't modify the FBC settings. 581 * Note that we make the fundamental assumption that the fb->obj 582 * cannot be unpinned (and have its GTT offset and fence revoked) 583 * without first being decoupled from the scanout and FBC disabled. 584 */ 585 if (dev_priv->fbc.plane == intel_crtc->plane && 586 dev_priv->fbc.fb_id == fb->base.id && 587 dev_priv->fbc.y == crtc->y) 588 return; 589 590 if (intel_fbc_enabled(dev)) { 591 /* We update FBC along two paths, after changing fb/crtc 592 * configuration (modeswitching) and after page-flipping 593 * finishes. For the latter, we know that not only did 594 * we disable the FBC at the start of the page-flip 595 * sequence, but also more than one vblank has passed. 596 * 597 * For the former case of modeswitching, it is possible 598 * to switch between two FBC valid configurations 599 * instantaneously so we do need to disable the FBC 600 * before we can modify its control registers. We also 601 * have to wait for the next vblank for that to take 602 * effect. However, since we delay enabling FBC we can 603 * assume that a vblank has passed since disabling and 604 * that we can safely alter the registers in the deferred 605 * callback. 606 * 607 * In the scenario that we go from a valid to invalid 608 * and then back to valid FBC configuration we have 609 * no strict enforcement that a vblank occurred since 610 * disabling the FBC. However, along all current pipe 611 * disabling paths we do need to wait for a vblank at 612 * some point. And we wait before enabling FBC anyway. 613 */ 614 DRM_DEBUG_KMS("disabling active FBC for update\n"); 615 intel_disable_fbc(dev); 616 } 617 618 intel_enable_fbc(crtc); 619 dev_priv->fbc.no_fbc_reason = FBC_OK; 620 return; 621 622 out_disable: 623 /* Multiple disables should be harmless */ 624 if (intel_fbc_enabled(dev)) { 625 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 626 intel_disable_fbc(dev); 627 } 628 i915_gem_stolen_cleanup_compression(dev); 629 } 630 631 static void i915_pineview_get_mem_freq(struct drm_device *dev) 632 { 633 struct drm_i915_private *dev_priv = dev->dev_private; 634 u32 tmp; 635 636 tmp = I915_READ(CLKCFG); 637 638 switch (tmp & CLKCFG_FSB_MASK) { 639 case CLKCFG_FSB_533: 640 dev_priv->fsb_freq = 533; /* 133*4 */ 641 break; 642 case CLKCFG_FSB_800: 643 dev_priv->fsb_freq = 800; /* 200*4 */ 644 break; 645 case CLKCFG_FSB_667: 646 dev_priv->fsb_freq = 667; /* 167*4 */ 647 break; 648 case CLKCFG_FSB_400: 649 dev_priv->fsb_freq = 400; /* 100*4 */ 650 break; 651 } 652 653 switch (tmp & CLKCFG_MEM_MASK) { 654 case CLKCFG_MEM_533: 655 dev_priv->mem_freq = 533; 656 break; 657 case CLKCFG_MEM_667: 658 dev_priv->mem_freq = 667; 659 break; 660 case CLKCFG_MEM_800: 661 dev_priv->mem_freq = 800; 662 break; 663 } 664 665 /* detect pineview DDR3 setting */ 666 tmp = I915_READ(CSHRDDR3CTL); 667 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 668 } 669 670 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 671 { 672 struct drm_i915_private *dev_priv = dev->dev_private; 673 u16 ddrpll, csipll; 674 675 ddrpll = I915_READ16(DDRMPLL1); 676 csipll = I915_READ16(CSIPLL0); 677 678 switch (ddrpll & 0xff) { 679 case 0xc: 680 dev_priv->mem_freq = 800; 681 break; 682 case 0x10: 683 dev_priv->mem_freq = 1066; 684 break; 685 case 0x14: 686 dev_priv->mem_freq = 1333; 687 break; 688 case 0x18: 689 dev_priv->mem_freq = 1600; 690 break; 691 default: 692 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 693 ddrpll & 0xff); 694 dev_priv->mem_freq = 0; 695 break; 696 } 697 698 dev_priv->ips.r_t = dev_priv->mem_freq; 699 700 switch (csipll & 0x3ff) { 701 case 0x00c: 702 dev_priv->fsb_freq = 3200; 703 break; 704 case 0x00e: 705 dev_priv->fsb_freq = 3733; 706 break; 707 case 0x010: 708 dev_priv->fsb_freq = 4266; 709 break; 710 case 0x012: 711 dev_priv->fsb_freq = 4800; 712 break; 713 case 0x014: 714 dev_priv->fsb_freq = 5333; 715 break; 716 case 0x016: 717 dev_priv->fsb_freq = 5866; 718 break; 719 case 0x018: 720 dev_priv->fsb_freq = 6400; 721 break; 722 default: 723 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 724 csipll & 0x3ff); 725 dev_priv->fsb_freq = 0; 726 break; 727 } 728 729 if (dev_priv->fsb_freq == 3200) { 730 dev_priv->ips.c_m = 0; 731 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 732 dev_priv->ips.c_m = 1; 733 } else { 734 dev_priv->ips.c_m = 2; 735 } 736 } 737 738 static const struct cxsr_latency cxsr_latency_table[] = { 739 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 740 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 741 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 742 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 743 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 744 745 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 746 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 747 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 748 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 749 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 750 751 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 752 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 753 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 754 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 755 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 756 757 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 758 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 759 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 760 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 761 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 762 763 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 764 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 765 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 766 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 767 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 768 769 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 770 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 771 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 772 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 773 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 774 }; 775 776 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 777 int is_ddr3, 778 int fsb, 779 int mem) 780 { 781 const struct cxsr_latency *latency; 782 int i; 783 784 if (fsb == 0 || mem == 0) 785 return NULL; 786 787 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 788 latency = &cxsr_latency_table[i]; 789 if (is_desktop == latency->is_desktop && 790 is_ddr3 == latency->is_ddr3 && 791 fsb == latency->fsb_freq && mem == latency->mem_freq) 792 return latency; 793 } 794 795 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 796 797 return NULL; 798 } 799 800 static void pineview_disable_cxsr(struct drm_device *dev) 801 { 802 struct drm_i915_private *dev_priv = dev->dev_private; 803 804 /* deactivate cxsr */ 805 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 806 } 807 808 /* 809 * Latency for FIFO fetches is dependent on several factors: 810 * - memory configuration (speed, channels) 811 * - chipset 812 * - current MCH state 813 * It can be fairly high in some situations, so here we assume a fairly 814 * pessimal value. It's a tradeoff between extra memory fetches (if we 815 * set this value too high, the FIFO will fetch frequently to stay full) 816 * and power consumption (set it too low to save power and we might see 817 * FIFO underruns and display "flicker"). 818 * 819 * A value of 5us seems to be a good balance; safe for very low end 820 * platforms but not overly aggressive on lower latency configs. 821 */ 822 static const int latency_ns = 5000; 823 824 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 825 { 826 struct drm_i915_private *dev_priv = dev->dev_private; 827 uint32_t dsparb = I915_READ(DSPARB); 828 int size; 829 830 size = dsparb & 0x7f; 831 if (plane) 832 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 833 834 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 835 plane ? "B" : "A", size); 836 837 return size; 838 } 839 840 static int i830_get_fifo_size(struct drm_device *dev, int plane) 841 { 842 struct drm_i915_private *dev_priv = dev->dev_private; 843 uint32_t dsparb = I915_READ(DSPARB); 844 int size; 845 846 size = dsparb & 0x1ff; 847 if (plane) 848 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 849 size >>= 1; /* Convert to cachelines */ 850 851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 852 plane ? "B" : "A", size); 853 854 return size; 855 } 856 857 static int i845_get_fifo_size(struct drm_device *dev, int plane) 858 { 859 struct drm_i915_private *dev_priv = dev->dev_private; 860 uint32_t dsparb = I915_READ(DSPARB); 861 int size; 862 863 size = dsparb & 0x7f; 864 size >>= 2; /* Convert to cachelines */ 865 866 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 867 plane ? "B" : "A", 868 size); 869 870 return size; 871 } 872 873 /* Pineview has different values for various configs */ 874 static const struct intel_watermark_params pineview_display_wm = { 875 PINEVIEW_DISPLAY_FIFO, 876 PINEVIEW_MAX_WM, 877 PINEVIEW_DFT_WM, 878 PINEVIEW_GUARD_WM, 879 PINEVIEW_FIFO_LINE_SIZE 880 }; 881 static const struct intel_watermark_params pineview_display_hplloff_wm = { 882 PINEVIEW_DISPLAY_FIFO, 883 PINEVIEW_MAX_WM, 884 PINEVIEW_DFT_HPLLOFF_WM, 885 PINEVIEW_GUARD_WM, 886 PINEVIEW_FIFO_LINE_SIZE 887 }; 888 static const struct intel_watermark_params pineview_cursor_wm = { 889 PINEVIEW_CURSOR_FIFO, 890 PINEVIEW_CURSOR_MAX_WM, 891 PINEVIEW_CURSOR_DFT_WM, 892 PINEVIEW_CURSOR_GUARD_WM, 893 PINEVIEW_FIFO_LINE_SIZE, 894 }; 895 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 896 PINEVIEW_CURSOR_FIFO, 897 PINEVIEW_CURSOR_MAX_WM, 898 PINEVIEW_CURSOR_DFT_WM, 899 PINEVIEW_CURSOR_GUARD_WM, 900 PINEVIEW_FIFO_LINE_SIZE 901 }; 902 static const struct intel_watermark_params g4x_wm_info = { 903 G4X_FIFO_SIZE, 904 G4X_MAX_WM, 905 G4X_MAX_WM, 906 2, 907 G4X_FIFO_LINE_SIZE, 908 }; 909 static const struct intel_watermark_params g4x_cursor_wm_info = { 910 I965_CURSOR_FIFO, 911 I965_CURSOR_MAX_WM, 912 I965_CURSOR_DFT_WM, 913 2, 914 G4X_FIFO_LINE_SIZE, 915 }; 916 static const struct intel_watermark_params valleyview_wm_info = { 917 VALLEYVIEW_FIFO_SIZE, 918 VALLEYVIEW_MAX_WM, 919 VALLEYVIEW_MAX_WM, 920 2, 921 G4X_FIFO_LINE_SIZE, 922 }; 923 static const struct intel_watermark_params valleyview_cursor_wm_info = { 924 I965_CURSOR_FIFO, 925 VALLEYVIEW_CURSOR_MAX_WM, 926 I965_CURSOR_DFT_WM, 927 2, 928 G4X_FIFO_LINE_SIZE, 929 }; 930 static const struct intel_watermark_params i965_cursor_wm_info = { 931 I965_CURSOR_FIFO, 932 I965_CURSOR_MAX_WM, 933 I965_CURSOR_DFT_WM, 934 2, 935 I915_FIFO_LINE_SIZE, 936 }; 937 static const struct intel_watermark_params i945_wm_info = { 938 I945_FIFO_SIZE, 939 I915_MAX_WM, 940 1, 941 2, 942 I915_FIFO_LINE_SIZE 943 }; 944 static const struct intel_watermark_params i915_wm_info = { 945 I915_FIFO_SIZE, 946 I915_MAX_WM, 947 1, 948 2, 949 I915_FIFO_LINE_SIZE 950 }; 951 static const struct intel_watermark_params i830_wm_info = { 952 I855GM_FIFO_SIZE, 953 I915_MAX_WM, 954 1, 955 2, 956 I830_FIFO_LINE_SIZE 957 }; 958 static const struct intel_watermark_params i845_wm_info = { 959 I830_FIFO_SIZE, 960 I915_MAX_WM, 961 1, 962 2, 963 I830_FIFO_LINE_SIZE 964 }; 965 966 /** 967 * intel_calculate_wm - calculate watermark level 968 * @clock_in_khz: pixel clock 969 * @wm: chip FIFO params 970 * @pixel_size: display pixel size 971 * @latency_ns: memory latency for the platform 972 * 973 * Calculate the watermark level (the level at which the display plane will 974 * start fetching from memory again). Each chip has a different display 975 * FIFO size and allocation, so the caller needs to figure that out and pass 976 * in the correct intel_watermark_params structure. 977 * 978 * As the pixel clock runs, the FIFO will be drained at a rate that depends 979 * on the pixel size. When it reaches the watermark level, it'll start 980 * fetching FIFO line sized based chunks from memory until the FIFO fills 981 * past the watermark point. If the FIFO drains completely, a FIFO underrun 982 * will occur, and a display engine hang could result. 983 */ 984 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 985 const struct intel_watermark_params *wm, 986 int fifo_size, 987 int pixel_size, 988 unsigned long latency_ns) 989 { 990 long entries_required, wm_size; 991 992 /* 993 * Note: we need to make sure we don't overflow for various clock & 994 * latency values. 995 * clocks go from a few thousand to several hundred thousand. 996 * latency is usually a few thousand 997 */ 998 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 999 1000; 1000 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 1001 1002 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 1003 1004 wm_size = fifo_size - (entries_required + wm->guard_size); 1005 1006 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 1007 1008 /* Don't promote wm_size to unsigned... */ 1009 if (wm_size > (long)wm->max_wm) 1010 wm_size = wm->max_wm; 1011 if (wm_size <= 0) 1012 wm_size = wm->default_wm; 1013 return wm_size; 1014 } 1015 1016 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 1017 { 1018 struct drm_crtc *crtc, *enabled = NULL; 1019 1020 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1021 if (intel_crtc_active(crtc)) { 1022 if (enabled) 1023 return NULL; 1024 enabled = crtc; 1025 } 1026 } 1027 1028 return enabled; 1029 } 1030 1031 static void pineview_update_wm(struct drm_crtc *unused_crtc) 1032 { 1033 struct drm_device *dev = unused_crtc->dev; 1034 struct drm_i915_private *dev_priv = dev->dev_private; 1035 struct drm_crtc *crtc; 1036 const struct cxsr_latency *latency; 1037 u32 reg; 1038 unsigned long wm; 1039 1040 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 1041 dev_priv->fsb_freq, dev_priv->mem_freq); 1042 if (!latency) { 1043 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 1044 pineview_disable_cxsr(dev); 1045 return; 1046 } 1047 1048 crtc = single_enabled_crtc(dev); 1049 if (crtc) { 1050 const struct drm_display_mode *adjusted_mode; 1051 int pixel_size = crtc->primary->fb->bits_per_pixel / 8; 1052 int clock; 1053 1054 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1055 clock = adjusted_mode->crtc_clock; 1056 1057 /* Display SR */ 1058 wm = intel_calculate_wm(clock, &pineview_display_wm, 1059 pineview_display_wm.fifo_size, 1060 pixel_size, latency->display_sr); 1061 reg = I915_READ(DSPFW1); 1062 reg &= ~DSPFW_SR_MASK; 1063 reg |= wm << DSPFW_SR_SHIFT; 1064 I915_WRITE(DSPFW1, reg); 1065 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1066 1067 /* cursor SR */ 1068 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1069 pineview_display_wm.fifo_size, 1070 pixel_size, latency->cursor_sr); 1071 reg = I915_READ(DSPFW3); 1072 reg &= ~DSPFW_CURSOR_SR_MASK; 1073 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1074 I915_WRITE(DSPFW3, reg); 1075 1076 /* Display HPLL off SR */ 1077 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1078 pineview_display_hplloff_wm.fifo_size, 1079 pixel_size, latency->display_hpll_disable); 1080 reg = I915_READ(DSPFW3); 1081 reg &= ~DSPFW_HPLL_SR_MASK; 1082 reg |= wm & DSPFW_HPLL_SR_MASK; 1083 I915_WRITE(DSPFW3, reg); 1084 1085 /* cursor HPLL off SR */ 1086 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1087 pineview_display_hplloff_wm.fifo_size, 1088 pixel_size, latency->cursor_hpll_disable); 1089 reg = I915_READ(DSPFW3); 1090 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1091 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1092 I915_WRITE(DSPFW3, reg); 1093 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1094 1095 /* activate cxsr */ 1096 I915_WRITE(DSPFW3, 1097 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1098 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1099 } else { 1100 pineview_disable_cxsr(dev); 1101 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1102 } 1103 } 1104 1105 static bool g4x_compute_wm0(struct drm_device *dev, 1106 int plane, 1107 const struct intel_watermark_params *display, 1108 int display_latency_ns, 1109 const struct intel_watermark_params *cursor, 1110 int cursor_latency_ns, 1111 int *plane_wm, 1112 int *cursor_wm) 1113 { 1114 struct drm_crtc *crtc; 1115 const struct drm_display_mode *adjusted_mode; 1116 int htotal, hdisplay, clock, pixel_size; 1117 int line_time_us, line_count; 1118 int entries, tlb_miss; 1119 1120 crtc = intel_get_crtc_for_plane(dev, plane); 1121 if (!intel_crtc_active(crtc)) { 1122 *cursor_wm = cursor->guard_size; 1123 *plane_wm = display->guard_size; 1124 return false; 1125 } 1126 1127 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1128 clock = adjusted_mode->crtc_clock; 1129 htotal = adjusted_mode->crtc_htotal; 1130 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1131 pixel_size = crtc->primary->fb->bits_per_pixel / 8; 1132 1133 /* Use the small buffer method to calculate plane watermark */ 1134 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1135 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1136 if (tlb_miss > 0) 1137 entries += tlb_miss; 1138 entries = DIV_ROUND_UP(entries, display->cacheline_size); 1139 *plane_wm = entries + display->guard_size; 1140 if (*plane_wm > (int)display->max_wm) 1141 *plane_wm = display->max_wm; 1142 1143 /* Use the large buffer method to calculate cursor watermark */ 1144 line_time_us = max(htotal * 1000 / clock, 1); 1145 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1146 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; 1147 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1148 if (tlb_miss > 0) 1149 entries += tlb_miss; 1150 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1151 *cursor_wm = entries + cursor->guard_size; 1152 if (*cursor_wm > (int)cursor->max_wm) 1153 *cursor_wm = (int)cursor->max_wm; 1154 1155 return true; 1156 } 1157 1158 /* 1159 * Check the wm result. 1160 * 1161 * If any calculated watermark values is larger than the maximum value that 1162 * can be programmed into the associated watermark register, that watermark 1163 * must be disabled. 1164 */ 1165 static bool g4x_check_srwm(struct drm_device *dev, 1166 int display_wm, int cursor_wm, 1167 const struct intel_watermark_params *display, 1168 const struct intel_watermark_params *cursor) 1169 { 1170 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1171 display_wm, cursor_wm); 1172 1173 if (display_wm > display->max_wm) { 1174 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1175 display_wm, display->max_wm); 1176 return false; 1177 } 1178 1179 if (cursor_wm > cursor->max_wm) { 1180 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1181 cursor_wm, cursor->max_wm); 1182 return false; 1183 } 1184 1185 if (!(display_wm || cursor_wm)) { 1186 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1187 return false; 1188 } 1189 1190 return true; 1191 } 1192 1193 static bool g4x_compute_srwm(struct drm_device *dev, 1194 int plane, 1195 int latency_ns, 1196 const struct intel_watermark_params *display, 1197 const struct intel_watermark_params *cursor, 1198 int *display_wm, int *cursor_wm) 1199 { 1200 struct drm_crtc *crtc; 1201 const struct drm_display_mode *adjusted_mode; 1202 int hdisplay, htotal, pixel_size, clock; 1203 unsigned long line_time_us; 1204 int line_count, line_size; 1205 int small, large; 1206 int entries; 1207 1208 if (!latency_ns) { 1209 *display_wm = *cursor_wm = 0; 1210 return false; 1211 } 1212 1213 crtc = intel_get_crtc_for_plane(dev, plane); 1214 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1215 clock = adjusted_mode->crtc_clock; 1216 htotal = adjusted_mode->crtc_htotal; 1217 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1218 pixel_size = crtc->primary->fb->bits_per_pixel / 8; 1219 1220 line_time_us = max(htotal * 1000 / clock, 1); 1221 line_count = (latency_ns / line_time_us + 1000) / 1000; 1222 line_size = hdisplay * pixel_size; 1223 1224 /* Use the minimum of the small and large buffer method for primary */ 1225 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1226 large = line_count * line_size; 1227 1228 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1229 *display_wm = entries + display->guard_size; 1230 1231 /* calculate the self-refresh watermark for display cursor */ 1232 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; 1233 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1234 *cursor_wm = entries + cursor->guard_size; 1235 1236 return g4x_check_srwm(dev, 1237 *display_wm, *cursor_wm, 1238 display, cursor); 1239 } 1240 1241 static bool vlv_compute_drain_latency(struct drm_device *dev, 1242 int plane, 1243 int *plane_prec_mult, 1244 int *plane_dl, 1245 int *cursor_prec_mult, 1246 int *cursor_dl) 1247 { 1248 struct drm_crtc *crtc; 1249 int clock, pixel_size; 1250 int entries; 1251 1252 crtc = intel_get_crtc_for_plane(dev, plane); 1253 if (!intel_crtc_active(crtc)) 1254 return false; 1255 1256 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; 1257 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ 1258 1259 entries = (clock / 1000) * pixel_size; 1260 *plane_prec_mult = (entries > 256) ? 1261 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1262 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * 1263 pixel_size); 1264 1265 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1266 *cursor_prec_mult = (entries > 256) ? 1267 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1268 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); 1269 1270 return true; 1271 } 1272 1273 /* 1274 * Update drain latency registers of memory arbiter 1275 * 1276 * Valleyview SoC has a new memory arbiter and needs drain latency registers 1277 * to be programmed. Each plane has a drain latency multiplier and a drain 1278 * latency value. 1279 */ 1280 1281 static void vlv_update_drain_latency(struct drm_device *dev) 1282 { 1283 struct drm_i915_private *dev_priv = dev->dev_private; 1284 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1285 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1286 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1287 either 16 or 32 */ 1288 1289 /* For plane A, Cursor A */ 1290 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1291 &cursor_prec_mult, &cursora_dl)) { 1292 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1293 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; 1294 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1295 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; 1296 1297 I915_WRITE(VLV_DDL1, cursora_prec | 1298 (cursora_dl << DDL_CURSORA_SHIFT) | 1299 planea_prec | planea_dl); 1300 } 1301 1302 /* For plane B, Cursor B */ 1303 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1304 &cursor_prec_mult, &cursorb_dl)) { 1305 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1306 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; 1307 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1308 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; 1309 1310 I915_WRITE(VLV_DDL2, cursorb_prec | 1311 (cursorb_dl << DDL_CURSORB_SHIFT) | 1312 planeb_prec | planeb_dl); 1313 } 1314 } 1315 1316 #define single_plane_enabled(mask) is_power_of_2(mask) 1317 1318 static void valleyview_update_wm(struct drm_crtc *crtc) 1319 { 1320 struct drm_device *dev = crtc->dev; 1321 static const int sr_latency_ns = 12000; 1322 struct drm_i915_private *dev_priv = dev->dev_private; 1323 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1324 int plane_sr, cursor_sr; 1325 int ignore_plane_sr, ignore_cursor_sr; 1326 unsigned int enabled = 0; 1327 1328 vlv_update_drain_latency(dev); 1329 1330 if (g4x_compute_wm0(dev, PIPE_A, 1331 &valleyview_wm_info, latency_ns, 1332 &valleyview_cursor_wm_info, latency_ns, 1333 &planea_wm, &cursora_wm)) 1334 enabled |= 1 << PIPE_A; 1335 1336 if (g4x_compute_wm0(dev, PIPE_B, 1337 &valleyview_wm_info, latency_ns, 1338 &valleyview_cursor_wm_info, latency_ns, 1339 &planeb_wm, &cursorb_wm)) 1340 enabled |= 1 << PIPE_B; 1341 1342 if (single_plane_enabled(enabled) && 1343 g4x_compute_srwm(dev, ffs(enabled) - 1, 1344 sr_latency_ns, 1345 &valleyview_wm_info, 1346 &valleyview_cursor_wm_info, 1347 &plane_sr, &ignore_cursor_sr) && 1348 g4x_compute_srwm(dev, ffs(enabled) - 1, 1349 2*sr_latency_ns, 1350 &valleyview_wm_info, 1351 &valleyview_cursor_wm_info, 1352 &ignore_plane_sr, &cursor_sr)) { 1353 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1354 } else { 1355 I915_WRITE(FW_BLC_SELF_VLV, 1356 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1357 plane_sr = cursor_sr = 0; 1358 } 1359 1360 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1361 planea_wm, cursora_wm, 1362 planeb_wm, cursorb_wm, 1363 plane_sr, cursor_sr); 1364 1365 I915_WRITE(DSPFW1, 1366 (plane_sr << DSPFW_SR_SHIFT) | 1367 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1368 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1369 planea_wm); 1370 I915_WRITE(DSPFW2, 1371 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1372 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1373 I915_WRITE(DSPFW3, 1374 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | 1375 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1376 } 1377 1378 static void g4x_update_wm(struct drm_crtc *crtc) 1379 { 1380 struct drm_device *dev = crtc->dev; 1381 static const int sr_latency_ns = 12000; 1382 struct drm_i915_private *dev_priv = dev->dev_private; 1383 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1384 int plane_sr, cursor_sr; 1385 unsigned int enabled = 0; 1386 1387 if (g4x_compute_wm0(dev, PIPE_A, 1388 &g4x_wm_info, latency_ns, 1389 &g4x_cursor_wm_info, latency_ns, 1390 &planea_wm, &cursora_wm)) 1391 enabled |= 1 << PIPE_A; 1392 1393 if (g4x_compute_wm0(dev, PIPE_B, 1394 &g4x_wm_info, latency_ns, 1395 &g4x_cursor_wm_info, latency_ns, 1396 &planeb_wm, &cursorb_wm)) 1397 enabled |= 1 << PIPE_B; 1398 1399 if (single_plane_enabled(enabled) && 1400 g4x_compute_srwm(dev, ffs(enabled) - 1, 1401 sr_latency_ns, 1402 &g4x_wm_info, 1403 &g4x_cursor_wm_info, 1404 &plane_sr, &cursor_sr)) { 1405 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1406 } else { 1407 I915_WRITE(FW_BLC_SELF, 1408 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1409 plane_sr = cursor_sr = 0; 1410 } 1411 1412 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1413 planea_wm, cursora_wm, 1414 planeb_wm, cursorb_wm, 1415 plane_sr, cursor_sr); 1416 1417 I915_WRITE(DSPFW1, 1418 (plane_sr << DSPFW_SR_SHIFT) | 1419 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1420 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1421 planea_wm); 1422 I915_WRITE(DSPFW2, 1423 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1424 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1425 /* HPLL off in SR has some issues on G4x... disable it */ 1426 I915_WRITE(DSPFW3, 1427 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1429 } 1430 1431 static void i965_update_wm(struct drm_crtc *unused_crtc) 1432 { 1433 struct drm_device *dev = unused_crtc->dev; 1434 struct drm_i915_private *dev_priv = dev->dev_private; 1435 struct drm_crtc *crtc; 1436 int srwm = 1; 1437 int cursor_sr = 16; 1438 1439 /* Calc sr entries for one plane configs */ 1440 crtc = single_enabled_crtc(dev); 1441 if (crtc) { 1442 /* self-refresh has much higher latency */ 1443 static const int sr_latency_ns = 12000; 1444 const struct drm_display_mode *adjusted_mode = 1445 &to_intel_crtc(crtc)->config.adjusted_mode; 1446 int clock = adjusted_mode->crtc_clock; 1447 int htotal = adjusted_mode->crtc_htotal; 1448 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1449 int pixel_size = crtc->primary->fb->bits_per_pixel / 8; 1450 unsigned long line_time_us; 1451 int entries; 1452 1453 line_time_us = max(htotal * 1000 / clock, 1); 1454 1455 /* Use ns/us then divide to preserve precision */ 1456 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1457 pixel_size * hdisplay; 1458 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1459 srwm = I965_FIFO_SIZE - entries; 1460 if (srwm < 0) 1461 srwm = 1; 1462 srwm &= 0x1ff; 1463 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1464 entries, srwm); 1465 1466 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1467 pixel_size * to_intel_crtc(crtc)->cursor_width; 1468 entries = DIV_ROUND_UP(entries, 1469 i965_cursor_wm_info.cacheline_size); 1470 cursor_sr = i965_cursor_wm_info.fifo_size - 1471 (entries + i965_cursor_wm_info.guard_size); 1472 1473 if (cursor_sr > i965_cursor_wm_info.max_wm) 1474 cursor_sr = i965_cursor_wm_info.max_wm; 1475 1476 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1477 "cursor %d\n", srwm, cursor_sr); 1478 1479 if (IS_CRESTLINE(dev)) 1480 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1481 } else { 1482 /* Turn off self refresh if both pipes are enabled */ 1483 if (IS_CRESTLINE(dev)) 1484 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1485 & ~FW_BLC_SELF_EN); 1486 } 1487 1488 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1489 srwm); 1490 1491 /* 965 has limitations... */ 1492 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1493 (8 << 16) | (8 << 8) | (8 << 0)); 1494 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1495 /* update cursor SR watermark */ 1496 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1497 } 1498 1499 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1500 { 1501 struct drm_device *dev = unused_crtc->dev; 1502 struct drm_i915_private *dev_priv = dev->dev_private; 1503 const struct intel_watermark_params *wm_info; 1504 uint32_t fwater_lo; 1505 uint32_t fwater_hi; 1506 int cwm, srwm = 1; 1507 int fifo_size; 1508 int planea_wm, planeb_wm; 1509 struct drm_crtc *crtc, *enabled = NULL; 1510 1511 if (IS_I945GM(dev)) 1512 wm_info = &i945_wm_info; 1513 else if (!IS_GEN2(dev)) 1514 wm_info = &i915_wm_info; 1515 else 1516 wm_info = &i830_wm_info; 1517 1518 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1519 crtc = intel_get_crtc_for_plane(dev, 0); 1520 if (intel_crtc_active(crtc)) { 1521 const struct drm_display_mode *adjusted_mode; 1522 int cpp = crtc->primary->fb->bits_per_pixel / 8; 1523 if (IS_GEN2(dev)) 1524 cpp = 4; 1525 1526 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1527 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1528 wm_info, fifo_size, cpp, 1529 latency_ns); 1530 enabled = crtc; 1531 } else 1532 planea_wm = fifo_size - wm_info->guard_size; 1533 1534 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1535 crtc = intel_get_crtc_for_plane(dev, 1); 1536 if (intel_crtc_active(crtc)) { 1537 const struct drm_display_mode *adjusted_mode; 1538 int cpp = crtc->primary->fb->bits_per_pixel / 8; 1539 if (IS_GEN2(dev)) 1540 cpp = 4; 1541 1542 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1543 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1544 wm_info, fifo_size, cpp, 1545 latency_ns); 1546 if (enabled == NULL) 1547 enabled = crtc; 1548 else 1549 enabled = NULL; 1550 } else 1551 planeb_wm = fifo_size - wm_info->guard_size; 1552 1553 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1554 1555 if (IS_I915GM(dev) && enabled) { 1556 struct intel_framebuffer *fb; 1557 1558 fb = to_intel_framebuffer(enabled->primary->fb); 1559 1560 /* self-refresh seems busted with untiled */ 1561 if (fb->obj->tiling_mode == I915_TILING_NONE) 1562 enabled = NULL; 1563 } 1564 1565 /* 1566 * Overlay gets an aggressive default since video jitter is bad. 1567 */ 1568 cwm = 2; 1569 1570 /* Play safe and disable self-refresh before adjusting watermarks. */ 1571 if (IS_I945G(dev) || IS_I945GM(dev)) 1572 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1573 else if (IS_I915GM(dev)) 1574 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN)); 1575 1576 /* Calc sr entries for one plane configs */ 1577 if (HAS_FW_BLC(dev) && enabled) { 1578 /* self-refresh has much higher latency */ 1579 static const int sr_latency_ns = 6000; 1580 const struct drm_display_mode *adjusted_mode = 1581 &to_intel_crtc(enabled)->config.adjusted_mode; 1582 int clock = adjusted_mode->crtc_clock; 1583 int htotal = adjusted_mode->crtc_htotal; 1584 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; 1585 int pixel_size = enabled->primary->fb->bits_per_pixel / 8; 1586 unsigned long line_time_us; 1587 int entries; 1588 1589 line_time_us = max(htotal * 1000 / clock, 1); 1590 1591 /* Use ns/us then divide to preserve precision */ 1592 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1593 pixel_size * hdisplay; 1594 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1595 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1596 srwm = wm_info->fifo_size - entries; 1597 if (srwm < 0) 1598 srwm = 1; 1599 1600 if (IS_I945G(dev) || IS_I945GM(dev)) 1601 I915_WRITE(FW_BLC_SELF, 1602 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1603 else if (IS_I915GM(dev)) 1604 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1605 } 1606 1607 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1608 planea_wm, planeb_wm, cwm, srwm); 1609 1610 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1611 fwater_hi = (cwm & 0x1f); 1612 1613 /* Set request length to 8 cachelines per fetch */ 1614 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1615 fwater_hi = fwater_hi | (1 << 8); 1616 1617 I915_WRITE(FW_BLC, fwater_lo); 1618 I915_WRITE(FW_BLC2, fwater_hi); 1619 1620 if (HAS_FW_BLC(dev)) { 1621 if (enabled) { 1622 if (IS_I945G(dev) || IS_I945GM(dev)) 1623 I915_WRITE(FW_BLC_SELF, 1624 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1625 else if (IS_I915GM(dev)) 1626 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN)); 1627 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1628 } else 1629 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1630 } 1631 } 1632 1633 static void i845_update_wm(struct drm_crtc *unused_crtc) 1634 { 1635 struct drm_device *dev = unused_crtc->dev; 1636 struct drm_i915_private *dev_priv = dev->dev_private; 1637 struct drm_crtc *crtc; 1638 const struct drm_display_mode *adjusted_mode; 1639 uint32_t fwater_lo; 1640 int planea_wm; 1641 1642 crtc = single_enabled_crtc(dev); 1643 if (crtc == NULL) 1644 return; 1645 1646 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1647 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1648 &i845_wm_info, 1649 dev_priv->display.get_fifo_size(dev, 0), 1650 4, latency_ns); 1651 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1652 fwater_lo |= (3<<8) | planea_wm; 1653 1654 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1655 1656 I915_WRITE(FW_BLC, fwater_lo); 1657 } 1658 1659 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, 1660 struct drm_crtc *crtc) 1661 { 1662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1663 uint32_t pixel_rate; 1664 1665 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; 1666 1667 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1668 * adjust the pixel_rate here. */ 1669 1670 if (intel_crtc->config.pch_pfit.enabled) { 1671 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1672 uint32_t pfit_size = intel_crtc->config.pch_pfit.size; 1673 1674 pipe_w = intel_crtc->config.pipe_src_w; 1675 pipe_h = intel_crtc->config.pipe_src_h; 1676 pfit_w = (pfit_size >> 16) & 0xFFFF; 1677 pfit_h = pfit_size & 0xFFFF; 1678 if (pipe_w < pfit_w) 1679 pipe_w = pfit_w; 1680 if (pipe_h < pfit_h) 1681 pipe_h = pfit_h; 1682 1683 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1684 pfit_w * pfit_h); 1685 } 1686 1687 return pixel_rate; 1688 } 1689 1690 /* latency must be in 0.1us units. */ 1691 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1692 uint32_t latency) 1693 { 1694 uint64_t ret; 1695 1696 if (WARN(latency == 0, "Latency value missing\n")) 1697 return UINT_MAX; 1698 1699 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1700 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1701 1702 return ret; 1703 } 1704 1705 /* latency must be in 0.1us units. */ 1706 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1707 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1708 uint32_t latency) 1709 { 1710 uint32_t ret; 1711 1712 if (WARN(latency == 0, "Latency value missing\n")) 1713 return UINT_MAX; 1714 1715 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1716 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1717 ret = DIV_ROUND_UP(ret, 64) + 2; 1718 return ret; 1719 } 1720 1721 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1722 uint8_t bytes_per_pixel) 1723 { 1724 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1725 } 1726 1727 struct ilk_pipe_wm_parameters { 1728 bool active; 1729 uint32_t pipe_htotal; 1730 uint32_t pixel_rate; 1731 struct intel_plane_wm_parameters pri; 1732 struct intel_plane_wm_parameters spr; 1733 struct intel_plane_wm_parameters cur; 1734 }; 1735 1736 struct ilk_wm_maximums { 1737 uint16_t pri; 1738 uint16_t spr; 1739 uint16_t cur; 1740 uint16_t fbc; 1741 }; 1742 1743 /* used in computing the new watermarks state */ 1744 struct intel_wm_config { 1745 unsigned int num_pipes_active; 1746 bool sprites_enabled; 1747 bool sprites_scaled; 1748 }; 1749 1750 /* 1751 * For both WM_PIPE and WM_LP. 1752 * mem_value must be in 0.1us units. 1753 */ 1754 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, 1755 uint32_t mem_value, 1756 bool is_lp) 1757 { 1758 uint32_t method1, method2; 1759 1760 if (!params->active || !params->pri.enabled) 1761 return 0; 1762 1763 method1 = ilk_wm_method1(params->pixel_rate, 1764 params->pri.bytes_per_pixel, 1765 mem_value); 1766 1767 if (!is_lp) 1768 return method1; 1769 1770 method2 = ilk_wm_method2(params->pixel_rate, 1771 params->pipe_htotal, 1772 params->pri.horiz_pixels, 1773 params->pri.bytes_per_pixel, 1774 mem_value); 1775 1776 return min(method1, method2); 1777 } 1778 1779 /* 1780 * For both WM_PIPE and WM_LP. 1781 * mem_value must be in 0.1us units. 1782 */ 1783 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, 1784 uint32_t mem_value) 1785 { 1786 uint32_t method1, method2; 1787 1788 if (!params->active || !params->spr.enabled) 1789 return 0; 1790 1791 method1 = ilk_wm_method1(params->pixel_rate, 1792 params->spr.bytes_per_pixel, 1793 mem_value); 1794 method2 = ilk_wm_method2(params->pixel_rate, 1795 params->pipe_htotal, 1796 params->spr.horiz_pixels, 1797 params->spr.bytes_per_pixel, 1798 mem_value); 1799 return min(method1, method2); 1800 } 1801 1802 /* 1803 * For both WM_PIPE and WM_LP. 1804 * mem_value must be in 0.1us units. 1805 */ 1806 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, 1807 uint32_t mem_value) 1808 { 1809 if (!params->active || !params->cur.enabled) 1810 return 0; 1811 1812 return ilk_wm_method2(params->pixel_rate, 1813 params->pipe_htotal, 1814 params->cur.horiz_pixels, 1815 params->cur.bytes_per_pixel, 1816 mem_value); 1817 } 1818 1819 /* Only for WM_LP. */ 1820 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, 1821 uint32_t pri_val) 1822 { 1823 if (!params->active || !params->pri.enabled) 1824 return 0; 1825 1826 return ilk_wm_fbc(pri_val, 1827 params->pri.horiz_pixels, 1828 params->pri.bytes_per_pixel); 1829 } 1830 1831 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1832 { 1833 if (INTEL_INFO(dev)->gen >= 8) 1834 return 3072; 1835 else if (INTEL_INFO(dev)->gen >= 7) 1836 return 768; 1837 else 1838 return 512; 1839 } 1840 1841 /* Calculate the maximum primary/sprite plane watermark */ 1842 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1843 int level, 1844 const struct intel_wm_config *config, 1845 enum intel_ddb_partitioning ddb_partitioning, 1846 bool is_sprite) 1847 { 1848 unsigned int fifo_size = ilk_display_fifo_size(dev); 1849 unsigned int max; 1850 1851 /* if sprites aren't enabled, sprites get nothing */ 1852 if (is_sprite && !config->sprites_enabled) 1853 return 0; 1854 1855 /* HSW allows LP1+ watermarks even with multiple pipes */ 1856 if (level == 0 || config->num_pipes_active > 1) { 1857 fifo_size /= INTEL_INFO(dev)->num_pipes; 1858 1859 /* 1860 * For some reason the non self refresh 1861 * FIFO size is only half of the self 1862 * refresh FIFO size on ILK/SNB. 1863 */ 1864 if (INTEL_INFO(dev)->gen <= 6) 1865 fifo_size /= 2; 1866 } 1867 1868 if (config->sprites_enabled) { 1869 /* level 0 is always calculated with 1:1 split */ 1870 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1871 if (is_sprite) 1872 fifo_size *= 5; 1873 fifo_size /= 6; 1874 } else { 1875 fifo_size /= 2; 1876 } 1877 } 1878 1879 /* clamp to max that the registers can hold */ 1880 if (INTEL_INFO(dev)->gen >= 8) 1881 max = level == 0 ? 255 : 2047; 1882 else if (INTEL_INFO(dev)->gen >= 7) 1883 /* IVB/HSW primary/sprite plane watermarks */ 1884 max = level == 0 ? 127 : 1023; 1885 else if (!is_sprite) 1886 /* ILK/SNB primary plane watermarks */ 1887 max = level == 0 ? 127 : 511; 1888 else 1889 /* ILK/SNB sprite plane watermarks */ 1890 max = level == 0 ? 63 : 255; 1891 1892 return min(fifo_size, max); 1893 } 1894 1895 /* Calculate the maximum cursor plane watermark */ 1896 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1897 int level, 1898 const struct intel_wm_config *config) 1899 { 1900 /* HSW LP1+ watermarks w/ multiple pipes */ 1901 if (level > 0 && config->num_pipes_active > 1) 1902 return 64; 1903 1904 /* otherwise just report max that registers can hold */ 1905 if (INTEL_INFO(dev)->gen >= 7) 1906 return level == 0 ? 63 : 255; 1907 else 1908 return level == 0 ? 31 : 63; 1909 } 1910 1911 /* Calculate the maximum FBC watermark */ 1912 static unsigned int ilk_fbc_wm_max(const struct drm_device *dev) 1913 { 1914 /* max that registers can hold */ 1915 if (INTEL_INFO(dev)->gen >= 8) 1916 return 31; 1917 else 1918 return 15; 1919 } 1920 1921 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1922 int level, 1923 const struct intel_wm_config *config, 1924 enum intel_ddb_partitioning ddb_partitioning, 1925 struct ilk_wm_maximums *max) 1926 { 1927 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1928 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1929 max->cur = ilk_cursor_wm_max(dev, level, config); 1930 max->fbc = ilk_fbc_wm_max(dev); 1931 } 1932 1933 static bool ilk_validate_wm_level(int level, 1934 const struct ilk_wm_maximums *max, 1935 struct intel_wm_level *result) 1936 { 1937 bool ret; 1938 1939 /* already determined to be invalid? */ 1940 if (!result->enable) 1941 return false; 1942 1943 result->enable = result->pri_val <= max->pri && 1944 result->spr_val <= max->spr && 1945 result->cur_val <= max->cur; 1946 1947 ret = result->enable; 1948 1949 /* 1950 * HACK until we can pre-compute everything, 1951 * and thus fail gracefully if LP0 watermarks 1952 * are exceeded... 1953 */ 1954 if (level == 0 && !result->enable) { 1955 if (result->pri_val > max->pri) 1956 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1957 level, result->pri_val, max->pri); 1958 if (result->spr_val > max->spr) 1959 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1960 level, result->spr_val, max->spr); 1961 if (result->cur_val > max->cur) 1962 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1963 level, result->cur_val, max->cur); 1964 1965 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1966 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1967 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1968 result->enable = true; 1969 } 1970 1971 return ret; 1972 } 1973 1974 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 1975 int level, 1976 const struct ilk_pipe_wm_parameters *p, 1977 struct intel_wm_level *result) 1978 { 1979 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 1980 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 1981 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 1982 1983 /* WM1+ latency values stored in 0.5us units */ 1984 if (level > 0) { 1985 pri_latency *= 5; 1986 spr_latency *= 5; 1987 cur_latency *= 5; 1988 } 1989 1990 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); 1991 result->spr_val = ilk_compute_spr_wm(p, spr_latency); 1992 result->cur_val = ilk_compute_cur_wm(p, cur_latency); 1993 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); 1994 result->enable = true; 1995 } 1996 1997 static uint32_t 1998 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 1999 { 2000 struct drm_i915_private *dev_priv = dev->dev_private; 2001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2002 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 2003 u32 linetime, ips_linetime; 2004 2005 if (!intel_crtc_active(crtc)) 2006 return 0; 2007 2008 /* The WM are computed with base on how long it takes to fill a single 2009 * row at the given clock rate, multiplied by 8. 2010 * */ 2011 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, 2012 mode->crtc_clock); 2013 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, 2014 intel_ddi_get_cdclk_freq(dev_priv)); 2015 2016 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2017 PIPE_WM_LINETIME_TIME(linetime); 2018 } 2019 2020 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2021 { 2022 struct drm_i915_private *dev_priv = dev->dev_private; 2023 2024 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2025 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2026 2027 wm[0] = (sskpd >> 56) & 0xFF; 2028 if (wm[0] == 0) 2029 wm[0] = sskpd & 0xF; 2030 wm[1] = (sskpd >> 4) & 0xFF; 2031 wm[2] = (sskpd >> 12) & 0xFF; 2032 wm[3] = (sskpd >> 20) & 0x1FF; 2033 wm[4] = (sskpd >> 32) & 0x1FF; 2034 } else if (INTEL_INFO(dev)->gen >= 6) { 2035 uint32_t sskpd = I915_READ(MCH_SSKPD); 2036 2037 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2038 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2039 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2040 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2041 } else if (INTEL_INFO(dev)->gen >= 5) { 2042 uint32_t mltr = I915_READ(MLTR_ILK); 2043 2044 /* ILK primary LP0 latency is 700 ns */ 2045 wm[0] = 7; 2046 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2047 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2048 } 2049 } 2050 2051 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2052 { 2053 /* ILK sprite LP0 latency is 1300 ns */ 2054 if (INTEL_INFO(dev)->gen == 5) 2055 wm[0] = 13; 2056 } 2057 2058 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2059 { 2060 /* ILK cursor LP0 latency is 1300 ns */ 2061 if (INTEL_INFO(dev)->gen == 5) 2062 wm[0] = 13; 2063 2064 /* WaDoubleCursorLP3Latency:ivb */ 2065 if (IS_IVYBRIDGE(dev)) 2066 wm[3] *= 2; 2067 } 2068 2069 static int ilk_wm_max_level(const struct drm_device *dev) 2070 { 2071 /* how many WM levels are we expecting */ 2072 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2073 return 4; 2074 else if (INTEL_INFO(dev)->gen >= 6) 2075 return 3; 2076 else 2077 return 2; 2078 } 2079 2080 static void intel_print_wm_latency(struct drm_device *dev, 2081 const char *name, 2082 const uint16_t wm[5]) 2083 { 2084 int level, max_level = ilk_wm_max_level(dev); 2085 2086 for (level = 0; level <= max_level; level++) { 2087 unsigned int latency = wm[level]; 2088 2089 if (latency == 0) { 2090 DRM_ERROR("%s WM%d latency not provided\n", 2091 name, level); 2092 continue; 2093 } 2094 2095 /* WM1+ latency values in 0.5us units */ 2096 if (level > 0) 2097 latency *= 5; 2098 2099 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2100 name, level, wm[level], 2101 latency / 10, latency % 10); 2102 } 2103 } 2104 2105 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2106 uint16_t wm[5], uint16_t min) 2107 { 2108 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2109 2110 if (wm[0] >= min) 2111 return false; 2112 2113 wm[0] = max(wm[0], min); 2114 for (level = 1; level <= max_level; level++) 2115 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2116 2117 return true; 2118 } 2119 2120 static void snb_wm_latency_quirk(struct drm_device *dev) 2121 { 2122 struct drm_i915_private *dev_priv = dev->dev_private; 2123 bool changed; 2124 2125 /* 2126 * The BIOS provided WM memory latency values are often 2127 * inadequate for high resolution displays. Adjust them. 2128 */ 2129 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2130 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2131 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2132 2133 if (!changed) 2134 return; 2135 2136 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2137 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2138 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2139 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2140 } 2141 2142 static void ilk_setup_wm_latency(struct drm_device *dev) 2143 { 2144 struct drm_i915_private *dev_priv = dev->dev_private; 2145 2146 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2147 2148 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2149 sizeof(dev_priv->wm.pri_latency)); 2150 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2151 sizeof(dev_priv->wm.pri_latency)); 2152 2153 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2154 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2155 2156 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2157 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2158 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2159 2160 if (IS_GEN6(dev)) 2161 snb_wm_latency_quirk(dev); 2162 } 2163 2164 static void ilk_compute_wm_parameters(struct drm_crtc *crtc, 2165 struct ilk_pipe_wm_parameters *p, 2166 struct intel_wm_config *config) 2167 { 2168 struct drm_device *dev = crtc->dev; 2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2170 enum pipe pipe = intel_crtc->pipe; 2171 struct drm_plane *plane; 2172 2173 p->active = intel_crtc_active(crtc); 2174 if (p->active) { 2175 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; 2176 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); 2177 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; 2178 p->cur.bytes_per_pixel = 4; 2179 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; 2180 p->cur.horiz_pixels = intel_crtc->cursor_width; 2181 /* TODO: for now, assume primary and cursor planes are always enabled. */ 2182 p->pri.enabled = true; 2183 p->cur.enabled = true; 2184 } 2185 2186 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 2187 config->num_pipes_active += intel_crtc_active(crtc); 2188 2189 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { 2190 struct intel_plane *intel_plane = to_intel_plane(plane); 2191 2192 if (intel_plane->pipe == pipe) 2193 p->spr = intel_plane->wm; 2194 2195 config->sprites_enabled |= intel_plane->wm.enabled; 2196 config->sprites_scaled |= intel_plane->wm.scaled; 2197 } 2198 } 2199 2200 /* Compute new watermarks for the pipe */ 2201 static bool intel_compute_pipe_wm(struct drm_crtc *crtc, 2202 const struct ilk_pipe_wm_parameters *params, 2203 struct intel_pipe_wm *pipe_wm) 2204 { 2205 struct drm_device *dev = crtc->dev; 2206 const struct drm_i915_private *dev_priv = dev->dev_private; 2207 int level, max_level = ilk_wm_max_level(dev); 2208 /* LP0 watermark maximums depend on this pipe alone */ 2209 struct intel_wm_config config = { 2210 .num_pipes_active = 1, 2211 .sprites_enabled = params->spr.enabled, 2212 .sprites_scaled = params->spr.scaled, 2213 }; 2214 struct ilk_wm_maximums max; 2215 2216 /* LP0 watermarks always use 1/2 DDB partitioning */ 2217 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2218 2219 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2220 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) 2221 max_level = 1; 2222 2223 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2224 if (params->spr.scaled) 2225 max_level = 0; 2226 2227 for (level = 0; level <= max_level; level++) 2228 ilk_compute_wm_level(dev_priv, level, params, 2229 &pipe_wm->wm[level]); 2230 2231 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2232 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2233 2234 /* At least LP0 must be valid */ 2235 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]); 2236 } 2237 2238 /* 2239 * Merge the watermarks from all active pipes for a specific level. 2240 */ 2241 static void ilk_merge_wm_level(struct drm_device *dev, 2242 int level, 2243 struct intel_wm_level *ret_wm) 2244 { 2245 const struct intel_crtc *intel_crtc; 2246 2247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { 2248 const struct intel_wm_level *wm = 2249 &intel_crtc->wm.active.wm[level]; 2250 2251 if (!wm->enable) 2252 return; 2253 2254 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2255 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2256 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2257 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2258 } 2259 2260 ret_wm->enable = true; 2261 } 2262 2263 /* 2264 * Merge all low power watermarks for all active pipes. 2265 */ 2266 static void ilk_wm_merge(struct drm_device *dev, 2267 const struct intel_wm_config *config, 2268 const struct ilk_wm_maximums *max, 2269 struct intel_pipe_wm *merged) 2270 { 2271 int level, max_level = ilk_wm_max_level(dev); 2272 2273 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2274 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2275 config->num_pipes_active > 1) 2276 return; 2277 2278 /* ILK: FBC WM must be disabled always */ 2279 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2280 2281 /* merge each WM1+ level */ 2282 for (level = 1; level <= max_level; level++) { 2283 struct intel_wm_level *wm = &merged->wm[level]; 2284 2285 ilk_merge_wm_level(dev, level, wm); 2286 2287 if (!ilk_validate_wm_level(level, max, wm)) 2288 break; 2289 2290 /* 2291 * The spec says it is preferred to disable 2292 * FBC WMs instead of disabling a WM level. 2293 */ 2294 if (wm->fbc_val > max->fbc) { 2295 merged->fbc_wm_enabled = false; 2296 wm->fbc_val = 0; 2297 } 2298 } 2299 2300 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2301 /* 2302 * FIXME this is racy. FBC might get enabled later. 2303 * What we should check here is whether FBC can be 2304 * enabled sometime later. 2305 */ 2306 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { 2307 for (level = 2; level <= max_level; level++) { 2308 struct intel_wm_level *wm = &merged->wm[level]; 2309 2310 wm->enable = false; 2311 } 2312 } 2313 } 2314 2315 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2316 { 2317 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2318 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2319 } 2320 2321 /* The value we need to program into the WM_LPx latency field */ 2322 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2323 { 2324 struct drm_i915_private *dev_priv = dev->dev_private; 2325 2326 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2327 return 2 * level; 2328 else 2329 return dev_priv->wm.pri_latency[level]; 2330 } 2331 2332 static void ilk_compute_wm_results(struct drm_device *dev, 2333 const struct intel_pipe_wm *merged, 2334 enum intel_ddb_partitioning partitioning, 2335 struct ilk_wm_values *results) 2336 { 2337 struct intel_crtc *intel_crtc; 2338 int level, wm_lp; 2339 2340 results->enable_fbc_wm = merged->fbc_wm_enabled; 2341 results->partitioning = partitioning; 2342 2343 /* LP1+ register values */ 2344 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2345 const struct intel_wm_level *r; 2346 2347 level = ilk_wm_lp_to_level(wm_lp, merged); 2348 2349 r = &merged->wm[level]; 2350 if (!r->enable) 2351 break; 2352 2353 results->wm_lp[wm_lp - 1] = WM3_LP_EN | 2354 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2355 (r->pri_val << WM1_LP_SR_SHIFT) | 2356 r->cur_val; 2357 2358 if (INTEL_INFO(dev)->gen >= 8) 2359 results->wm_lp[wm_lp - 1] |= 2360 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2361 else 2362 results->wm_lp[wm_lp - 1] |= 2363 r->fbc_val << WM1_LP_FBC_SHIFT; 2364 2365 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2366 WARN_ON(wm_lp != 1); 2367 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2368 } else 2369 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2370 } 2371 2372 /* LP0 register values */ 2373 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { 2374 enum pipe pipe = intel_crtc->pipe; 2375 const struct intel_wm_level *r = 2376 &intel_crtc->wm.active.wm[0]; 2377 2378 if (WARN_ON(!r->enable)) 2379 continue; 2380 2381 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2382 2383 results->wm_pipe[pipe] = 2384 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2385 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2386 r->cur_val; 2387 } 2388 } 2389 2390 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2391 * case both are at the same level. Prefer r1 in case they're the same. */ 2392 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2393 struct intel_pipe_wm *r1, 2394 struct intel_pipe_wm *r2) 2395 { 2396 int level, max_level = ilk_wm_max_level(dev); 2397 int level1 = 0, level2 = 0; 2398 2399 for (level = 1; level <= max_level; level++) { 2400 if (r1->wm[level].enable) 2401 level1 = level; 2402 if (r2->wm[level].enable) 2403 level2 = level; 2404 } 2405 2406 if (level1 == level2) { 2407 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2408 return r2; 2409 else 2410 return r1; 2411 } else if (level1 > level2) { 2412 return r1; 2413 } else { 2414 return r2; 2415 } 2416 } 2417 2418 /* dirty bits used to track which watermarks need changes */ 2419 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2420 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2421 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2422 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2423 #define WM_DIRTY_FBC (1 << 24) 2424 #define WM_DIRTY_DDB (1 << 25) 2425 2426 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, 2427 const struct ilk_wm_values *old, 2428 const struct ilk_wm_values *new) 2429 { 2430 unsigned int dirty = 0; 2431 enum pipe pipe; 2432 int wm_lp; 2433 2434 for_each_pipe(pipe) { 2435 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2436 dirty |= WM_DIRTY_LINETIME(pipe); 2437 /* Must disable LP1+ watermarks too */ 2438 dirty |= WM_DIRTY_LP_ALL; 2439 } 2440 2441 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2442 dirty |= WM_DIRTY_PIPE(pipe); 2443 /* Must disable LP1+ watermarks too */ 2444 dirty |= WM_DIRTY_LP_ALL; 2445 } 2446 } 2447 2448 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2449 dirty |= WM_DIRTY_FBC; 2450 /* Must disable LP1+ watermarks too */ 2451 dirty |= WM_DIRTY_LP_ALL; 2452 } 2453 2454 if (old->partitioning != new->partitioning) { 2455 dirty |= WM_DIRTY_DDB; 2456 /* Must disable LP1+ watermarks too */ 2457 dirty |= WM_DIRTY_LP_ALL; 2458 } 2459 2460 /* LP1+ watermarks already deemed dirty, no need to continue */ 2461 if (dirty & WM_DIRTY_LP_ALL) 2462 return dirty; 2463 2464 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2465 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2466 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2467 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2468 break; 2469 } 2470 2471 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2472 for (; wm_lp <= 3; wm_lp++) 2473 dirty |= WM_DIRTY_LP(wm_lp); 2474 2475 return dirty; 2476 } 2477 2478 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2479 unsigned int dirty) 2480 { 2481 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2482 bool changed = false; 2483 2484 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2485 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2486 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2487 changed = true; 2488 } 2489 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2490 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2491 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2492 changed = true; 2493 } 2494 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2495 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2496 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2497 changed = true; 2498 } 2499 2500 /* 2501 * Don't touch WM1S_LP_EN here. 2502 * Doing so could cause underruns. 2503 */ 2504 2505 return changed; 2506 } 2507 2508 /* 2509 * The spec says we shouldn't write when we don't need, because every write 2510 * causes WMs to be re-evaluated, expending some power. 2511 */ 2512 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2513 struct ilk_wm_values *results) 2514 { 2515 struct drm_device *dev = dev_priv->dev; 2516 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2517 unsigned int dirty; 2518 uint32_t val; 2519 2520 dirty = ilk_compute_wm_dirty(dev, previous, results); 2521 if (!dirty) 2522 return; 2523 2524 _ilk_disable_lp_wm(dev_priv, dirty); 2525 2526 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2527 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2528 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2529 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2530 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2531 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2532 2533 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2534 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2535 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2536 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2537 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2538 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2539 2540 if (dirty & WM_DIRTY_DDB) { 2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2542 val = I915_READ(WM_MISC); 2543 if (results->partitioning == INTEL_DDB_PART_1_2) 2544 val &= ~WM_MISC_DATA_PARTITION_5_6; 2545 else 2546 val |= WM_MISC_DATA_PARTITION_5_6; 2547 I915_WRITE(WM_MISC, val); 2548 } else { 2549 val = I915_READ(DISP_ARB_CTL2); 2550 if (results->partitioning == INTEL_DDB_PART_1_2) 2551 val &= ~DISP_DATA_PARTITION_5_6; 2552 else 2553 val |= DISP_DATA_PARTITION_5_6; 2554 I915_WRITE(DISP_ARB_CTL2, val); 2555 } 2556 } 2557 2558 if (dirty & WM_DIRTY_FBC) { 2559 val = I915_READ(DISP_ARB_CTL); 2560 if (results->enable_fbc_wm) 2561 val &= ~DISP_FBC_WM_DIS; 2562 else 2563 val |= DISP_FBC_WM_DIS; 2564 I915_WRITE(DISP_ARB_CTL, val); 2565 } 2566 2567 if (dirty & WM_DIRTY_LP(1) && 2568 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2569 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2570 2571 if (INTEL_INFO(dev)->gen >= 7) { 2572 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2573 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2574 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2575 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2576 } 2577 2578 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2579 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2580 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2581 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2582 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2583 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2584 2585 dev_priv->wm.hw = *results; 2586 } 2587 2588 static bool ilk_disable_lp_wm(struct drm_device *dev) 2589 { 2590 struct drm_i915_private *dev_priv = dev->dev_private; 2591 2592 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2593 } 2594 2595 static void ilk_update_wm(struct drm_crtc *crtc) 2596 { 2597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2598 struct drm_device *dev = crtc->dev; 2599 struct drm_i915_private *dev_priv = dev->dev_private; 2600 struct ilk_wm_maximums max; 2601 struct ilk_pipe_wm_parameters params = {}; 2602 struct ilk_wm_values results = {}; 2603 enum intel_ddb_partitioning partitioning; 2604 struct intel_pipe_wm pipe_wm = {}; 2605 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; 2606 struct intel_wm_config config = {}; 2607 2608 ilk_compute_wm_parameters(crtc, ¶ms, &config); 2609 2610 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); 2611 2612 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 2613 return; 2614 2615 intel_crtc->wm.active = pipe_wm; 2616 2617 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 2618 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 2619 2620 /* 5/6 split only in single pipe config on IVB+ */ 2621 if (INTEL_INFO(dev)->gen >= 7 && 2622 config.num_pipes_active == 1 && config.sprites_enabled) { 2623 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 2624 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 2625 2626 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 2627 } else { 2628 best_lp_wm = &lp_wm_1_2; 2629 } 2630 2631 partitioning = (best_lp_wm == &lp_wm_1_2) ? 2632 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 2633 2634 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 2635 2636 ilk_write_wm_values(dev_priv, &results); 2637 } 2638 2639 static void ilk_update_sprite_wm(struct drm_plane *plane, 2640 struct drm_crtc *crtc, 2641 uint32_t sprite_width, int pixel_size, 2642 bool enabled, bool scaled) 2643 { 2644 struct drm_device *dev = plane->dev; 2645 struct intel_plane *intel_plane = to_intel_plane(plane); 2646 2647 intel_plane->wm.enabled = enabled; 2648 intel_plane->wm.scaled = scaled; 2649 intel_plane->wm.horiz_pixels = sprite_width; 2650 intel_plane->wm.bytes_per_pixel = pixel_size; 2651 2652 /* 2653 * IVB workaround: must disable low power watermarks for at least 2654 * one frame before enabling scaling. LP watermarks can be re-enabled 2655 * when scaling is disabled. 2656 * 2657 * WaCxSRDisabledForSpriteScaling:ivb 2658 */ 2659 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 2660 intel_wait_for_vblank(dev, intel_plane->pipe); 2661 2662 ilk_update_wm(crtc); 2663 } 2664 2665 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 2666 { 2667 struct drm_device *dev = crtc->dev; 2668 struct drm_i915_private *dev_priv = dev->dev_private; 2669 struct ilk_wm_values *hw = &dev_priv->wm.hw; 2670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2671 struct intel_pipe_wm *active = &intel_crtc->wm.active; 2672 enum pipe pipe = intel_crtc->pipe; 2673 static const unsigned int wm0_pipe_reg[] = { 2674 [PIPE_A] = WM0_PIPEA_ILK, 2675 [PIPE_B] = WM0_PIPEB_ILK, 2676 [PIPE_C] = WM0_PIPEC_IVB, 2677 }; 2678 2679 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 2680 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2681 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 2682 2683 if (intel_crtc_active(crtc)) { 2684 u32 tmp = hw->wm_pipe[pipe]; 2685 2686 /* 2687 * For active pipes LP0 watermark is marked as 2688 * enabled, and LP1+ watermaks as disabled since 2689 * we can't really reverse compute them in case 2690 * multiple pipes are active. 2691 */ 2692 active->wm[0].enable = true; 2693 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 2694 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 2695 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 2696 active->linetime = hw->wm_linetime[pipe]; 2697 } else { 2698 int level, max_level = ilk_wm_max_level(dev); 2699 2700 /* 2701 * For inactive pipes, all watermark levels 2702 * should be marked as enabled but zeroed, 2703 * which is what we'd compute them to. 2704 */ 2705 for (level = 0; level <= max_level; level++) 2706 active->wm[level].enable = true; 2707 } 2708 } 2709 2710 void ilk_wm_get_hw_state(struct drm_device *dev) 2711 { 2712 struct drm_i915_private *dev_priv = dev->dev_private; 2713 struct ilk_wm_values *hw = &dev_priv->wm.hw; 2714 struct drm_crtc *crtc; 2715 2716 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 2717 ilk_pipe_wm_get_hw_state(crtc); 2718 2719 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 2720 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 2721 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 2722 2723 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 2724 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 2725 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 2726 2727 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2728 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 2729 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 2730 else if (IS_IVYBRIDGE(dev)) 2731 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 2732 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 2733 2734 hw->enable_fbc_wm = 2735 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 2736 } 2737 2738 /** 2739 * intel_update_watermarks - update FIFO watermark values based on current modes 2740 * 2741 * Calculate watermark values for the various WM regs based on current mode 2742 * and plane configuration. 2743 * 2744 * There are several cases to deal with here: 2745 * - normal (i.e. non-self-refresh) 2746 * - self-refresh (SR) mode 2747 * - lines are large relative to FIFO size (buffer can hold up to 2) 2748 * - lines are small relative to FIFO size (buffer can hold more than 2 2749 * lines), so need to account for TLB latency 2750 * 2751 * The normal calculation is: 2752 * watermark = dotclock * bytes per pixel * latency 2753 * where latency is platform & configuration dependent (we assume pessimal 2754 * values here). 2755 * 2756 * The SR calculation is: 2757 * watermark = (trunc(latency/line time)+1) * surface width * 2758 * bytes per pixel 2759 * where 2760 * line time = htotal / dotclock 2761 * surface width = hdisplay for normal plane and 64 for cursor 2762 * and latency is assumed to be high, as above. 2763 * 2764 * The final value programmed to the register should always be rounded up, 2765 * and include an extra 2 entries to account for clock crossings. 2766 * 2767 * We don't use the sprite, so we can ignore that. And on Crestline we have 2768 * to set the non-SR watermarks to 8. 2769 */ 2770 void intel_update_watermarks(struct drm_crtc *crtc) 2771 { 2772 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2773 2774 if (dev_priv->display.update_wm) 2775 dev_priv->display.update_wm(crtc); 2776 } 2777 2778 void intel_update_sprite_watermarks(struct drm_plane *plane, 2779 struct drm_crtc *crtc, 2780 uint32_t sprite_width, int pixel_size, 2781 bool enabled, bool scaled) 2782 { 2783 struct drm_i915_private *dev_priv = plane->dev->dev_private; 2784 2785 if (dev_priv->display.update_sprite_wm) 2786 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width, 2787 pixel_size, enabled, scaled); 2788 } 2789 2790 static struct drm_i915_gem_object * 2791 intel_alloc_context_page(struct drm_device *dev) 2792 { 2793 struct drm_i915_gem_object *ctx; 2794 int ret; 2795 2796 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2797 2798 ctx = i915_gem_alloc_object(dev, 4096); 2799 if (!ctx) { 2800 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 2801 return NULL; 2802 } 2803 2804 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); 2805 if (ret) { 2806 DRM_ERROR("failed to pin power context: %d\n", ret); 2807 goto err_unref; 2808 } 2809 2810 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 2811 if (ret) { 2812 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 2813 goto err_unpin; 2814 } 2815 2816 return ctx; 2817 2818 err_unpin: 2819 i915_gem_object_ggtt_unpin(ctx); 2820 err_unref: 2821 drm_gem_object_unreference(&ctx->base); 2822 return NULL; 2823 } 2824 2825 /** 2826 * Lock protecting IPS related data structures 2827 */ 2828 #ifdef __NetBSD__ 2829 spinlock_t mchdev_lock; 2830 #else 2831 DEFINE_SPINLOCK(mchdev_lock); 2832 #endif 2833 2834 /* Global for IPS driver to get at the current i915 device. Protected by 2835 * mchdev_lock. */ 2836 static struct drm_i915_private *i915_mch_dev; 2837 2838 bool ironlake_set_drps(struct drm_device *dev, u8 val) 2839 { 2840 struct drm_i915_private *dev_priv = dev->dev_private; 2841 u16 rgvswctl; 2842 2843 assert_spin_locked(&mchdev_lock); 2844 2845 rgvswctl = I915_READ16(MEMSWCTL); 2846 if (rgvswctl & MEMCTL_CMD_STS) { 2847 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2848 return false; /* still busy with another command */ 2849 } 2850 2851 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2852 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2853 I915_WRITE16(MEMSWCTL, rgvswctl); 2854 POSTING_READ16(MEMSWCTL); 2855 2856 rgvswctl |= MEMCTL_CMD_STS; 2857 I915_WRITE16(MEMSWCTL, rgvswctl); 2858 2859 return true; 2860 } 2861 2862 static void ironlake_enable_drps(struct drm_device *dev) 2863 { 2864 struct drm_i915_private *dev_priv = dev->dev_private; 2865 u32 rgvmodectl = I915_READ(MEMMODECTL); 2866 u8 fmax, fmin, fstart, vstart; 2867 2868 spin_lock_irq(&mchdev_lock); 2869 2870 /* Enable temp reporting */ 2871 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2872 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2873 2874 /* 100ms RC evaluation intervals */ 2875 I915_WRITE(RCUPEI, 100000); 2876 I915_WRITE(RCDNEI, 100000); 2877 2878 /* Set max/min thresholds to 90ms and 80ms respectively */ 2879 I915_WRITE(RCBMAXAVG, 90000); 2880 I915_WRITE(RCBMINAVG, 80000); 2881 2882 I915_WRITE(MEMIHYST, 1); 2883 2884 /* Set up min, max, and cur for interrupt handling */ 2885 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2886 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2887 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2888 MEMMODE_FSTART_SHIFT; 2889 2890 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2891 PXVFREQ_PX_SHIFT; 2892 2893 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 2894 dev_priv->ips.fstart = fstart; 2895 2896 dev_priv->ips.max_delay = fstart; 2897 dev_priv->ips.min_delay = fmin; 2898 dev_priv->ips.cur_delay = fstart; 2899 2900 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 2901 fmax, fmin, fstart); 2902 2903 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2904 2905 /* 2906 * Interrupts will be enabled in ironlake_irq_postinstall 2907 */ 2908 2909 I915_WRITE(VIDSTART, vstart); 2910 POSTING_READ(VIDSTART); 2911 2912 rgvmodectl |= MEMMODE_SWMODE_EN; 2913 I915_WRITE(MEMMODECTL, rgvmodectl); 2914 2915 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 2916 DRM_ERROR("stuck trying to change perf mode\n"); 2917 mdelay(1); 2918 2919 ironlake_set_drps(dev, fstart); 2920 2921 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2922 I915_READ(0x112e0); 2923 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 2924 dev_priv->ips.last_count2 = I915_READ(0x112f4); 2925 getrawmonotonic(&dev_priv->ips.last_time2); 2926 2927 spin_unlock_irq(&mchdev_lock); 2928 } 2929 2930 static void ironlake_disable_drps(struct drm_device *dev) 2931 { 2932 struct drm_i915_private *dev_priv = dev->dev_private; 2933 u16 rgvswctl; 2934 2935 spin_lock_irq(&mchdev_lock); 2936 2937 rgvswctl = I915_READ16(MEMSWCTL); 2938 2939 /* Ack interrupts, disable EFC interrupt */ 2940 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2941 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2942 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2943 I915_WRITE(DEIIR, DE_PCU_EVENT); 2944 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2945 2946 /* Go back to the starting frequency */ 2947 ironlake_set_drps(dev, dev_priv->ips.fstart); 2948 mdelay(1); 2949 rgvswctl |= MEMCTL_CMD_STS; 2950 I915_WRITE(MEMSWCTL, rgvswctl); 2951 mdelay(1); 2952 2953 spin_unlock_irq(&mchdev_lock); 2954 } 2955 2956 /* There's a funny hw issue where the hw returns all 0 when reading from 2957 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 2958 * ourselves, instead of doing a rmw cycle (which might result in us clearing 2959 * all limits and the gpu stuck at whatever frequency it is at atm). 2960 */ 2961 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) 2962 { 2963 u32 limits; 2964 2965 /* Only set the down limit when we've reached the lowest level to avoid 2966 * getting more interrupts, otherwise leave this clear. This prevents a 2967 * race in the hw when coming out of rc6: There's a tiny window where 2968 * the hw runs at the minimal clock before selecting the desired 2969 * frequency, if the down threshold expires in that window we will not 2970 * receive a down interrupt. */ 2971 limits = dev_priv->rps.max_freq_softlimit << 24; 2972 if (val <= dev_priv->rps.min_freq_softlimit) 2973 limits |= dev_priv->rps.min_freq_softlimit << 16; 2974 2975 return limits; 2976 } 2977 2978 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 2979 { 2980 int new_power; 2981 2982 new_power = dev_priv->rps.power; 2983 switch (dev_priv->rps.power) { 2984 case LOW_POWER: 2985 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 2986 new_power = BETWEEN; 2987 break; 2988 2989 case BETWEEN: 2990 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 2991 new_power = LOW_POWER; 2992 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 2993 new_power = HIGH_POWER; 2994 break; 2995 2996 case HIGH_POWER: 2997 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 2998 new_power = BETWEEN; 2999 break; 3000 } 3001 /* Max/min bins are special */ 3002 if (val == dev_priv->rps.min_freq_softlimit) 3003 new_power = LOW_POWER; 3004 if (val == dev_priv->rps.max_freq_softlimit) 3005 new_power = HIGH_POWER; 3006 if (new_power == dev_priv->rps.power) 3007 return; 3008 3009 /* Note the units here are not exactly 1us, but 1280ns. */ 3010 switch (new_power) { 3011 case LOW_POWER: 3012 /* Upclock if more than 95% busy over 16ms */ 3013 I915_WRITE(GEN6_RP_UP_EI, 12500); 3014 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); 3015 3016 /* Downclock if less than 85% busy over 32ms */ 3017 I915_WRITE(GEN6_RP_DOWN_EI, 25000); 3018 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); 3019 3020 I915_WRITE(GEN6_RP_CONTROL, 3021 GEN6_RP_MEDIA_TURBO | 3022 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3023 GEN6_RP_MEDIA_IS_GFX | 3024 GEN6_RP_ENABLE | 3025 GEN6_RP_UP_BUSY_AVG | 3026 GEN6_RP_DOWN_IDLE_AVG); 3027 break; 3028 3029 case BETWEEN: 3030 /* Upclock if more than 90% busy over 13ms */ 3031 I915_WRITE(GEN6_RP_UP_EI, 10250); 3032 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); 3033 3034 /* Downclock if less than 75% busy over 32ms */ 3035 I915_WRITE(GEN6_RP_DOWN_EI, 25000); 3036 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); 3037 3038 I915_WRITE(GEN6_RP_CONTROL, 3039 GEN6_RP_MEDIA_TURBO | 3040 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3041 GEN6_RP_MEDIA_IS_GFX | 3042 GEN6_RP_ENABLE | 3043 GEN6_RP_UP_BUSY_AVG | 3044 GEN6_RP_DOWN_IDLE_AVG); 3045 break; 3046 3047 case HIGH_POWER: 3048 /* Upclock if more than 85% busy over 10ms */ 3049 I915_WRITE(GEN6_RP_UP_EI, 8000); 3050 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); 3051 3052 /* Downclock if less than 60% busy over 32ms */ 3053 I915_WRITE(GEN6_RP_DOWN_EI, 25000); 3054 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); 3055 3056 I915_WRITE(GEN6_RP_CONTROL, 3057 GEN6_RP_MEDIA_TURBO | 3058 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3059 GEN6_RP_MEDIA_IS_GFX | 3060 GEN6_RP_ENABLE | 3061 GEN6_RP_UP_BUSY_AVG | 3062 GEN6_RP_DOWN_IDLE_AVG); 3063 break; 3064 } 3065 3066 dev_priv->rps.power = new_power; 3067 dev_priv->rps.last_adj = 0; 3068 } 3069 3070 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 3071 { 3072 u32 mask = 0; 3073 3074 if (val > dev_priv->rps.min_freq_softlimit) 3075 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 3076 if (val < dev_priv->rps.max_freq_softlimit) 3077 mask |= GEN6_PM_RP_UP_THRESHOLD; 3078 3079 /* IVB and SNB hard hangs on looping batchbuffer 3080 * if GEN6_PM_UP_EI_EXPIRED is masked. 3081 */ 3082 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) 3083 mask |= GEN6_PM_RP_UP_EI_EXPIRED; 3084 3085 return ~mask; 3086 } 3087 3088 /* gen6_set_rps is called to update the frequency request, but should also be 3089 * called when the range (min_delay and max_delay) is modified so that we can 3090 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 3091 void gen6_set_rps(struct drm_device *dev, u8 val) 3092 { 3093 struct drm_i915_private *dev_priv = dev->dev_private; 3094 3095 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3096 WARN_ON(val > dev_priv->rps.max_freq_softlimit); 3097 WARN_ON(val < dev_priv->rps.min_freq_softlimit); 3098 3099 /* min/max delay may still have been modified so be sure to 3100 * write the limits value. 3101 */ 3102 if (val != dev_priv->rps.cur_freq) { 3103 gen6_set_rps_thresholds(dev_priv, val); 3104 3105 if (IS_HASWELL(dev)) 3106 I915_WRITE(GEN6_RPNSWREQ, 3107 HSW_FREQUENCY(val)); 3108 else 3109 I915_WRITE(GEN6_RPNSWREQ, 3110 GEN6_FREQUENCY(val) | 3111 GEN6_OFFSET(0) | 3112 GEN6_AGGRESSIVE_TURBO); 3113 } 3114 3115 /* Make sure we continue to get interrupts 3116 * until we hit the minimum or maximum frequencies. 3117 */ 3118 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); 3119 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 3120 3121 POSTING_READ(GEN6_RPNSWREQ); 3122 3123 dev_priv->rps.cur_freq = val; 3124 trace_intel_gpu_freq_change(val * 50); 3125 } 3126 3127 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down 3128 * 3129 * * If Gfx is Idle, then 3130 * 1. Mask Turbo interrupts 3131 * 2. Bring up Gfx clock 3132 * 3. Change the freq to Rpn and wait till P-Unit updates freq 3133 * 4. Clear the Force GFX CLK ON bit so that Gfx can down 3134 * 5. Unmask Turbo interrupts 3135 */ 3136 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 3137 { 3138 /* 3139 * When we are idle. Drop to min voltage state. 3140 */ 3141 3142 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) 3143 return; 3144 3145 /* Mask turbo interrupt so that they will not come in between */ 3146 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 3147 3148 /* Bring up the Gfx clock */ 3149 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, 3150 I915_READ(VLV_GTLC_SURVIVABILITY_REG) | 3151 VLV_GFX_CLK_FORCE_ON_BIT); 3152 3153 if (wait_for(((VLV_GFX_CLK_STATUS_BIT & 3154 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) { 3155 DRM_ERROR("GFX_CLK_ON request timed out\n"); 3156 return; 3157 } 3158 3159 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; 3160 3161 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, 3162 dev_priv->rps.min_freq_softlimit); 3163 3164 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) 3165 & GENFREQSTATUS) == 0, 5)) 3166 DRM_ERROR("timed out waiting for Punit\n"); 3167 3168 /* Release the Gfx clock */ 3169 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, 3170 I915_READ(VLV_GTLC_SURVIVABILITY_REG) & 3171 ~VLV_GFX_CLK_FORCE_ON_BIT); 3172 3173 I915_WRITE(GEN6_PMINTRMSK, 3174 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 3175 } 3176 3177 void gen6_rps_idle(struct drm_i915_private *dev_priv) 3178 { 3179 struct drm_device *dev = dev_priv->dev; 3180 3181 mutex_lock(&dev_priv->rps.hw_lock); 3182 if (dev_priv->rps.enabled) { 3183 if (IS_VALLEYVIEW(dev)) 3184 vlv_set_rps_idle(dev_priv); 3185 else 3186 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3187 dev_priv->rps.last_adj = 0; 3188 } 3189 mutex_unlock(&dev_priv->rps.hw_lock); 3190 } 3191 3192 void gen6_rps_boost(struct drm_i915_private *dev_priv) 3193 { 3194 struct drm_device *dev = dev_priv->dev; 3195 3196 mutex_lock(&dev_priv->rps.hw_lock); 3197 if (dev_priv->rps.enabled) { 3198 if (IS_VALLEYVIEW(dev)) 3199 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); 3200 else 3201 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); 3202 dev_priv->rps.last_adj = 0; 3203 } 3204 mutex_unlock(&dev_priv->rps.hw_lock); 3205 } 3206 3207 void valleyview_set_rps(struct drm_device *dev, u8 val) 3208 { 3209 struct drm_i915_private *dev_priv = dev->dev_private; 3210 3211 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3212 WARN_ON(val > dev_priv->rps.max_freq_softlimit); 3213 WARN_ON(val < dev_priv->rps.min_freq_softlimit); 3214 3215 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", 3216 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 3217 dev_priv->rps.cur_freq, 3218 vlv_gpu_freq(dev_priv, val), val); 3219 3220 if (val != dev_priv->rps.cur_freq) 3221 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 3222 3223 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 3224 3225 dev_priv->rps.cur_freq = val; 3226 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); 3227 } 3228 3229 static void gen6_disable_rps_interrupts(struct drm_device *dev) 3230 { 3231 struct drm_i915_private *dev_priv = dev->dev_private; 3232 3233 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 3234 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & 3235 ~dev_priv->pm_rps_events); 3236 /* Complete PM interrupt masking here doesn't race with the rps work 3237 * item again unmasking PM interrupts because that is using a different 3238 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 3239 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 3240 3241 spin_lock_irq(&dev_priv->irq_lock); 3242 dev_priv->rps.pm_iir = 0; 3243 spin_unlock_irq(&dev_priv->irq_lock); 3244 3245 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); 3246 } 3247 3248 static void gen6_disable_rps(struct drm_device *dev) 3249 { 3250 struct drm_i915_private *dev_priv = dev->dev_private; 3251 3252 I915_WRITE(GEN6_RC_CONTROL, 0); 3253 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 3254 3255 gen6_disable_rps_interrupts(dev); 3256 } 3257 3258 static void valleyview_disable_rps(struct drm_device *dev) 3259 { 3260 struct drm_i915_private *dev_priv = dev->dev_private; 3261 3262 I915_WRITE(GEN6_RC_CONTROL, 0); 3263 3264 gen6_disable_rps_interrupts(dev); 3265 } 3266 3267 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 3268 { 3269 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 3270 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 3271 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 3272 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 3273 } 3274 3275 int intel_enable_rc6(const struct drm_device *dev) 3276 { 3277 /* No RC6 before Ironlake */ 3278 if (INTEL_INFO(dev)->gen < 5) 3279 return 0; 3280 3281 /* Respect the kernel parameter if it is set */ 3282 if (i915.enable_rc6 >= 0) 3283 return i915.enable_rc6; 3284 3285 /* Disable RC6 on Ironlake */ 3286 if (INTEL_INFO(dev)->gen == 5) 3287 return 0; 3288 3289 if (IS_IVYBRIDGE(dev)) 3290 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 3291 3292 return INTEL_RC6_ENABLE; 3293 } 3294 3295 static void gen6_enable_rps_interrupts(struct drm_device *dev) 3296 { 3297 struct drm_i915_private *dev_priv = dev->dev_private; 3298 3299 spin_lock_irq(&dev_priv->irq_lock); 3300 WARN_ON(dev_priv->rps.pm_iir); 3301 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); 3302 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); 3303 spin_unlock_irq(&dev_priv->irq_lock); 3304 } 3305 3306 static void gen8_enable_rps(struct drm_device *dev) 3307 { 3308 struct drm_i915_private *dev_priv = dev->dev_private; 3309 struct intel_ring_buffer *ring; 3310 uint32_t rc6_mask = 0, rp_state_cap; 3311 int unused; 3312 3313 /* 1a: Software RC state - RC0 */ 3314 I915_WRITE(GEN6_RC_STATE, 0); 3315 3316 /* 1c & 1d: Get forcewake during program sequence. Although the driver 3317 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 3318 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 3319 3320 /* 2a: Disable RC states. */ 3321 I915_WRITE(GEN6_RC_CONTROL, 0); 3322 3323 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 3324 3325 /* 2b: Program RC6 thresholds.*/ 3326 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 3327 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 3328 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 3329 for_each_ring(ring, dev_priv, unused) 3330 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 3331 I915_WRITE(GEN6_RC_SLEEP, 0); 3332 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 3333 3334 /* 3: Enable RC6 */ 3335 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 3336 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 3337 intel_print_rc6_info(dev, rc6_mask); 3338 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 3339 GEN6_RC_CTL_EI_MODE(1) | 3340 rc6_mask); 3341 3342 /* 4 Program defaults and thresholds for RPS*/ 3343 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ 3344 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */ 3345 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 3346 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 3347 3348 /* Docs recommend 900MHz, and 300 MHz respectively */ 3349 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 3350 dev_priv->rps.max_freq_softlimit << 24 | 3351 dev_priv->rps.min_freq_softlimit << 16); 3352 3353 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 3354 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 3355 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 3356 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 3357 3358 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3359 3360 /* 5: Enable RPS */ 3361 I915_WRITE(GEN6_RP_CONTROL, 3362 GEN6_RP_MEDIA_TURBO | 3363 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3364 GEN6_RP_MEDIA_IS_GFX | 3365 GEN6_RP_ENABLE | 3366 GEN6_RP_UP_BUSY_AVG | 3367 GEN6_RP_DOWN_IDLE_AVG); 3368 3369 /* 6: Ring frequency + overclocking (our driver does this later */ 3370 3371 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); 3372 3373 gen6_enable_rps_interrupts(dev); 3374 3375 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 3376 } 3377 3378 static void gen6_enable_rps(struct drm_device *dev) 3379 { 3380 struct drm_i915_private *dev_priv = dev->dev_private; 3381 struct intel_ring_buffer *ring; 3382 u32 rp_state_cap; 3383 u32 gt_perf_status; 3384 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 3385 u32 gtfifodbg; 3386 int rc6_mode; 3387 int i, ret; 3388 3389 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3390 3391 /* Here begins a magic sequence of register writes to enable 3392 * auto-downclocking. 3393 * 3394 * Perhaps there might be some value in exposing these to 3395 * userspace... 3396 */ 3397 I915_WRITE(GEN6_RC_STATE, 0); 3398 3399 /* Clear the DBG now so we don't confuse earlier errors */ 3400 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 3401 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 3402 I915_WRITE(GTFIFODBG, gtfifodbg); 3403 } 3404 3405 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 3406 3407 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 3408 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 3409 3410 /* All of these values are in units of 50MHz */ 3411 dev_priv->rps.cur_freq = 0; 3412 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ 3413 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 3414 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 3415 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 3416 /* XXX: only BYT has a special efficient freq */ 3417 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 3418 /* hw_max = RP0 until we check for overclocking */ 3419 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 3420 3421 /* Preserve min/max settings in case of re-init */ 3422 if (dev_priv->rps.max_freq_softlimit == 0) 3423 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 3424 3425 if (dev_priv->rps.min_freq_softlimit == 0) 3426 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 3427 3428 /* disable the counters and set deterministic thresholds */ 3429 I915_WRITE(GEN6_RC_CONTROL, 0); 3430 3431 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 3432 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 3433 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 3434 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 3435 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 3436 3437 for_each_ring(ring, dev_priv, i) 3438 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 3439 3440 I915_WRITE(GEN6_RC_SLEEP, 0); 3441 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 3442 if (IS_IVYBRIDGE(dev)) 3443 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 3444 else 3445 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 3446 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 3447 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 3448 3449 /* Check if we are enabling RC6 */ 3450 rc6_mode = intel_enable_rc6(dev_priv->dev); 3451 if (rc6_mode & INTEL_RC6_ENABLE) 3452 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 3453 3454 /* We don't use those on Haswell */ 3455 if (!IS_HASWELL(dev)) { 3456 if (rc6_mode & INTEL_RC6p_ENABLE) 3457 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 3458 3459 if (rc6_mode & INTEL_RC6pp_ENABLE) 3460 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 3461 } 3462 3463 intel_print_rc6_info(dev, rc6_mask); 3464 3465 I915_WRITE(GEN6_RC_CONTROL, 3466 rc6_mask | 3467 GEN6_RC_CTL_EI_MODE(1) | 3468 GEN6_RC_CTL_HW_ENABLE); 3469 3470 /* Power down if completely idle for over 50ms */ 3471 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 3472 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3473 3474 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 3475 if (ret) 3476 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 3477 3478 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 3479 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 3480 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 3481 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 3482 (pcu_mbox & 0xff) * 50); 3483 dev_priv->rps.max_freq = pcu_mbox & 0xff; 3484 } 3485 3486 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 3487 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3488 3489 gen6_enable_rps_interrupts(dev); 3490 3491 rc6vids = 0; 3492 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 3493 if (IS_GEN6(dev) && ret) { 3494 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 3495 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 3496 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 3497 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 3498 rc6vids &= 0xffff00; 3499 rc6vids |= GEN6_ENCODE_RC6_VID(450); 3500 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 3501 if (ret) 3502 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 3503 } 3504 3505 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 3506 } 3507 3508 void gen6_update_ring_freq(struct drm_device *dev) 3509 { 3510 struct drm_i915_private *dev_priv = dev->dev_private; 3511 int min_freq = 15; 3512 unsigned int gpu_freq; 3513 unsigned int max_ia_freq, min_ring_freq; 3514 int scaling_factor = 180; 3515 #ifndef __NetBSD__ 3516 struct cpufreq_policy *policy; 3517 #endif 3518 3519 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3520 3521 #ifdef __NetBSD__ 3522 { 3523 extern uint64_t tsc_freq; /* x86 TSC frequency in Hz */ 3524 max_ia_freq = (tsc_freq / 1000); 3525 } 3526 #else 3527 policy = cpufreq_cpu_get(0); 3528 if (policy) { 3529 max_ia_freq = policy->cpuinfo.max_freq; 3530 cpufreq_cpu_put(policy); 3531 } else { 3532 /* 3533 * Default to measured freq if none found, PCU will ensure we 3534 * don't go over 3535 */ 3536 max_ia_freq = tsc_khz; 3537 } 3538 #endif 3539 3540 /* Convert from kHz to MHz */ 3541 max_ia_freq /= 1000; 3542 3543 min_ring_freq = I915_READ(DCLK) & 0xf; 3544 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 3545 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 3546 3547 /* 3548 * For each potential GPU frequency, load a ring frequency we'd like 3549 * to use for memory access. We do this by specifying the IA frequency 3550 * the PCU should use as a reference to determine the ring frequency. 3551 */ 3552 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; 3553 gpu_freq--) { 3554 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; 3555 unsigned int ia_freq = 0, ring_freq = 0; 3556 3557 if (INTEL_INFO(dev)->gen >= 8) { 3558 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 3559 ring_freq = max(min_ring_freq, gpu_freq); 3560 } else if (IS_HASWELL(dev)) { 3561 ring_freq = mult_frac(gpu_freq, 5, 4); 3562 ring_freq = max(min_ring_freq, ring_freq); 3563 /* leave ia_freq as the default, chosen by cpufreq */ 3564 } else { 3565 /* On older processors, there is no separate ring 3566 * clock domain, so in order to boost the bandwidth 3567 * of the ring, we need to upclock the CPU (ia_freq). 3568 * 3569 * For GPU frequencies less than 750MHz, 3570 * just use the lowest ring freq. 3571 */ 3572 if (gpu_freq < min_freq) 3573 ia_freq = 800; 3574 else 3575 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 3576 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 3577 } 3578 3579 sandybridge_pcode_write(dev_priv, 3580 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 3581 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 3582 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 3583 gpu_freq); 3584 } 3585 } 3586 3587 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 3588 { 3589 u32 val, rp0; 3590 3591 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 3592 3593 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 3594 /* Clamp to max */ 3595 rp0 = min_t(u32, rp0, 0xea); 3596 3597 return rp0; 3598 } 3599 3600 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 3601 { 3602 u32 val, rpe; 3603 3604 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 3605 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 3606 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 3607 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 3608 3609 return rpe; 3610 } 3611 3612 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 3613 { 3614 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 3615 } 3616 3617 /* Check that the pctx buffer wasn't move under us. */ 3618 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 3619 { 3620 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 3621 3622 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 3623 dev_priv->vlv_pctx->stolen->start); 3624 } 3625 3626 static void valleyview_setup_pctx(struct drm_device *dev) 3627 { 3628 struct drm_i915_private *dev_priv = dev->dev_private; 3629 struct drm_i915_gem_object *pctx; 3630 unsigned long pctx_paddr; 3631 u32 pcbr; 3632 int pctx_size = 24*1024; 3633 3634 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 3635 3636 pcbr = I915_READ(VLV_PCBR); 3637 if (pcbr) { 3638 /* BIOS set it up already, grab the pre-alloc'd space */ 3639 int pcbr_offset; 3640 3641 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 3642 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 3643 pcbr_offset, 3644 I915_GTT_OFFSET_NONE, 3645 pctx_size); 3646 goto out; 3647 } 3648 3649 /* 3650 * From the Gunit register HAS: 3651 * The Gfx driver is expected to program this register and ensure 3652 * proper allocation within Gfx stolen memory. For example, this 3653 * register should be programmed such than the PCBR range does not 3654 * overlap with other ranges, such as the frame buffer, protected 3655 * memory, or any other relevant ranges. 3656 */ 3657 pctx = i915_gem_object_create_stolen(dev, pctx_size); 3658 if (!pctx) { 3659 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 3660 return; 3661 } 3662 3663 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 3664 I915_WRITE(VLV_PCBR, pctx_paddr); 3665 3666 out: 3667 dev_priv->vlv_pctx = pctx; 3668 } 3669 3670 static void valleyview_cleanup_pctx(struct drm_device *dev) 3671 { 3672 struct drm_i915_private *dev_priv = dev->dev_private; 3673 3674 if (WARN_ON(!dev_priv->vlv_pctx)) 3675 return; 3676 3677 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 3678 dev_priv->vlv_pctx = NULL; 3679 } 3680 3681 static void valleyview_enable_rps(struct drm_device *dev) 3682 { 3683 struct drm_i915_private *dev_priv = dev->dev_private; 3684 struct intel_ring_buffer *ring; 3685 u32 gtfifodbg, val, rc6_mode = 0; 3686 int i; 3687 3688 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3689 3690 valleyview_check_pctx(dev_priv); 3691 3692 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 3693 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 3694 gtfifodbg); 3695 I915_WRITE(GTFIFODBG, gtfifodbg); 3696 } 3697 3698 /* If VLV, Forcewake all wells, else re-direct to regular path */ 3699 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 3700 3701 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 3702 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 3703 I915_WRITE(GEN6_RP_UP_EI, 66000); 3704 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 3705 3706 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3707 3708 I915_WRITE(GEN6_RP_CONTROL, 3709 GEN6_RP_MEDIA_TURBO | 3710 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3711 GEN6_RP_MEDIA_IS_GFX | 3712 GEN6_RP_ENABLE | 3713 GEN6_RP_UP_BUSY_AVG | 3714 GEN6_RP_DOWN_IDLE_CONT); 3715 3716 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 3717 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 3718 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 3719 3720 for_each_ring(ring, dev_priv, i) 3721 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 3722 3723 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 3724 3725 /* allows RC6 residency counter to work */ 3726 I915_WRITE(VLV_COUNTER_CONTROL, 3727 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 3728 VLV_MEDIA_RC6_COUNT_EN | 3729 VLV_RENDER_RC6_COUNT_EN)); 3730 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 3731 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 3732 3733 intel_print_rc6_info(dev, rc6_mode); 3734 3735 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 3736 3737 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 3738 3739 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); 3740 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 3741 3742 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 3743 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 3744 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 3745 dev_priv->rps.cur_freq); 3746 3747 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 3748 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 3749 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 3750 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), 3751 dev_priv->rps.max_freq); 3752 3753 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 3754 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 3755 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 3756 dev_priv->rps.efficient_freq); 3757 3758 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 3759 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 3760 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), 3761 dev_priv->rps.min_freq); 3762 3763 /* Preserve min/max settings in case of re-init */ 3764 if (dev_priv->rps.max_freq_softlimit == 0) 3765 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 3766 3767 if (dev_priv->rps.min_freq_softlimit == 0) 3768 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 3769 3770 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 3771 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 3772 dev_priv->rps.efficient_freq); 3773 3774 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 3775 3776 gen6_enable_rps_interrupts(dev); 3777 3778 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 3779 } 3780 3781 void ironlake_teardown_rc6(struct drm_device *dev) 3782 { 3783 struct drm_i915_private *dev_priv = dev->dev_private; 3784 3785 if (dev_priv->ips.renderctx) { 3786 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); 3787 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 3788 dev_priv->ips.renderctx = NULL; 3789 } 3790 3791 if (dev_priv->ips.pwrctx) { 3792 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); 3793 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 3794 dev_priv->ips.pwrctx = NULL; 3795 } 3796 } 3797 3798 static void ironlake_disable_rc6(struct drm_device *dev) 3799 { 3800 struct drm_i915_private *dev_priv = dev->dev_private; 3801 3802 if (I915_READ(PWRCTXA)) { 3803 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 3804 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 3805 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 3806 50); 3807 3808 I915_WRITE(PWRCTXA, 0); 3809 POSTING_READ(PWRCTXA); 3810 3811 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 3812 POSTING_READ(RSTDBYCTL); 3813 } 3814 } 3815 3816 static int ironlake_setup_rc6(struct drm_device *dev) 3817 { 3818 struct drm_i915_private *dev_priv = dev->dev_private; 3819 3820 if (dev_priv->ips.renderctx == NULL) 3821 dev_priv->ips.renderctx = intel_alloc_context_page(dev); 3822 if (!dev_priv->ips.renderctx) 3823 return -ENOMEM; 3824 3825 if (dev_priv->ips.pwrctx == NULL) 3826 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); 3827 if (!dev_priv->ips.pwrctx) { 3828 ironlake_teardown_rc6(dev); 3829 return -ENOMEM; 3830 } 3831 3832 return 0; 3833 } 3834 3835 static void ironlake_enable_rc6(struct drm_device *dev) 3836 { 3837 struct drm_i915_private *dev_priv = dev->dev_private; 3838 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 3839 bool was_interruptible; 3840 int ret; 3841 3842 /* rc6 disabled by default due to repeated reports of hanging during 3843 * boot and resume. 3844 */ 3845 if (!intel_enable_rc6(dev)) 3846 return; 3847 3848 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 3849 3850 ret = ironlake_setup_rc6(dev); 3851 if (ret) 3852 return; 3853 3854 was_interruptible = dev_priv->mm.interruptible; 3855 dev_priv->mm.interruptible = false; 3856 3857 /* 3858 * GPU can automatically power down the render unit if given a page 3859 * to save state. 3860 */ 3861 ret = intel_ring_begin(ring, 6); 3862 if (ret) { 3863 ironlake_teardown_rc6(dev); 3864 dev_priv->mm.interruptible = was_interruptible; 3865 return; 3866 } 3867 3868 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 3869 intel_ring_emit(ring, MI_SET_CONTEXT); 3870 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | 3871 MI_MM_SPACE_GTT | 3872 MI_SAVE_EXT_STATE_EN | 3873 MI_RESTORE_EXT_STATE_EN | 3874 MI_RESTORE_INHIBIT); 3875 intel_ring_emit(ring, MI_SUSPEND_FLUSH); 3876 intel_ring_emit(ring, MI_NOOP); 3877 intel_ring_emit(ring, MI_FLUSH); 3878 intel_ring_advance(ring); 3879 3880 /* 3881 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 3882 * does an implicit flush, combined with MI_FLUSH above, it should be 3883 * safe to assume that renderctx is valid 3884 */ 3885 ret = intel_ring_idle(ring); 3886 dev_priv->mm.interruptible = was_interruptible; 3887 if (ret) { 3888 DRM_ERROR("failed to enable ironlake power savings\n"); 3889 ironlake_teardown_rc6(dev); 3890 return; 3891 } 3892 3893 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); 3894 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 3895 3896 intel_print_rc6_info(dev, INTEL_RC6_ENABLE); 3897 } 3898 3899 static unsigned long intel_pxfreq(u32 vidfreq) 3900 { 3901 unsigned long freq; 3902 int div = (vidfreq & 0x3f0000) >> 16; 3903 int post = (vidfreq & 0x3000) >> 12; 3904 int pre = (vidfreq & 0x7); 3905 3906 if (!pre) 3907 return 0; 3908 3909 freq = ((div * 133333) / ((1<<post) * pre)); 3910 3911 return freq; 3912 } 3913 3914 static const struct cparams { 3915 u16 i; 3916 u16 t; 3917 u16 m; 3918 u16 c; 3919 } cparams[] = { 3920 { 1, 1333, 301, 28664 }, 3921 { 1, 1066, 294, 24460 }, 3922 { 1, 800, 294, 25192 }, 3923 { 0, 1333, 276, 27605 }, 3924 { 0, 1066, 276, 27605 }, 3925 { 0, 800, 231, 23784 }, 3926 }; 3927 3928 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 3929 { 3930 u64 total_count, diff, ret; 3931 u32 count1, count2, count3, m = 0, c = 0; 3932 unsigned long now = jiffies_to_msecs(jiffies), diff1; 3933 int i; 3934 3935 assert_spin_locked(&mchdev_lock); 3936 3937 diff1 = now - dev_priv->ips.last_time1; 3938 3939 /* Prevent division-by-zero if we are asking too fast. 3940 * Also, we don't get interesting results if we are polling 3941 * faster than once in 10ms, so just return the saved value 3942 * in such cases. 3943 */ 3944 if (diff1 <= 10) 3945 return dev_priv->ips.chipset_power; 3946 3947 count1 = I915_READ(DMIEC); 3948 count2 = I915_READ(DDREC); 3949 count3 = I915_READ(CSIEC); 3950 3951 total_count = count1 + count2 + count3; 3952 3953 /* FIXME: handle per-counter overflow */ 3954 if (total_count < dev_priv->ips.last_count1) { 3955 diff = ~0UL - dev_priv->ips.last_count1; 3956 diff += total_count; 3957 } else { 3958 diff = total_count - dev_priv->ips.last_count1; 3959 } 3960 3961 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 3962 if (cparams[i].i == dev_priv->ips.c_m && 3963 cparams[i].t == dev_priv->ips.r_t) { 3964 m = cparams[i].m; 3965 c = cparams[i].c; 3966 break; 3967 } 3968 } 3969 3970 diff = div_u64(diff, diff1); 3971 ret = ((m * diff) + c); 3972 ret = div_u64(ret, 10); 3973 3974 dev_priv->ips.last_count1 = total_count; 3975 dev_priv->ips.last_time1 = now; 3976 3977 dev_priv->ips.chipset_power = ret; 3978 3979 return ret; 3980 } 3981 3982 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 3983 { 3984 struct drm_device *dev = dev_priv->dev; 3985 unsigned long val; 3986 3987 if (INTEL_INFO(dev)->gen != 5) 3988 return 0; 3989 3990 spin_lock_irq(&mchdev_lock); 3991 3992 val = __i915_chipset_val(dev_priv); 3993 3994 spin_unlock_irq(&mchdev_lock); 3995 3996 return val; 3997 } 3998 3999 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 4000 { 4001 unsigned long m, x, b; 4002 u32 tsfs; 4003 4004 tsfs = I915_READ(TSFS); 4005 4006 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 4007 x = I915_READ8(TR1); 4008 4009 b = tsfs & TSFS_INTR_MASK; 4010 4011 return ((m * x) / 127) - b; 4012 } 4013 4014 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 4015 { 4016 struct drm_device *dev = dev_priv->dev; 4017 static const struct v_table { 4018 u16 vd; /* in .1 mil */ 4019 u16 vm; /* in .1 mil */ 4020 } v_table[] = { 4021 { 0, 0, }, 4022 { 375, 0, }, 4023 { 500, 0, }, 4024 { 625, 0, }, 4025 { 750, 0, }, 4026 { 875, 0, }, 4027 { 1000, 0, }, 4028 { 1125, 0, }, 4029 { 4125, 3000, }, 4030 { 4125, 3000, }, 4031 { 4125, 3000, }, 4032 { 4125, 3000, }, 4033 { 4125, 3000, }, 4034 { 4125, 3000, }, 4035 { 4125, 3000, }, 4036 { 4125, 3000, }, 4037 { 4125, 3000, }, 4038 { 4125, 3000, }, 4039 { 4125, 3000, }, 4040 { 4125, 3000, }, 4041 { 4125, 3000, }, 4042 { 4125, 3000, }, 4043 { 4125, 3000, }, 4044 { 4125, 3000, }, 4045 { 4125, 3000, }, 4046 { 4125, 3000, }, 4047 { 4125, 3000, }, 4048 { 4125, 3000, }, 4049 { 4125, 3000, }, 4050 { 4125, 3000, }, 4051 { 4125, 3000, }, 4052 { 4125, 3000, }, 4053 { 4250, 3125, }, 4054 { 4375, 3250, }, 4055 { 4500, 3375, }, 4056 { 4625, 3500, }, 4057 { 4750, 3625, }, 4058 { 4875, 3750, }, 4059 { 5000, 3875, }, 4060 { 5125, 4000, }, 4061 { 5250, 4125, }, 4062 { 5375, 4250, }, 4063 { 5500, 4375, }, 4064 { 5625, 4500, }, 4065 { 5750, 4625, }, 4066 { 5875, 4750, }, 4067 { 6000, 4875, }, 4068 { 6125, 5000, }, 4069 { 6250, 5125, }, 4070 { 6375, 5250, }, 4071 { 6500, 5375, }, 4072 { 6625, 5500, }, 4073 { 6750, 5625, }, 4074 { 6875, 5750, }, 4075 { 7000, 5875, }, 4076 { 7125, 6000, }, 4077 { 7250, 6125, }, 4078 { 7375, 6250, }, 4079 { 7500, 6375, }, 4080 { 7625, 6500, }, 4081 { 7750, 6625, }, 4082 { 7875, 6750, }, 4083 { 8000, 6875, }, 4084 { 8125, 7000, }, 4085 { 8250, 7125, }, 4086 { 8375, 7250, }, 4087 { 8500, 7375, }, 4088 { 8625, 7500, }, 4089 { 8750, 7625, }, 4090 { 8875, 7750, }, 4091 { 9000, 7875, }, 4092 { 9125, 8000, }, 4093 { 9250, 8125, }, 4094 { 9375, 8250, }, 4095 { 9500, 8375, }, 4096 { 9625, 8500, }, 4097 { 9750, 8625, }, 4098 { 9875, 8750, }, 4099 { 10000, 8875, }, 4100 { 10125, 9000, }, 4101 { 10250, 9125, }, 4102 { 10375, 9250, }, 4103 { 10500, 9375, }, 4104 { 10625, 9500, }, 4105 { 10750, 9625, }, 4106 { 10875, 9750, }, 4107 { 11000, 9875, }, 4108 { 11125, 10000, }, 4109 { 11250, 10125, }, 4110 { 11375, 10250, }, 4111 { 11500, 10375, }, 4112 { 11625, 10500, }, 4113 { 11750, 10625, }, 4114 { 11875, 10750, }, 4115 { 12000, 10875, }, 4116 { 12125, 11000, }, 4117 { 12250, 11125, }, 4118 { 12375, 11250, }, 4119 { 12500, 11375, }, 4120 { 12625, 11500, }, 4121 { 12750, 11625, }, 4122 { 12875, 11750, }, 4123 { 13000, 11875, }, 4124 { 13125, 12000, }, 4125 { 13250, 12125, }, 4126 { 13375, 12250, }, 4127 { 13500, 12375, }, 4128 { 13625, 12500, }, 4129 { 13750, 12625, }, 4130 { 13875, 12750, }, 4131 { 14000, 12875, }, 4132 { 14125, 13000, }, 4133 { 14250, 13125, }, 4134 { 14375, 13250, }, 4135 { 14500, 13375, }, 4136 { 14625, 13500, }, 4137 { 14750, 13625, }, 4138 { 14875, 13750, }, 4139 { 15000, 13875, }, 4140 { 15125, 14000, }, 4141 { 15250, 14125, }, 4142 { 15375, 14250, }, 4143 { 15500, 14375, }, 4144 { 15625, 14500, }, 4145 { 15750, 14625, }, 4146 { 15875, 14750, }, 4147 { 16000, 14875, }, 4148 { 16125, 15000, }, 4149 }; 4150 if (INTEL_INFO(dev)->is_mobile) 4151 return v_table[pxvid].vm; 4152 else 4153 return v_table[pxvid].vd; 4154 } 4155 4156 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 4157 { 4158 struct timespec now, diff1; 4159 u64 diff; 4160 unsigned long diffms; 4161 u32 count; 4162 4163 assert_spin_locked(&mchdev_lock); 4164 4165 getrawmonotonic(&now); 4166 diff1 = timespec_sub(now, dev_priv->ips.last_time2); 4167 4168 /* Don't divide by 0 */ 4169 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 4170 if (!diffms) 4171 return; 4172 4173 count = I915_READ(GFXEC); 4174 4175 if (count < dev_priv->ips.last_count2) { 4176 diff = ~0UL - dev_priv->ips.last_count2; 4177 diff += count; 4178 } else { 4179 diff = count - dev_priv->ips.last_count2; 4180 } 4181 4182 dev_priv->ips.last_count2 = count; 4183 dev_priv->ips.last_time2 = now; 4184 4185 /* More magic constants... */ 4186 diff = diff * 1181; 4187 diff = div_u64(diff, diffms * 10); 4188 dev_priv->ips.gfx_power = diff; 4189 } 4190 4191 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 4192 { 4193 struct drm_device *dev = dev_priv->dev; 4194 4195 if (INTEL_INFO(dev)->gen != 5) 4196 return; 4197 4198 spin_lock_irq(&mchdev_lock); 4199 4200 __i915_update_gfx_val(dev_priv); 4201 4202 spin_unlock_irq(&mchdev_lock); 4203 } 4204 4205 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 4206 { 4207 unsigned long t, corr, state1, corr2, state2; 4208 u32 pxvid, ext_v; 4209 4210 assert_spin_locked(&mchdev_lock); 4211 4212 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); 4213 pxvid = (pxvid >> 24) & 0x7f; 4214 ext_v = pvid_to_extvid(dev_priv, pxvid); 4215 4216 state1 = ext_v; 4217 4218 t = i915_mch_val(dev_priv); 4219 4220 /* Revel in the empirically derived constants */ 4221 4222 /* Correction factor in 1/100000 units */ 4223 if (t > 80) 4224 corr = ((t * 2349) + 135940); 4225 else if (t >= 50) 4226 corr = ((t * 964) + 29317); 4227 else /* < 50 */ 4228 corr = ((t * 301) + 1004); 4229 4230 corr = corr * ((150142 * state1) / 10000 - 78642); 4231 corr /= 100000; 4232 corr2 = (corr * dev_priv->ips.corr); 4233 4234 state2 = (corr2 * state1) / 10000; 4235 state2 /= 100; /* convert to mW */ 4236 4237 __i915_update_gfx_val(dev_priv); 4238 4239 return dev_priv->ips.gfx_power + state2; 4240 } 4241 4242 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 4243 { 4244 struct drm_device *dev = dev_priv->dev; 4245 unsigned long val; 4246 4247 if (INTEL_INFO(dev)->gen != 5) 4248 return 0; 4249 4250 spin_lock_irq(&mchdev_lock); 4251 4252 val = __i915_gfx_val(dev_priv); 4253 4254 spin_unlock_irq(&mchdev_lock); 4255 4256 return val; 4257 } 4258 4259 /** 4260 * i915_read_mch_val - return value for IPS use 4261 * 4262 * Calculate and return a value for the IPS driver to use when deciding whether 4263 * we have thermal and power headroom to increase CPU or GPU power budget. 4264 */ 4265 unsigned long i915_read_mch_val(void) 4266 { 4267 struct drm_i915_private *dev_priv; 4268 unsigned long chipset_val, graphics_val, ret = 0; 4269 4270 spin_lock_irq(&mchdev_lock); 4271 if (!i915_mch_dev) 4272 goto out_unlock; 4273 dev_priv = i915_mch_dev; 4274 4275 chipset_val = __i915_chipset_val(dev_priv); 4276 graphics_val = __i915_gfx_val(dev_priv); 4277 4278 ret = chipset_val + graphics_val; 4279 4280 out_unlock: 4281 spin_unlock_irq(&mchdev_lock); 4282 4283 return ret; 4284 } 4285 EXPORT_SYMBOL_GPL(i915_read_mch_val); 4286 4287 /** 4288 * i915_gpu_raise - raise GPU frequency limit 4289 * 4290 * Raise the limit; IPS indicates we have thermal headroom. 4291 */ 4292 bool i915_gpu_raise(void) 4293 { 4294 struct drm_i915_private *dev_priv; 4295 bool ret = true; 4296 4297 spin_lock_irq(&mchdev_lock); 4298 if (!i915_mch_dev) { 4299 ret = false; 4300 goto out_unlock; 4301 } 4302 dev_priv = i915_mch_dev; 4303 4304 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 4305 dev_priv->ips.max_delay--; 4306 4307 out_unlock: 4308 spin_unlock_irq(&mchdev_lock); 4309 4310 return ret; 4311 } 4312 EXPORT_SYMBOL_GPL(i915_gpu_raise); 4313 4314 /** 4315 * i915_gpu_lower - lower GPU frequency limit 4316 * 4317 * IPS indicates we're close to a thermal limit, so throttle back the GPU 4318 * frequency maximum. 4319 */ 4320 bool i915_gpu_lower(void) 4321 { 4322 struct drm_i915_private *dev_priv; 4323 bool ret = true; 4324 4325 spin_lock_irq(&mchdev_lock); 4326 if (!i915_mch_dev) { 4327 ret = false; 4328 goto out_unlock; 4329 } 4330 dev_priv = i915_mch_dev; 4331 4332 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 4333 dev_priv->ips.max_delay++; 4334 4335 out_unlock: 4336 spin_unlock_irq(&mchdev_lock); 4337 4338 return ret; 4339 } 4340 EXPORT_SYMBOL_GPL(i915_gpu_lower); 4341 4342 /** 4343 * i915_gpu_busy - indicate GPU business to IPS 4344 * 4345 * Tell the IPS driver whether or not the GPU is busy. 4346 */ 4347 bool i915_gpu_busy(void) 4348 { 4349 struct drm_i915_private *dev_priv; 4350 struct intel_ring_buffer *ring; 4351 bool ret = false; 4352 int i; 4353 4354 spin_lock_irq(&mchdev_lock); 4355 if (!i915_mch_dev) 4356 goto out_unlock; 4357 dev_priv = i915_mch_dev; 4358 4359 for_each_ring(ring, dev_priv, i) 4360 ret |= !list_empty(&ring->request_list); 4361 4362 out_unlock: 4363 spin_unlock_irq(&mchdev_lock); 4364 4365 return ret; 4366 } 4367 EXPORT_SYMBOL_GPL(i915_gpu_busy); 4368 4369 /** 4370 * i915_gpu_turbo_disable - disable graphics turbo 4371 * 4372 * Disable graphics turbo by resetting the max frequency and setting the 4373 * current frequency to the default. 4374 */ 4375 bool i915_gpu_turbo_disable(void) 4376 { 4377 struct drm_i915_private *dev_priv; 4378 bool ret = true; 4379 4380 spin_lock_irq(&mchdev_lock); 4381 if (!i915_mch_dev) { 4382 ret = false; 4383 goto out_unlock; 4384 } 4385 dev_priv = i915_mch_dev; 4386 4387 dev_priv->ips.max_delay = dev_priv->ips.fstart; 4388 4389 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 4390 ret = false; 4391 4392 out_unlock: 4393 spin_unlock_irq(&mchdev_lock); 4394 4395 return ret; 4396 } 4397 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 4398 4399 /** 4400 * Tells the intel_ips driver that the i915 driver is now loaded, if 4401 * IPS got loaded first. 4402 * 4403 * This awkward dance is so that neither module has to depend on the 4404 * other in order for IPS to do the appropriate communication of 4405 * GPU turbo limits to i915. 4406 */ 4407 static void 4408 ips_ping_for_i915_load(void) 4409 { 4410 void (*link)(void); 4411 4412 link = symbol_get(ips_link_to_i915_driver); 4413 if (link) { 4414 link(); 4415 symbol_put(ips_link_to_i915_driver); 4416 } 4417 } 4418 4419 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 4420 { 4421 #ifdef __NetBSD__ /* XXX */ 4422 /* 4423 * This seems as good a place as any to initialize mchdev_lock. 4424 * Taking the lock in the rest of this routine is silly, but... 4425 */ 4426 spin_lock_init(&mchdev_lock); 4427 #endif 4428 4429 /* We only register the i915 ips part with intel-ips once everything is 4430 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 4431 spin_lock_irq(&mchdev_lock); 4432 i915_mch_dev = dev_priv; 4433 spin_unlock_irq(&mchdev_lock); 4434 4435 ips_ping_for_i915_load(); 4436 } 4437 4438 void intel_gpu_ips_teardown(void) 4439 { 4440 #ifdef __NetBSD__ 4441 if (i915_mch_dev == NULL) 4442 return; 4443 #endif 4444 4445 spin_lock_irq(&mchdev_lock); 4446 i915_mch_dev = NULL; 4447 spin_unlock_irq(&mchdev_lock); 4448 4449 #ifdef __NetBSD__ 4450 spin_lock_destroy(&mchdev_lock); 4451 #endif 4452 } 4453 4454 static void intel_init_emon(struct drm_device *dev) 4455 { 4456 struct drm_i915_private *dev_priv = dev->dev_private; 4457 u32 lcfuse; 4458 u8 pxw[16]; 4459 int i; 4460 4461 /* Disable to program */ 4462 I915_WRITE(ECR, 0); 4463 POSTING_READ(ECR); 4464 4465 /* Program energy weights for various events */ 4466 I915_WRITE(SDEW, 0x15040d00); 4467 I915_WRITE(CSIEW0, 0x007f0000); 4468 I915_WRITE(CSIEW1, 0x1e220004); 4469 I915_WRITE(CSIEW2, 0x04000004); 4470 4471 for (i = 0; i < 5; i++) 4472 I915_WRITE(PEW + (i * 4), 0); 4473 for (i = 0; i < 3; i++) 4474 I915_WRITE(DEW + (i * 4), 0); 4475 4476 /* Program P-state weights to account for frequency power adjustment */ 4477 for (i = 0; i < 16; i++) { 4478 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 4479 unsigned long freq = intel_pxfreq(pxvidfreq); 4480 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 4481 PXVFREQ_PX_SHIFT; 4482 unsigned long val; 4483 4484 val = vid * vid; 4485 val *= (freq / 1000); 4486 val *= 255; 4487 val /= (127*127*900); 4488 if (val > 0xff) 4489 DRM_ERROR("bad pxval: %ld\n", val); 4490 pxw[i] = val; 4491 } 4492 /* Render standby states get 0 weight */ 4493 pxw[14] = 0; 4494 pxw[15] = 0; 4495 4496 for (i = 0; i < 4; i++) { 4497 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 4498 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 4499 I915_WRITE(PXW + (i * 4), val); 4500 } 4501 4502 /* Adjust magic regs to magic values (more experimental results) */ 4503 I915_WRITE(OGW0, 0); 4504 I915_WRITE(OGW1, 0); 4505 I915_WRITE(EG0, 0x00007f00); 4506 I915_WRITE(EG1, 0x0000000e); 4507 I915_WRITE(EG2, 0x000e0000); 4508 I915_WRITE(EG3, 0x68000300); 4509 I915_WRITE(EG4, 0x42000000); 4510 I915_WRITE(EG5, 0x00140031); 4511 I915_WRITE(EG6, 0); 4512 I915_WRITE(EG7, 0); 4513 4514 for (i = 0; i < 8; i++) 4515 I915_WRITE(PXWL + (i * 4), 0); 4516 4517 /* Enable PMON + select events */ 4518 I915_WRITE(ECR, 0x80000019); 4519 4520 lcfuse = I915_READ(LCFUSE02); 4521 4522 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 4523 } 4524 4525 void intel_init_gt_powersave(struct drm_device *dev) 4526 { 4527 if (IS_VALLEYVIEW(dev)) 4528 valleyview_setup_pctx(dev); 4529 } 4530 4531 void intel_cleanup_gt_powersave(struct drm_device *dev) 4532 { 4533 if (IS_VALLEYVIEW(dev)) 4534 valleyview_cleanup_pctx(dev); 4535 } 4536 4537 void intel_disable_gt_powersave(struct drm_device *dev) 4538 { 4539 struct drm_i915_private *dev_priv = dev->dev_private; 4540 4541 /* Interrupts should be disabled already to avoid re-arming. */ 4542 WARN_ON(dev->irq_enabled); 4543 4544 if (IS_IRONLAKE_M(dev)) { 4545 ironlake_disable_drps(dev); 4546 ironlake_disable_rc6(dev); 4547 } else if (INTEL_INFO(dev)->gen >= 6) { 4548 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 4549 cancel_work_sync(&dev_priv->rps.work); 4550 mutex_lock(&dev_priv->rps.hw_lock); 4551 if (IS_VALLEYVIEW(dev)) 4552 valleyview_disable_rps(dev); 4553 else 4554 gen6_disable_rps(dev); 4555 dev_priv->rps.enabled = false; 4556 mutex_unlock(&dev_priv->rps.hw_lock); 4557 } 4558 } 4559 4560 static void intel_gen6_powersave_work(struct work_struct *work) 4561 { 4562 struct drm_i915_private *dev_priv = 4563 container_of(work, struct drm_i915_private, 4564 rps.delayed_resume_work.work); 4565 struct drm_device *dev = dev_priv->dev; 4566 4567 mutex_lock(&dev_priv->rps.hw_lock); 4568 4569 if (IS_VALLEYVIEW(dev)) { 4570 valleyview_enable_rps(dev); 4571 } else if (IS_BROADWELL(dev)) { 4572 gen8_enable_rps(dev); 4573 gen6_update_ring_freq(dev); 4574 } else { 4575 gen6_enable_rps(dev); 4576 gen6_update_ring_freq(dev); 4577 } 4578 dev_priv->rps.enabled = true; 4579 mutex_unlock(&dev_priv->rps.hw_lock); 4580 } 4581 4582 void intel_enable_gt_powersave(struct drm_device *dev) 4583 { 4584 struct drm_i915_private *dev_priv = dev->dev_private; 4585 4586 if (IS_IRONLAKE_M(dev)) { 4587 ironlake_enable_drps(dev); 4588 ironlake_enable_rc6(dev); 4589 intel_init_emon(dev); 4590 } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 4591 /* 4592 * PCU communication is slow and this doesn't need to be 4593 * done at any specific time, so do this out of our fast path 4594 * to make resume and init faster. 4595 */ 4596 schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 4597 round_jiffies_up_relative(HZ)); 4598 } 4599 } 4600 4601 static void ibx_init_clock_gating(struct drm_device *dev) 4602 { 4603 struct drm_i915_private *dev_priv = dev->dev_private; 4604 4605 /* 4606 * On Ibex Peak and Cougar Point, we need to disable clock 4607 * gating for the panel power sequencer or it will fail to 4608 * start up when no ports are active. 4609 */ 4610 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 4611 } 4612 4613 static void g4x_disable_trickle_feed(struct drm_device *dev) 4614 { 4615 struct drm_i915_private *dev_priv = dev->dev_private; 4616 int pipe; 4617 4618 for_each_pipe(pipe) { 4619 I915_WRITE(DSPCNTR(pipe), 4620 I915_READ(DSPCNTR(pipe)) | 4621 DISPPLANE_TRICKLE_FEED_DISABLE); 4622 intel_flush_primary_plane(dev_priv, pipe); 4623 } 4624 } 4625 4626 static void ilk_init_lp_watermarks(struct drm_device *dev) 4627 { 4628 struct drm_i915_private *dev_priv = dev->dev_private; 4629 4630 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 4631 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 4632 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 4633 4634 /* 4635 * Don't touch WM1S_LP_EN here. 4636 * Doing so could cause underruns. 4637 */ 4638 } 4639 4640 static void ironlake_init_clock_gating(struct drm_device *dev) 4641 { 4642 struct drm_i915_private *dev_priv = dev->dev_private; 4643 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 4644 4645 /* 4646 * Required for FBC 4647 * WaFbcDisableDpfcClockGating:ilk 4648 */ 4649 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 4650 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 4651 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 4652 4653 I915_WRITE(PCH_3DCGDIS0, 4654 MARIUNIT_CLOCK_GATE_DISABLE | 4655 SVSMUNIT_CLOCK_GATE_DISABLE); 4656 I915_WRITE(PCH_3DCGDIS1, 4657 VFMUNIT_CLOCK_GATE_DISABLE); 4658 4659 /* 4660 * According to the spec the following bits should be set in 4661 * order to enable memory self-refresh 4662 * The bit 22/21 of 0x42004 4663 * The bit 5 of 0x42020 4664 * The bit 15 of 0x45000 4665 */ 4666 I915_WRITE(ILK_DISPLAY_CHICKEN2, 4667 (I915_READ(ILK_DISPLAY_CHICKEN2) | 4668 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 4669 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 4670 I915_WRITE(DISP_ARB_CTL, 4671 (I915_READ(DISP_ARB_CTL) | 4672 DISP_FBC_WM_DIS)); 4673 4674 ilk_init_lp_watermarks(dev); 4675 4676 /* 4677 * Based on the document from hardware guys the following bits 4678 * should be set unconditionally in order to enable FBC. 4679 * The bit 22 of 0x42000 4680 * The bit 22 of 0x42004 4681 * The bit 7,8,9 of 0x42020. 4682 */ 4683 if (IS_IRONLAKE_M(dev)) { 4684 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 4685 I915_WRITE(ILK_DISPLAY_CHICKEN1, 4686 I915_READ(ILK_DISPLAY_CHICKEN1) | 4687 ILK_FBCQ_DIS); 4688 I915_WRITE(ILK_DISPLAY_CHICKEN2, 4689 I915_READ(ILK_DISPLAY_CHICKEN2) | 4690 ILK_DPARB_GATE); 4691 } 4692 4693 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 4694 4695 I915_WRITE(ILK_DISPLAY_CHICKEN2, 4696 I915_READ(ILK_DISPLAY_CHICKEN2) | 4697 ILK_ELPIN_409_SELECT); 4698 I915_WRITE(_3D_CHICKEN2, 4699 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 4700 _3D_CHICKEN2_WM_READ_PIPELINED); 4701 4702 /* WaDisableRenderCachePipelinedFlush:ilk */ 4703 I915_WRITE(CACHE_MODE_0, 4704 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4705 4706 g4x_disable_trickle_feed(dev); 4707 4708 ibx_init_clock_gating(dev); 4709 } 4710 4711 static void cpt_init_clock_gating(struct drm_device *dev) 4712 { 4713 struct drm_i915_private *dev_priv = dev->dev_private; 4714 int pipe; 4715 uint32_t val; 4716 4717 /* 4718 * On Ibex Peak and Cougar Point, we need to disable clock 4719 * gating for the panel power sequencer or it will fail to 4720 * start up when no ports are active. 4721 */ 4722 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 4723 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 4724 PCH_CPUNIT_CLOCK_GATE_DISABLE); 4725 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 4726 DPLS_EDP_PPS_FIX_DIS); 4727 /* The below fixes the weird display corruption, a few pixels shifted 4728 * downward, on (only) LVDS of some HP laptops with IVY. 4729 */ 4730 for_each_pipe(pipe) { 4731 val = I915_READ(TRANS_CHICKEN2(pipe)); 4732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 4733 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 4734 if (dev_priv->vbt.fdi_rx_polarity_inverted) 4735 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 4736 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 4737 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 4738 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 4739 I915_WRITE(TRANS_CHICKEN2(pipe), val); 4740 } 4741 /* WADP0ClockGatingDisable */ 4742 for_each_pipe(pipe) { 4743 I915_WRITE(TRANS_CHICKEN1(pipe), 4744 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 4745 } 4746 } 4747 4748 static void gen6_check_mch_setup(struct drm_device *dev) 4749 { 4750 struct drm_i915_private *dev_priv = dev->dev_private; 4751 uint32_t tmp; 4752 4753 tmp = I915_READ(MCH_SSKPD); 4754 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { 4755 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); 4756 DRM_INFO("This can cause pipe underruns and display issues.\n"); 4757 DRM_INFO("Please upgrade your BIOS to fix this.\n"); 4758 } 4759 } 4760 4761 static void gen6_init_clock_gating(struct drm_device *dev) 4762 { 4763 struct drm_i915_private *dev_priv = dev->dev_private; 4764 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 4765 4766 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 4767 4768 I915_WRITE(ILK_DISPLAY_CHICKEN2, 4769 I915_READ(ILK_DISPLAY_CHICKEN2) | 4770 ILK_ELPIN_409_SELECT); 4771 4772 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 4773 I915_WRITE(_3D_CHICKEN, 4774 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 4775 4776 /* WaSetupGtModeTdRowDispatch:snb */ 4777 if (IS_SNB_GT1(dev)) 4778 I915_WRITE(GEN6_GT_MODE, 4779 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 4780 4781 /* 4782 * BSpec recoomends 8x4 when MSAA is used, 4783 * however in practice 16x4 seems fastest. 4784 * 4785 * Note that PS/WM thread counts depend on the WIZ hashing 4786 * disable bit, which we don't touch here, but it's good 4787 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 4788 */ 4789 I915_WRITE(GEN6_GT_MODE, 4790 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); 4791 4792 ilk_init_lp_watermarks(dev); 4793 4794 I915_WRITE(CACHE_MODE_0, 4795 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 4796 4797 I915_WRITE(GEN6_UCGCTL1, 4798 I915_READ(GEN6_UCGCTL1) | 4799 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 4800 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 4801 4802 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 4803 * gating disable must be set. Failure to set it results in 4804 * flickering pixels due to Z write ordering failures after 4805 * some amount of runtime in the Mesa "fire" demo, and Unigine 4806 * Sanctuary and Tropics, and apparently anything else with 4807 * alpha test or pixel discard. 4808 * 4809 * According to the spec, bit 11 (RCCUNIT) must also be set, 4810 * but we didn't debug actual testcases to find it out. 4811 * 4812 * WaDisableRCCUnitClockGating:snb 4813 * WaDisableRCPBUnitClockGating:snb 4814 */ 4815 I915_WRITE(GEN6_UCGCTL2, 4816 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 4817 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 4818 4819 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 4820 I915_WRITE(_3D_CHICKEN3, 4821 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 4822 4823 /* 4824 * Bspec says: 4825 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 4826 * 3DSTATE_SF number of SF output attributes is more than 16." 4827 */ 4828 I915_WRITE(_3D_CHICKEN3, 4829 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 4830 4831 /* 4832 * According to the spec the following bits should be 4833 * set in order to enable memory self-refresh and fbc: 4834 * The bit21 and bit22 of 0x42000 4835 * The bit21 and bit22 of 0x42004 4836 * The bit5 and bit7 of 0x42020 4837 * The bit14 of 0x70180 4838 * The bit14 of 0x71180 4839 * 4840 * WaFbcAsynchFlipDisableFbcQueue:snb 4841 */ 4842 I915_WRITE(ILK_DISPLAY_CHICKEN1, 4843 I915_READ(ILK_DISPLAY_CHICKEN1) | 4844 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 4845 I915_WRITE(ILK_DISPLAY_CHICKEN2, 4846 I915_READ(ILK_DISPLAY_CHICKEN2) | 4847 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 4848 I915_WRITE(ILK_DSPCLK_GATE_D, 4849 I915_READ(ILK_DSPCLK_GATE_D) | 4850 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 4851 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 4852 4853 g4x_disable_trickle_feed(dev); 4854 4855 cpt_init_clock_gating(dev); 4856 4857 gen6_check_mch_setup(dev); 4858 } 4859 4860 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 4861 { 4862 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 4863 4864 /* 4865 * WaVSThreadDispatchOverride:ivb,vlv 4866 * 4867 * This actually overrides the dispatch 4868 * mode for all thread types. 4869 */ 4870 reg &= ~GEN7_FF_SCHED_MASK; 4871 reg |= GEN7_FF_TS_SCHED_HW; 4872 reg |= GEN7_FF_VS_SCHED_HW; 4873 reg |= GEN7_FF_DS_SCHED_HW; 4874 4875 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 4876 } 4877 4878 static void lpt_init_clock_gating(struct drm_device *dev) 4879 { 4880 struct drm_i915_private *dev_priv = dev->dev_private; 4881 4882 /* 4883 * TODO: this bit should only be enabled when really needed, then 4884 * disabled when not needed anymore in order to save power. 4885 */ 4886 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 4887 I915_WRITE(SOUTH_DSPCLK_GATE_D, 4888 I915_READ(SOUTH_DSPCLK_GATE_D) | 4889 PCH_LP_PARTITION_LEVEL_DISABLE); 4890 4891 /* WADPOClockGatingDisable:hsw */ 4892 I915_WRITE(_TRANSA_CHICKEN1, 4893 I915_READ(_TRANSA_CHICKEN1) | 4894 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 4895 } 4896 4897 static void lpt_suspend_hw(struct drm_device *dev) 4898 { 4899 struct drm_i915_private *dev_priv = dev->dev_private; 4900 4901 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 4902 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 4903 4904 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 4905 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 4906 } 4907 } 4908 4909 static void gen8_init_clock_gating(struct drm_device *dev) 4910 { 4911 struct drm_i915_private *dev_priv = dev->dev_private; 4912 enum pipe pipe; 4913 4914 I915_WRITE(WM3_LP_ILK, 0); 4915 I915_WRITE(WM2_LP_ILK, 0); 4916 I915_WRITE(WM1_LP_ILK, 0); 4917 4918 /* FIXME(BDW): Check all the w/a, some might only apply to 4919 * pre-production hw. */ 4920 4921 /* WaDisablePartialInstShootdown:bdw */ 4922 I915_WRITE(GEN8_ROW_CHICKEN, 4923 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); 4924 4925 /* WaDisableThreadStallDopClockGating:bdw */ 4926 /* FIXME: Unclear whether we really need this on production bdw. */ 4927 I915_WRITE(GEN8_ROW_CHICKEN, 4928 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); 4929 4930 /* 4931 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for 4932 * pre-production hardware 4933 */ 4934 I915_WRITE(HALF_SLICE_CHICKEN3, 4935 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); 4936 I915_WRITE(HALF_SLICE_CHICKEN3, 4937 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); 4938 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); 4939 4940 I915_WRITE(_3D_CHICKEN3, 4941 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); 4942 4943 I915_WRITE(COMMON_SLICE_CHICKEN2, 4944 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); 4945 4946 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 4947 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); 4948 4949 /* WaSwitchSolVfFArbitrationPriority:bdw */ 4950 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 4951 4952 /* WaPsrDPAMaskVBlankInSRD:bdw */ 4953 I915_WRITE(CHICKEN_PAR1_1, 4954 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 4955 4956 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 4957 for_each_pipe(pipe) { 4958 I915_WRITE(CHICKEN_PIPESL_1(pipe), 4959 I915_READ(CHICKEN_PIPESL_1(pipe)) | 4960 BDW_DPRS_MASK_VBLANK_SRD); 4961 } 4962 4963 /* Use Force Non-Coherent whenever executing a 3D context. This is a 4964 * workaround for for a possible hang in the unlikely event a TLB 4965 * invalidation occurs during a PSD flush. 4966 */ 4967 I915_WRITE(HDC_CHICKEN0, 4968 I915_READ(HDC_CHICKEN0) | 4969 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); 4970 4971 /* WaVSRefCountFullforceMissDisable:bdw */ 4972 /* WaDSRefCountFullforceMissDisable:bdw */ 4973 I915_WRITE(GEN7_FF_THREAD_MODE, 4974 I915_READ(GEN7_FF_THREAD_MODE) & 4975 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 4976 4977 /* 4978 * BSpec recommends 8x4 when MSAA is used, 4979 * however in practice 16x4 seems fastest. 4980 * 4981 * Note that PS/WM thread counts depend on the WIZ hashing 4982 * disable bit, which we don't touch here, but it's good 4983 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 4984 */ 4985 I915_WRITE(GEN7_GT_MODE, 4986 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); 4987 4988 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 4989 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 4990 4991 /* WaDisableSDEUnitClockGating:bdw */ 4992 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 4993 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 4994 4995 /* Wa4x4STCOptimizationDisable:bdw */ 4996 I915_WRITE(CACHE_MODE_1, 4997 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); 4998 } 4999 5000 static void haswell_init_clock_gating(struct drm_device *dev) 5001 { 5002 struct drm_i915_private *dev_priv = dev->dev_private; 5003 5004 ilk_init_lp_watermarks(dev); 5005 5006 /* L3 caching of data atomics doesn't work -- disable it. */ 5007 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 5008 I915_WRITE(HSW_ROW_CHICKEN3, 5009 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 5010 5011 /* This is required by WaCatErrorRejectionIssue:hsw */ 5012 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 5013 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 5014 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 5015 5016 /* WaVSRefCountFullforceMissDisable:hsw */ 5017 I915_WRITE(GEN7_FF_THREAD_MODE, 5018 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 5019 5020 /* enable HiZ Raw Stall Optimization */ 5021 I915_WRITE(CACHE_MODE_0_GEN7, 5022 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 5023 5024 /* WaDisable4x2SubspanOptimization:hsw */ 5025 I915_WRITE(CACHE_MODE_1, 5026 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 5027 5028 /* 5029 * BSpec recommends 8x4 when MSAA is used, 5030 * however in practice 16x4 seems fastest. 5031 * 5032 * Note that PS/WM thread counts depend on the WIZ hashing 5033 * disable bit, which we don't touch here, but it's good 5034 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 5035 */ 5036 I915_WRITE(GEN7_GT_MODE, 5037 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); 5038 5039 /* WaSwitchSolVfFArbitrationPriority:hsw */ 5040 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 5041 5042 /* WaRsPkgCStateDisplayPMReq:hsw */ 5043 I915_WRITE(CHICKEN_PAR1_1, 5044 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 5045 5046 lpt_init_clock_gating(dev); 5047 } 5048 5049 static void ivybridge_init_clock_gating(struct drm_device *dev) 5050 { 5051 struct drm_i915_private *dev_priv = dev->dev_private; 5052 uint32_t snpcr; 5053 5054 ilk_init_lp_watermarks(dev); 5055 5056 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 5057 5058 /* WaDisableEarlyCull:ivb */ 5059 I915_WRITE(_3D_CHICKEN3, 5060 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 5061 5062 /* WaDisableBackToBackFlipFix:ivb */ 5063 I915_WRITE(IVB_CHICKEN3, 5064 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 5065 CHICKEN3_DGMG_DONE_FIX_DISABLE); 5066 5067 /* WaDisablePSDDualDispatchEnable:ivb */ 5068 if (IS_IVB_GT1(dev)) 5069 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 5070 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 5071 5072 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 5073 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 5074 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 5075 5076 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 5077 I915_WRITE(GEN7_L3CNTLREG1, 5078 GEN7_WA_FOR_GEN7_L3_CONTROL); 5079 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 5080 GEN7_WA_L3_CHICKEN_MODE); 5081 if (IS_IVB_GT1(dev)) 5082 I915_WRITE(GEN7_ROW_CHICKEN2, 5083 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 5084 else { 5085 /* must write both registers */ 5086 I915_WRITE(GEN7_ROW_CHICKEN2, 5087 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 5088 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 5089 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 5090 } 5091 5092 /* WaForceL3Serialization:ivb */ 5093 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 5094 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 5095 5096 /* 5097 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 5098 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 5099 */ 5100 I915_WRITE(GEN6_UCGCTL2, 5101 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 5102 5103 /* This is required by WaCatErrorRejectionIssue:ivb */ 5104 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 5105 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 5106 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 5107 5108 g4x_disable_trickle_feed(dev); 5109 5110 gen7_setup_fixed_func_scheduler(dev_priv); 5111 5112 if (0) { /* causes HiZ corruption on ivb:gt1 */ 5113 /* enable HiZ Raw Stall Optimization */ 5114 I915_WRITE(CACHE_MODE_0_GEN7, 5115 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 5116 } 5117 5118 /* WaDisable4x2SubspanOptimization:ivb */ 5119 I915_WRITE(CACHE_MODE_1, 5120 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 5121 5122 /* 5123 * BSpec recommends 8x4 when MSAA is used, 5124 * however in practice 16x4 seems fastest. 5125 * 5126 * Note that PS/WM thread counts depend on the WIZ hashing 5127 * disable bit, which we don't touch here, but it's good 5128 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 5129 */ 5130 I915_WRITE(GEN7_GT_MODE, 5131 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); 5132 5133 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5134 snpcr &= ~GEN6_MBC_SNPCR_MASK; 5135 snpcr |= GEN6_MBC_SNPCR_MED; 5136 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 5137 5138 if (!HAS_PCH_NOP(dev)) 5139 cpt_init_clock_gating(dev); 5140 5141 gen6_check_mch_setup(dev); 5142 } 5143 5144 static void valleyview_init_clock_gating(struct drm_device *dev) 5145 { 5146 struct drm_i915_private *dev_priv = dev->dev_private; 5147 u32 val; 5148 5149 mutex_lock(&dev_priv->rps.hw_lock); 5150 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5151 mutex_unlock(&dev_priv->rps.hw_lock); 5152 switch ((val >> 6) & 3) { 5153 case 0: 5154 case 1: 5155 dev_priv->mem_freq = 800; 5156 break; 5157 case 2: 5158 dev_priv->mem_freq = 1066; 5159 break; 5160 case 3: 5161 dev_priv->mem_freq = 1333; 5162 break; 5163 } 5164 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); 5165 5166 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 5167 5168 /* WaDisableEarlyCull:vlv */ 5169 I915_WRITE(_3D_CHICKEN3, 5170 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 5171 5172 /* WaDisableBackToBackFlipFix:vlv */ 5173 I915_WRITE(IVB_CHICKEN3, 5174 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 5175 CHICKEN3_DGMG_DONE_FIX_DISABLE); 5176 5177 /* WaPsdDispatchEnable:vlv */ 5178 /* WaDisablePSDDualDispatchEnable:vlv */ 5179 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 5180 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 5181 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 5182 5183 /* WaForceL3Serialization:vlv */ 5184 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 5185 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 5186 5187 /* WaDisableDopClockGating:vlv */ 5188 I915_WRITE(GEN7_ROW_CHICKEN2, 5189 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 5190 5191 /* This is required by WaCatErrorRejectionIssue:vlv */ 5192 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 5193 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 5194 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 5195 5196 gen7_setup_fixed_func_scheduler(dev_priv); 5197 5198 /* 5199 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 5200 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 5201 */ 5202 I915_WRITE(GEN6_UCGCTL2, 5203 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 5204 5205 /* WaDisableL3Bank2xClockGate:vlv */ 5206 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 5207 5208 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 5209 5210 /* 5211 * BSpec says this must be set, even though 5212 * WaDisable4x2SubspanOptimization isn't listed for VLV. 5213 */ 5214 I915_WRITE(CACHE_MODE_1, 5215 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 5216 5217 /* 5218 * WaIncreaseL3CreditsForVLVB0:vlv 5219 * This is the hardware default actually. 5220 */ 5221 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 5222 5223 /* 5224 * WaDisableVLVClockGating_VBIIssue:vlv 5225 * Disable clock gating on th GCFG unit to prevent a delay 5226 * in the reporting of vblank events. 5227 */ 5228 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 5229 } 5230 5231 static void g4x_init_clock_gating(struct drm_device *dev) 5232 { 5233 struct drm_i915_private *dev_priv = dev->dev_private; 5234 uint32_t dspclk_gate; 5235 5236 I915_WRITE(RENCLK_GATE_D1, 0); 5237 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 5238 GS_UNIT_CLOCK_GATE_DISABLE | 5239 CL_UNIT_CLOCK_GATE_DISABLE); 5240 I915_WRITE(RAMCLK_GATE_D, 0); 5241 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 5242 OVRUNIT_CLOCK_GATE_DISABLE | 5243 OVCUNIT_CLOCK_GATE_DISABLE; 5244 if (IS_GM45(dev)) 5245 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 5246 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 5247 5248 /* WaDisableRenderCachePipelinedFlush */ 5249 I915_WRITE(CACHE_MODE_0, 5250 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 5251 5252 g4x_disable_trickle_feed(dev); 5253 } 5254 5255 static void crestline_init_clock_gating(struct drm_device *dev) 5256 { 5257 struct drm_i915_private *dev_priv = dev->dev_private; 5258 5259 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 5260 I915_WRITE(RENCLK_GATE_D2, 0); 5261 I915_WRITE(DSPCLK_GATE_D, 0); 5262 I915_WRITE(RAMCLK_GATE_D, 0); 5263 I915_WRITE16(DEUC, 0); 5264 I915_WRITE(MI_ARB_STATE, 5265 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 5266 } 5267 5268 static void broadwater_init_clock_gating(struct drm_device *dev) 5269 { 5270 struct drm_i915_private *dev_priv = dev->dev_private; 5271 5272 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 5273 I965_RCC_CLOCK_GATE_DISABLE | 5274 I965_RCPB_CLOCK_GATE_DISABLE | 5275 I965_ISC_CLOCK_GATE_DISABLE | 5276 I965_FBC_CLOCK_GATE_DISABLE); 5277 I915_WRITE(RENCLK_GATE_D2, 0); 5278 I915_WRITE(MI_ARB_STATE, 5279 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 5280 } 5281 5282 static void gen3_init_clock_gating(struct drm_device *dev) 5283 { 5284 struct drm_i915_private *dev_priv = dev->dev_private; 5285 u32 dstate = I915_READ(D_STATE); 5286 5287 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 5288 DSTATE_DOT_CLOCK_GATING; 5289 I915_WRITE(D_STATE, dstate); 5290 5291 if (IS_PINEVIEW(dev)) 5292 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 5293 5294 /* IIR "flip pending" means done if this bit is set */ 5295 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 5296 } 5297 5298 static void i85x_init_clock_gating(struct drm_device *dev) 5299 { 5300 struct drm_i915_private *dev_priv = dev->dev_private; 5301 5302 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 5303 } 5304 5305 static void i830_init_clock_gating(struct drm_device *dev) 5306 { 5307 struct drm_i915_private *dev_priv = dev->dev_private; 5308 5309 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 5310 } 5311 5312 void intel_init_clock_gating(struct drm_device *dev) 5313 { 5314 struct drm_i915_private *dev_priv = dev->dev_private; 5315 5316 dev_priv->display.init_clock_gating(dev); 5317 } 5318 5319 void intel_suspend_hw(struct drm_device *dev) 5320 { 5321 if (HAS_PCH_LPT(dev)) 5322 lpt_suspend_hw(dev); 5323 } 5324 5325 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 5326 for (i = 0; \ 5327 i < (power_domains)->power_well_count && \ 5328 ((power_well) = &(power_domains)->power_wells[i]); \ 5329 i++) \ 5330 if ((power_well)->domains & (domain_mask)) 5331 5332 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 5333 for (i = (power_domains)->power_well_count - 1; \ 5334 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 5335 i--) \ 5336 if ((power_well)->domains & (domain_mask)) 5337 5338 /** 5339 * We should only use the power well if we explicitly asked the hardware to 5340 * enable it, so check if it's enabled and also check if we've requested it to 5341 * be enabled. 5342 */ 5343 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 5344 struct i915_power_well *power_well) 5345 { 5346 return I915_READ(HSW_PWR_WELL_DRIVER) == 5347 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 5348 } 5349 5350 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, 5351 enum intel_display_power_domain domain) 5352 { 5353 struct i915_power_domains *power_domains; 5354 5355 power_domains = &dev_priv->power_domains; 5356 5357 return power_domains->domain_use_count[domain]; 5358 } 5359 5360 bool intel_display_power_enabled(struct drm_i915_private *dev_priv, 5361 enum intel_display_power_domain domain) 5362 { 5363 struct i915_power_domains *power_domains; 5364 struct i915_power_well *power_well; 5365 bool is_enabled; 5366 int i; 5367 5368 if (dev_priv->pm.suspended) 5369 return false; 5370 5371 power_domains = &dev_priv->power_domains; 5372 5373 is_enabled = true; 5374 5375 mutex_lock(&power_domains->lock); 5376 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 5377 if (power_well->always_on) 5378 continue; 5379 5380 if (!power_well->ops->is_enabled(dev_priv, power_well)) { 5381 is_enabled = false; 5382 break; 5383 } 5384 } 5385 mutex_unlock(&power_domains->lock); 5386 5387 return is_enabled; 5388 } 5389 5390 /* 5391 * Starting with Haswell, we have a "Power Down Well" that can be turned off 5392 * when not needed anymore. We have 4 registers that can request the power well 5393 * to be enabled, and it will only be disabled if none of the registers is 5394 * requesting it to be enabled. 5395 */ 5396 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 5397 { 5398 struct drm_device *dev = dev_priv->dev; 5399 unsigned long irqflags; 5400 5401 /* 5402 * After we re-enable the power well, if we touch VGA register 0x3d5 5403 * we'll get unclaimed register interrupts. This stops after we write 5404 * anything to the VGA MSR register. The vgacon module uses this 5405 * register all the time, so if we unbind our driver and, as a 5406 * consequence, bind vgacon, we'll get stuck in an infinite loop at 5407 * console_unlock(). So make here we touch the VGA MSR register, making 5408 * sure vgacon can keep working normally without triggering interrupts 5409 * and error messages. 5410 */ 5411 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 5412 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 5413 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 5414 5415 if (IS_BROADWELL(dev)) { 5416 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 5417 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B), 5418 dev_priv->de_irq_mask[PIPE_B]); 5419 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B), 5420 ~dev_priv->de_irq_mask[PIPE_B] | 5421 GEN8_PIPE_VBLANK); 5422 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C), 5423 dev_priv->de_irq_mask[PIPE_C]); 5424 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C), 5425 ~dev_priv->de_irq_mask[PIPE_C] | 5426 GEN8_PIPE_VBLANK); 5427 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C)); 5428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 5429 } 5430 } 5431 5432 static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe) 5433 { 5434 assert_spin_locked(&dev->vbl_lock); 5435 5436 dev->vblank[pipe].last = 0; 5437 } 5438 5439 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv) 5440 { 5441 struct drm_device *dev = dev_priv->dev; 5442 enum pipe pipe; 5443 unsigned long irqflags; 5444 5445 /* 5446 * After this, the registers on the pipes that are part of the power 5447 * well will become zero, so we have to adjust our counters according to 5448 * that. 5449 * 5450 * FIXME: Should we do this in general in drm_vblank_post_modeset? 5451 */ 5452 spin_lock_irqsave(&dev->vbl_lock, irqflags); 5453 for_each_pipe(pipe) 5454 if (pipe != PIPE_A) 5455 reset_vblank_counter(dev, pipe); 5456 spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 5457 } 5458 5459 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 5460 struct i915_power_well *power_well, bool enable) 5461 { 5462 bool is_enabled, enable_requested; 5463 uint32_t tmp; 5464 5465 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5466 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 5467 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 5468 5469 if (enable) { 5470 if (!enable_requested) 5471 I915_WRITE(HSW_PWR_WELL_DRIVER, 5472 HSW_PWR_WELL_ENABLE_REQUEST); 5473 5474 if (!is_enabled) { 5475 DRM_DEBUG_KMS("Enabling power well\n"); 5476 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 5477 HSW_PWR_WELL_STATE_ENABLED), 20)) 5478 DRM_ERROR("Timeout enabling power well\n"); 5479 } 5480 5481 hsw_power_well_post_enable(dev_priv); 5482 } else { 5483 if (enable_requested) { 5484 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 5485 POSTING_READ(HSW_PWR_WELL_DRIVER); 5486 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 5487 5488 hsw_power_well_post_disable(dev_priv); 5489 } 5490 } 5491 } 5492 5493 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 5494 struct i915_power_well *power_well) 5495 { 5496 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 5497 5498 /* 5499 * We're taking over the BIOS, so clear any requests made by it since 5500 * the driver is in charge now. 5501 */ 5502 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 5503 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 5504 } 5505 5506 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 5507 struct i915_power_well *power_well) 5508 { 5509 hsw_set_power_well(dev_priv, power_well, true); 5510 } 5511 5512 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 5513 struct i915_power_well *power_well) 5514 { 5515 hsw_set_power_well(dev_priv, power_well, false); 5516 } 5517 5518 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 5519 struct i915_power_well *power_well) 5520 { 5521 } 5522 5523 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 5524 struct i915_power_well *power_well) 5525 { 5526 return true; 5527 } 5528 5529 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 5530 struct i915_power_well *power_well, bool enable) 5531 { 5532 enum punit_power_well power_well_id = power_well->data; 5533 u32 mask; 5534 u32 state; 5535 u32 ctrl; 5536 5537 mask = PUNIT_PWRGT_MASK(power_well_id); 5538 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 5539 PUNIT_PWRGT_PWR_GATE(power_well_id); 5540 5541 mutex_lock(&dev_priv->rps.hw_lock); 5542 5543 #define COND \ 5544 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 5545 5546 if (COND) 5547 goto out; 5548 5549 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 5550 ctrl &= ~mask; 5551 ctrl |= state; 5552 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 5553 5554 if (wait_for(COND, 100)) 5555 DRM_ERROR("timout setting power well state %08x (%08x)\n", 5556 state, 5557 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 5558 5559 #undef COND 5560 5561 out: 5562 mutex_unlock(&dev_priv->rps.hw_lock); 5563 } 5564 5565 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 5566 struct i915_power_well *power_well) 5567 { 5568 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 5569 } 5570 5571 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 5572 struct i915_power_well *power_well) 5573 { 5574 vlv_set_power_well(dev_priv, power_well, true); 5575 } 5576 5577 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 5578 struct i915_power_well *power_well) 5579 { 5580 vlv_set_power_well(dev_priv, power_well, false); 5581 } 5582 5583 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 5584 struct i915_power_well *power_well) 5585 { 5586 int power_well_id = power_well->data; 5587 bool enabled = false; 5588 u32 mask; 5589 u32 state; 5590 u32 ctrl; 5591 5592 mask = PUNIT_PWRGT_MASK(power_well_id); 5593 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 5594 5595 mutex_lock(&dev_priv->rps.hw_lock); 5596 5597 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 5598 /* 5599 * We only ever set the power-on and power-gate states, anything 5600 * else is unexpected. 5601 */ 5602 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 5603 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 5604 if (state == ctrl) 5605 enabled = true; 5606 5607 /* 5608 * A transient state at this point would mean some unexpected party 5609 * is poking at the power controls too. 5610 */ 5611 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 5612 WARN_ON(ctrl != state); 5613 5614 mutex_unlock(&dev_priv->rps.hw_lock); 5615 5616 return enabled; 5617 } 5618 5619 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 5620 struct i915_power_well *power_well) 5621 { 5622 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 5623 5624 vlv_set_power_well(dev_priv, power_well, true); 5625 5626 spin_lock_irq(&dev_priv->irq_lock); 5627 valleyview_enable_display_irqs(dev_priv); 5628 spin_unlock_irq(&dev_priv->irq_lock); 5629 5630 /* 5631 * During driver initialization we need to defer enabling hotplug 5632 * processing until fbdev is set up. 5633 */ 5634 if (dev_priv->enable_hotplug_processing) 5635 intel_hpd_init(dev_priv->dev); 5636 5637 i915_redisable_vga_power_on(dev_priv->dev); 5638 } 5639 5640 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 5641 struct i915_power_well *power_well) 5642 { 5643 struct drm_device *dev = dev_priv->dev; 5644 enum pipe pipe; 5645 5646 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 5647 5648 spin_lock_irq(&dev_priv->irq_lock); 5649 for_each_pipe(pipe) 5650 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); 5651 5652 valleyview_disable_display_irqs(dev_priv); 5653 spin_unlock_irq(&dev_priv->irq_lock); 5654 5655 spin_lock_irq(&dev->vbl_lock); 5656 for_each_pipe(pipe) 5657 reset_vblank_counter(dev, pipe); 5658 spin_unlock_irq(&dev->vbl_lock); 5659 5660 vlv_set_power_well(dev_priv, power_well, false); 5661 } 5662 5663 static void check_power_well_state(struct drm_i915_private *dev_priv, 5664 struct i915_power_well *power_well) 5665 { 5666 bool enabled = power_well->ops->is_enabled(dev_priv, power_well); 5667 5668 if (power_well->always_on || !i915.disable_power_well) { 5669 if (!enabled) 5670 goto mismatch; 5671 5672 return; 5673 } 5674 5675 if (enabled != (power_well->count > 0)) 5676 goto mismatch; 5677 5678 return; 5679 5680 mismatch: 5681 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", 5682 power_well->name, power_well->always_on, enabled, 5683 power_well->count, i915.disable_power_well); 5684 } 5685 5686 void intel_display_power_get(struct drm_i915_private *dev_priv, 5687 enum intel_display_power_domain domain) 5688 { 5689 struct i915_power_domains *power_domains; 5690 struct i915_power_well *power_well; 5691 int i; 5692 5693 intel_runtime_pm_get(dev_priv); 5694 5695 power_domains = &dev_priv->power_domains; 5696 5697 mutex_lock(&power_domains->lock); 5698 5699 for_each_power_well(i, power_well, BIT(domain), power_domains) { 5700 if (!power_well->count++) { 5701 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 5702 power_well->ops->enable(dev_priv, power_well); 5703 } 5704 5705 check_power_well_state(dev_priv, power_well); 5706 } 5707 5708 power_domains->domain_use_count[domain]++; 5709 5710 mutex_unlock(&power_domains->lock); 5711 } 5712 5713 void intel_display_power_put(struct drm_i915_private *dev_priv, 5714 enum intel_display_power_domain domain) 5715 { 5716 struct i915_power_domains *power_domains; 5717 struct i915_power_well *power_well; 5718 int i; 5719 5720 power_domains = &dev_priv->power_domains; 5721 5722 mutex_lock(&power_domains->lock); 5723 5724 WARN_ON(!power_domains->domain_use_count[domain]); 5725 power_domains->domain_use_count[domain]--; 5726 5727 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 5728 WARN_ON(!power_well->count); 5729 5730 if (!--power_well->count && i915.disable_power_well) { 5731 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 5732 power_well->ops->disable(dev_priv, power_well); 5733 } 5734 5735 check_power_well_state(dev_priv, power_well); 5736 } 5737 5738 mutex_unlock(&power_domains->lock); 5739 5740 intel_runtime_pm_put(dev_priv); 5741 } 5742 5743 static struct i915_power_domains *hsw_pwr; 5744 5745 /* Display audio driver power well request */ 5746 void i915_request_power_well(void) 5747 { 5748 struct drm_i915_private *dev_priv; 5749 5750 if (WARN_ON(!hsw_pwr)) 5751 return; 5752 5753 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5754 power_domains); 5755 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 5756 } 5757 EXPORT_SYMBOL_GPL(i915_request_power_well); 5758 5759 /* Display audio driver power well release */ 5760 void i915_release_power_well(void) 5761 { 5762 struct drm_i915_private *dev_priv; 5763 5764 if (WARN_ON(!hsw_pwr)) 5765 return; 5766 5767 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5768 power_domains); 5769 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 5770 } 5771 EXPORT_SYMBOL_GPL(i915_release_power_well); 5772 5773 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 5774 5775 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 5776 BIT(POWER_DOMAIN_PIPE_A) | \ 5777 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 5778 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 5779 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 5780 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 5781 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 5782 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 5783 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 5784 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 5785 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 5786 BIT(POWER_DOMAIN_PORT_CRT) | \ 5787 BIT(POWER_DOMAIN_INIT)) 5788 #define HSW_DISPLAY_POWER_DOMAINS ( \ 5789 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 5790 BIT(POWER_DOMAIN_INIT)) 5791 5792 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 5793 HSW_ALWAYS_ON_POWER_DOMAINS | \ 5794 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 5795 #define BDW_DISPLAY_POWER_DOMAINS ( \ 5796 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 5797 BIT(POWER_DOMAIN_INIT)) 5798 5799 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 5800 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 5801 5802 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 5803 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 5804 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 5805 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 5806 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 5807 BIT(POWER_DOMAIN_PORT_CRT) | \ 5808 BIT(POWER_DOMAIN_INIT)) 5809 5810 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 5811 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 5812 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 5813 BIT(POWER_DOMAIN_INIT)) 5814 5815 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 5816 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 5817 BIT(POWER_DOMAIN_INIT)) 5818 5819 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 5820 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 5821 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 5822 BIT(POWER_DOMAIN_INIT)) 5823 5824 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 5825 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 5826 BIT(POWER_DOMAIN_INIT)) 5827 5828 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 5829 .sync_hw = i9xx_always_on_power_well_noop, 5830 .enable = i9xx_always_on_power_well_noop, 5831 .disable = i9xx_always_on_power_well_noop, 5832 .is_enabled = i9xx_always_on_power_well_enabled, 5833 }; 5834 5835 static struct i915_power_well i9xx_always_on_power_well[] = { 5836 { 5837 .name = "always-on", 5838 .always_on = 1, 5839 .domains = POWER_DOMAIN_MASK, 5840 .ops = &i9xx_always_on_power_well_ops, 5841 }, 5842 }; 5843 5844 static const struct i915_power_well_ops hsw_power_well_ops = { 5845 .sync_hw = hsw_power_well_sync_hw, 5846 .enable = hsw_power_well_enable, 5847 .disable = hsw_power_well_disable, 5848 .is_enabled = hsw_power_well_enabled, 5849 }; 5850 5851 static struct i915_power_well hsw_power_wells[] = { 5852 { 5853 .name = "always-on", 5854 .always_on = 1, 5855 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 5856 .ops = &i9xx_always_on_power_well_ops, 5857 }, 5858 { 5859 .name = "display", 5860 .domains = HSW_DISPLAY_POWER_DOMAINS, 5861 .ops = &hsw_power_well_ops, 5862 }, 5863 }; 5864 5865 static struct i915_power_well bdw_power_wells[] = { 5866 { 5867 .name = "always-on", 5868 .always_on = 1, 5869 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 5870 .ops = &i9xx_always_on_power_well_ops, 5871 }, 5872 { 5873 .name = "display", 5874 .domains = BDW_DISPLAY_POWER_DOMAINS, 5875 .ops = &hsw_power_well_ops, 5876 }, 5877 }; 5878 5879 static const struct i915_power_well_ops vlv_display_power_well_ops = { 5880 .sync_hw = vlv_power_well_sync_hw, 5881 .enable = vlv_display_power_well_enable, 5882 .disable = vlv_display_power_well_disable, 5883 .is_enabled = vlv_power_well_enabled, 5884 }; 5885 5886 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 5887 .sync_hw = vlv_power_well_sync_hw, 5888 .enable = vlv_power_well_enable, 5889 .disable = vlv_power_well_disable, 5890 .is_enabled = vlv_power_well_enabled, 5891 }; 5892 5893 static struct i915_power_well vlv_power_wells[] = { 5894 { 5895 .name = "always-on", 5896 .always_on = 1, 5897 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 5898 .ops = &i9xx_always_on_power_well_ops, 5899 }, 5900 { 5901 .name = "display", 5902 .domains = VLV_DISPLAY_POWER_DOMAINS, 5903 .data = PUNIT_POWER_WELL_DISP2D, 5904 .ops = &vlv_display_power_well_ops, 5905 }, 5906 { 5907 .name = "dpio-common", 5908 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 5909 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 5910 .ops = &vlv_dpio_power_well_ops, 5911 }, 5912 { 5913 .name = "dpio-tx-b-01", 5914 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 5915 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 5916 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 5917 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 5918 .ops = &vlv_dpio_power_well_ops, 5919 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 5920 }, 5921 { 5922 .name = "dpio-tx-b-23", 5923 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 5924 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 5925 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 5926 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 5927 .ops = &vlv_dpio_power_well_ops, 5928 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 5929 }, 5930 { 5931 .name = "dpio-tx-c-01", 5932 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 5933 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 5934 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 5935 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 5936 .ops = &vlv_dpio_power_well_ops, 5937 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 5938 }, 5939 { 5940 .name = "dpio-tx-c-23", 5941 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 5942 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 5943 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 5944 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 5945 .ops = &vlv_dpio_power_well_ops, 5946 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 5947 }, 5948 }; 5949 5950 #define set_power_wells(power_domains, __power_wells) ({ \ 5951 (power_domains)->power_wells = (__power_wells); \ 5952 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 5953 }) 5954 5955 int intel_power_domains_init(struct drm_i915_private *dev_priv) 5956 { 5957 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5958 5959 mutex_init(&power_domains->lock); 5960 5961 /* 5962 * The enabling order will be from lower to higher indexed wells, 5963 * the disabling order is reversed. 5964 */ 5965 if (IS_HASWELL(dev_priv->dev)) { 5966 set_power_wells(power_domains, hsw_power_wells); 5967 hsw_pwr = power_domains; 5968 } else if (IS_BROADWELL(dev_priv->dev)) { 5969 set_power_wells(power_domains, bdw_power_wells); 5970 hsw_pwr = power_domains; 5971 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 5972 set_power_wells(power_domains, vlv_power_wells); 5973 } else { 5974 set_power_wells(power_domains, i9xx_always_on_power_well); 5975 } 5976 5977 return 0; 5978 } 5979 5980 void intel_power_domains_remove(struct drm_i915_private *dev_priv) 5981 { 5982 hsw_pwr = NULL; 5983 } 5984 5985 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 5986 { 5987 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5988 struct i915_power_well *power_well; 5989 int i; 5990 5991 mutex_lock(&power_domains->lock); 5992 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) 5993 power_well->ops->sync_hw(dev_priv, power_well); 5994 mutex_unlock(&power_domains->lock); 5995 } 5996 5997 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 5998 { 5999 /* For now, we need the power well to be always enabled. */ 6000 intel_display_set_init_power(dev_priv, true); 6001 intel_power_domains_resume(dev_priv); 6002 } 6003 6004 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 6005 { 6006 intel_runtime_pm_get(dev_priv); 6007 } 6008 6009 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 6010 { 6011 intel_runtime_pm_put(dev_priv); 6012 } 6013 6014 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 6015 { 6016 struct drm_device *dev = dev_priv->dev; 6017 struct device *device = &dev->pdev->dev; 6018 6019 if (!HAS_RUNTIME_PM(dev)) 6020 return; 6021 6022 pm_runtime_get_sync(device); 6023 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 6024 } 6025 6026 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 6027 { 6028 struct drm_device *dev = dev_priv->dev; 6029 struct device *device = &dev->pdev->dev; 6030 6031 if (!HAS_RUNTIME_PM(dev)) 6032 return; 6033 6034 pm_runtime_mark_last_busy(device); 6035 pm_runtime_put_autosuspend(device); 6036 } 6037 6038 void intel_init_runtime_pm(struct drm_i915_private *dev_priv) 6039 { 6040 struct drm_device *dev = dev_priv->dev; 6041 struct device *device = &dev->pdev->dev; 6042 6043 if (!HAS_RUNTIME_PM(dev)) 6044 return; 6045 6046 pm_runtime_set_active(device); 6047 6048 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 6049 pm_runtime_mark_last_busy(device); 6050 pm_runtime_use_autosuspend(device); 6051 6052 pm_runtime_put_autosuspend(device); 6053 } 6054 6055 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) 6056 { 6057 struct drm_device *dev = dev_priv->dev; 6058 struct device *device = &dev->pdev->dev; 6059 6060 if (!HAS_RUNTIME_PM(dev)) 6061 return; 6062 6063 /* Make sure we're not suspended first. */ 6064 pm_runtime_get_sync(device); 6065 pm_runtime_disable(device); 6066 } 6067 6068 /* Set up chip specific power management-related functions */ 6069 void intel_init_pm(struct drm_device *dev) 6070 { 6071 struct drm_i915_private *dev_priv = dev->dev_private; 6072 6073 if (HAS_FBC(dev)) { 6074 if (INTEL_INFO(dev)->gen >= 7) { 6075 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 6076 dev_priv->display.enable_fbc = gen7_enable_fbc; 6077 dev_priv->display.disable_fbc = ironlake_disable_fbc; 6078 } else if (INTEL_INFO(dev)->gen >= 5) { 6079 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 6080 dev_priv->display.enable_fbc = ironlake_enable_fbc; 6081 dev_priv->display.disable_fbc = ironlake_disable_fbc; 6082 } else if (IS_GM45(dev)) { 6083 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 6084 dev_priv->display.enable_fbc = g4x_enable_fbc; 6085 dev_priv->display.disable_fbc = g4x_disable_fbc; 6086 } else { 6087 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 6088 dev_priv->display.enable_fbc = i8xx_enable_fbc; 6089 dev_priv->display.disable_fbc = i8xx_disable_fbc; 6090 6091 /* This value was pulled out of someone's hat */ 6092 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); 6093 } 6094 } 6095 6096 /* For cxsr */ 6097 if (IS_PINEVIEW(dev)) 6098 i915_pineview_get_mem_freq(dev); 6099 else if (IS_GEN5(dev)) 6100 i915_ironlake_get_mem_freq(dev); 6101 6102 /* For FIFO watermark updates */ 6103 if (HAS_PCH_SPLIT(dev)) { 6104 ilk_setup_wm_latency(dev); 6105 6106 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 6107 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 6108 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 6109 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 6110 dev_priv->display.update_wm = ilk_update_wm; 6111 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 6112 } else { 6113 DRM_DEBUG_KMS("Failed to read display plane latency. " 6114 "Disable CxSR\n"); 6115 } 6116 6117 if (IS_GEN5(dev)) 6118 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 6119 else if (IS_GEN6(dev)) 6120 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 6121 else if (IS_IVYBRIDGE(dev)) 6122 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 6123 else if (IS_HASWELL(dev)) 6124 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 6125 else if (INTEL_INFO(dev)->gen == 8) 6126 dev_priv->display.init_clock_gating = gen8_init_clock_gating; 6127 } else if (IS_VALLEYVIEW(dev)) { 6128 dev_priv->display.update_wm = valleyview_update_wm; 6129 dev_priv->display.init_clock_gating = 6130 valleyview_init_clock_gating; 6131 } else if (IS_PINEVIEW(dev)) { 6132 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 6133 dev_priv->is_ddr3, 6134 dev_priv->fsb_freq, 6135 dev_priv->mem_freq)) { 6136 DRM_INFO("failed to find known CxSR latency " 6137 "(found ddr%s fsb freq %d, mem freq %d), " 6138 "disabling CxSR\n", 6139 (dev_priv->is_ddr3 == 1) ? "3" : "2", 6140 dev_priv->fsb_freq, dev_priv->mem_freq); 6141 /* Disable CxSR and never update its watermark again */ 6142 pineview_disable_cxsr(dev); 6143 dev_priv->display.update_wm = NULL; 6144 } else 6145 dev_priv->display.update_wm = pineview_update_wm; 6146 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 6147 } else if (IS_G4X(dev)) { 6148 dev_priv->display.update_wm = g4x_update_wm; 6149 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 6150 } else if (IS_GEN4(dev)) { 6151 dev_priv->display.update_wm = i965_update_wm; 6152 if (IS_CRESTLINE(dev)) 6153 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 6154 else if (IS_BROADWATER(dev)) 6155 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 6156 } else if (IS_GEN3(dev)) { 6157 dev_priv->display.update_wm = i9xx_update_wm; 6158 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 6159 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 6160 } else if (IS_GEN2(dev)) { 6161 if (INTEL_INFO(dev)->num_pipes == 1) { 6162 dev_priv->display.update_wm = i845_update_wm; 6163 dev_priv->display.get_fifo_size = i845_get_fifo_size; 6164 } else { 6165 dev_priv->display.update_wm = i9xx_update_wm; 6166 dev_priv->display.get_fifo_size = i830_get_fifo_size; 6167 } 6168 6169 if (IS_I85X(dev) || IS_I865G(dev)) 6170 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 6171 else 6172 dev_priv->display.init_clock_gating = i830_init_clock_gating; 6173 } else { 6174 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 6175 } 6176 } 6177 6178 #ifdef __NetBSD__ /* XXX gt fini */ 6179 void 6180 intel_gt_fini(struct drm_device *dev) 6181 { 6182 struct drm_i915_private *dev_priv = dev->dev_private; 6183 6184 spin_lock_destroy(&dev_priv->gt_lock); 6185 } 6186 #endif 6187 6188 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 6189 { 6190 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 6191 6192 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 6193 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 6194 return -EAGAIN; 6195 } 6196 6197 I915_WRITE(GEN6_PCODE_DATA, *val); 6198 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 6199 6200 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 6201 500)) { 6202 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 6203 return -ETIMEDOUT; 6204 } 6205 6206 *val = I915_READ(GEN6_PCODE_DATA); 6207 I915_WRITE(GEN6_PCODE_DATA, 0); 6208 6209 return 0; 6210 } 6211 6212 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 6213 { 6214 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 6215 6216 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 6217 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 6218 return -EAGAIN; 6219 } 6220 6221 I915_WRITE(GEN6_PCODE_DATA, val); 6222 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 6223 6224 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 6225 500)) { 6226 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 6227 return -ETIMEDOUT; 6228 } 6229 6230 I915_WRITE(GEN6_PCODE_DATA, 0); 6231 6232 return 0; 6233 } 6234 6235 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) 6236 { 6237 int div; 6238 6239 /* 4 x czclk */ 6240 switch (dev_priv->mem_freq) { 6241 case 800: 6242 div = 10; 6243 break; 6244 case 1066: 6245 div = 12; 6246 break; 6247 case 1333: 6248 div = 16; 6249 break; 6250 default: 6251 return -1; 6252 } 6253 6254 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); 6255 } 6256 6257 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) 6258 { 6259 int mul; 6260 6261 /* 4 x czclk */ 6262 switch (dev_priv->mem_freq) { 6263 case 800: 6264 mul = 10; 6265 break; 6266 case 1066: 6267 mul = 12; 6268 break; 6269 case 1333: 6270 mul = 16; 6271 break; 6272 default: 6273 return -1; 6274 } 6275 6276 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; 6277 } 6278 6279 void intel_pm_setup(struct drm_device *dev) 6280 { 6281 struct drm_i915_private *dev_priv = dev->dev_private; 6282 6283 mutex_init(&dev_priv->rps.hw_lock); 6284 6285 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 6286 intel_gen6_powersave_work); 6287 6288 dev_priv->pm.suspended = false; 6289 dev_priv->pm.irqs_disabled = false; 6290 } 6291
Indexes created Sat Oct 11 19:10:01 GMT 2025