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      1  1.1  riastrad /*	$NetBSD: intel_pm.h,v 1.2 2021/12/18 23:45:28 riastradh Exp $	*/
      2  1.1  riastrad 
      3  1.1  riastrad /* SPDX-License-Identifier: MIT */
      4  1.1  riastrad /*
      5  1.1  riastrad  * Copyright  2019 Intel Corporation
      6  1.1  riastrad  */
      7  1.1  riastrad 
      8  1.1  riastrad #ifndef __INTEL_PM_H__
      9  1.1  riastrad #define __INTEL_PM_H__
     10  1.1  riastrad 
     11  1.1  riastrad #include <linux/types.h>
     12  1.1  riastrad 
     13  1.1  riastrad #include "i915_reg.h"
     14  1.1  riastrad 
     15  1.1  riastrad struct drm_device;
     16  1.1  riastrad struct drm_i915_private;
     17  1.1  riastrad struct i915_request;
     18  1.1  riastrad struct intel_atomic_state;
     19  1.1  riastrad struct intel_crtc;
     20  1.1  riastrad struct intel_crtc_state;
     21  1.1  riastrad struct intel_plane;
     22  1.1  riastrad struct skl_ddb_allocation;
     23  1.1  riastrad struct skl_ddb_entry;
     24  1.1  riastrad struct skl_pipe_wm;
     25  1.1  riastrad struct skl_wm_level;
     26  1.1  riastrad 
     27  1.1  riastrad void intel_init_clock_gating(struct drm_i915_private *dev_priv);
     28  1.1  riastrad void intel_suspend_hw(struct drm_i915_private *dev_priv);
     29  1.1  riastrad int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
     30  1.1  riastrad void intel_update_watermarks(struct intel_crtc *crtc);
     31  1.1  riastrad void intel_init_pm(struct drm_i915_private *dev_priv);
     32  1.1  riastrad void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
     33  1.1  riastrad void intel_pm_setup(struct drm_i915_private *dev_priv);
     34  1.1  riastrad void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
     35  1.1  riastrad void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
     36  1.1  riastrad void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
     37  1.1  riastrad void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
     38  1.1  riastrad void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
     39  1.1  riastrad 			       struct skl_ddb_entry *ddb_y,
     40  1.1  riastrad 			       struct skl_ddb_entry *ddb_uv);
     41  1.1  riastrad void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
     42  1.1  riastrad 			  struct skl_ddb_allocation *ddb /* out */);
     43  1.1  riastrad void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
     44  1.1  riastrad 			      struct skl_pipe_wm *out);
     45  1.1  riastrad void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
     46  1.1  riastrad void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
     47  1.1  riastrad bool intel_can_enable_sagv(struct intel_atomic_state *state);
     48  1.1  riastrad int intel_enable_sagv(struct drm_i915_private *dev_priv);
     49  1.1  riastrad int intel_disable_sagv(struct drm_i915_private *dev_priv);
     50  1.1  riastrad bool skl_wm_level_equals(const struct skl_wm_level *l1,
     51  1.1  riastrad 			 const struct skl_wm_level *l2);
     52  1.1  riastrad bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
     53  1.1  riastrad 				 const struct skl_ddb_entry *entries,
     54  1.1  riastrad 				 int num_entries, int ignore_idx);
     55  1.1  riastrad void skl_write_plane_wm(struct intel_plane *plane,
     56  1.1  riastrad 			const struct intel_crtc_state *crtc_state);
     57  1.1  riastrad void skl_write_cursor_wm(struct intel_plane *plane,
     58  1.1  riastrad 			 const struct intel_crtc_state *crtc_state);
     59  1.1  riastrad bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
     60  1.1  riastrad void intel_init_ipc(struct drm_i915_private *dev_priv);
     61  1.1  riastrad void intel_enable_ipc(struct drm_i915_private *dev_priv);
     62  1.1  riastrad 
     63  1.1  riastrad bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
     64  1.1  riastrad 
     65  1.1  riastrad #endif /* __INTEL_PM_H__ */
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