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intel_pm.h revision 1.1.1.1 
      1 /*	$NetBSD: intel_pm.h,v 1.1.1.1 2021/12/18 20:15:26 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 /*
      5  * Copyright  2019 Intel Corporation
      6  */
      7 
      8 #ifndef __INTEL_PM_H__
      9 #define __INTEL_PM_H__
     10 
     11 #include <linux/types.h>
     12 
     13 #include "i915_reg.h"
     14 
     15 struct drm_device;
     16 struct drm_i915_private;
     17 struct i915_request;
     18 struct intel_atomic_state;
     19 struct intel_crtc;
     20 struct intel_crtc_state;
     21 struct intel_plane;
     22 struct skl_ddb_allocation;
     23 struct skl_ddb_entry;
     24 struct skl_pipe_wm;
     25 struct skl_wm_level;
     26 
     27 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
     28 void intel_suspend_hw(struct drm_i915_private *dev_priv);
     29 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
     30 void intel_update_watermarks(struct intel_crtc *crtc);
     31 void intel_init_pm(struct drm_i915_private *dev_priv);
     32 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
     33 void intel_pm_setup(struct drm_i915_private *dev_priv);
     34 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
     35 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
     36 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
     37 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
     38 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
     39 			       struct skl_ddb_entry *ddb_y,
     40 			       struct skl_ddb_entry *ddb_uv);
     41 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
     42 			  struct skl_ddb_allocation *ddb /* out */);
     43 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
     44 			      struct skl_pipe_wm *out);
     45 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
     46 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
     47 bool intel_can_enable_sagv(struct intel_atomic_state *state);
     48 int intel_enable_sagv(struct drm_i915_private *dev_priv);
     49 int intel_disable_sagv(struct drm_i915_private *dev_priv);
     50 bool skl_wm_level_equals(const struct skl_wm_level *l1,
     51 			 const struct skl_wm_level *l2);
     52 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
     53 				 const struct skl_ddb_entry *entries,
     54 				 int num_entries, int ignore_idx);
     55 void skl_write_plane_wm(struct intel_plane *plane,
     56 			const struct intel_crtc_state *crtc_state);
     57 void skl_write_cursor_wm(struct intel_plane *plane,
     58 			 const struct intel_crtc_state *crtc_state);
     59 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
     60 void intel_init_ipc(struct drm_i915_private *dev_priv);
     61 void intel_enable_ipc(struct drm_i915_private *dev_priv);
     62 
     63 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
     64 
     65 #endif /* __INTEL_PM_H__ */
     66