intel_runtime_pm.c revision 1.5.2.3
1 /* $NetBSD: intel_runtime_pm.c,v 1.5.2.3 2018/09/30 01:45:54 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2012-2014 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eugeni Dodonov <eugeni.dodonov (at) intel.com> 27 * Daniel Vetter <daniel.vetter (at) ffwll.ch> 28 * 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: intel_runtime_pm.c,v 1.5.2.3 2018/09/30 01:45:54 pgoyette Exp $"); 33 34 #include <linux/pm_runtime.h> 35 #include <linux/vgaarb.h> 36 37 #include "i915_drv.h" 38 #include "intel_drv.h" 39 40 /** 41 * DOC: runtime pm 42 * 43 * The i915 driver supports dynamic enabling and disabling of entire hardware 44 * blocks at runtime. This is especially important on the display side where 45 * software is supposed to control many power gates manually on recent hardware, 46 * since on the GT side a lot of the power management is done by the hardware. 47 * But even there some manual control at the device level is required. 48 * 49 * Since i915 supports a diverse set of platforms with a unified codebase and 50 * hardware engineers just love to shuffle functionality around between power 51 * domains there's a sizeable amount of indirection required. This file provides 52 * generic functions to the driver for grabbing and releasing references for 53 * abstract power domains. It then maps those to the actual power wells 54 * present for a given platform. 55 */ 56 57 #define GEN9_ENABLE_DC5(dev) 0 58 #define SKL_ENABLE_DC6(dev) (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 59 60 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 61 for (i = 0; \ 62 i < (power_domains)->power_well_count && \ 63 ((power_well) = &(power_domains)->power_wells[i]); \ 64 i++) \ 65 if ((power_well)->domains & (domain_mask)) 66 67 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 68 for (i = (power_domains)->power_well_count - 1; \ 69 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 70 i--) \ 71 if ((power_well)->domains & (domain_mask)) 72 73 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 74 int power_well_id); 75 76 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 77 struct i915_power_well *power_well) 78 { 79 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 80 power_well->ops->enable(dev_priv, power_well); 81 power_well->hw_enabled = true; 82 } 83 84 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 85 struct i915_power_well *power_well) 86 { 87 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 88 power_well->hw_enabled = false; 89 power_well->ops->disable(dev_priv, power_well); 90 } 91 92 /* 93 * We should only use the power well if we explicitly asked the hardware to 94 * enable it, so check if it's enabled and also check if we've requested it to 95 * be enabled. 96 */ 97 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 98 struct i915_power_well *power_well) 99 { 100 return I915_READ(HSW_PWR_WELL_DRIVER) == 101 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 102 } 103 104 /** 105 * __intel_display_power_is_enabled - unlocked check for a power domain 106 * @dev_priv: i915 device instance 107 * @domain: power domain to check 108 * 109 * This is the unlocked version of intel_display_power_is_enabled() and should 110 * only be used from error capture and recovery code where deadlocks are 111 * possible. 112 * 113 * Returns: 114 * True when the power domain is enabled, false otherwise. 115 */ 116 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 117 enum intel_display_power_domain domain) 118 { 119 struct i915_power_domains *power_domains; 120 struct i915_power_well *power_well; 121 bool is_enabled; 122 int i; 123 124 if (dev_priv->pm.suspended) 125 return false; 126 127 power_domains = &dev_priv->power_domains; 128 129 is_enabled = true; 130 131 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 132 if (power_well->always_on) 133 continue; 134 135 if (!power_well->hw_enabled) { 136 is_enabled = false; 137 break; 138 } 139 } 140 141 return is_enabled; 142 } 143 144 /** 145 * intel_display_power_is_enabled - check for a power domain 146 * @dev_priv: i915 device instance 147 * @domain: power domain to check 148 * 149 * This function can be used to check the hw power domain state. It is mostly 150 * used in hardware state readout functions. Everywhere else code should rely 151 * upon explicit power domain reference counting to ensure that the hardware 152 * block is powered up before accessing it. 153 * 154 * Callers must hold the relevant modesetting locks to ensure that concurrent 155 * threads can't disable the power well while the caller tries to read a few 156 * registers. 157 * 158 * Returns: 159 * True when the power domain is enabled, false otherwise. 160 */ 161 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 162 enum intel_display_power_domain domain) 163 { 164 struct i915_power_domains *power_domains; 165 bool ret; 166 167 power_domains = &dev_priv->power_domains; 168 169 mutex_lock(&power_domains->lock); 170 ret = __intel_display_power_is_enabled(dev_priv, domain); 171 mutex_unlock(&power_domains->lock); 172 173 return ret; 174 } 175 176 /** 177 * intel_display_set_init_power - set the initial power domain state 178 * @dev_priv: i915 device instance 179 * @enable: whether to enable or disable the initial power domain state 180 * 181 * For simplicity our driver load/unload and system suspend/resume code assumes 182 * that all power domains are always enabled. This functions controls the state 183 * of this little hack. While the initial power domain state is enabled runtime 184 * pm is effectively disabled. 185 */ 186 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 187 bool enable) 188 { 189 if (dev_priv->power_domains.init_power_on == enable) 190 return; 191 192 if (enable) 193 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 194 else 195 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 196 197 dev_priv->power_domains.init_power_on = enable; 198 } 199 200 static inline void 201 touch_vga_msr(struct drm_device *dev) 202 { 203 #ifdef __NetBSD__ 204 const bus_addr_t vgabase = 0x3c0; 205 const bus_space_tag_t iot = dev->pdev->pd_pa.pa_iot; 206 bus_space_handle_t ioh; 207 uint8_t msr; 208 int error; 209 210 error = bus_space_map(iot, vgabase, 0x10, 0, &ioh); 211 if (error) { 212 device_printf(dev->pdev->pd_dev, 213 "unable to map VGA registers: %d\n", error); 214 } else { 215 CTASSERT(vgabase <= VGA_MSR_READ); 216 msr = bus_space_read_1(iot, ioh, VGA_MSR_READ - vgabase); 217 bus_space_write_1(iot, ioh, VGA_MSR_READ - vgabase, msr); 218 bus_space_unmap(iot, ioh, 0x10); 219 } 220 #else 221 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 222 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 223 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 224 #endif 225 } 226 227 /* 228 * Starting with Haswell, we have a "Power Down Well" that can be turned off 229 * when not needed anymore. We have 4 registers that can request the power well 230 * to be enabled, and it will only be disabled if none of the registers is 231 * requesting it to be enabled. 232 */ 233 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 234 { 235 struct drm_device *dev = dev_priv->dev; 236 237 /* 238 * After we re-enable the power well, if we touch VGA register 0x3d5 239 * we'll get unclaimed register interrupts. This stops after we write 240 * anything to the VGA MSR register. The vgacon module uses this 241 * register all the time, so if we unbind our driver and, as a 242 * consequence, bind vgacon, we'll get stuck in an infinite loop at 243 * console_unlock(). So make here we touch the VGA MSR register, making 244 * sure vgacon can keep working normally without triggering interrupts 245 * and error messages. 246 */ 247 touch_vga_msr(dev); 248 249 if (IS_BROADWELL(dev)) 250 gen8_irq_power_well_post_enable(dev_priv, 251 1 << PIPE_C | 1 << PIPE_B); 252 } 253 254 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 255 struct i915_power_well *power_well) 256 { 257 struct drm_device *dev = dev_priv->dev; 258 259 /* 260 * After we re-enable the power well, if we touch VGA register 0x3d5 261 * we'll get unclaimed register interrupts. This stops after we write 262 * anything to the VGA MSR register. The vgacon module uses this 263 * register all the time, so if we unbind our driver and, as a 264 * consequence, bind vgacon, we'll get stuck in an infinite loop at 265 * console_unlock(). So make here we touch the VGA MSR register, making 266 * sure vgacon can keep working normally without triggering interrupts 267 * and error messages. 268 */ 269 if (power_well->data == SKL_DISP_PW_2) { 270 touch_vga_msr(dev); 271 272 gen8_irq_power_well_post_enable(dev_priv, 273 1 << PIPE_C | 1 << PIPE_B); 274 } 275 276 if (power_well->data == SKL_DISP_PW_1) { 277 if (!dev_priv->power_domains.initializing) 278 intel_prepare_ddi(dev); 279 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); 280 } 281 } 282 283 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 284 struct i915_power_well *power_well, bool enable) 285 { 286 bool is_enabled, enable_requested; 287 uint32_t tmp; 288 289 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 290 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 291 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 292 293 if (enable) { 294 if (!enable_requested) 295 I915_WRITE(HSW_PWR_WELL_DRIVER, 296 HSW_PWR_WELL_ENABLE_REQUEST); 297 298 if (!is_enabled) { 299 DRM_DEBUG_KMS("Enabling power well\n"); 300 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 301 HSW_PWR_WELL_STATE_ENABLED), 20)) 302 DRM_ERROR("Timeout enabling power well\n"); 303 hsw_power_well_post_enable(dev_priv); 304 } 305 306 } else { 307 if (enable_requested) { 308 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 309 POSTING_READ(HSW_PWR_WELL_DRIVER); 310 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 311 } 312 } 313 } 314 315 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 316 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 317 BIT(POWER_DOMAIN_PIPE_B) | \ 318 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 319 BIT(POWER_DOMAIN_PIPE_C) | \ 320 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 321 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 322 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 323 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 324 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 325 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 326 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 327 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 328 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 329 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 330 BIT(POWER_DOMAIN_AUX_B) | \ 331 BIT(POWER_DOMAIN_AUX_C) | \ 332 BIT(POWER_DOMAIN_AUX_D) | \ 333 BIT(POWER_DOMAIN_AUDIO) | \ 334 BIT(POWER_DOMAIN_VGA) | \ 335 BIT(POWER_DOMAIN_INIT)) 336 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 337 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 338 BIT(POWER_DOMAIN_PLLS) | \ 339 BIT(POWER_DOMAIN_PIPE_A) | \ 340 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 341 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 342 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 343 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 344 BIT(POWER_DOMAIN_AUX_A) | \ 345 BIT(POWER_DOMAIN_INIT)) 346 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 347 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 348 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 349 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 350 BIT(POWER_DOMAIN_INIT)) 351 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 352 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 353 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 354 BIT(POWER_DOMAIN_INIT)) 355 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 356 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 357 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 358 BIT(POWER_DOMAIN_INIT)) 359 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 360 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 361 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 362 BIT(POWER_DOMAIN_INIT)) 363 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ 364 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 365 BIT(POWER_DOMAIN_PLLS) | \ 366 BIT(POWER_DOMAIN_INIT)) 367 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 368 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 369 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 370 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ 371 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ 372 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ 373 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ 374 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ 375 BIT(POWER_DOMAIN_INIT)) 376 377 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 378 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 379 BIT(POWER_DOMAIN_PIPE_B) | \ 380 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 381 BIT(POWER_DOMAIN_PIPE_C) | \ 382 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 383 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 384 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 385 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 386 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 387 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 388 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 389 BIT(POWER_DOMAIN_AUX_B) | \ 390 BIT(POWER_DOMAIN_AUX_C) | \ 391 BIT(POWER_DOMAIN_AUDIO) | \ 392 BIT(POWER_DOMAIN_VGA) | \ 393 BIT(POWER_DOMAIN_GMBUS) | \ 394 BIT(POWER_DOMAIN_INIT)) 395 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 396 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 397 BIT(POWER_DOMAIN_PIPE_A) | \ 398 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 399 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 400 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 401 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 402 BIT(POWER_DOMAIN_AUX_A) | \ 403 BIT(POWER_DOMAIN_PLLS) | \ 404 BIT(POWER_DOMAIN_INIT)) 405 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 406 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 407 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 408 BIT(POWER_DOMAIN_INIT)) 409 410 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 411 { 412 struct drm_device *dev = dev_priv->dev; 413 414 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 415 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 416 "DC9 already programmed to be enabled.\n"); 417 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 418 "DC5 still not disabled to enable DC9.\n"); 419 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 420 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 421 422 /* 423 * TODO: check for the following to verify the conditions to enter DC9 424 * state are satisfied: 425 * 1] Check relevant display engine registers to verify if mode set 426 * disable sequence was followed. 427 * 2] Check if display uninitialize sequence is initialized. 428 */ 429 } 430 431 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 432 { 433 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 434 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 435 "DC9 already programmed to be disabled.\n"); 436 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 437 "DC5 still not disabled.\n"); 438 439 /* 440 * TODO: check for the following to verify DC9 state was indeed 441 * entered before programming to disable it: 442 * 1] Check relevant display engine registers to verify if mode 443 * set disable sequence was followed. 444 * 2] Check if display uninitialize sequence is initialized. 445 */ 446 } 447 448 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 449 { 450 uint32_t val; 451 452 assert_can_enable_dc9(dev_priv); 453 454 DRM_DEBUG_KMS("Enabling DC9\n"); 455 456 val = I915_READ(DC_STATE_EN); 457 val |= DC_STATE_EN_DC9; 458 I915_WRITE(DC_STATE_EN, val); 459 POSTING_READ(DC_STATE_EN); 460 } 461 462 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 463 { 464 uint32_t val; 465 466 assert_can_disable_dc9(dev_priv); 467 468 DRM_DEBUG_KMS("Disabling DC9\n"); 469 470 val = I915_READ(DC_STATE_EN); 471 val &= ~DC_STATE_EN_DC9; 472 I915_WRITE(DC_STATE_EN, val); 473 POSTING_READ(DC_STATE_EN); 474 } 475 476 static void gen9_set_dc_state_debugmask_memory_up( 477 struct drm_i915_private *dev_priv) 478 { 479 uint32_t val; 480 481 /* The below bit doesn't need to be cleared ever afterwards */ 482 val = I915_READ(DC_STATE_DEBUG); 483 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { 484 val |= DC_STATE_DEBUG_MASK_MEMORY_UP; 485 I915_WRITE(DC_STATE_DEBUG, val); 486 POSTING_READ(DC_STATE_DEBUG); 487 } 488 } 489 490 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 491 { 492 struct drm_device *dev = dev_priv->dev; 493 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 494 SKL_DISP_PW_2); 495 496 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), 497 "Platform doesn't support DC5.\n"); 498 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 499 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 500 501 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 502 "DC5 already programmed to be enabled.\n"); 503 WARN_ONCE(dev_priv->pm.suspended, 504 "DC5 cannot be enabled, if platform is runtime-suspended.\n"); 505 506 assert_csr_loaded(dev_priv); 507 } 508 509 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 510 { 511 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 512 SKL_DISP_PW_2); 513 /* 514 * During initialization, the firmware may not be loaded yet. 515 * We still want to make sure that the DC enabling flag is cleared. 516 */ 517 if (dev_priv->power_domains.initializing) 518 return; 519 520 WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); 521 WARN_ONCE(dev_priv->pm.suspended, 522 "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); 523 } 524 525 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 526 { 527 uint32_t val; 528 529 assert_can_enable_dc5(dev_priv); 530 531 DRM_DEBUG_KMS("Enabling DC5\n"); 532 533 gen9_set_dc_state_debugmask_memory_up(dev_priv); 534 535 val = I915_READ(DC_STATE_EN); 536 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 537 val |= DC_STATE_EN_UPTO_DC5; 538 I915_WRITE(DC_STATE_EN, val); 539 POSTING_READ(DC_STATE_EN); 540 } 541 542 static void gen9_disable_dc5(struct drm_i915_private *dev_priv) 543 { 544 uint32_t val; 545 546 assert_can_disable_dc5(dev_priv); 547 548 DRM_DEBUG_KMS("Disabling DC5\n"); 549 550 val = I915_READ(DC_STATE_EN); 551 val &= ~DC_STATE_EN_UPTO_DC5; 552 I915_WRITE(DC_STATE_EN, val); 553 POSTING_READ(DC_STATE_EN); 554 } 555 556 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 557 { 558 struct drm_device *dev = dev_priv->dev; 559 560 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), 561 "Platform doesn't support DC6.\n"); 562 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 563 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 564 "Backlight is not disabled.\n"); 565 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 566 "DC6 already programmed to be enabled.\n"); 567 568 assert_csr_loaded(dev_priv); 569 } 570 571 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 572 { 573 /* 574 * During initialization, the firmware may not be loaded yet. 575 * We still want to make sure that the DC enabling flag is cleared. 576 */ 577 if (dev_priv->power_domains.initializing) 578 return; 579 580 assert_csr_loaded(dev_priv); 581 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 582 "DC6 already programmed to be disabled.\n"); 583 } 584 585 static void skl_enable_dc6(struct drm_i915_private *dev_priv) 586 { 587 uint32_t val; 588 589 assert_can_enable_dc6(dev_priv); 590 591 DRM_DEBUG_KMS("Enabling DC6\n"); 592 593 gen9_set_dc_state_debugmask_memory_up(dev_priv); 594 595 val = I915_READ(DC_STATE_EN); 596 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 597 val |= DC_STATE_EN_UPTO_DC6; 598 I915_WRITE(DC_STATE_EN, val); 599 POSTING_READ(DC_STATE_EN); 600 } 601 602 static void skl_disable_dc6(struct drm_i915_private *dev_priv) 603 { 604 uint32_t val; 605 606 assert_can_disable_dc6(dev_priv); 607 608 DRM_DEBUG_KMS("Disabling DC6\n"); 609 610 val = I915_READ(DC_STATE_EN); 611 val &= ~DC_STATE_EN_UPTO_DC6; 612 I915_WRITE(DC_STATE_EN, val); 613 POSTING_READ(DC_STATE_EN); 614 } 615 616 static void skl_set_power_well(struct drm_i915_private *dev_priv, 617 struct i915_power_well *power_well, bool enable) 618 { 619 struct drm_device *dev = dev_priv->dev; 620 uint32_t tmp, fuse_status; 621 uint32_t req_mask, state_mask; 622 bool is_enabled, enable_requested, check_fuse_status = false; 623 624 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 625 fuse_status = I915_READ(SKL_FUSE_STATUS); 626 627 switch (power_well->data) { 628 case SKL_DISP_PW_1: 629 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 630 SKL_FUSE_PG0_DIST_STATUS), 1)) { 631 DRM_ERROR("PG0 not enabled\n"); 632 return; 633 } 634 break; 635 case SKL_DISP_PW_2: 636 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 637 DRM_ERROR("PG1 in disabled state\n"); 638 return; 639 } 640 break; 641 case SKL_DISP_PW_DDI_A_E: 642 case SKL_DISP_PW_DDI_B: 643 case SKL_DISP_PW_DDI_C: 644 case SKL_DISP_PW_DDI_D: 645 case SKL_DISP_PW_MISC_IO: 646 break; 647 default: 648 WARN(1, "Unknown power well %lu\n", power_well->data); 649 return; 650 } 651 652 req_mask = SKL_POWER_WELL_REQ(power_well->data); 653 enable_requested = tmp & req_mask; 654 state_mask = SKL_POWER_WELL_STATE(power_well->data); 655 is_enabled = tmp & state_mask; 656 657 if (enable) { 658 if (!enable_requested) { 659 WARN((tmp & state_mask) && 660 !I915_READ(HSW_PWR_WELL_BIOS), 661 "Invalid for power well status to be enabled, unless done by the BIOS, \ 662 when request is to disable!\n"); 663 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 664 power_well->data == SKL_DISP_PW_2) { 665 if (SKL_ENABLE_DC6(dev)) { 666 skl_disable_dc6(dev_priv); 667 /* 668 * DDI buffer programming unnecessary during driver-load/resume 669 * as it's already done during modeset initialization then. 670 * It's also invalid here as encoder list is still uninitialized. 671 */ 672 if (!dev_priv->power_domains.initializing) 673 intel_prepare_ddi(dev); 674 } else { 675 gen9_disable_dc5(dev_priv); 676 } 677 } 678 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 679 } 680 681 if (!is_enabled) { 682 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 683 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 684 state_mask), 1)) 685 DRM_ERROR("%s enable timeout\n", 686 power_well->name); 687 check_fuse_status = true; 688 } 689 } else { 690 if (enable_requested) { 691 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && 692 (power_well->data == SKL_DISP_PW_1) && 693 (intel_csr_load_status_get(dev_priv) == FW_LOADED)) 694 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); 695 else { 696 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 697 POSTING_READ(HSW_PWR_WELL_DRIVER); 698 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 699 } 700 701 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 702 power_well->data == SKL_DISP_PW_2) { 703 enum csr_state state; 704 /* TODO: wait for a completion event or 705 * similar here instead of busy 706 * waiting using wait_for function. 707 */ 708 wait_for((state = intel_csr_load_status_get(dev_priv)) != 709 FW_UNINITIALIZED, 1000); 710 if (state != FW_LOADED) 711 DRM_DEBUG("CSR firmware not ready (%d)\n", 712 state); 713 else 714 if (SKL_ENABLE_DC6(dev)) 715 skl_enable_dc6(dev_priv); 716 else 717 gen9_enable_dc5(dev_priv); 718 } 719 } 720 } 721 722 if (check_fuse_status) { 723 if (power_well->data == SKL_DISP_PW_1) { 724 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 725 SKL_FUSE_PG1_DIST_STATUS), 1)) 726 DRM_ERROR("PG1 distributing status timeout\n"); 727 } else if (power_well->data == SKL_DISP_PW_2) { 728 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 729 SKL_FUSE_PG2_DIST_STATUS), 1)) 730 DRM_ERROR("PG2 distributing status timeout\n"); 731 } 732 } 733 734 if (enable && !is_enabled) 735 skl_power_well_post_enable(dev_priv, power_well); 736 } 737 738 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 739 struct i915_power_well *power_well) 740 { 741 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 742 743 /* 744 * We're taking over the BIOS, so clear any requests made by it since 745 * the driver is in charge now. 746 */ 747 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 748 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 749 } 750 751 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 752 struct i915_power_well *power_well) 753 { 754 hsw_set_power_well(dev_priv, power_well, true); 755 } 756 757 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 758 struct i915_power_well *power_well) 759 { 760 hsw_set_power_well(dev_priv, power_well, false); 761 } 762 763 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 764 struct i915_power_well *power_well) 765 { 766 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 767 SKL_POWER_WELL_STATE(power_well->data); 768 769 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 770 } 771 772 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 773 struct i915_power_well *power_well) 774 { 775 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 776 777 /* Clear any request made by BIOS as driver is taking over */ 778 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 779 } 780 781 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 782 struct i915_power_well *power_well) 783 { 784 skl_set_power_well(dev_priv, power_well, true); 785 } 786 787 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 788 struct i915_power_well *power_well) 789 { 790 skl_set_power_well(dev_priv, power_well, false); 791 } 792 793 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 794 struct i915_power_well *power_well) 795 { 796 } 797 798 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 799 struct i915_power_well *power_well) 800 { 801 return true; 802 } 803 804 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 805 struct i915_power_well *power_well, bool enable) 806 { 807 enum punit_power_well power_well_id = power_well->data; 808 u32 mask; 809 u32 state; 810 u32 ctrl; 811 812 mask = PUNIT_PWRGT_MASK(power_well_id); 813 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 814 PUNIT_PWRGT_PWR_GATE(power_well_id); 815 816 mutex_lock(&dev_priv->rps.hw_lock); 817 818 #define COND \ 819 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 820 821 if (COND) 822 goto out; 823 824 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 825 ctrl &= ~mask; 826 ctrl |= state; 827 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 828 829 if (wait_for(COND, 100)) 830 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 831 state, 832 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 833 834 #undef COND 835 836 out: 837 mutex_unlock(&dev_priv->rps.hw_lock); 838 } 839 840 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 841 struct i915_power_well *power_well) 842 { 843 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 844 } 845 846 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 847 struct i915_power_well *power_well) 848 { 849 vlv_set_power_well(dev_priv, power_well, true); 850 } 851 852 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 853 struct i915_power_well *power_well) 854 { 855 vlv_set_power_well(dev_priv, power_well, false); 856 } 857 858 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 859 struct i915_power_well *power_well) 860 { 861 int power_well_id = power_well->data; 862 bool enabled = false; 863 u32 mask; 864 u32 state; 865 u32 ctrl; 866 867 mask = PUNIT_PWRGT_MASK(power_well_id); 868 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 869 870 mutex_lock(&dev_priv->rps.hw_lock); 871 872 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 873 /* 874 * We only ever set the power-on and power-gate states, anything 875 * else is unexpected. 876 */ 877 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 878 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 879 if (state == ctrl) 880 enabled = true; 881 882 /* 883 * A transient state at this point would mean some unexpected party 884 * is poking at the power controls too. 885 */ 886 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 887 WARN_ON(ctrl != state); 888 889 mutex_unlock(&dev_priv->rps.hw_lock); 890 891 return enabled; 892 } 893 894 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 895 { 896 enum i915_pipe pipe; 897 898 /* 899 * Enable the CRI clock source so we can get at the 900 * display and the reference clock for VGA 901 * hotplug / manual detection. Supposedly DSI also 902 * needs the ref clock up and running. 903 * 904 * CHV DPLL B/C have some issues if VGA mode is enabled. 905 */ 906 for_each_pipe(dev_priv->dev, pipe) { 907 u32 val = I915_READ(DPLL(pipe)); 908 909 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 910 if (pipe != PIPE_A) 911 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 912 913 I915_WRITE(DPLL(pipe), val); 914 } 915 916 spin_lock_irq(&dev_priv->irq_lock); 917 valleyview_enable_display_irqs(dev_priv); 918 spin_unlock_irq(&dev_priv->irq_lock); 919 920 /* 921 * During driver initialization/resume we can avoid restoring the 922 * part of the HW/SW state that will be inited anyway explicitly. 923 */ 924 if (dev_priv->power_domains.initializing) 925 return; 926 927 intel_hpd_init(dev_priv); 928 929 i915_redisable_vga_power_on(dev_priv->dev); 930 } 931 932 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 933 { 934 spin_lock_irq(&dev_priv->irq_lock); 935 valleyview_disable_display_irqs(dev_priv); 936 spin_unlock_irq(&dev_priv->irq_lock); 937 938 vlv_power_sequencer_reset(dev_priv); 939 } 940 941 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 942 struct i915_power_well *power_well) 943 { 944 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 945 946 vlv_set_power_well(dev_priv, power_well, true); 947 948 vlv_display_power_well_init(dev_priv); 949 } 950 951 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 952 struct i915_power_well *power_well) 953 { 954 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 955 956 vlv_display_power_well_deinit(dev_priv); 957 958 vlv_set_power_well(dev_priv, power_well, false); 959 } 960 961 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 962 struct i915_power_well *power_well) 963 { 964 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 965 966 /* since ref/cri clock was enabled */ 967 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 968 969 vlv_set_power_well(dev_priv, power_well, true); 970 971 /* 972 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 973 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 974 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 975 * b. The other bits such as sfr settings / modesel may all 976 * be set to 0. 977 * 978 * This should only be done on init and resume from S3 with 979 * both PLLs disabled, or we risk losing DPIO and PLL 980 * synchronization. 981 */ 982 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 983 } 984 985 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 986 struct i915_power_well *power_well) 987 { 988 enum i915_pipe pipe; 989 990 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 991 992 for_each_pipe(dev_priv, pipe) 993 assert_pll_disabled(dev_priv, pipe); 994 995 /* Assert common reset */ 996 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 997 998 vlv_set_power_well(dev_priv, power_well, false); 999 } 1000 1001 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1002 1003 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1004 int power_well_id) 1005 { 1006 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1007 struct i915_power_well *power_well; 1008 int i; 1009 1010 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1011 if (power_well->data == power_well_id) 1012 return power_well; 1013 } 1014 1015 return NULL; 1016 } 1017 1018 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1019 1020 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1021 { 1022 struct i915_power_well *cmn_bc = 1023 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1024 struct i915_power_well *cmn_d = 1025 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1026 u32 phy_control = dev_priv->chv_phy_control; 1027 u32 phy_status = 0; 1028 u32 phy_status_mask = 0xffffffff; 1029 u32 tmp; 1030 1031 /* 1032 * The BIOS can leave the PHY is some weird state 1033 * where it doesn't fully power down some parts. 1034 * Disable the asserts until the PHY has been fully 1035 * reset (ie. the power well has been disabled at 1036 * least once). 1037 */ 1038 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1039 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1040 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1041 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1042 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1043 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1044 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1045 1046 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1047 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1048 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1049 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1050 1051 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1052 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1053 1054 /* this assumes override is only used to enable lanes */ 1055 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1056 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1057 1058 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1059 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1060 1061 /* CL1 is on whenever anything is on in either channel */ 1062 if (BITS_SET(phy_control, 1063 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1064 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1065 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1066 1067 /* 1068 * The DPLLB check accounts for the pipe B + port A usage 1069 * with CL2 powered up but all the lanes in the second channel 1070 * powered down. 1071 */ 1072 if (BITS_SET(phy_control, 1073 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1074 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1075 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1076 1077 if (BITS_SET(phy_control, 1078 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1079 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1080 if (BITS_SET(phy_control, 1081 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1082 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1083 1084 if (BITS_SET(phy_control, 1085 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1086 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1087 if (BITS_SET(phy_control, 1088 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1089 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1090 } 1091 1092 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1093 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1094 1095 /* this assumes override is only used to enable lanes */ 1096 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1097 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1098 1099 if (BITS_SET(phy_control, 1100 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1101 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1102 1103 if (BITS_SET(phy_control, 1104 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1105 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1106 if (BITS_SET(phy_control, 1107 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1108 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1109 } 1110 1111 phy_status &= phy_status_mask; 1112 1113 /* 1114 * The PHY may be busy with some initial calibration and whatnot, 1115 * so the power state can take a while to actually change. 1116 */ 1117 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1118 WARN(phy_status != tmp, 1119 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1120 tmp, phy_status, dev_priv->chv_phy_control); 1121 } 1122 1123 #undef BITS_SET 1124 1125 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1126 struct i915_power_well *power_well) 1127 { 1128 enum dpio_phy phy; 1129 enum i915_pipe pipe; 1130 uint32_t tmp; 1131 1132 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1133 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1134 1135 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1136 pipe = PIPE_A; 1137 phy = DPIO_PHY0; 1138 } else { 1139 pipe = PIPE_C; 1140 phy = DPIO_PHY1; 1141 } 1142 1143 /* since ref/cri clock was enabled */ 1144 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1145 vlv_set_power_well(dev_priv, power_well, true); 1146 1147 /* Poll for phypwrgood signal */ 1148 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1149 DRM_ERROR("Display PHY %d is not power up\n", phy); 1150 1151 mutex_lock(&dev_priv->sb_lock); 1152 1153 /* Enable dynamic power down */ 1154 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1155 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1156 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1157 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1158 1159 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1160 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1161 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1162 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1163 } else { 1164 /* 1165 * Force the non-existing CL2 off. BXT does this 1166 * too, so maybe it saves some power even though 1167 * CL2 doesn't exist? 1168 */ 1169 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1170 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1171 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1172 } 1173 1174 mutex_unlock(&dev_priv->sb_lock); 1175 1176 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1177 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1178 1179 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1180 phy, dev_priv->chv_phy_control); 1181 1182 assert_chv_phy_status(dev_priv); 1183 } 1184 1185 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1186 struct i915_power_well *power_well) 1187 { 1188 enum dpio_phy phy; 1189 1190 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1191 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1192 1193 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1194 phy = DPIO_PHY0; 1195 assert_pll_disabled(dev_priv, PIPE_A); 1196 assert_pll_disabled(dev_priv, PIPE_B); 1197 } else { 1198 phy = DPIO_PHY1; 1199 assert_pll_disabled(dev_priv, PIPE_C); 1200 } 1201 1202 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1203 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1204 1205 vlv_set_power_well(dev_priv, power_well, false); 1206 1207 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1208 phy, dev_priv->chv_phy_control); 1209 1210 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1211 dev_priv->chv_phy_assert[phy] = true; 1212 1213 assert_chv_phy_status(dev_priv); 1214 } 1215 1216 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1217 enum dpio_channel ch, bool override, unsigned int mask) 1218 { 1219 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1220 u32 reg, val, expected, actual; 1221 1222 /* 1223 * The BIOS can leave the PHY is some weird state 1224 * where it doesn't fully power down some parts. 1225 * Disable the asserts until the PHY has been fully 1226 * reset (ie. the power well has been disabled at 1227 * least once). 1228 */ 1229 if (!dev_priv->chv_phy_assert[phy]) 1230 return; 1231 1232 if (ch == DPIO_CH0) 1233 reg = _CHV_CMN_DW0_CH0; 1234 else 1235 reg = _CHV_CMN_DW6_CH1; 1236 1237 mutex_lock(&dev_priv->sb_lock); 1238 val = vlv_dpio_read(dev_priv, pipe, reg); 1239 mutex_unlock(&dev_priv->sb_lock); 1240 1241 /* 1242 * This assumes !override is only used when the port is disabled. 1243 * All lanes should power down even without the override when 1244 * the port is disabled. 1245 */ 1246 if (!override || mask == 0xf) { 1247 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1248 /* 1249 * If CH1 common lane is not active anymore 1250 * (eg. for pipe B DPLL) the entire channel will 1251 * shut down, which causes the common lane registers 1252 * to read as 0. That means we can't actually check 1253 * the lane power down status bits, but as the entire 1254 * register reads as 0 it's a good indication that the 1255 * channel is indeed entirely powered down. 1256 */ 1257 if (ch == DPIO_CH1 && val == 0) 1258 expected = 0; 1259 } else if (mask != 0x0) { 1260 expected = DPIO_ANYDL_POWERDOWN; 1261 } else { 1262 expected = 0; 1263 } 1264 1265 if (ch == DPIO_CH0) 1266 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1267 else 1268 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1269 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1270 1271 WARN(actual != expected, 1272 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1273 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1274 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1275 reg, val); 1276 } 1277 1278 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1279 enum dpio_channel ch, bool override) 1280 { 1281 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1282 bool was_override; 1283 1284 mutex_lock(&power_domains->lock); 1285 1286 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1287 1288 if (override == was_override) 1289 goto out; 1290 1291 if (override) 1292 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1293 else 1294 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1295 1296 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1297 1298 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1299 phy, ch, dev_priv->chv_phy_control); 1300 1301 assert_chv_phy_status(dev_priv); 1302 1303 out: 1304 mutex_unlock(&power_domains->lock); 1305 1306 return was_override; 1307 } 1308 1309 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1310 bool override, unsigned int mask) 1311 { 1312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1313 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1314 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1315 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1316 1317 mutex_lock(&power_domains->lock); 1318 1319 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1320 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1321 1322 if (override) 1323 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1324 else 1325 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1326 1327 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1328 1329 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1330 phy, ch, mask, dev_priv->chv_phy_control); 1331 1332 assert_chv_phy_status(dev_priv); 1333 1334 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1335 1336 mutex_unlock(&power_domains->lock); 1337 } 1338 1339 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1340 struct i915_power_well *power_well) 1341 { 1342 enum i915_pipe pipe = power_well->data; 1343 bool enabled; 1344 u32 state, ctrl; 1345 1346 mutex_lock(&dev_priv->rps.hw_lock); 1347 1348 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1349 /* 1350 * We only ever set the power-on and power-gate states, anything 1351 * else is unexpected. 1352 */ 1353 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1354 enabled = state == DP_SSS_PWR_ON(pipe); 1355 1356 /* 1357 * A transient state at this point would mean some unexpected party 1358 * is poking at the power controls too. 1359 */ 1360 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1361 WARN_ON(ctrl << 16 != state); 1362 1363 mutex_unlock(&dev_priv->rps.hw_lock); 1364 1365 return enabled; 1366 } 1367 1368 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1369 struct i915_power_well *power_well, 1370 bool enable) 1371 { 1372 enum i915_pipe pipe = power_well->data; 1373 u32 state; 1374 u32 ctrl; 1375 1376 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1377 1378 mutex_lock(&dev_priv->rps.hw_lock); 1379 1380 #define COND \ 1381 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1382 1383 if (COND) 1384 goto out; 1385 1386 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1387 ctrl &= ~DP_SSC_MASK(pipe); 1388 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1389 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1390 1391 if (wait_for(COND, 100)) 1392 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1393 state, 1394 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1395 1396 #undef COND 1397 1398 out: 1399 mutex_unlock(&dev_priv->rps.hw_lock); 1400 } 1401 1402 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1403 struct i915_power_well *power_well) 1404 { 1405 WARN_ON_ONCE(power_well->data != PIPE_A); 1406 1407 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1408 } 1409 1410 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1411 struct i915_power_well *power_well) 1412 { 1413 WARN_ON_ONCE(power_well->data != PIPE_A); 1414 1415 chv_set_pipe_power_well(dev_priv, power_well, true); 1416 1417 vlv_display_power_well_init(dev_priv); 1418 } 1419 1420 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1421 struct i915_power_well *power_well) 1422 { 1423 WARN_ON_ONCE(power_well->data != PIPE_A); 1424 1425 vlv_display_power_well_deinit(dev_priv); 1426 1427 chv_set_pipe_power_well(dev_priv, power_well, false); 1428 } 1429 1430 /** 1431 * intel_display_power_get - grab a power domain reference 1432 * @dev_priv: i915 device instance 1433 * @domain: power domain to reference 1434 * 1435 * This function grabs a power domain reference for @domain and ensures that the 1436 * power domain and all its parents are powered up. Therefore users should only 1437 * grab a reference to the innermost power domain they need. 1438 * 1439 * Any power domain reference obtained by this function must have a symmetric 1440 * call to intel_display_power_put() to release the reference again. 1441 */ 1442 void intel_display_power_get(struct drm_i915_private *dev_priv, 1443 enum intel_display_power_domain domain) 1444 { 1445 struct i915_power_domains *power_domains; 1446 struct i915_power_well *power_well; 1447 int i; 1448 1449 intel_runtime_pm_get(dev_priv); 1450 1451 power_domains = &dev_priv->power_domains; 1452 1453 mutex_lock(&power_domains->lock); 1454 1455 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1456 if (!power_well->count++) 1457 intel_power_well_enable(dev_priv, power_well); 1458 } 1459 1460 power_domains->domain_use_count[domain]++; 1461 1462 mutex_unlock(&power_domains->lock); 1463 } 1464 1465 /** 1466 * intel_display_power_put - release a power domain reference 1467 * @dev_priv: i915 device instance 1468 * @domain: power domain to reference 1469 * 1470 * This function drops the power domain reference obtained by 1471 * intel_display_power_get() and might power down the corresponding hardware 1472 * block right away if this is the last reference. 1473 */ 1474 void intel_display_power_put(struct drm_i915_private *dev_priv, 1475 enum intel_display_power_domain domain) 1476 { 1477 struct i915_power_domains *power_domains; 1478 struct i915_power_well *power_well; 1479 int i; 1480 1481 power_domains = &dev_priv->power_domains; 1482 1483 mutex_lock(&power_domains->lock); 1484 1485 WARN_ON(!power_domains->domain_use_count[domain]); 1486 power_domains->domain_use_count[domain]--; 1487 1488 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1489 WARN_ON(!power_well->count); 1490 1491 if (!--power_well->count && i915.disable_power_well) 1492 intel_power_well_disable(dev_priv, power_well); 1493 } 1494 1495 mutex_unlock(&power_domains->lock); 1496 1497 intel_runtime_pm_put(dev_priv); 1498 } 1499 1500 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1501 BIT(POWER_DOMAIN_PIPE_A) | \ 1502 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1503 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 1504 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 1505 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1506 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1507 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1508 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1509 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1510 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1511 BIT(POWER_DOMAIN_PORT_CRT) | \ 1512 BIT(POWER_DOMAIN_PLLS) | \ 1513 BIT(POWER_DOMAIN_AUX_A) | \ 1514 BIT(POWER_DOMAIN_AUX_B) | \ 1515 BIT(POWER_DOMAIN_AUX_C) | \ 1516 BIT(POWER_DOMAIN_AUX_D) | \ 1517 BIT(POWER_DOMAIN_GMBUS) | \ 1518 BIT(POWER_DOMAIN_INIT)) 1519 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1520 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1521 BIT(POWER_DOMAIN_INIT)) 1522 1523 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1524 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1525 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1526 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1527 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1528 BIT(POWER_DOMAIN_INIT)) 1529 1530 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1531 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1532 1533 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1534 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1535 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1536 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1537 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1538 BIT(POWER_DOMAIN_PORT_CRT) | \ 1539 BIT(POWER_DOMAIN_AUX_B) | \ 1540 BIT(POWER_DOMAIN_AUX_C) | \ 1541 BIT(POWER_DOMAIN_INIT)) 1542 1543 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1544 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1545 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1546 BIT(POWER_DOMAIN_AUX_B) | \ 1547 BIT(POWER_DOMAIN_INIT)) 1548 1549 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1550 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1551 BIT(POWER_DOMAIN_AUX_B) | \ 1552 BIT(POWER_DOMAIN_INIT)) 1553 1554 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1555 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1556 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1557 BIT(POWER_DOMAIN_AUX_C) | \ 1558 BIT(POWER_DOMAIN_INIT)) 1559 1560 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1561 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1562 BIT(POWER_DOMAIN_AUX_C) | \ 1563 BIT(POWER_DOMAIN_INIT)) 1564 1565 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1566 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1567 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1568 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1569 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1570 BIT(POWER_DOMAIN_AUX_B) | \ 1571 BIT(POWER_DOMAIN_AUX_C) | \ 1572 BIT(POWER_DOMAIN_INIT)) 1573 1574 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1575 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1576 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1577 BIT(POWER_DOMAIN_AUX_D) | \ 1578 BIT(POWER_DOMAIN_INIT)) 1579 1580 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1581 .sync_hw = i9xx_always_on_power_well_noop, 1582 .enable = i9xx_always_on_power_well_noop, 1583 .disable = i9xx_always_on_power_well_noop, 1584 .is_enabled = i9xx_always_on_power_well_enabled, 1585 }; 1586 1587 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1588 .sync_hw = chv_pipe_power_well_sync_hw, 1589 .enable = chv_pipe_power_well_enable, 1590 .disable = chv_pipe_power_well_disable, 1591 .is_enabled = chv_pipe_power_well_enabled, 1592 }; 1593 1594 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1595 .sync_hw = vlv_power_well_sync_hw, 1596 .enable = chv_dpio_cmn_power_well_enable, 1597 .disable = chv_dpio_cmn_power_well_disable, 1598 .is_enabled = vlv_power_well_enabled, 1599 }; 1600 1601 static struct i915_power_well i9xx_always_on_power_well[] = { 1602 { 1603 .name = "always-on", 1604 .always_on = 1, 1605 .domains = POWER_DOMAIN_MASK, 1606 .ops = &i9xx_always_on_power_well_ops, 1607 }, 1608 }; 1609 1610 static const struct i915_power_well_ops hsw_power_well_ops = { 1611 .sync_hw = hsw_power_well_sync_hw, 1612 .enable = hsw_power_well_enable, 1613 .disable = hsw_power_well_disable, 1614 .is_enabled = hsw_power_well_enabled, 1615 }; 1616 1617 static const struct i915_power_well_ops skl_power_well_ops = { 1618 .sync_hw = skl_power_well_sync_hw, 1619 .enable = skl_power_well_enable, 1620 .disable = skl_power_well_disable, 1621 .is_enabled = skl_power_well_enabled, 1622 }; 1623 1624 static struct i915_power_well hsw_power_wells[] = { 1625 { 1626 .name = "always-on", 1627 .always_on = 1, 1628 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1629 .ops = &i9xx_always_on_power_well_ops, 1630 }, 1631 { 1632 .name = "display", 1633 .domains = HSW_DISPLAY_POWER_DOMAINS, 1634 .ops = &hsw_power_well_ops, 1635 }, 1636 }; 1637 1638 static struct i915_power_well bdw_power_wells[] = { 1639 { 1640 .name = "always-on", 1641 .always_on = 1, 1642 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1643 .ops = &i9xx_always_on_power_well_ops, 1644 }, 1645 { 1646 .name = "display", 1647 .domains = BDW_DISPLAY_POWER_DOMAINS, 1648 .ops = &hsw_power_well_ops, 1649 }, 1650 }; 1651 1652 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1653 .sync_hw = vlv_power_well_sync_hw, 1654 .enable = vlv_display_power_well_enable, 1655 .disable = vlv_display_power_well_disable, 1656 .is_enabled = vlv_power_well_enabled, 1657 }; 1658 1659 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1660 .sync_hw = vlv_power_well_sync_hw, 1661 .enable = vlv_dpio_cmn_power_well_enable, 1662 .disable = vlv_dpio_cmn_power_well_disable, 1663 .is_enabled = vlv_power_well_enabled, 1664 }; 1665 1666 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1667 .sync_hw = vlv_power_well_sync_hw, 1668 .enable = vlv_power_well_enable, 1669 .disable = vlv_power_well_disable, 1670 .is_enabled = vlv_power_well_enabled, 1671 }; 1672 1673 static struct i915_power_well vlv_power_wells[] = { 1674 { 1675 .name = "always-on", 1676 .always_on = 1, 1677 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1678 .ops = &i9xx_always_on_power_well_ops, 1679 }, 1680 { 1681 .name = "display", 1682 .domains = VLV_DISPLAY_POWER_DOMAINS, 1683 .data = PUNIT_POWER_WELL_DISP2D, 1684 .ops = &vlv_display_power_well_ops, 1685 }, 1686 { 1687 .name = "dpio-tx-b-01", 1688 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1689 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1690 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1691 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1692 .ops = &vlv_dpio_power_well_ops, 1693 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1694 }, 1695 { 1696 .name = "dpio-tx-b-23", 1697 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1698 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1699 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1700 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1701 .ops = &vlv_dpio_power_well_ops, 1702 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1703 }, 1704 { 1705 .name = "dpio-tx-c-01", 1706 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1707 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1708 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1709 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1710 .ops = &vlv_dpio_power_well_ops, 1711 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1712 }, 1713 { 1714 .name = "dpio-tx-c-23", 1715 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1716 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1717 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1718 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1719 .ops = &vlv_dpio_power_well_ops, 1720 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1721 }, 1722 { 1723 .name = "dpio-common", 1724 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1725 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1726 .ops = &vlv_dpio_cmn_power_well_ops, 1727 }, 1728 }; 1729 1730 static struct i915_power_well chv_power_wells[] = { 1731 { 1732 .name = "always-on", 1733 .always_on = 1, 1734 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1735 .ops = &i9xx_always_on_power_well_ops, 1736 }, 1737 { 1738 .name = "display", 1739 /* 1740 * Pipe A power well is the new disp2d well. Pipe B and C 1741 * power wells don't actually exist. Pipe A power well is 1742 * required for any pipe to work. 1743 */ 1744 .domains = VLV_DISPLAY_POWER_DOMAINS, 1745 .data = PIPE_A, 1746 .ops = &chv_pipe_power_well_ops, 1747 }, 1748 { 1749 .name = "dpio-common-bc", 1750 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1751 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1752 .ops = &chv_dpio_cmn_power_well_ops, 1753 }, 1754 { 1755 .name = "dpio-common-d", 1756 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1757 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1758 .ops = &chv_dpio_cmn_power_well_ops, 1759 }, 1760 }; 1761 1762 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1763 int power_well_id) 1764 { 1765 struct i915_power_well *power_well; 1766 bool ret; 1767 1768 power_well = lookup_power_well(dev_priv, power_well_id); 1769 ret = power_well->ops->is_enabled(dev_priv, power_well); 1770 1771 return ret; 1772 } 1773 1774 static struct i915_power_well skl_power_wells[] = { 1775 { 1776 .name = "always-on", 1777 .always_on = 1, 1778 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1779 .ops = &i9xx_always_on_power_well_ops, 1780 }, 1781 { 1782 .name = "power well 1", 1783 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1784 .ops = &skl_power_well_ops, 1785 .data = SKL_DISP_PW_1, 1786 }, 1787 { 1788 .name = "MISC IO power well", 1789 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, 1790 .ops = &skl_power_well_ops, 1791 .data = SKL_DISP_PW_MISC_IO, 1792 }, 1793 { 1794 .name = "power well 2", 1795 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1796 .ops = &skl_power_well_ops, 1797 .data = SKL_DISP_PW_2, 1798 }, 1799 { 1800 .name = "DDI A/E power well", 1801 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1802 .ops = &skl_power_well_ops, 1803 .data = SKL_DISP_PW_DDI_A_E, 1804 }, 1805 { 1806 .name = "DDI B power well", 1807 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1808 .ops = &skl_power_well_ops, 1809 .data = SKL_DISP_PW_DDI_B, 1810 }, 1811 { 1812 .name = "DDI C power well", 1813 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1814 .ops = &skl_power_well_ops, 1815 .data = SKL_DISP_PW_DDI_C, 1816 }, 1817 { 1818 .name = "DDI D power well", 1819 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1820 .ops = &skl_power_well_ops, 1821 .data = SKL_DISP_PW_DDI_D, 1822 }, 1823 }; 1824 1825 static struct i915_power_well bxt_power_wells[] = { 1826 { 1827 .name = "always-on", 1828 .always_on = 1, 1829 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1830 .ops = &i9xx_always_on_power_well_ops, 1831 }, 1832 { 1833 .name = "power well 1", 1834 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1835 .ops = &skl_power_well_ops, 1836 .data = SKL_DISP_PW_1, 1837 }, 1838 { 1839 .name = "power well 2", 1840 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1841 .ops = &skl_power_well_ops, 1842 .data = SKL_DISP_PW_2, 1843 } 1844 }; 1845 1846 static int 1847 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 1848 int disable_power_well) 1849 { 1850 if (disable_power_well >= 0) 1851 return !!disable_power_well; 1852 1853 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1854 DRM_DEBUG_KMS("Disabling display power well support\n"); 1855 return 0; 1856 } 1857 1858 return 1; 1859 } 1860 1861 #define set_power_wells(power_domains, __power_wells) ({ \ 1862 (power_domains)->power_wells = (__power_wells); \ 1863 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1864 }) 1865 1866 /** 1867 * intel_power_domains_init - initializes the power domain structures 1868 * @dev_priv: i915 device instance 1869 * 1870 * Initializes the power domain structures for @dev_priv depending upon the 1871 * supported platform. 1872 */ 1873 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1874 { 1875 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1876 1877 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 1878 i915.disable_power_well); 1879 1880 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 1881 1882 #ifdef __NetBSD__ 1883 linux_mutex_init(&power_domains->lock); 1884 #else 1885 mutex_init(&power_domains->lock); 1886 #endif 1887 1888 /* 1889 * The enabling order will be from lower to higher indexed wells, 1890 * the disabling order is reversed. 1891 */ 1892 if (IS_HASWELL(dev_priv->dev)) { 1893 set_power_wells(power_domains, hsw_power_wells); 1894 } else if (IS_BROADWELL(dev_priv->dev)) { 1895 set_power_wells(power_domains, bdw_power_wells); 1896 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { 1897 set_power_wells(power_domains, skl_power_wells); 1898 } else if (IS_BROXTON(dev_priv->dev)) { 1899 set_power_wells(power_domains, bxt_power_wells); 1900 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1901 set_power_wells(power_domains, chv_power_wells); 1902 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1903 set_power_wells(power_domains, vlv_power_wells); 1904 } else { 1905 set_power_wells(power_domains, i9xx_always_on_power_well); 1906 } 1907 1908 return 0; 1909 } 1910 1911 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 1912 { 1913 struct drm_device *dev = dev_priv->dev; 1914 struct device *device = dev->dev; 1915 1916 if (!HAS_RUNTIME_PM(dev)) 1917 return; 1918 1919 if (!intel_enable_rc6(dev)) 1920 return; 1921 1922 /* Make sure we're not suspended first. */ 1923 pm_runtime_get_sync(device); 1924 } 1925 1926 /** 1927 * intel_power_domains_fini - finalizes the power domain structures 1928 * @dev_priv: i915 device instance 1929 * 1930 * Finalizes the power domain structures for @dev_priv depending upon the 1931 * supported platform. This function also disables runtime pm and ensures that 1932 * the device stays powered up so that the driver can be reloaded. 1933 */ 1934 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1935 { 1936 intel_runtime_pm_disable(dev_priv); 1937 1938 /* The i915.ko module is still not prepared to be loaded when 1939 * the power well is not enabled, so just enable it in case 1940 * we're going to unload/reload. */ 1941 intel_display_set_init_power(dev_priv, true); 1942 1943 #ifdef __NetBSD__ 1944 linux_mutex_destroy(&dev_priv->power_domains.lock); 1945 #else 1946 mutex_destroy(&dev_priv->power_domains.lock); 1947 #endif 1948 } 1949 1950 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 1951 { 1952 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1953 struct i915_power_well *power_well; 1954 int i; 1955 1956 mutex_lock(&power_domains->lock); 1957 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1958 power_well->ops->sync_hw(dev_priv, power_well); 1959 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 1960 power_well); 1961 } 1962 mutex_unlock(&power_domains->lock); 1963 } 1964 1965 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1966 { 1967 struct i915_power_well *cmn_bc = 1968 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1969 struct i915_power_well *cmn_d = 1970 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1971 1972 /* 1973 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1974 * workaround never ever read DISPLAY_PHY_CONTROL, and 1975 * instead maintain a shadow copy ourselves. Use the actual 1976 * power well state and lane status to reconstruct the 1977 * expected initial value. 1978 */ 1979 dev_priv->chv_phy_control = 1980 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1981 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1982 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1983 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1984 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1985 1986 /* 1987 * If all lanes are disabled we leave the override disabled 1988 * with all power down bits cleared to match the state we 1989 * would use after disabling the port. Otherwise enable the 1990 * override and set the lane powerdown bits accding to the 1991 * current lane status. 1992 */ 1993 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1994 uint32_t status = I915_READ(DPLL(PIPE_A)); 1995 unsigned int mask; 1996 1997 mask = status & DPLL_PORTB_READY_MASK; 1998 if (mask == 0xf) 1999 mask = 0x0; 2000 else 2001 dev_priv->chv_phy_control |= 2002 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2003 2004 dev_priv->chv_phy_control |= 2005 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2006 2007 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2008 if (mask == 0xf) 2009 mask = 0x0; 2010 else 2011 dev_priv->chv_phy_control |= 2012 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2013 2014 dev_priv->chv_phy_control |= 2015 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2016 2017 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2018 2019 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2020 } else { 2021 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2022 } 2023 2024 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2025 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2026 unsigned int mask; 2027 2028 mask = status & DPLL_PORTD_READY_MASK; 2029 2030 if (mask == 0xf) 2031 mask = 0x0; 2032 else 2033 dev_priv->chv_phy_control |= 2034 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2035 2036 dev_priv->chv_phy_control |= 2037 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2038 2039 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2040 2041 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2042 } else { 2043 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2044 } 2045 2046 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2047 2048 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2049 dev_priv->chv_phy_control); 2050 } 2051 2052 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2053 { 2054 struct i915_power_well *cmn = 2055 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2056 struct i915_power_well *disp2d = 2057 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2058 2059 /* If the display might be already active skip this */ 2060 if (cmn->ops->is_enabled(dev_priv, cmn) && 2061 disp2d->ops->is_enabled(dev_priv, disp2d) && 2062 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2063 return; 2064 2065 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2066 2067 /* cmnlane needs DPLL registers */ 2068 disp2d->ops->enable(dev_priv, disp2d); 2069 2070 /* 2071 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2072 * Need to assert and de-assert PHY SB reset by gating the 2073 * common lane power, then un-gating it. 2074 * Simply ungating isn't enough to reset the PHY enough to get 2075 * ports and lanes running. 2076 */ 2077 cmn->ops->disable(dev_priv, cmn); 2078 } 2079 2080 /** 2081 * intel_power_domains_init_hw - initialize hardware power domain state 2082 * @dev_priv: i915 device instance 2083 * 2084 * This function initializes the hardware power domain state and enables all 2085 * power domains using intel_display_set_init_power(). 2086 */ 2087 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 2088 { 2089 struct drm_device *dev = dev_priv->dev; 2090 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2091 2092 power_domains->initializing = true; 2093 2094 if (IS_CHERRYVIEW(dev)) { 2095 mutex_lock(&power_domains->lock); 2096 chv_phy_control_init(dev_priv); 2097 mutex_unlock(&power_domains->lock); 2098 } else if (IS_VALLEYVIEW(dev)) { 2099 mutex_lock(&power_domains->lock); 2100 vlv_cmnlane_wa(dev_priv); 2101 mutex_unlock(&power_domains->lock); 2102 } 2103 2104 /* For now, we need the power well to be always enabled. */ 2105 intel_display_set_init_power(dev_priv, true); 2106 intel_power_domains_resume(dev_priv); 2107 power_domains->initializing = false; 2108 } 2109 2110 /** 2111 * intel_runtime_pm_get - grab a runtime pm reference 2112 * @dev_priv: i915 device instance 2113 * 2114 * This function grabs a device-level runtime pm reference (mostly used for GEM 2115 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2116 * 2117 * Any runtime pm reference obtained by this function must have a symmetric 2118 * call to intel_runtime_pm_put() to release the reference again. 2119 */ 2120 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2121 { 2122 struct drm_device *dev = dev_priv->dev; 2123 struct device *device = dev->dev; 2124 2125 if (!HAS_RUNTIME_PM(dev)) 2126 return; 2127 2128 pm_runtime_get_sync(device); 2129 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 2130 } 2131 2132 /** 2133 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2134 * @dev_priv: i915 device instance 2135 * 2136 * This function grabs a device-level runtime pm reference (mostly used for GEM 2137 * code to ensure the GTT or GT is on). 2138 * 2139 * It will _not_ power up the device but instead only check that it's powered 2140 * on. Therefore it is only valid to call this functions from contexts where 2141 * the device is known to be powered up and where trying to power it up would 2142 * result in hilarity and deadlocks. That pretty much means only the system 2143 * suspend/resume code where this is used to grab runtime pm references for 2144 * delayed setup down in work items. 2145 * 2146 * Any runtime pm reference obtained by this function must have a symmetric 2147 * call to intel_runtime_pm_put() to release the reference again. 2148 */ 2149 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2150 { 2151 struct drm_device *dev = dev_priv->dev; 2152 struct device *device = dev->dev; 2153 2154 if (!HAS_RUNTIME_PM(dev)) 2155 return; 2156 2157 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); 2158 pm_runtime_get_noresume(device); 2159 } 2160 2161 /** 2162 * intel_runtime_pm_put - release a runtime pm reference 2163 * @dev_priv: i915 device instance 2164 * 2165 * This function drops the device-level runtime pm reference obtained by 2166 * intel_runtime_pm_get() and might power down the corresponding 2167 * hardware block right away if this is the last reference. 2168 */ 2169 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2170 { 2171 struct drm_device *dev = dev_priv->dev; 2172 struct device *device = dev->dev; 2173 2174 if (!HAS_RUNTIME_PM(dev)) 2175 return; 2176 2177 pm_runtime_mark_last_busy(device); 2178 pm_runtime_put_autosuspend(device); 2179 } 2180 2181 /** 2182 * intel_runtime_pm_enable - enable runtime pm 2183 * @dev_priv: i915 device instance 2184 * 2185 * This function enables runtime pm at the end of the driver load sequence. 2186 * 2187 * Note that this function does currently not enable runtime pm for the 2188 * subordinate display power domains. That is only done on the first modeset 2189 * using intel_display_set_init_power(). 2190 */ 2191 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2192 { 2193 struct drm_device *dev = dev_priv->dev; 2194 struct device *device = dev->dev; 2195 2196 if (!HAS_RUNTIME_PM(dev)) 2197 return; 2198 2199 /* 2200 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 2201 * requirement. 2202 */ 2203 if (!intel_enable_rc6(dev)) { 2204 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 2205 return; 2206 } 2207 2208 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2209 pm_runtime_mark_last_busy(device); 2210 pm_runtime_use_autosuspend(device); 2211 2212 pm_runtime_put_autosuspend(device); 2213 } 2214 2215
Indexes created Wed Oct 01 18:09:54 GMT 2025