intel_wopcm.c revision 1.1
1 /* $NetBSD: intel_wopcm.c,v 1.1 2021/12/18 20:15:27 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 /* 5 * Copyright 2017-2019 Intel Corporation 6 */ 7 8 #include <sys/cdefs.h> 9 __KERNEL_RCSID(0, "$NetBSD: intel_wopcm.c,v 1.1 2021/12/18 20:15:27 riastradh Exp $"); 10 11 #include "intel_wopcm.h" 12 #include "i915_drv.h" 13 14 /** 15 * DOC: WOPCM Layout 16 * 17 * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and 18 * offset registers whose values are calculated and determined by HuC/GuC 19 * firmware size and set of hardware requirements/restrictions as shown below: 20 * 21 * :: 22 * 23 * +=========> +====================+ <== WOPCM Top 24 * ^ | HW contexts RSVD | 25 * | +===> +====================+ <== GuC WOPCM Top 26 * | ^ | | 27 * | | | | 28 * | | | | 29 * | GuC | | 30 * | WOPCM | | 31 * | Size +--------------------+ 32 * WOPCM | | GuC FW RSVD | 33 * | | +--------------------+ 34 * | | | GuC Stack RSVD | 35 * | | +------------------- + 36 * | v | GuC WOPCM RSVD | 37 * | +===> +====================+ <== GuC WOPCM base 38 * | | WOPCM RSVD | 39 * | +------------------- + <== HuC Firmware Top 40 * v | HuC FW | 41 * +=========> +====================+ <== WOPCM Base 42 * 43 * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. 44 * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 45 * context). 46 */ 47 48 /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */ 49 #define GEN11_WOPCM_SIZE SZ_2M 50 #define GEN9_WOPCM_SIZE SZ_1M 51 /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */ 52 #define WOPCM_RESERVED_SIZE SZ_16K 53 54 /* 16KB reserved at the beginning of GuC WOPCM. */ 55 #define GUC_WOPCM_RESERVED SZ_16K 56 /* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */ 57 #define GUC_WOPCM_STACK_RESERVED SZ_8K 58 59 /* GuC WOPCM Offset value needs to be aligned to 16KB. */ 60 #define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT) 61 62 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */ 63 #define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K) 64 /* 36KB WOPCM reserved at the end of WOPCM on CNL. */ 65 #define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K) 66 67 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */ 68 #define GEN9_GUC_FW_RESERVED SZ_128K 69 #define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED) 70 71 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) 72 { 73 return container_of(wopcm, struct drm_i915_private, wopcm); 74 } 75 76 /** 77 * intel_wopcm_init_early() - Early initialization of the WOPCM. 78 * @wopcm: pointer to intel_wopcm. 79 * 80 * Setup the size of WOPCM which will be used by later on WOPCM partitioning. 81 */ 82 void intel_wopcm_init_early(struct intel_wopcm *wopcm) 83 { 84 struct drm_i915_private *i915 = wopcm_to_i915(wopcm); 85 86 if (!HAS_GT_UC(i915)) 87 return; 88 89 if (INTEL_GEN(i915) >= 11) 90 wopcm->size = GEN11_WOPCM_SIZE; 91 else 92 wopcm->size = GEN9_WOPCM_SIZE; 93 94 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "WOPCM: %uK\n", wopcm->size / 1024); 95 } 96 97 static inline u32 context_reserved_size(struct drm_i915_private *i915) 98 { 99 if (IS_GEN9_LP(i915)) 100 return BXT_WOPCM_RC6_CTX_RESERVED; 101 else if (INTEL_GEN(i915) >= 10) 102 return CNL_WOPCM_HW_CTX_RESERVED; 103 else 104 return 0; 105 } 106 107 static inline bool gen9_check_dword_gap(struct drm_i915_private *i915, 108 u32 guc_wopcm_base, u32 guc_wopcm_size) 109 { 110 u32 offset; 111 112 /* 113 * GuC WOPCM size shall be at least a dword larger than the offset from 114 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET) 115 * due to hardware limitation on Gen9. 116 */ 117 offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET; 118 if (offset > guc_wopcm_size || 119 (guc_wopcm_size - offset) < sizeof(u32)) { 120 dev_err(i915->drm.dev, 121 "WOPCM: invalid GuC region size: %uK < %uK\n", 122 guc_wopcm_size / SZ_1K, 123 (u32)(offset + sizeof(u32)) / SZ_1K); 124 return false; 125 } 126 127 return true; 128 } 129 130 static inline bool gen9_check_huc_fw_fits(struct drm_i915_private *i915, 131 u32 guc_wopcm_size, u32 huc_fw_size) 132 { 133 /* 134 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM 135 * size to be larger than or equal to HuC firmware size. Otherwise, 136 * firmware uploading would fail. 137 */ 138 if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) { 139 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 140 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), 141 (guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K, 142 huc_fw_size / 1024); 143 return false; 144 } 145 146 return true; 147 } 148 149 static inline bool check_hw_restrictions(struct drm_i915_private *i915, 150 u32 guc_wopcm_base, u32 guc_wopcm_size, 151 u32 huc_fw_size) 152 { 153 if (IS_GEN(i915, 9) && !gen9_check_dword_gap(i915, guc_wopcm_base, 154 guc_wopcm_size)) 155 return false; 156 157 if ((IS_GEN(i915, 9) || 158 IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)) && 159 !gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size)) 160 return false; 161 162 return true; 163 } 164 165 static inline bool __check_layout(struct drm_i915_private *i915, u32 wopcm_size, 166 u32 guc_wopcm_base, u32 guc_wopcm_size, 167 u32 guc_fw_size, u32 huc_fw_size) 168 { 169 const u32 ctx_rsvd = context_reserved_size(i915); 170 u32 size; 171 172 size = wopcm_size - ctx_rsvd; 173 if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) { 174 dev_err(i915->drm.dev, 175 "WOPCM: invalid GuC region layout: %uK + %uK > %uK\n", 176 guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K, 177 size / SZ_1K); 178 return false; 179 } 180 181 size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED; 182 if (unlikely(guc_wopcm_size < size)) { 183 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 184 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), 185 guc_wopcm_size / SZ_1K, size / SZ_1K); 186 return false; 187 } 188 189 size = huc_fw_size + WOPCM_RESERVED_SIZE; 190 if (unlikely(guc_wopcm_base < size)) { 191 dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", 192 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC), 193 guc_wopcm_base / SZ_1K, size / SZ_1K); 194 return false; 195 } 196 197 return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size, 198 huc_fw_size); 199 } 200 201 static bool __wopcm_regs_locked(struct intel_uncore *uncore, 202 u32 *guc_wopcm_base, u32 *guc_wopcm_size) 203 { 204 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); 205 u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE); 206 207 if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) || 208 !(reg_base & GUC_WOPCM_OFFSET_VALID)) 209 return false; 210 211 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK; 212 *guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK; 213 return true; 214 } 215 216 /** 217 * intel_wopcm_init() - Initialize the WOPCM structure. 218 * @wopcm: pointer to intel_wopcm. 219 * 220 * This function will partition WOPCM space based on GuC and HuC firmware sizes 221 * and will allocate max remaining for use by GuC. This function will also 222 * enforce platform dependent hardware restrictions on GuC WOPCM offset and 223 * size. It will fail the WOPCM init if any of these checks fail, so that the 224 * following WOPCM registers setup and GuC firmware uploading would be aborted. 225 */ 226 void intel_wopcm_init(struct intel_wopcm *wopcm) 227 { 228 struct drm_i915_private *i915 = wopcm_to_i915(wopcm); 229 struct intel_gt *gt = &i915->gt; 230 u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw); 231 u32 huc_fw_size = intel_uc_fw_get_upload_size(>->uc.huc.fw); 232 u32 ctx_rsvd = context_reserved_size(i915); 233 u32 guc_wopcm_base; 234 u32 guc_wopcm_size; 235 236 if (!guc_fw_size) 237 return; 238 239 GEM_BUG_ON(!wopcm->size); 240 GEM_BUG_ON(wopcm->guc.base); 241 GEM_BUG_ON(wopcm->guc.size); 242 GEM_BUG_ON(guc_fw_size >= wopcm->size); 243 GEM_BUG_ON(huc_fw_size >= wopcm->size); 244 GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm->size); 245 246 if (i915_inject_probe_failure(i915)) 247 return; 248 249 if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) { 250 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, 251 "GuC WOPCM is already locked [%uK, %uK)\n", 252 guc_wopcm_base / SZ_1K, 253 guc_wopcm_size / SZ_1K); 254 goto check; 255 } 256 257 /* 258 * Aligned value of guc_wopcm_base will determine available WOPCM space 259 * for HuC firmware and mandatory reserved area. 260 */ 261 guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE; 262 guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT); 263 264 /* 265 * Need to clamp guc_wopcm_base now to make sure the following math is 266 * correct. Formal check of whole WOPCM layout will be done below. 267 */ 268 guc_wopcm_base = min(guc_wopcm_base, wopcm->size - ctx_rsvd); 269 270 /* Aligned remainings of usable WOPCM space can be assigned to GuC. */ 271 guc_wopcm_size = wopcm->size - ctx_rsvd - guc_wopcm_base; 272 guc_wopcm_size &= GUC_WOPCM_SIZE_MASK; 273 274 DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "Calculated GuC WOPCM [%uK, %uK)\n", 275 guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K); 276 277 check: 278 if (__check_layout(i915, wopcm->size, guc_wopcm_base, guc_wopcm_size, 279 guc_fw_size, huc_fw_size)) { 280 wopcm->guc.base = guc_wopcm_base; 281 wopcm->guc.size = guc_wopcm_size; 282 GEM_BUG_ON(!wopcm->guc.base); 283 GEM_BUG_ON(!wopcm->guc.size); 284 } 285 } 286
Indexes created Wed Oct 15 16:09:53 GMT 2025