mga_drv.h revision 1.1.1.2.30.1
1 /* $NetBSD: mga_drv.h,v 1.1.1.2.30.1 2019/06/10 22:08:06 christos Exp $ */ 2 3 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 4 * Created: Mon Dec 13 01:50:01 1999 by jhartmann (at) precisioninsight.com 5 * 6 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 7 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 8 * All rights reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice (including the next 18 * paragraph) shall be included in all copies or substantial portions of the 19 * Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 * OTHER DEALINGS IN THE SOFTWARE. 28 * 29 * Authors: 30 * Gareth Hughes <gareth (at) valinux.com> 31 */ 32 33 #ifndef __MGA_DRV_H__ 34 #define __MGA_DRV_H__ 35 36 #include <drm/drm_legacy.h> 37 38 /* General customization: 39 */ 40 41 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 42 43 #define DRIVER_NAME "mga" 44 #define DRIVER_DESC "Matrox G200/G400" 45 #define DRIVER_DATE "20051102" 46 47 #define DRIVER_MAJOR 3 48 #define DRIVER_MINOR 2 49 #define DRIVER_PATCHLEVEL 1 50 51 typedef struct drm_mga_primary_buffer { 52 u8 *start; 53 u8 *end; 54 int size; 55 56 u32 tail; 57 int space; 58 volatile long wrapped; 59 60 volatile u32 *status; 61 62 u32 last_flush; 63 u32 last_wrap; 64 65 u32 high_mark; 66 } drm_mga_primary_buffer_t; 67 68 typedef struct drm_mga_freelist { 69 struct drm_mga_freelist *next; 70 struct drm_mga_freelist *prev; 71 drm_mga_age_t age; 72 struct drm_buf *buf; 73 } drm_mga_freelist_t; 74 75 typedef struct { 76 drm_mga_freelist_t *list_entry; 77 int discard; 78 int dispatched; 79 } drm_mga_buf_priv_t; 80 81 typedef struct drm_mga_private { 82 drm_mga_primary_buffer_t prim; 83 drm_mga_sarea_t *sarea_priv; 84 85 drm_mga_freelist_t *head; 86 drm_mga_freelist_t *tail; 87 88 unsigned int warp_pipe; 89 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 90 91 int chipset; 92 int usec_timeout; 93 94 /** 95 * If set, the new DMA initialization sequence was used. This is 96 * primarilly used to select how the driver should uninitialized its 97 * internal DMA structures. 98 */ 99 int used_new_dma_init; 100 101 /** 102 * If AGP memory is used for DMA buffers, this will be the value 103 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer). 104 */ 105 u32 dma_access; 106 107 /** 108 * If AGP memory is used for DMA buffers, this will be the value 109 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI 110 * transfer). 111 */ 112 u32 wagp_enable; 113 114 /** 115 * \name MMIO region parameters. 116 * 117 * \sa drm_mga_private_t::mmio 118 */ 119 /*@{ */ 120 resource_size_t mmio_base; /**< Bus address of base of MMIO. */ 121 resource_size_t mmio_size; /**< Size of the MMIO region. */ 122 /*@} */ 123 124 u32 clear_cmd; 125 u32 maccess; 126 127 atomic_t vbl_received; /**< Number of vblanks received. */ 128 wait_queue_head_t fence_queue; 129 atomic_t last_fence_retired; 130 u32 next_fence_to_post; 131 132 unsigned int fb_cpp; 133 unsigned int front_offset; 134 unsigned int front_pitch; 135 unsigned int back_offset; 136 unsigned int back_pitch; 137 138 unsigned int depth_cpp; 139 unsigned int depth_offset; 140 unsigned int depth_pitch; 141 142 unsigned int texture_offset; 143 unsigned int texture_size; 144 145 drm_local_map_t *sarea; 146 drm_local_map_t *mmio; 147 drm_local_map_t *status; 148 drm_local_map_t *warp; 149 drm_local_map_t *primary; 150 drm_local_map_t *agp_textures; 151 152 unsigned long agp_handle; 153 unsigned int agp_size; 154 } drm_mga_private_t; 155 156 extern const struct drm_ioctl_desc mga_ioctls[]; 157 extern int mga_max_ioctl; 158 159 /* mga_dma.c */ 160 extern int mga_dma_bootstrap(struct drm_device *dev, void *data, 161 struct drm_file *file_priv); 162 extern int mga_dma_init(struct drm_device *dev, void *data, 163 struct drm_file *file_priv); 164 extern int mga_dma_flush(struct drm_device *dev, void *data, 165 struct drm_file *file_priv); 166 extern int mga_dma_reset(struct drm_device *dev, void *data, 167 struct drm_file *file_priv); 168 extern int mga_dma_buffers(struct drm_device *dev, void *data, 169 struct drm_file *file_priv); 170 extern int mga_driver_load(struct drm_device *dev, unsigned long flags); 171 extern int mga_driver_unload(struct drm_device *dev); 172 extern void mga_driver_lastclose(struct drm_device *dev); 173 extern int mga_driver_dma_quiescent(struct drm_device *dev); 174 175 extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv); 176 177 extern void mga_do_dma_flush(drm_mga_private_t *dev_priv); 178 extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv); 179 extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv); 180 181 extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf); 182 183 /* mga_warp.c */ 184 extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv); 185 extern int mga_warp_init(drm_mga_private_t *dev_priv); 186 187 /* mga_irq.c */ 188 extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe); 189 extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe); 190 extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe); 191 extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence); 192 extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); 193 extern irqreturn_t mga_driver_irq_handler(int irq, void *arg); 194 extern void mga_driver_irq_preinstall(struct drm_device *dev); 195 extern int mga_driver_irq_postinstall(struct drm_device *dev); 196 extern void mga_driver_irq_uninstall(struct drm_device *dev); 197 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, 198 unsigned long arg); 199 200 #define mga_flush_write_combine() wmb() 201 202 #define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg)) 203 #define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg)) 204 #define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 205 #define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 206 207 #define DWGREG0 0x1c00 208 #define DWGREG0_END 0x1dff 209 #define DWGREG1 0x2c00 210 #define DWGREG1_END 0x2dff 211 212 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 213 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 214 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 215 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 216 217 /* ================================================================ 218 * Helper macross... 219 */ 220 221 #define MGA_EMIT_STATE(dev_priv, dirty) \ 222 do { \ 223 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \ 224 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \ 225 mga_g400_emit_state(dev_priv); \ 226 else \ 227 mga_g200_emit_state(dev_priv); \ 228 } \ 229 } while (0) 230 231 #define WRAP_TEST_WITH_RETURN(dev_priv) \ 232 do { \ 233 if (test_bit(0, &dev_priv->prim.wrapped)) { \ 234 if (mga_is_idle(dev_priv)) { \ 235 mga_do_dma_wrap_end(dev_priv); \ 236 } else if (dev_priv->prim.space < \ 237 dev_priv->prim.high_mark) { \ 238 if (MGA_DMA_DEBUG) \ 239 DRM_INFO("wrap...\n"); \ 240 return -EBUSY; \ 241 } \ 242 } \ 243 } while (0) 244 245 #define WRAP_WAIT_WITH_RETURN(dev_priv) \ 246 do { \ 247 if (test_bit(0, &dev_priv->prim.wrapped)) { \ 248 if (mga_do_wait_for_idle(dev_priv) < 0) { \ 249 if (MGA_DMA_DEBUG) \ 250 DRM_INFO("wrap...\n"); \ 251 return -EBUSY; \ 252 } \ 253 mga_do_dma_wrap_end(dev_priv); \ 254 } \ 255 } while (0) 256 257 /* ================================================================ 258 * Primary DMA command stream 259 */ 260 261 #define MGA_VERBOSE 0 262 263 #define DMA_LOCALS unsigned int write; volatile u8 *prim; 264 265 #define DMA_BLOCK_SIZE (5 * sizeof(u32)) 266 267 #define BEGIN_DMA(n) \ 268 do { \ 269 if (MGA_VERBOSE) { \ 270 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \ 271 DRM_INFO(" space=0x%x req=0x%Zx\n", \ 272 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \ 273 } \ 274 prim = dev_priv->prim.start; \ 275 write = dev_priv->prim.tail; \ 276 } while (0) 277 278 #define BEGIN_DMA_WRAP() \ 279 do { \ 280 if (MGA_VERBOSE) { \ 281 DRM_INFO("BEGIN_DMA()\n"); \ 282 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \ 283 } \ 284 prim = dev_priv->prim.start; \ 285 write = dev_priv->prim.tail; \ 286 } while (0) 287 288 #define ADVANCE_DMA() \ 289 do { \ 290 dev_priv->prim.tail = write; \ 291 if (MGA_VERBOSE) \ 292 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 293 write, dev_priv->prim.space); \ 294 } while (0) 295 296 #define FLUSH_DMA() \ 297 do { \ 298 if (0) { \ 299 DRM_INFO("\n"); \ 300 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \ 301 dev_priv->prim.tail, \ 302 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \ 303 dev_priv->primary->offset)); \ 304 } \ 305 if (!test_bit(0, &dev_priv->prim.wrapped)) { \ 306 if (dev_priv->prim.space < dev_priv->prim.high_mark) \ 307 mga_do_dma_wrap_start(dev_priv); \ 308 else \ 309 mga_do_dma_flush(dev_priv); \ 310 } \ 311 } while (0) 312 313 /* Never use this, always use DMA_BLOCK(...) for primary DMA output. 314 */ 315 #define DMA_WRITE(offset, val) \ 316 do { \ 317 if (MGA_VERBOSE) \ 318 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ 319 (u32)(val), write + (offset) * sizeof(u32)); \ 320 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 321 } while (0) 322 323 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ 324 do { \ 325 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \ 326 (DMAREG(reg1) << 8) | \ 327 (DMAREG(reg2) << 16) | \ 328 (DMAREG(reg3) << 24))); \ 329 DMA_WRITE(1, val0); \ 330 DMA_WRITE(2, val1); \ 331 DMA_WRITE(3, val2); \ 332 DMA_WRITE(4, val3); \ 333 write += DMA_BLOCK_SIZE; \ 334 } while (0) 335 336 /* Buffer aging via primary DMA stream head pointer. 337 */ 338 339 #define SET_AGE(age, h, w) \ 340 do { \ 341 (age)->head = h; \ 342 (age)->wrap = w; \ 343 } while (0) 344 345 #define TEST_AGE(age, h, w) ((age)->wrap < w || \ 346 ((age)->wrap == w && \ 347 (age)->head < h)) 348 349 #define AGE_BUFFER(buf_priv) \ 350 do { \ 351 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 352 if ((buf_priv)->dispatched) { \ 353 entry->age.head = (dev_priv->prim.tail + \ 354 dev_priv->primary->offset); \ 355 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 356 } else { \ 357 entry->age.head = 0; \ 358 entry->age.wrap = 0; \ 359 } \ 360 } while (0) 361 362 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 363 MGA_DWGENGSTS | \ 364 MGA_ENDPRDMASTS) 365 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 366 MGA_ENDPRDMASTS) 367 368 #define MGA_DMA_DEBUG 0 369 370 /* A reduced set of the mga registers. 371 */ 372 #define MGA_CRTC_INDEX 0x1fd4 373 #define MGA_CRTC_DATA 0x1fd5 374 375 /* CRTC11 */ 376 #define MGA_VINTCLR (1 << 4) 377 #define MGA_VINTEN (1 << 5) 378 379 #define MGA_ALPHACTRL 0x2c7c 380 #define MGA_AR0 0x1c60 381 #define MGA_AR1 0x1c64 382 #define MGA_AR2 0x1c68 383 #define MGA_AR3 0x1c6c 384 #define MGA_AR4 0x1c70 385 #define MGA_AR5 0x1c74 386 #define MGA_AR6 0x1c78 387 388 #define MGA_CXBNDRY 0x1c80 389 #define MGA_CXLEFT 0x1ca0 390 #define MGA_CXRIGHT 0x1ca4 391 392 #define MGA_DMAPAD 0x1c54 393 #define MGA_DSTORG 0x2cb8 394 #define MGA_DWGCTL 0x1c00 395 # define MGA_OPCOD_MASK (15 << 0) 396 # define MGA_OPCOD_TRAP (4 << 0) 397 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 398 # define MGA_OPCOD_BITBLT (8 << 0) 399 # define MGA_OPCOD_ILOAD (9 << 0) 400 # define MGA_ATYPE_MASK (7 << 4) 401 # define MGA_ATYPE_RPL (0 << 4) 402 # define MGA_ATYPE_RSTR (1 << 4) 403 # define MGA_ATYPE_ZI (3 << 4) 404 # define MGA_ATYPE_BLK (4 << 4) 405 # define MGA_ATYPE_I (7 << 4) 406 # define MGA_LINEAR (1 << 7) 407 # define MGA_ZMODE_MASK (7 << 8) 408 # define MGA_ZMODE_NOZCMP (0 << 8) 409 # define MGA_ZMODE_ZE (2 << 8) 410 # define MGA_ZMODE_ZNE (3 << 8) 411 # define MGA_ZMODE_ZLT (4 << 8) 412 # define MGA_ZMODE_ZLTE (5 << 8) 413 # define MGA_ZMODE_ZGT (6 << 8) 414 # define MGA_ZMODE_ZGTE (7 << 8) 415 # define MGA_SOLID (1 << 11) 416 # define MGA_ARZERO (1 << 12) 417 # define MGA_SGNZERO (1 << 13) 418 # define MGA_SHIFTZERO (1 << 14) 419 # define MGA_BOP_MASK (15 << 16) 420 # define MGA_BOP_ZERO (0 << 16) 421 # define MGA_BOP_DST (10 << 16) 422 # define MGA_BOP_SRC (12 << 16) 423 # define MGA_BOP_ONE (15 << 16) 424 # define MGA_TRANS_SHIFT 20 425 # define MGA_TRANS_MASK (15 << 20) 426 # define MGA_BLTMOD_MASK (15 << 25) 427 # define MGA_BLTMOD_BMONOLEF (0 << 25) 428 # define MGA_BLTMOD_BMONOWF (4 << 25) 429 # define MGA_BLTMOD_PLAN (1 << 25) 430 # define MGA_BLTMOD_BFCOL (2 << 25) 431 # define MGA_BLTMOD_BU32BGR (3 << 25) 432 # define MGA_BLTMOD_BU32RGB (7 << 25) 433 # define MGA_BLTMOD_BU24BGR (11 << 25) 434 # define MGA_BLTMOD_BU24RGB (15 << 25) 435 # define MGA_PATTERN (1 << 29) 436 # define MGA_TRANSC (1 << 30) 437 # define MGA_CLIPDIS (1 << 31) 438 #define MGA_DWGSYNC 0x2c4c 439 440 #define MGA_FCOL 0x1c24 441 #define MGA_FIFOSTATUS 0x1e10 442 #define MGA_FOGCOL 0x1cf4 443 #define MGA_FXBNDRY 0x1c84 444 #define MGA_FXLEFT 0x1ca8 445 #define MGA_FXRIGHT 0x1cac 446 447 #define MGA_ICLEAR 0x1e18 448 # define MGA_SOFTRAPICLR (1 << 0) 449 # define MGA_VLINEICLR (1 << 5) 450 #define MGA_IEN 0x1e1c 451 # define MGA_SOFTRAPIEN (1 << 0) 452 # define MGA_VLINEIEN (1 << 5) 453 454 #define MGA_LEN 0x1c5c 455 456 #define MGA_MACCESS 0x1c04 457 458 #define MGA_PITCH 0x1c8c 459 #define MGA_PLNWT 0x1c1c 460 #define MGA_PRIMADDRESS 0x1e58 461 # define MGA_DMA_GENERAL (0 << 0) 462 # define MGA_DMA_BLIT (1 << 0) 463 # define MGA_DMA_VECTOR (2 << 0) 464 # define MGA_DMA_VERTEX (3 << 0) 465 #define MGA_PRIMEND 0x1e5c 466 # define MGA_PRIMNOSTART (1 << 0) 467 # define MGA_PAGPXFER (1 << 1) 468 #define MGA_PRIMPTR 0x1e50 469 # define MGA_PRIMPTREN0 (1 << 0) 470 # define MGA_PRIMPTREN1 (1 << 1) 471 472 #define MGA_RST 0x1e40 473 # define MGA_SOFTRESET (1 << 0) 474 # define MGA_SOFTEXTRST (1 << 1) 475 476 #define MGA_SECADDRESS 0x2c40 477 #define MGA_SECEND 0x2c44 478 #define MGA_SETUPADDRESS 0x2cd0 479 #define MGA_SETUPEND 0x2cd4 480 #define MGA_SGN 0x1c58 481 #define MGA_SOFTRAP 0x2c48 482 #define MGA_SRCORG 0x2cb4 483 # define MGA_SRMMAP_MASK (1 << 0) 484 # define MGA_SRCMAP_FB (0 << 0) 485 # define MGA_SRCMAP_SYSMEM (1 << 0) 486 # define MGA_SRCACC_MASK (1 << 1) 487 # define MGA_SRCACC_PCI (0 << 1) 488 # define MGA_SRCACC_AGP (1 << 1) 489 #define MGA_STATUS 0x1e14 490 # define MGA_SOFTRAPEN (1 << 0) 491 # define MGA_VSYNCPEN (1 << 4) 492 # define MGA_VLINEPEN (1 << 5) 493 # define MGA_DWGENGSTS (1 << 16) 494 # define MGA_ENDPRDMASTS (1 << 17) 495 #define MGA_STENCIL 0x2cc8 496 #define MGA_STENCILCTL 0x2ccc 497 498 #define MGA_TDUALSTAGE0 0x2cf8 499 #define MGA_TDUALSTAGE1 0x2cfc 500 #define MGA_TEXBORDERCOL 0x2c5c 501 #define MGA_TEXCTL 0x2c30 502 #define MGA_TEXCTL2 0x2c3c 503 # define MGA_DUALTEX (1 << 7) 504 # define MGA_G400_TC2_MAGIC (1 << 15) 505 # define MGA_MAP1_ENABLE (1 << 31) 506 #define MGA_TEXFILTER 0x2c58 507 #define MGA_TEXHEIGHT 0x2c2c 508 #define MGA_TEXORG 0x2c24 509 # define MGA_TEXORGMAP_MASK (1 << 0) 510 # define MGA_TEXORGMAP_FB (0 << 0) 511 # define MGA_TEXORGMAP_SYSMEM (1 << 0) 512 # define MGA_TEXORGACC_MASK (1 << 1) 513 # define MGA_TEXORGACC_PCI (0 << 1) 514 # define MGA_TEXORGACC_AGP (1 << 1) 515 #define MGA_TEXORG1 0x2ca4 516 #define MGA_TEXORG2 0x2ca8 517 #define MGA_TEXORG3 0x2cac 518 #define MGA_TEXORG4 0x2cb0 519 #define MGA_TEXTRANS 0x2c34 520 #define MGA_TEXTRANSHIGH 0x2c38 521 #define MGA_TEXWIDTH 0x2c28 522 523 #define MGA_WACCEPTSEQ 0x1dd4 524 #define MGA_WCODEADDR 0x1e6c 525 #define MGA_WFLAG 0x1dc4 526 #define MGA_WFLAG1 0x1de0 527 #define MGA_WFLAGNB 0x1e64 528 #define MGA_WFLAGNB1 0x1e08 529 #define MGA_WGETMSB 0x1dc8 530 #define MGA_WIADDR 0x1dc0 531 #define MGA_WIADDR2 0x1dd8 532 # define MGA_WMODE_SUSPEND (0 << 0) 533 # define MGA_WMODE_RESUME (1 << 0) 534 # define MGA_WMODE_JUMP (2 << 0) 535 # define MGA_WMODE_START (3 << 0) 536 # define MGA_WAGP_ENABLE (1 << 2) 537 #define MGA_WMISC 0x1e70 538 # define MGA_WUCODECACHE_ENABLE (1 << 0) 539 # define MGA_WMASTER_ENABLE (1 << 1) 540 # define MGA_WCACHEFLUSH_ENABLE (1 << 3) 541 #define MGA_WVRTXSZ 0x1dcc 542 543 #define MGA_YBOT 0x1c9c 544 #define MGA_YDST 0x1c90 545 #define MGA_YDSTLEN 0x1c88 546 #define MGA_YDSTORG 0x1c94 547 #define MGA_YTOP 0x1c98 548 549 #define MGA_ZORG 0x1c0c 550 551 /* This finishes the current batch of commands 552 */ 553 #define MGA_EXEC 0x0100 554 555 /* AGP PLL encoding (for G200 only). 556 */ 557 #define MGA_AGP_PLL 0x1e4c 558 # define MGA_AGP2XPLL_DISABLE (0 << 0) 559 # define MGA_AGP2XPLL_ENABLE (1 << 0) 560 561 /* Warp registers 562 */ 563 #define MGA_WR0 0x2d00 564 #define MGA_WR1 0x2d04 565 #define MGA_WR2 0x2d08 566 #define MGA_WR3 0x2d0c 567 #define MGA_WR4 0x2d10 568 #define MGA_WR5 0x2d14 569 #define MGA_WR6 0x2d18 570 #define MGA_WR7 0x2d1c 571 #define MGA_WR8 0x2d20 572 #define MGA_WR9 0x2d24 573 #define MGA_WR10 0x2d28 574 #define MGA_WR11 0x2d2c 575 #define MGA_WR12 0x2d30 576 #define MGA_WR13 0x2d34 577 #define MGA_WR14 0x2d38 578 #define MGA_WR15 0x2d3c 579 #define MGA_WR16 0x2d40 580 #define MGA_WR17 0x2d44 581 #define MGA_WR18 0x2d48 582 #define MGA_WR19 0x2d4c 583 #define MGA_WR20 0x2d50 584 #define MGA_WR21 0x2d54 585 #define MGA_WR22 0x2d58 586 #define MGA_WR23 0x2d5c 587 #define MGA_WR24 0x2d60 588 #define MGA_WR25 0x2d64 589 #define MGA_WR26 0x2d68 590 #define MGA_WR27 0x2d6c 591 #define MGA_WR28 0x2d70 592 #define MGA_WR29 0x2d74 593 #define MGA_WR30 0x2d78 594 #define MGA_WR31 0x2d7c 595 #define MGA_WR32 0x2d80 596 #define MGA_WR33 0x2d84 597 #define MGA_WR34 0x2d88 598 #define MGA_WR35 0x2d8c 599 #define MGA_WR36 0x2d90 600 #define MGA_WR37 0x2d94 601 #define MGA_WR38 0x2d98 602 #define MGA_WR39 0x2d9c 603 #define MGA_WR40 0x2da0 604 #define MGA_WR41 0x2da4 605 #define MGA_WR42 0x2da8 606 #define MGA_WR43 0x2dac 607 #define MGA_WR44 0x2db0 608 #define MGA_WR45 0x2db4 609 #define MGA_WR46 0x2db8 610 #define MGA_WR47 0x2dbc 611 #define MGA_WR48 0x2dc0 612 #define MGA_WR49 0x2dc4 613 #define MGA_WR50 0x2dc8 614 #define MGA_WR51 0x2dcc 615 #define MGA_WR52 0x2dd0 616 #define MGA_WR53 0x2dd4 617 #define MGA_WR54 0x2dd8 618 #define MGA_WR55 0x2ddc 619 #define MGA_WR56 0x2de0 620 #define MGA_WR57 0x2de4 621 #define MGA_WR58 0x2de8 622 #define MGA_WR59 0x2dec 623 #define MGA_WR60 0x2df0 624 #define MGA_WR61 0x2df4 625 #define MGA_WR62 0x2df8 626 #define MGA_WR63 0x2dfc 627 # define MGA_G400_WR_MAGIC (1 << 6) 628 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 629 630 #define MGA_ILOAD_ALIGN 64 631 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 632 633 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 634 MGA_ATYPE_I | \ 635 MGA_ZMODE_NOZCMP | \ 636 MGA_ARZERO | \ 637 MGA_SGNZERO | \ 638 MGA_BOP_SRC | \ 639 (15 << MGA_TRANS_SHIFT)) 640 641 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 642 MGA_ZMODE_NOZCMP | \ 643 MGA_SOLID | \ 644 MGA_ARZERO | \ 645 MGA_SGNZERO | \ 646 MGA_SHIFTZERO | \ 647 MGA_BOP_SRC | \ 648 (0 << MGA_TRANS_SHIFT) | \ 649 MGA_BLTMOD_BMONOLEF | \ 650 MGA_TRANSC | \ 651 MGA_CLIPDIS) 652 653 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 654 MGA_ATYPE_RPL | \ 655 MGA_SGNZERO | \ 656 MGA_SHIFTZERO | \ 657 MGA_BOP_SRC | \ 658 (0 << MGA_TRANS_SHIFT) | \ 659 MGA_BLTMOD_BFCOL | \ 660 MGA_CLIPDIS) 661 662 /* Simple idle test. 663 */ 664 static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv) 665 { 666 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 667 return (status == MGA_ENDPRDMASTS); 668 } 669 670 #endif 671
Indexes created Sun Oct 19 02:09:48 GMT 2025