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disp.h revision 1.1.1.1.30.1 
      1 /*	$NetBSD: disp.h,v 1.1.1.1.30.1 2018/09/06 06:56:23 pgoyette Exp $	*/
      2 
      3 #ifndef __NV04_DISPLAY_H__
      4 #define __NV04_DISPLAY_H__
      5 
      6 #include <subdev/bios/pll.h>
      7 
      8 #include "nouveau_display.h"
      9 
     10 enum nv04_fp_display_regs {
     11 	FP_DISPLAY_END,
     12 	FP_TOTAL,
     13 	FP_CRTC,
     14 	FP_SYNC_START,
     15 	FP_SYNC_END,
     16 	FP_VALID_START,
     17 	FP_VALID_END
     18 };
     19 
     20 struct nv04_crtc_reg {
     21 	unsigned char MiscOutReg;
     22 	uint8_t CRTC[0xa0];
     23 	uint8_t CR58[0x10];
     24 	uint8_t Sequencer[5];
     25 	uint8_t Graphics[9];
     26 	uint8_t Attribute[21];
     27 	unsigned char DAC[768];
     28 
     29 	/* PCRTC regs */
     30 	uint32_t fb_start;
     31 	uint32_t crtc_cfg;
     32 	uint32_t cursor_cfg;
     33 	uint32_t gpio_ext;
     34 	uint32_t crtc_830;
     35 	uint32_t crtc_834;
     36 	uint32_t crtc_850;
     37 	uint32_t crtc_eng_ctrl;
     38 
     39 	/* PRAMDAC regs */
     40 	uint32_t nv10_cursync;
     41 	struct nvkm_pll_vals pllvals;
     42 	uint32_t ramdac_gen_ctrl;
     43 	uint32_t ramdac_630;
     44 	uint32_t ramdac_634;
     45 	uint32_t tv_setup;
     46 	uint32_t tv_vtotal;
     47 	uint32_t tv_vskew;
     48 	uint32_t tv_vsync_delay;
     49 	uint32_t tv_htotal;
     50 	uint32_t tv_hskew;
     51 	uint32_t tv_hsync_delay;
     52 	uint32_t tv_hsync_delay2;
     53 	uint32_t fp_horiz_regs[7];
     54 	uint32_t fp_vert_regs[7];
     55 	uint32_t dither;
     56 	uint32_t fp_control;
     57 	uint32_t dither_regs[6];
     58 	uint32_t fp_debug_0;
     59 	uint32_t fp_debug_1;
     60 	uint32_t fp_debug_2;
     61 	uint32_t fp_margin_color;
     62 	uint32_t ramdac_8c0;
     63 	uint32_t ramdac_a20;
     64 	uint32_t ramdac_a24;
     65 	uint32_t ramdac_a34;
     66 	uint32_t ctv_regs[38];
     67 };
     68 
     69 struct nv04_output_reg {
     70 	uint32_t output;
     71 	int head;
     72 };
     73 
     74 struct nv04_mode_state {
     75 	struct nv04_crtc_reg crtc_reg[2];
     76 	uint32_t pllsel;
     77 	uint32_t sel_clk;
     78 };
     79 
     80 struct nv04_display {
     81 	struct nv04_mode_state mode_reg;
     82 	struct nv04_mode_state saved_reg;
     83 	uint32_t saved_vga_font[4][16384];
     84 	uint32_t dac_users[4];
     85 	struct nouveau_bo *image[2];
     86 };
     87 
     88 static inline struct nv04_display *
     89 nv04_display(struct drm_device *dev)
     90 {
     91 	return nouveau_display(dev)->priv;
     92 }
     93 
     94 /* nv04_display.c */
     95 int nv04_display_create(struct drm_device *);
     96 void nv04_display_destroy(struct drm_device *);
     97 int nv04_display_init(struct drm_device *);
     98 void nv04_display_fini(struct drm_device *);
     99 
    100 /* nv04_crtc.c */
    101 int nv04_crtc_create(struct drm_device *, int index);
    102 
    103 /* nv04_dac.c */
    104 int nv04_dac_create(struct drm_connector *, struct dcb_output *);
    105 uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
    106 int nv04_dac_output_offset(struct drm_encoder *encoder);
    107 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
    108 bool nv04_dac_in_use(struct drm_encoder *encoder);
    109 
    110 /* nv04_dfp.c */
    111 int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
    112 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
    113 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
    114 			       int head, bool dl);
    115 void nv04_dfp_disable(struct drm_device *dev, int head);
    116 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
    117 
    118 /* nv04_tv.c */
    119 int nv04_tv_identify(struct drm_device *dev, int i2c_index);
    120 int nv04_tv_create(struct drm_connector *, struct dcb_output *);
    121 
    122 /* nv17_tv.c */
    123 int nv17_tv_create(struct drm_connector *, struct dcb_output *);
    124 
    125 /* overlay.c */
    126 void nouveau_overlay_init(struct drm_device *dev);
    127 
    128 static inline bool
    129 nv_two_heads(struct drm_device *dev)
    130 {
    131 	struct nouveau_drm *drm = nouveau_drm(dev);
    132 	const int impl = dev->pdev->device & 0x0ff0;
    133 
    134 	if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
    135 	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
    136 		return true;
    137 
    138 	return false;
    139 }
    140 
    141 static inline bool
    142 nv_gf4_disp_arch(struct drm_device *dev)
    143 {
    144 	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
    145 }
    146 
    147 static inline bool
    148 nv_two_reg_pll(struct drm_device *dev)
    149 {
    150 	struct nouveau_drm *drm = nouveau_drm(dev);
    151 	const int impl = dev->pdev->device & 0x0ff0;
    152 
    153 	if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE)
    154 		return true;
    155 	return false;
    156 }
    157 
    158 static inline bool
    159 nv_match_device(struct drm_device *dev, unsigned device,
    160 		unsigned sub_vendor, unsigned sub_device)
    161 {
    162 	return dev->pdev->device == device &&
    163 		dev->pdev->subsystem_vendor == sub_vendor &&
    164 		dev->pdev->subsystem_device == sub_device;
    165 }
    166 
    167 #include <subdev/bios.h>
    168 #include <subdev/bios/init.h>
    169 
    170 static inline void
    171 nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
    172 			    struct dcb_output *outp, int crtc)
    173 {
    174 	struct nouveau_drm *drm = nouveau_drm(dev);
    175 	struct nvkm_bios *bios = nvxx_bios(&drm->device);
    176 	struct nvbios_init init = {
    177 		.subdev = &bios->subdev,
    178 		.bios = bios,
    179 		.offset = table,
    180 		.outp = outp,
    181 		.crtc = crtc,
    182 		.execute = 1,
    183 	};
    184 
    185 	nvbios_exec(&init);
    186 }
    187 
    188 #endif
    189