1 1.1 riastrad /* $NetBSD: cl5070.h,v 1.2 2021/12/18 23:45:33 riastradh Exp $ */ 2 1.1 riastrad 3 1.1 riastrad /* SPDX-License-Identifier: MIT */ 4 1.1 riastrad #ifndef __NVIF_CL5070_H__ 5 1.1 riastrad #define __NVIF_CL5070_H__ 6 1.1 riastrad 7 1.1 riastrad #define NV50_DISP_MTHD 0x00 8 1.1 riastrad 9 1.1 riastrad struct nv50_disp_mthd_v0 { 10 1.1 riastrad __u8 version; 11 1.1 riastrad #define NV50_DISP_SCANOUTPOS 0x00 12 1.1 riastrad __u8 method; 13 1.1 riastrad __u8 head; 14 1.1 riastrad __u8 pad03[5]; 15 1.1 riastrad }; 16 1.1 riastrad 17 1.1 riastrad struct nv50_disp_scanoutpos_v0 { 18 1.1 riastrad __u8 version; 19 1.1 riastrad __u8 pad01[7]; 20 1.1 riastrad __s64 time[2]; 21 1.1 riastrad __u16 vblanks; 22 1.1 riastrad __u16 vblanke; 23 1.1 riastrad __u16 vtotal; 24 1.1 riastrad __u16 vline; 25 1.1 riastrad __u16 hblanks; 26 1.1 riastrad __u16 hblanke; 27 1.1 riastrad __u16 htotal; 28 1.1 riastrad __u16 hline; 29 1.1 riastrad }; 30 1.1 riastrad 31 1.1 riastrad struct nv50_disp_mthd_v1 { 32 1.1 riastrad __u8 version; 33 1.1 riastrad #define NV50_DISP_MTHD_V1_ACQUIRE 0x01 34 1.1 riastrad #define NV50_DISP_MTHD_V1_RELEASE 0x02 35 1.1 riastrad #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 36 1.1 riastrad #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 37 1.1 riastrad #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 38 1.1 riastrad #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 39 1.1 riastrad #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK 0x25 40 1.1 riastrad #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI 0x26 41 1.1 riastrad __u8 method; 42 1.1 riastrad __u16 hasht; 43 1.1 riastrad __u16 hashm; 44 1.1 riastrad __u8 pad06[2]; 45 1.1 riastrad }; 46 1.1 riastrad 47 1.1 riastrad struct nv50_disp_acquire_v0 { 48 1.1 riastrad __u8 version; 49 1.1 riastrad __u8 or; 50 1.1 riastrad __u8 link; 51 1.1 riastrad __u8 pad03[5]; 52 1.1 riastrad }; 53 1.1 riastrad 54 1.1 riastrad struct nv50_disp_dac_load_v0 { 55 1.1 riastrad __u8 version; 56 1.1 riastrad __u8 load; 57 1.1 riastrad __u8 pad02[2]; 58 1.1 riastrad __u32 data; 59 1.1 riastrad }; 60 1.1 riastrad 61 1.1 riastrad struct nv50_disp_sor_hda_eld_v0 { 62 1.1 riastrad __u8 version; 63 1.1 riastrad __u8 pad01[7]; 64 1.1 riastrad __u8 data[]; 65 1.1 riastrad }; 66 1.1 riastrad 67 1.1 riastrad struct nv50_disp_sor_hdmi_pwr_v0 { 68 1.1 riastrad __u8 version; 69 1.1 riastrad __u8 state; 70 1.1 riastrad __u8 max_ac_packet; 71 1.1 riastrad __u8 rekey; 72 1.1 riastrad __u8 avi_infoframe_length; 73 1.1 riastrad __u8 vendor_infoframe_length; 74 1.1 riastrad #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0) 75 1.1 riastrad #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1) 76 1.1 riastrad __u8 scdc; 77 1.1 riastrad __u8 pad07[1]; 78 1.1 riastrad }; 79 1.1 riastrad 80 1.1 riastrad struct nv50_disp_sor_lvds_script_v0 { 81 1.1 riastrad __u8 version; 82 1.1 riastrad __u8 pad01[1]; 83 1.1 riastrad __u16 script; 84 1.1 riastrad __u8 pad04[4]; 85 1.1 riastrad }; 86 1.1 riastrad 87 1.1 riastrad struct nv50_disp_sor_dp_mst_link_v0 { 88 1.1 riastrad __u8 version; 89 1.1 riastrad __u8 state; 90 1.1 riastrad __u8 pad02[6]; 91 1.1 riastrad }; 92 1.1 riastrad 93 1.1 riastrad struct nv50_disp_sor_dp_mst_vcpi_v0 { 94 1.1 riastrad __u8 version; 95 1.1 riastrad __u8 pad01[1]; 96 1.1 riastrad __u8 start_slot; 97 1.1 riastrad __u8 num_slots; 98 1.1 riastrad __u16 pbn; 99 1.1 riastrad __u16 aligned_pbn; 100 1.1 riastrad }; 101 1.1 riastrad #endif 102
Indexes created Wed Oct 01 19:09:53 GMT 2025