nouveau_dma.h revision 1.1.1.1.30.1
1 /* $NetBSD: nouveau_dma.h,v 1.1.1.1.30.1 2018/09/06 06:56:18 pgoyette Exp $ */ 2 3 /* 4 * Copyright (C) 2007 Ben Skeggs. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sublicense, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #ifndef __NOUVEAU_DMA_H__ 30 #define __NOUVEAU_DMA_H__ 31 32 #include "nouveau_bo.h" 33 #include "nouveau_chan.h" 34 35 int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 36 void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, 37 int delta, int length); 38 39 /* 40 * There's a hw race condition where you can't jump to your PUT offset, 41 * to avoid this we jump to offset + SKIPS and fill the difference with 42 * NOPs. 43 * 44 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses 45 * a SKIPS value of 8. Lets assume that the race condition is to do 46 * with writing into the fetch area, we configure a fetch size of 128 47 * bytes so we need a larger SKIPS value. 48 */ 49 #define NOUVEAU_DMA_SKIPS (128 / 4) 50 51 /* Hardcoded object assignments to subchannels (subchannel id). */ 52 enum { 53 NvSubCtxSurf2D = 0, 54 NvSubSw = 1, 55 NvSubImageBlit = 2, 56 NvSubGdiRect = 3, 57 58 NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ 59 NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ 60 FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ 61 }; 62 63 /* Object handles - for stuff that's doesn't use handle == oclass. */ 64 enum { 65 NvDmaFB = 0x80000002, 66 NvDmaTT = 0x80000003, 67 NvNotify0 = 0x80000006, 68 NvSema = 0x8000000f, 69 NvEvoSema0 = 0x80000010, 70 NvEvoSema1 = 0x80000011, 71 }; 72 73 #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 74 #define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 75 #define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 76 #define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 77 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 78 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 79 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 80 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 81 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 82 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c 83 84 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 85 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 86 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c 87 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 88 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c 89 90 static __must_check inline int 91 RING_SPACE(struct nouveau_channel *chan, int size) 92 { 93 int ret; 94 95 ret = nouveau_dma_wait(chan, 1, size); 96 if (ret) 97 return ret; 98 99 chan->dma.free -= size; 100 return 0; 101 } 102 103 static inline void 104 OUT_RING(struct nouveau_channel *chan, int data) 105 { 106 nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); 107 } 108 109 extern void 110 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); 111 112 static inline void 113 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) 114 { 115 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); 116 } 117 118 static inline void 119 BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) 120 { 121 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); 122 } 123 124 static inline void 125 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) 126 { 127 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); 128 } 129 130 static inline void 131 BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) 132 { 133 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); 134 } 135 136 static inline void 137 BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) 138 { 139 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); 140 } 141 142 #define WRITE_PUT(val) do { \ 143 mb(); \ 144 nouveau_bo_rd32(chan->push.buffer, 0); \ 145 nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.vma.offset); \ 146 } while (0) 147 148 static inline void 149 FIRE_RING(struct nouveau_channel *chan) 150 { 151 if (chan->dma.cur == chan->dma.put) 152 return; 153 chan->accel_done = true; 154 155 if (chan->dma.ib_max) { 156 nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2, 157 (chan->dma.cur - chan->dma.put) << 2); 158 } else { 159 WRITE_PUT(chan->dma.cur); 160 } 161 162 chan->dma.put = chan->dma.cur; 163 } 164 165 static inline void 166 WIND_RING(struct nouveau_channel *chan) 167 { 168 chan->dma.cur = chan->dma.put; 169 } 170 171 /* FIFO methods */ 172 #define NV01_SUBCHAN_OBJECT 0x00000000 173 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 174 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 175 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 176 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c 177 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 178 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 179 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 180 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 181 #define NV84_SUBCHAN_UEVENT 0x00000020 182 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 183 #define NV10_SUBCHAN_REF_CNT 0x00000050 184 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 185 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 186 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 187 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c 188 #define NV40_SUBCHAN_YIELD 0x00000080 189 190 /* NV_SW object class */ 191 #define NV_SW_DMA_VBLSEM 0x0000018c 192 #define NV_SW_VBLSEM_OFFSET 0x00000400 193 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 194 #define NV_SW_VBLSEM_RELEASE 0x00000408 195 #define NV_SW_PAGE_FLIP 0x00000500 196 197 #endif 198
Indexes created Wed Oct 22 06:10:02 GMT 2025