nouveau_dma.h revision 1.1.1.1.6.2
1 /* 2 * Copyright (C) 2007 Ben Skeggs. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef __NOUVEAU_DMA_H__ 28 #define __NOUVEAU_DMA_H__ 29 30 #include "nouveau_bo.h" 31 #include "nouveau_chan.h" 32 33 int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 34 void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, 35 int delta, int length); 36 37 /* 38 * There's a hw race condition where you can't jump to your PUT offset, 39 * to avoid this we jump to offset + SKIPS and fill the difference with 40 * NOPs. 41 * 42 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses 43 * a SKIPS value of 8. Lets assume that the race condition is to do 44 * with writing into the fetch area, we configure a fetch size of 128 45 * bytes so we need a larger SKIPS value. 46 */ 47 #define NOUVEAU_DMA_SKIPS (128 / 4) 48 49 /* Hardcoded object assignments to subchannels (subchannel id). */ 50 enum { 51 NvSubCtxSurf2D = 0, 52 NvSubSw = 1, 53 NvSubImageBlit = 2, 54 NvSubGdiRect = 3, 55 56 NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ 57 NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ 58 FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ 59 }; 60 61 /* Object handles. */ 62 enum { 63 NvM2MF = 0x80000001, 64 NvDmaFB = 0x80000002, 65 NvDmaTT = 0x80000003, 66 NvNotify0 = 0x80000006, 67 Nv2D = 0x80000007, 68 NvCtxSurf2D = 0x80000008, 69 NvRop = 0x80000009, 70 NvImagePatt = 0x8000000a, 71 NvClipRect = 0x8000000b, 72 NvGdiRect = 0x8000000c, 73 NvImageBlit = 0x8000000d, 74 NvSw = 0x8000000e, 75 NvSema = 0x8000000f, 76 NvEvoSema0 = 0x80000010, 77 NvEvoSema1 = 0x80000011, 78 NvNotify1 = 0x80000012, 79 80 /* G80+ display objects */ 81 NvEvoVRAM = 0x01000000, 82 NvEvoFB16 = 0x01000001, 83 NvEvoFB32 = 0x01000002, 84 NvEvoVRAM_LP = 0x01000003, 85 NvEvoSync = 0xcafe0000 86 }; 87 88 #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 89 #define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 90 #define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 91 #define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 92 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 93 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 94 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 95 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 96 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 97 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c 98 99 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 100 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 101 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c 102 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 103 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c 104 105 static __must_check inline int 106 RING_SPACE(struct nouveau_channel *chan, int size) 107 { 108 int ret; 109 110 ret = nouveau_dma_wait(chan, 1, size); 111 if (ret) 112 return ret; 113 114 chan->dma.free -= size; 115 return 0; 116 } 117 118 static inline void 119 OUT_RING(struct nouveau_channel *chan, int data) 120 { 121 nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); 122 } 123 124 extern void 125 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); 126 127 static inline void 128 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) 129 { 130 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); 131 } 132 133 static inline void 134 BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) 135 { 136 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); 137 } 138 139 static inline void 140 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) 141 { 142 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); 143 } 144 145 static inline void 146 BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) 147 { 148 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); 149 } 150 151 static inline void 152 BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) 153 { 154 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); 155 } 156 157 #define WRITE_PUT(val) do { \ 158 mb(); \ 159 nouveau_bo_rd32(chan->push.buffer, 0); \ 160 nv_wo32(chan->object, chan->user_put, ((val) << 2) + chan->push.vma.offset); \ 161 } while (0) 162 163 static inline void 164 FIRE_RING(struct nouveau_channel *chan) 165 { 166 if (chan->dma.cur == chan->dma.put) 167 return; 168 chan->accel_done = true; 169 170 if (chan->dma.ib_max) { 171 nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2, 172 (chan->dma.cur - chan->dma.put) << 2); 173 } else { 174 WRITE_PUT(chan->dma.cur); 175 } 176 177 chan->dma.put = chan->dma.cur; 178 } 179 180 static inline void 181 WIND_RING(struct nouveau_channel *chan) 182 { 183 chan->dma.cur = chan->dma.put; 184 } 185 186 /* FIFO methods */ 187 #define NV01_SUBCHAN_OBJECT 0x00000000 188 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 189 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 190 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 191 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c 192 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 193 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 194 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 195 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 196 #define NV84_SUBCHAN_UEVENT 0x00000020 197 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 198 #define NV10_SUBCHAN_REF_CNT 0x00000050 199 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 200 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 201 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 202 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c 203 #define NV40_SUBCHAN_YIELD 0x00000080 204 205 /* NV_SW object class */ 206 #define NV_SW_DMA_VBLSEM 0x0000018c 207 #define NV_SW_VBLSEM_OFFSET 0x00000400 208 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 209 #define NV_SW_VBLSEM_RELEASE 0x00000408 210 #define NV_SW_PAGE_FLIP 0x00000500 211 212 #endif 213
Indexes created Wed Oct 22 13:09:56 GMT 2025