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nouveau_nv50_fence.c revision 1.1.1.1.32.1 
      1 /*	$NetBSD: nouveau_nv50_fence.c,v 1.1.1.1.32.1 2019/06/10 22:08:06 christos Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs <bskeggs (at) redhat.com>
     25  */
     26 
     27 #include <sys/cdefs.h>
     28 __KERNEL_RCSID(0, "$NetBSD: nouveau_nv50_fence.c,v 1.1.1.1.32.1 2019/06/10 22:08:06 christos Exp $");
     29 
     30 #include <nvif/os.h>
     31 #include <nvif/class.h>
     32 
     33 #include "nouveau_drm.h"
     34 #include "nouveau_dma.h"
     35 #include "nv10_fence.h"
     36 
     37 #include "nv50_display.h"
     38 
     39 static int
     40 nv50_fence_context_new(struct nouveau_channel *chan)
     41 {
     42 	struct drm_device *dev = chan->drm->dev;
     43 	struct nv10_fence_priv *priv = chan->drm->fence;
     44 	struct nv10_fence_chan *fctx;
     45 	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
     46 	u32 start = mem->start * PAGE_SIZE;
     47 	u32 limit = start + mem->size - 1;
     48 	int ret, i;
     49 
     50 	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
     51 	if (!fctx)
     52 		return -ENOMEM;
     53 
     54 	nouveau_fence_context_new(chan, &fctx->base);
     55 	fctx->base.emit = nv10_fence_emit;
     56 	fctx->base.read = nv10_fence_read;
     57 	fctx->base.sync = nv17_fence_sync;
     58 
     59 	ret = nvif_object_init(&chan->user, NvSema, NV_DMA_IN_MEMORY,
     60 			       &(struct nv_dma_v0) {
     61 					.target = NV_DMA_V0_TARGET_VRAM,
     62 					.access = NV_DMA_V0_ACCESS_RDWR,
     63 					.start = start,
     64 					.limit = limit,
     65 			       }, sizeof(struct nv_dma_v0),
     66 			       &fctx->sema);
     67 
     68 	/* dma objects for display sync channel semaphore blocks */
     69 	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
     70 		struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
     71 		u32 start = bo->bo.mem.start * PAGE_SIZE;
     72 		u32 limit = start + bo->bo.mem.size - 1;
     73 
     74 		ret = nvif_object_init(&chan->user, NvEvoSema0 + i,
     75 				       NV_DMA_IN_MEMORY, &(struct nv_dma_v0) {
     76 						.target = NV_DMA_V0_TARGET_VRAM,
     77 						.access = NV_DMA_V0_ACCESS_RDWR,
     78 						.start = start,
     79 						.limit = limit,
     80 				       }, sizeof(struct nv_dma_v0),
     81 				       &fctx->head[i]);
     82 	}
     83 
     84 	if (ret)
     85 		nv10_fence_context_del(chan);
     86 	return ret;
     87 }
     88 
     89 int
     90 nv50_fence_create(struct nouveau_drm *drm)
     91 {
     92 	struct nv10_fence_priv *priv;
     93 	int ret = 0;
     94 
     95 	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
     96 	if (!priv)
     97 		return -ENOMEM;
     98 
     99 	priv->base.dtor = nv10_fence_destroy;
    100 	priv->base.resume = nv17_fence_resume;
    101 	priv->base.context_new = nv50_fence_context_new;
    102 	priv->base.context_del = nv10_fence_context_del;
    103 	priv->base.contexts = 127;
    104 	priv->base.context_base = fence_context_alloc(priv->base.contexts);
    105 	spin_lock_init(&priv->lock);
    106 
    107 	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
    108 			     0, 0x0000, NULL, NULL, &priv->bo);
    109 	if (!ret) {
    110 		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
    111 		if (!ret) {
    112 			ret = nouveau_bo_map(priv->bo);
    113 			if (ret)
    114 				nouveau_bo_unpin(priv->bo);
    115 		}
    116 		if (ret)
    117 			nouveau_bo_ref(NULL, &priv->bo);
    118 	}
    119 
    120 	if (ret) {
    121 		nv10_fence_destroy(drm);
    122 		return ret;
    123 	}
    124 
    125 	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
    126 	return ret;
    127 }
    128