ci_dpm.h revision 1.1.1.1.32.1
1 /* $NetBSD: ci_dpm.h,v 1.1.1.1.32.1 2019/06/10 22:08:25 christos Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __CI_DPM_H__ 26 #define __CI_DPM_H__ 27 28 #include "ppsmc.h" 29 30 #define SMU__NUM_SCLK_DPM_STATE 8 31 #define SMU__NUM_MCLK_DPM_LEVELS 6 32 #define SMU__NUM_LCLK_DPM_LEVELS 8 33 #define SMU__NUM_PCIE_DPM_LEVELS 8 34 #include "smu7_discrete.h" 35 36 #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 37 38 #define CISLANDS_UNUSED_GPIO_PIN 0x7F 39 40 struct ci_pl { 41 u32 mclk; 42 u32 sclk; 43 enum radeon_pcie_gen pcie_gen; 44 u16 pcie_lane; 45 }; 46 47 struct ci_ps { 48 u16 performance_level_count; 49 bool dc_compatible; 50 u32 sclk_t; 51 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; 52 }; 53 54 struct ci_dpm_level { 55 bool enabled; 56 u32 value; 57 u32 param1; 58 }; 59 60 #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5 61 #define MAX_REGULAR_DPM_NUMBER 8 62 #define CISLAND_MINIMUM_ENGINE_CLOCK 800 63 64 struct ci_single_dpm_table { 65 u32 count; 66 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 67 }; 68 69 struct ci_dpm_table { 70 struct ci_single_dpm_table sclk_table; 71 struct ci_single_dpm_table mclk_table; 72 struct ci_single_dpm_table pcie_speed_table; 73 struct ci_single_dpm_table vddc_table; 74 struct ci_single_dpm_table vddci_table; 75 struct ci_single_dpm_table mvdd_table; 76 }; 77 78 struct ci_mc_reg_entry { 79 u32 mclk_max; 80 u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 81 }; 82 83 struct ci_mc_reg_table { 84 u8 last; 85 u8 num_entries; 86 u16 valid_flag; 87 struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 88 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 89 }; 90 91 struct ci_ulv_parm 92 { 93 bool supported; 94 u32 cg_ulv_parameter; 95 u32 volt_change_delay; 96 struct ci_pl pl; 97 }; 98 99 #define CISLANDS_MAX_LEAKAGE_COUNT 8 100 101 struct ci_leakage_voltage { 102 u16 count; 103 u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT]; 104 u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT]; 105 }; 106 107 struct ci_dpm_level_enable_mask { 108 u32 uvd_dpm_enable_mask; 109 u32 vce_dpm_enable_mask; 110 u32 acp_dpm_enable_mask; 111 u32 samu_dpm_enable_mask; 112 u32 sclk_dpm_enable_mask; 113 u32 mclk_dpm_enable_mask; 114 u32 pcie_dpm_enable_mask; 115 }; 116 117 struct ci_vbios_boot_state 118 { 119 u16 mvdd_bootup_value; 120 u16 vddc_bootup_value; 121 u16 vddci_bootup_value; 122 u32 sclk_bootup_value; 123 u32 mclk_bootup_value; 124 u16 pcie_gen_bootup_value; 125 u16 pcie_lane_bootup_value; 126 }; 127 128 struct ci_clock_registers { 129 u32 cg_spll_func_cntl; 130 u32 cg_spll_func_cntl_2; 131 u32 cg_spll_func_cntl_3; 132 u32 cg_spll_func_cntl_4; 133 u32 cg_spll_spread_spectrum; 134 u32 cg_spll_spread_spectrum_2; 135 u32 dll_cntl; 136 u32 mclk_pwrmgt_cntl; 137 u32 mpll_ad_func_cntl; 138 u32 mpll_dq_func_cntl; 139 u32 mpll_func_cntl; 140 u32 mpll_func_cntl_1; 141 u32 mpll_func_cntl_2; 142 u32 mpll_ss1; 143 u32 mpll_ss2; 144 }; 145 146 struct ci_thermal_temperature_setting { 147 s32 temperature_low; 148 s32 temperature_high; 149 s32 temperature_shutdown; 150 }; 151 152 struct ci_pcie_perf_range { 153 u16 max; 154 u16 min; 155 }; 156 157 enum ci_pt_config_reg_type { 158 CISLANDS_CONFIGREG_MMR = 0, 159 CISLANDS_CONFIGREG_SMC_IND, 160 CISLANDS_CONFIGREG_DIDT_IND, 161 CISLANDS_CONFIGREG_CACHE, 162 CISLANDS_CONFIGREG_MAX 163 }; 164 165 #define POWERCONTAINMENT_FEATURE_BAPM 0x00000001 166 #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 167 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 168 169 struct ci_pt_config_reg { 170 u32 offset; 171 u32 mask; 172 u32 shift; 173 u32 value; 174 enum ci_pt_config_reg_type type; 175 }; 176 177 struct ci_pt_defaults { 178 u8 svi_load_line_en; 179 u8 svi_load_line_vddc; 180 u8 tdc_vddc_throttle_release_limit_perc; 181 u8 tdc_mawt; 182 u8 tdc_waterfall_ctl; 183 u8 dte_ambient_temp_base; 184 u32 display_cac; 185 u32 bapm_temp_gradient; 186 u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 187 u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 188 }; 189 190 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 191 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 192 #define DPMTABLE_UPDATE_SCLK 0x00000004 193 #define DPMTABLE_UPDATE_MCLK 0x00000008 194 195 struct ci_power_info { 196 struct ci_dpm_table dpm_table; 197 u32 voltage_control; 198 u32 mvdd_control; 199 u32 vddci_control; 200 u32 active_auto_throttle_sources; 201 struct ci_clock_registers clock_registers; 202 u16 acpi_vddc; 203 u16 acpi_vddci; 204 enum radeon_pcie_gen force_pcie_gen; 205 enum radeon_pcie_gen acpi_pcie_gen; 206 struct ci_leakage_voltage vddc_leakage; 207 struct ci_leakage_voltage vddci_leakage; 208 u16 max_vddc_in_pp_table; 209 u16 min_vddc_in_pp_table; 210 u16 max_vddci_in_pp_table; 211 u16 min_vddci_in_pp_table; 212 u32 mclk_strobe_mode_threshold; 213 u32 mclk_stutter_mode_threshold; 214 u32 mclk_edc_enable_threshold; 215 u32 mclk_edc_wr_enable_threshold; 216 struct ci_vbios_boot_state vbios_boot_state; 217 /* smc offsets */ 218 u32 sram_end; 219 u32 dpm_table_start; 220 u32 soft_regs_start; 221 u32 mc_reg_table_start; 222 u32 fan_table_start; 223 u32 arb_table_start; 224 /* smc tables */ 225 SMU7_Discrete_DpmTable smc_state_table; 226 SMU7_Discrete_MCRegisters smc_mc_reg_table; 227 SMU7_Discrete_PmFuses smc_powertune_table; 228 /* other stuff */ 229 struct ci_mc_reg_table mc_reg_table; 230 struct atom_voltage_table vddc_voltage_table; 231 struct atom_voltage_table vddci_voltage_table; 232 struct atom_voltage_table mvdd_voltage_table; 233 struct ci_ulv_parm ulv; 234 u32 power_containment_features; 235 const struct ci_pt_defaults *powertune_defaults; 236 u32 dte_tj_offset; 237 bool vddc_phase_shed_control; 238 struct ci_thermal_temperature_setting thermal_temp_setting; 239 struct ci_dpm_level_enable_mask dpm_level_enable_mask; 240 u32 need_update_smu7_dpm_table; 241 u32 sclk_dpm_key_disabled; 242 u32 mclk_dpm_key_disabled; 243 u32 pcie_dpm_key_disabled; 244 u32 thermal_sclk_dpm_enabled; 245 struct ci_pcie_perf_range pcie_gen_performance; 246 struct ci_pcie_perf_range pcie_lane_performance; 247 struct ci_pcie_perf_range pcie_gen_powersaving; 248 struct ci_pcie_perf_range pcie_lane_powersaving; 249 u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; 250 u32 mclk_activity_target; 251 u32 low_sclk_interrupt_t; 252 u32 last_mclk_dpm_enable_mask; 253 u32 sys_pcie_mask; 254 /* caps */ 255 bool caps_power_containment; 256 bool caps_cac; 257 bool caps_sq_ramping; 258 bool caps_db_ramping; 259 bool caps_td_ramping; 260 bool caps_tcp_ramping; 261 bool caps_fps; 262 bool caps_sclk_ds; 263 bool caps_sclk_ss_support; 264 bool caps_mclk_ss_support; 265 bool caps_uvd_dpm; 266 bool caps_vce_dpm; 267 bool caps_samu_dpm; 268 bool caps_acp_dpm; 269 bool caps_automatic_dc_transition; 270 bool caps_sclk_throttle_low_notification; 271 bool caps_dynamic_ac_timing; 272 bool caps_od_fuzzy_fan_control_support; 273 /* flags */ 274 bool thermal_protection; 275 bool pcie_performance_request; 276 bool dynamic_ss; 277 bool dll_default_on; 278 bool cac_enabled; 279 bool uvd_enabled; 280 bool battery_state; 281 bool pspp_notify_required; 282 bool mem_gddr5; 283 bool enable_bapm_feature; 284 bool enable_tdc_limit_feature; 285 bool enable_pkg_pwr_tracking_feature; 286 bool use_pcie_performance_levels; 287 bool use_pcie_powersaving_levels; 288 bool uvd_power_gated; 289 /* driver states */ 290 struct radeon_ps current_rps; 291 struct ci_ps current_ps; 292 struct radeon_ps requested_rps; 293 struct ci_ps requested_ps; 294 /* fan control */ 295 bool fan_ctrl_is_in_default_mode; 296 bool fan_is_controlled_by_smc; 297 u32 t_min; 298 u32 fan_ctrl_default_mode; 299 }; 300 301 #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 302 #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 303 #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2 304 305 #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256 306 307 #define CISLANDS_VRC_DFLT0 0x3FFFC000 308 #define CISLANDS_VRC_DFLT1 0x000400 309 #define CISLANDS_VRC_DFLT2 0xC00080 310 #define CISLANDS_VRC_DFLT3 0xC00200 311 #define CISLANDS_VRC_DFLT4 0xC01680 312 #define CISLANDS_VRC_DFLT5 0xC00033 313 #define CISLANDS_VRC_DFLT6 0xC00033 314 #define CISLANDS_VRC_DFLT7 0x3FFFC000 315 316 #define CISLANDS_CGULVPARAMETER_DFLT 0x00040035 317 #define CISLAND_TARGETACTIVITY_DFLT 30 318 #define CISLAND_MCLK_TARGETACTIVITY_DFLT 10 319 320 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 321 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 322 #define PCIE_PERF_REQ_PECI_GEN1 2 323 #define PCIE_PERF_REQ_PECI_GEN2 3 324 #define PCIE_PERF_REQ_PECI_GEN3 4 325 326 int ci_copy_bytes_to_smc(struct radeon_device *rdev, 327 u32 smc_start_address, 328 const u8 *src, u32 byte_count, u32 limit); 329 void ci_start_smc(struct radeon_device *rdev); 330 void ci_reset_smc(struct radeon_device *rdev); 331 int ci_program_jump_on_start(struct radeon_device *rdev); 332 void ci_stop_smc_clock(struct radeon_device *rdev); 333 void ci_start_smc_clock(struct radeon_device *rdev); 334 bool ci_is_smc_running(struct radeon_device *rdev); 335 PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 336 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev); 337 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit); 338 int ci_read_smc_sram_dword(struct radeon_device *rdev, 339 u32 smc_address, u32 *value, u32 limit); 340 int ci_write_smc_sram_dword(struct radeon_device *rdev, 341 u32 smc_address, u32 value, u32 limit); 342 343 #endif 344
Indexes created Thu Oct 23 22:10:10 GMT 2025