r600d.h revision 1.1
1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* tiling bits */ 55 #define ARRAY_LINEAR_GENERAL 0x00000000 56 #define ARRAY_LINEAR_ALIGNED 0x00000001 57 #define ARRAY_1D_TILED_THIN1 0x00000002 58 #define ARRAY_2D_TILED_THIN1 0x00000004 59 60 /* Registers */ 61 #define ARB_POP 0x2418 62 #define ENABLE_TC128 (1 << 30) 63 #define ARB_GDEC_RD_CNTL 0x246C 64 65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 66 #define CC_RB_BACKEND_DISABLE 0x98F4 67 #define BACKEND_DISABLE(x) ((x) << 16) 68 69 #define R_028808_CB_COLOR_CONTROL 0x28808 70 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 71 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 72 #define C_028808_SPECIAL_OP 0xFFFFFF8F 73 #define V_028808_SPECIAL_NORMAL 0x00 74 #define V_028808_SPECIAL_DISABLE 0x01 75 #define V_028808_SPECIAL_RESOLVE_BOX 0x07 76 77 #define CB_COLOR0_BASE 0x28040 78 #define CB_COLOR1_BASE 0x28044 79 #define CB_COLOR2_BASE 0x28048 80 #define CB_COLOR3_BASE 0x2804C 81 #define CB_COLOR4_BASE 0x28050 82 #define CB_COLOR5_BASE 0x28054 83 #define CB_COLOR6_BASE 0x28058 84 #define CB_COLOR7_BASE 0x2805C 85 #define CB_COLOR7_FRAG 0x280FC 86 87 #define CB_COLOR0_SIZE 0x28060 88 #define CB_COLOR0_VIEW 0x28080 89 #define R_028080_CB_COLOR0_VIEW 0x028080 90 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 91 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 92 #define C_028080_SLICE_START 0xFFFFF800 93 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 94 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 95 #define C_028080_SLICE_MAX 0xFF001FFF 96 #define R_028084_CB_COLOR1_VIEW 0x028084 97 #define R_028088_CB_COLOR2_VIEW 0x028088 98 #define R_02808C_CB_COLOR3_VIEW 0x02808C 99 #define R_028090_CB_COLOR4_VIEW 0x028090 100 #define R_028094_CB_COLOR5_VIEW 0x028094 101 #define R_028098_CB_COLOR6_VIEW 0x028098 102 #define R_02809C_CB_COLOR7_VIEW 0x02809C 103 #define R_028100_CB_COLOR0_MASK 0x028100 104 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 105 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 106 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 107 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 108 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 109 #define C_028100_FMASK_TILE_MAX 0x00000FFF 110 #define R_028104_CB_COLOR1_MASK 0x028104 111 #define R_028108_CB_COLOR2_MASK 0x028108 112 #define R_02810C_CB_COLOR3_MASK 0x02810C 113 #define R_028110_CB_COLOR4_MASK 0x028110 114 #define R_028114_CB_COLOR5_MASK 0x028114 115 #define R_028118_CB_COLOR6_MASK 0x028118 116 #define R_02811C_CB_COLOR7_MASK 0x02811C 117 #define CB_COLOR0_INFO 0x280a0 118 # define CB_FORMAT(x) ((x) << 2) 119 # define CB_ARRAY_MODE(x) ((x) << 8) 120 # define CB_SOURCE_FORMAT(x) ((x) << 27) 121 # define CB_SF_EXPORT_FULL 0 122 # define CB_SF_EXPORT_NORM 1 123 #define CB_COLOR0_TILE 0x280c0 124 #define CB_COLOR0_FRAG 0x280e0 125 #define CB_COLOR0_MASK 0x28100 126 127 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 128 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 129 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 130 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 131 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 132 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 133 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 134 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 135 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 136 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 137 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 138 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 139 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 140 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 141 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 142 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 143 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 144 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 145 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 146 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 147 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 148 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 149 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 150 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 151 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 152 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 153 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 154 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 155 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 156 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 157 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 158 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 159 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 160 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 161 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 162 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 163 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 164 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 165 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 166 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 167 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 168 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 169 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 170 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 171 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 172 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 173 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 174 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 175 176 #define CONFIG_MEMSIZE 0x5428 177 #define CONFIG_CNTL 0x5424 178 #define CP_STALLED_STAT1 0x8674 179 #define CP_STALLED_STAT2 0x8678 180 #define CP_BUSY_STAT 0x867C 181 #define CP_STAT 0x8680 182 #define CP_COHER_BASE 0x85F8 183 #define CP_DEBUG 0xC1FC 184 #define R_0086D8_CP_ME_CNTL 0x86D8 185 #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) 186 #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) 187 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 188 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 189 #define CP_ME_RAM_DATA 0xC160 190 #define CP_ME_RAM_RADDR 0xC158 191 #define CP_ME_RAM_WADDR 0xC15C 192 #define CP_MEQ_THRESHOLDS 0x8764 193 #define MEQ_END(x) ((x) << 16) 194 #define ROQ_END(x) ((x) << 24) 195 #define CP_PERFMON_CNTL 0x87FC 196 #define CP_PFP_UCODE_ADDR 0xC150 197 #define CP_PFP_UCODE_DATA 0xC154 198 #define CP_QUEUE_THRESHOLDS 0x8760 199 #define ROQ_IB1_START(x) ((x) << 0) 200 #define ROQ_IB2_START(x) ((x) << 8) 201 #define CP_RB_BASE 0xC100 202 #define CP_RB_CNTL 0xC104 203 #define RB_BUFSZ(x) ((x) << 0) 204 #define RB_BLKSZ(x) ((x) << 8) 205 #define RB_NO_UPDATE (1 << 27) 206 #define RB_RPTR_WR_ENA (1 << 31) 207 #define BUF_SWAP_32BIT (2 << 16) 208 #define CP_RB_RPTR 0x8700 209 #define CP_RB_RPTR_ADDR 0xC10C 210 #define RB_RPTR_SWAP(x) ((x) << 0) 211 #define CP_RB_RPTR_ADDR_HI 0xC110 212 #define CP_RB_RPTR_WR 0xC108 213 #define CP_RB_WPTR 0xC114 214 #define CP_RB_WPTR_ADDR 0xC118 215 #define CP_RB_WPTR_ADDR_HI 0xC11C 216 #define CP_RB_WPTR_DELAY 0x8704 217 #define CP_ROQ_IB1_STAT 0x8784 218 #define CP_ROQ_IB2_STAT 0x8788 219 #define CP_SEM_WAIT_TIMER 0x85BC 220 221 #define DB_DEBUG 0x9830 222 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 223 #define DB_DEPTH_BASE 0x2800C 224 #define DB_HTILE_DATA_BASE 0x28014 225 #define DB_HTILE_SURFACE 0x28D24 226 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 227 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 228 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE 229 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 230 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 231 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 232 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 233 #define DB_WATERMARKS 0x9838 234 #define DEPTH_FREE(x) ((x) << 0) 235 #define DEPTH_FLUSH(x) ((x) << 5) 236 #define DEPTH_PENDING_FREE(x) ((x) << 15) 237 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 238 239 #define DCP_TILING_CONFIG 0x6CA0 240 #define PIPE_TILING(x) ((x) << 1) 241 #define BANK_TILING(x) ((x) << 4) 242 #define GROUP_SIZE(x) ((x) << 6) 243 #define ROW_TILING(x) ((x) << 8) 244 #define BANK_SWAPS(x) ((x) << 11) 245 #define SAMPLE_SPLIT(x) ((x) << 14) 246 #define BACKEND_MAP(x) ((x) << 16) 247 248 #define GB_TILING_CONFIG 0x98F0 249 #define PIPE_TILING__SHIFT 1 250 #define PIPE_TILING__MASK 0x0000000e 251 252 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 253 #define INACTIVE_QD_PIPES(x) ((x) << 8) 254 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 255 #define INACTIVE_SIMDS(x) ((x) << 16) 256 #define INACTIVE_SIMDS_MASK 0x00FF0000 257 258 #define SQ_CONFIG 0x8c00 259 # define VC_ENABLE (1 << 0) 260 # define EXPORT_SRC_C (1 << 1) 261 # define DX9_CONSTS (1 << 2) 262 # define ALU_INST_PREFER_VECTOR (1 << 3) 263 # define DX10_CLAMP (1 << 4) 264 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 265 # define PS_PRIO(x) ((x) << 24) 266 # define VS_PRIO(x) ((x) << 26) 267 # define GS_PRIO(x) ((x) << 28) 268 # define ES_PRIO(x) ((x) << 30) 269 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 270 # define NUM_PS_GPRS(x) ((x) << 0) 271 # define NUM_VS_GPRS(x) ((x) << 16) 272 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 273 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 274 # define NUM_GS_GPRS(x) ((x) << 0) 275 # define NUM_ES_GPRS(x) ((x) << 16) 276 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 277 # define NUM_PS_THREADS(x) ((x) << 0) 278 # define NUM_VS_THREADS(x) ((x) << 8) 279 # define NUM_GS_THREADS(x) ((x) << 16) 280 # define NUM_ES_THREADS(x) ((x) << 24) 281 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 282 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 283 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 284 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 285 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 286 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 287 #define SQ_ESGS_RING_BASE 0x8c40 288 #define SQ_GSVS_RING_BASE 0x8c48 289 #define SQ_ESTMP_RING_BASE 0x8c50 290 #define SQ_GSTMP_RING_BASE 0x8c58 291 #define SQ_VSTMP_RING_BASE 0x8c60 292 #define SQ_PSTMP_RING_BASE 0x8c68 293 #define SQ_FBUF_RING_BASE 0x8c70 294 #define SQ_REDUC_RING_BASE 0x8c78 295 296 #define GRBM_CNTL 0x8000 297 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 298 #define GRBM_STATUS 0x8010 299 #define CMDFIFO_AVAIL_MASK 0x0000001F 300 #define GUI_ACTIVE (1<<31) 301 #define GRBM_STATUS2 0x8014 302 #define GRBM_SOFT_RESET 0x8020 303 #define SOFT_RESET_CP (1<<0) 304 305 #define CG_THERMAL_CTRL 0x7F0 306 #define DIG_THERM_DPM(x) ((x) << 12) 307 #define DIG_THERM_DPM_MASK 0x000FF000 308 #define DIG_THERM_DPM_SHIFT 12 309 #define CG_THERMAL_STATUS 0x7F4 310 #define ASIC_T(x) ((x) << 0) 311 #define ASIC_T_MASK 0x1FF 312 #define ASIC_T_SHIFT 0 313 #define CG_THERMAL_INT 0x7F8 314 #define DIG_THERM_INTH(x) ((x) << 8) 315 #define DIG_THERM_INTH_MASK 0x0000FF00 316 #define DIG_THERM_INTH_SHIFT 8 317 #define DIG_THERM_INTL(x) ((x) << 16) 318 #define DIG_THERM_INTL_MASK 0x00FF0000 319 #define DIG_THERM_INTL_SHIFT 16 320 #define THERM_INT_MASK_HIGH (1 << 24) 321 #define THERM_INT_MASK_LOW (1 << 25) 322 323 #define RV770_CG_THERMAL_INT 0x734 324 325 #define HDP_HOST_PATH_CNTL 0x2C00 326 #define HDP_NONSURFACE_BASE 0x2C04 327 #define HDP_NONSURFACE_INFO 0x2C08 328 #define HDP_NONSURFACE_SIZE 0x2C0C 329 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 330 #define HDP_TILING_CONFIG 0x2F3C 331 #define HDP_DEBUG1 0x2F34 332 333 #define MC_VM_AGP_TOP 0x2184 334 #define MC_VM_AGP_BOT 0x2188 335 #define MC_VM_AGP_BASE 0x218C 336 #define MC_VM_FB_LOCATION 0x2180 337 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 338 #define ENABLE_L1_TLB (1 << 0) 339 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 340 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 341 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 342 #define SYSTEM_ACCESS_MODE_SHIFT 6 343 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 344 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 345 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 346 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 347 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 348 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 349 #define ENABLE_SEMAPHORE_MODE (1 << 10) 350 #define ENABLE_WAIT_L2_QUERY (1 << 11) 351 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 352 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 353 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 354 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 355 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 356 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 357 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 358 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 359 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 360 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 361 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 362 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 363 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 364 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 365 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 366 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 367 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 368 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 369 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 370 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 371 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 372 #define LOGICAL_PAGE_NUMBER_SHIFT 0 373 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 374 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 375 376 #define PA_CL_ENHANCE 0x8A14 377 #define CLIP_VTX_REORDER_ENA (1 << 0) 378 #define NUM_CLIP_SEQ(x) ((x) << 1) 379 #define PA_SC_AA_CONFIG 0x28C04 380 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 381 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 382 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 383 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 384 #define S0_X(x) ((x) << 0) 385 #define S0_Y(x) ((x) << 4) 386 #define S1_X(x) ((x) << 8) 387 #define S1_Y(x) ((x) << 12) 388 #define S2_X(x) ((x) << 16) 389 #define S2_Y(x) ((x) << 20) 390 #define S3_X(x) ((x) << 24) 391 #define S3_Y(x) ((x) << 28) 392 #define S4_X(x) ((x) << 0) 393 #define S4_Y(x) ((x) << 4) 394 #define S5_X(x) ((x) << 8) 395 #define S5_Y(x) ((x) << 12) 396 #define S6_X(x) ((x) << 16) 397 #define S6_Y(x) ((x) << 20) 398 #define S7_X(x) ((x) << 24) 399 #define S7_Y(x) ((x) << 28) 400 #define PA_SC_CLIPRECT_RULE 0x2820c 401 #define PA_SC_ENHANCE 0x8BF0 402 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 403 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 404 #define PA_SC_LINE_STIPPLE 0x28A0C 405 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 406 #define PA_SC_MODE_CNTL 0x28A4C 407 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 408 409 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 410 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 411 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 412 413 #define PCIE_PORT_INDEX 0x0038 414 #define PCIE_PORT_DATA 0x003C 415 416 #define CHMAP 0x2004 417 #define NOOFCHAN_SHIFT 12 418 #define NOOFCHAN_MASK 0x00003000 419 420 #define RAMCFG 0x2408 421 #define NOOFBANK_SHIFT 0 422 #define NOOFBANK_MASK 0x00000001 423 #define NOOFRANK_SHIFT 1 424 #define NOOFRANK_MASK 0x00000002 425 #define NOOFROWS_SHIFT 2 426 #define NOOFROWS_MASK 0x0000001C 427 #define NOOFCOLS_SHIFT 5 428 #define NOOFCOLS_MASK 0x00000060 429 #define CHANSIZE_SHIFT 7 430 #define CHANSIZE_MASK 0x00000080 431 #define BURSTLENGTH_SHIFT 8 432 #define BURSTLENGTH_MASK 0x00000100 433 #define CHANSIZE_OVERRIDE (1 << 10) 434 435 #define SCRATCH_REG0 0x8500 436 #define SCRATCH_REG1 0x8504 437 #define SCRATCH_REG2 0x8508 438 #define SCRATCH_REG3 0x850C 439 #define SCRATCH_REG4 0x8510 440 #define SCRATCH_REG5 0x8514 441 #define SCRATCH_REG6 0x8518 442 #define SCRATCH_REG7 0x851C 443 #define SCRATCH_UMSK 0x8540 444 #define SCRATCH_ADDR 0x8544 445 446 #define SPI_CONFIG_CNTL 0x9100 447 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 448 #define DISABLE_INTERP_1 (1 << 5) 449 #define SPI_CONFIG_CNTL_1 0x913C 450 #define VTX_DONE_DELAY(x) ((x) << 0) 451 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 452 #define SPI_INPUT_Z 0x286D8 453 #define SPI_PS_IN_CONTROL_0 0x286CC 454 #define NUM_INTERP(x) ((x)<<0) 455 #define POSITION_ENA (1<<8) 456 #define POSITION_CENTROID (1<<9) 457 #define POSITION_ADDR(x) ((x)<<10) 458 #define PARAM_GEN(x) ((x)<<15) 459 #define PARAM_GEN_ADDR(x) ((x)<<19) 460 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 461 #define PERSP_GRADIENT_ENA (1<<28) 462 #define LINEAR_GRADIENT_ENA (1<<29) 463 #define POSITION_SAMPLE (1<<30) 464 #define BARYC_AT_SAMPLE_ENA (1<<31) 465 #define SPI_PS_IN_CONTROL_1 0x286D0 466 #define GEN_INDEX_PIX (1<<0) 467 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 468 #define FRONT_FACE_ENA (1<<8) 469 #define FRONT_FACE_CHAN(x) ((x)<<9) 470 #define FRONT_FACE_ALL_BITS (1<<11) 471 #define FRONT_FACE_ADDR(x) ((x)<<12) 472 #define FOG_ADDR(x) ((x)<<17) 473 #define FIXED_PT_POSITION_ENA (1<<24) 474 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 475 476 #define SQ_MS_FIFO_SIZES 0x8CF0 477 #define CACHE_FIFO_SIZE(x) ((x) << 0) 478 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 479 #define DONE_FIFO_HIWATER(x) ((x) << 16) 480 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 481 #define SQ_PGM_START_ES 0x28880 482 #define SQ_PGM_START_FS 0x28894 483 #define SQ_PGM_START_GS 0x2886C 484 #define SQ_PGM_START_PS 0x28840 485 #define SQ_PGM_RESOURCES_PS 0x28850 486 #define SQ_PGM_EXPORTS_PS 0x28854 487 #define SQ_PGM_CF_OFFSET_PS 0x288cc 488 #define SQ_PGM_START_VS 0x28858 489 #define SQ_PGM_RESOURCES_VS 0x28868 490 #define SQ_PGM_CF_OFFSET_VS 0x288d0 491 492 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 493 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 494 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 495 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 496 # define SQ_VTXC_STRIDE(x) ((x) << 8) 497 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 498 # define SQ_ENDIAN_NONE 0 499 # define SQ_ENDIAN_8IN16 1 500 # define SQ_ENDIAN_8IN32 2 501 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 502 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 503 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 504 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 505 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 506 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 507 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 508 #define SQ_TEX_VTX_VALID_BUFFER 0x3 509 510 511 #define SX_MISC 0x28350 512 #define SX_MEMORY_EXPORT_BASE 0x9010 513 #define SX_DEBUG_1 0x9054 514 #define SMX_EVENT_RELEASE (1 << 0) 515 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 516 517 #define TA_CNTL_AUX 0x9508 518 #define DISABLE_CUBE_WRAP (1 << 0) 519 #define DISABLE_CUBE_ANISO (1 << 1) 520 #define SYNC_GRADIENT (1 << 24) 521 #define SYNC_WALKER (1 << 25) 522 #define SYNC_ALIGNER (1 << 26) 523 #define BILINEAR_PRECISION_6_BIT (0 << 31) 524 #define BILINEAR_PRECISION_8_BIT (1 << 31) 525 526 #define TC_CNTL 0x9608 527 #define TC_L2_SIZE(x) ((x)<<5) 528 #define L2_DISABLE_LATE_HIT (1<<9) 529 530 #define VC_ENHANCE 0x9714 531 532 #define VGT_CACHE_INVALIDATION 0x88C4 533 #define CACHE_INVALIDATION(x) ((x)<<0) 534 #define VC_ONLY 0 535 #define TC_ONLY 1 536 #define VC_AND_TC 2 537 #define VGT_DMA_BASE 0x287E8 538 #define VGT_DMA_BASE_HI 0x287E4 539 #define VGT_ES_PER_GS 0x88CC 540 #define VGT_GS_PER_ES 0x88C8 541 #define VGT_GS_PER_VS 0x88E8 542 #define VGT_GS_VERTEX_REUSE 0x88D4 543 #define VGT_PRIMITIVE_TYPE 0x8958 544 #define VGT_NUM_INSTANCES 0x8974 545 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 546 #define DEALLOC_DIST_MASK 0x0000007F 547 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 548 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 549 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 550 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 551 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 552 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 553 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 554 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 555 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 556 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 557 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 558 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 559 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 560 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 561 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 562 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 563 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 564 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 565 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 566 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 567 568 #define VGT_STRMOUT_EN 0x28AB0 569 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 570 #define VTX_REUSE_DEPTH_MASK 0x000000FF 571 #define VGT_EVENT_INITIATOR 0x28a90 572 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 573 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 574 575 #define VM_CONTEXT0_CNTL 0x1410 576 #define ENABLE_CONTEXT (1 << 0) 577 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 578 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 579 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 580 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 581 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 582 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 583 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 584 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 585 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 586 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 587 #define RESPONSE_TYPE_MASK 0x000000F0 588 #define RESPONSE_TYPE_SHIFT 4 589 #define VM_L2_CNTL 0x1400 590 #define ENABLE_L2_CACHE (1 << 0) 591 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 592 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 593 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 594 #define VM_L2_CNTL2 0x1404 595 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 596 #define INVALIDATE_L2_CACHE (1 << 1) 597 #define VM_L2_CNTL3 0x1408 598 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 599 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 600 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 601 #define VM_L2_STATUS 0x140C 602 #define L2_BUSY (1 << 0) 603 604 #define WAIT_UNTIL 0x8040 605 #define WAIT_CP_DMA_IDLE_bit (1 << 8) 606 #define WAIT_2D_IDLE_bit (1 << 14) 607 #define WAIT_3D_IDLE_bit (1 << 15) 608 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 609 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 610 611 /* async DMA */ 612 #define DMA_TILING_CONFIG 0x3ec4 613 #define DMA_CONFIG 0x3e4c 614 615 #define DMA_RB_CNTL 0xd000 616 # define DMA_RB_ENABLE (1 << 0) 617 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 618 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 619 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 620 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 621 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 622 #define DMA_RB_BASE 0xd004 623 #define DMA_RB_RPTR 0xd008 624 #define DMA_RB_WPTR 0xd00c 625 626 #define DMA_RB_RPTR_ADDR_HI 0xd01c 627 #define DMA_RB_RPTR_ADDR_LO 0xd020 628 629 #define DMA_IB_CNTL 0xd024 630 # define DMA_IB_ENABLE (1 << 0) 631 # define DMA_IB_SWAP_ENABLE (1 << 4) 632 #define DMA_IB_RPTR 0xd028 633 #define DMA_CNTL 0xd02c 634 # define TRAP_ENABLE (1 << 0) 635 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 636 # define SEM_WAIT_INT_ENABLE (1 << 2) 637 # define DATA_SWAP_ENABLE (1 << 3) 638 # define FENCE_SWAP_ENABLE (1 << 4) 639 # define CTXEMPTY_INT_ENABLE (1 << 28) 640 #define DMA_STATUS_REG 0xd034 641 # define DMA_IDLE (1 << 0) 642 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 643 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 644 #define DMA_MODE 0xd0bc 645 646 /* async DMA packets */ 647 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 648 (((t) & 0x1) << 23) | \ 649 (((s) & 0x1) << 22) | \ 650 (((n) & 0xFFFF) << 0)) 651 /* async DMA Packet types */ 652 #define DMA_PACKET_WRITE 0x2 653 #define DMA_PACKET_COPY 0x3 654 #define DMA_PACKET_INDIRECT_BUFFER 0x4 655 #define DMA_PACKET_SEMAPHORE 0x5 656 #define DMA_PACKET_FENCE 0x6 657 #define DMA_PACKET_TRAP 0x7 658 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 659 #define DMA_PACKET_NOP 0xf 660 661 #define IH_RB_CNTL 0x3e00 662 # define IH_RB_ENABLE (1 << 0) 663 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 664 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 665 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 666 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 667 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 668 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 669 #define IH_RB_BASE 0x3e04 670 #define IH_RB_RPTR 0x3e08 671 #define IH_RB_WPTR 0x3e0c 672 # define RB_OVERFLOW (1 << 0) 673 # define WPTR_OFFSET_MASK 0x3fffc 674 #define IH_RB_WPTR_ADDR_HI 0x3e10 675 #define IH_RB_WPTR_ADDR_LO 0x3e14 676 #define IH_CNTL 0x3e18 677 # define ENABLE_INTR (1 << 0) 678 # define IH_MC_SWAP(x) ((x) << 1) 679 # define IH_MC_SWAP_NONE 0 680 # define IH_MC_SWAP_16BIT 1 681 # define IH_MC_SWAP_32BIT 2 682 # define IH_MC_SWAP_64BIT 3 683 # define RPTR_REARM (1 << 4) 684 # define MC_WRREQ_CREDIT(x) ((x) << 15) 685 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 686 687 #define RLC_CNTL 0x3f00 688 # define RLC_ENABLE (1 << 0) 689 #define RLC_HB_BASE 0x3f10 690 #define RLC_HB_CNTL 0x3f0c 691 #define RLC_HB_RPTR 0x3f20 692 #define RLC_HB_WPTR 0x3f1c 693 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 694 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 695 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 696 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 697 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 698 #define RLC_MC_CNTL 0x3f44 699 #define RLC_UCODE_CNTL 0x3f48 700 #define RLC_UCODE_ADDR 0x3f2c 701 #define RLC_UCODE_DATA 0x3f30 702 703 #define SRBM_SOFT_RESET 0xe60 704 # define SOFT_RESET_BIF (1 << 1) 705 # define SOFT_RESET_DMA (1 << 12) 706 # define SOFT_RESET_RLC (1 << 13) 707 # define SOFT_RESET_UVD (1 << 18) 708 # define RV770_SOFT_RESET_DMA (1 << 20) 709 710 #define BIF_SCRATCH0 0x5438 711 712 #define BUS_CNTL 0x5420 713 # define BIOS_ROM_DIS (1 << 1) 714 # define VGA_COHE_SPEC_TIMER_DIS (1 << 9) 715 716 #define CP_INT_CNTL 0xc124 717 # define CNTX_BUSY_INT_ENABLE (1 << 19) 718 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 719 # define SCRATCH_INT_ENABLE (1 << 25) 720 # define TIME_STAMP_INT_ENABLE (1 << 26) 721 # define IB2_INT_ENABLE (1 << 29) 722 # define IB1_INT_ENABLE (1 << 30) 723 # define RB_INT_ENABLE (1 << 31) 724 #define CP_INT_STATUS 0xc128 725 # define SCRATCH_INT_STAT (1 << 25) 726 # define TIME_STAMP_INT_STAT (1 << 26) 727 # define IB2_INT_STAT (1 << 29) 728 # define IB1_INT_STAT (1 << 30) 729 # define RB_INT_STAT (1 << 31) 730 731 #define GRBM_INT_CNTL 0x8060 732 # define RDERR_INT_ENABLE (1 << 0) 733 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 734 # define GUI_IDLE_INT_ENABLE (1 << 19) 735 736 #define INTERRUPT_CNTL 0x5468 737 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 738 # define IH_DUMMY_RD_EN (1 << 1) 739 # define IH_REQ_NONSNOOP_EN (1 << 3) 740 # define GEN_IH_INT_EN (1 << 8) 741 #define INTERRUPT_CNTL2 0x546c 742 743 #define D1MODE_VBLANK_STATUS 0x6534 744 #define D2MODE_VBLANK_STATUS 0x6d34 745 # define DxMODE_VBLANK_OCCURRED (1 << 0) 746 # define DxMODE_VBLANK_ACK (1 << 4) 747 # define DxMODE_VBLANK_STAT (1 << 12) 748 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 749 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 750 #define D1MODE_VLINE_STATUS 0x653c 751 #define D2MODE_VLINE_STATUS 0x6d3c 752 # define DxMODE_VLINE_OCCURRED (1 << 0) 753 # define DxMODE_VLINE_ACK (1 << 4) 754 # define DxMODE_VLINE_STAT (1 << 12) 755 # define DxMODE_VLINE_INTERRUPT (1 << 16) 756 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 757 #define DxMODE_INT_MASK 0x6540 758 # define D1MODE_VBLANK_INT_MASK (1 << 0) 759 # define D1MODE_VLINE_INT_MASK (1 << 4) 760 # define D2MODE_VBLANK_INT_MASK (1 << 8) 761 # define D2MODE_VLINE_INT_MASK (1 << 12) 762 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 763 # define DC_HPD1_INTERRUPT (1 << 18) 764 # define DC_HPD2_INTERRUPT (1 << 19) 765 #define DISP_INTERRUPT_STATUS 0x7edc 766 # define LB_D1_VLINE_INTERRUPT (1 << 2) 767 # define LB_D2_VLINE_INTERRUPT (1 << 3) 768 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 769 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 770 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 771 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 772 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 773 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 774 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 775 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 776 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 777 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 778 # define DC_HPD4_INTERRUPT (1 << 14) 779 # define DC_HPD4_RX_INTERRUPT (1 << 15) 780 # define DC_HPD3_INTERRUPT (1 << 28) 781 # define DC_HPD1_RX_INTERRUPT (1 << 29) 782 # define DC_HPD2_RX_INTERRUPT (1 << 30) 783 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 784 # define DC_HPD3_RX_INTERRUPT (1 << 0) 785 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 786 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 787 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 788 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 789 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 790 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 791 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 792 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 793 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 794 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 795 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 796 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 797 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 798 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 799 /* DCE 3.2 */ 800 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 801 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 802 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 803 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 804 # define DC_HPD5_INTERRUPT (1 << 19) 805 # define DC_HPD5_RX_INTERRUPT (1 << 20) 806 # define DC_HPD6_INTERRUPT (1 << 21) 807 # define DC_HPD6_RX_INTERRUPT (1 << 22) 808 809 #define DACA_AUTO_DETECT_CONTROL 0x7828 810 #define DACB_AUTO_DETECT_CONTROL 0x7a28 811 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 812 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 813 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 814 # define DACx_AUTODETECT_MODE_NONE 0 815 # define DACx_AUTODETECT_MODE_CONNECT 1 816 # define DACx_AUTODETECT_MODE_DISCONNECT 2 817 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 818 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 819 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 820 821 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 822 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 823 #define DACA_AUTODETECT_INT_CONTROL 0x7838 824 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 825 # define DACx_AUTODETECT_ACK (1 << 0) 826 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 827 828 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 829 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 830 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 831 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 832 833 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 834 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 835 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 836 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 837 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 838 839 /* DCE 3.0 */ 840 #define DC_HPD1_INT_STATUS 0x7d00 841 #define DC_HPD2_INT_STATUS 0x7d0c 842 #define DC_HPD3_INT_STATUS 0x7d18 843 #define DC_HPD4_INT_STATUS 0x7d24 844 /* DCE 3.2 */ 845 #define DC_HPD5_INT_STATUS 0x7dc0 846 #define DC_HPD6_INT_STATUS 0x7df4 847 # define DC_HPDx_INT_STATUS (1 << 0) 848 # define DC_HPDx_SENSE (1 << 1) 849 # define DC_HPDx_RX_INT_STATUS (1 << 8) 850 851 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 852 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 853 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 854 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 855 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 856 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 857 /* DCE 3.0 */ 858 #define DC_HPD1_INT_CONTROL 0x7d04 859 #define DC_HPD2_INT_CONTROL 0x7d10 860 #define DC_HPD3_INT_CONTROL 0x7d1c 861 #define DC_HPD4_INT_CONTROL 0x7d28 862 /* DCE 3.2 */ 863 #define DC_HPD5_INT_CONTROL 0x7dc4 864 #define DC_HPD6_INT_CONTROL 0x7df8 865 # define DC_HPDx_INT_ACK (1 << 0) 866 # define DC_HPDx_INT_POLARITY (1 << 8) 867 # define DC_HPDx_INT_EN (1 << 16) 868 # define DC_HPDx_RX_INT_ACK (1 << 20) 869 # define DC_HPDx_RX_INT_EN (1 << 24) 870 871 /* DCE 3.0 */ 872 #define DC_HPD1_CONTROL 0x7d08 873 #define DC_HPD2_CONTROL 0x7d14 874 #define DC_HPD3_CONTROL 0x7d20 875 #define DC_HPD4_CONTROL 0x7d2c 876 /* DCE 3.2 */ 877 #define DC_HPD5_CONTROL 0x7dc8 878 #define DC_HPD6_CONTROL 0x7dfc 879 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 880 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 881 /* DCE 3.2 */ 882 # define DC_HPDx_EN (1 << 28) 883 884 #define D1GRPH_INTERRUPT_STATUS 0x6158 885 #define D2GRPH_INTERRUPT_STATUS 0x6958 886 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 887 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 888 #define D1GRPH_INTERRUPT_CONTROL 0x615c 889 #define D2GRPH_INTERRUPT_CONTROL 0x695c 890 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 891 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 892 893 /* PCIE link stuff */ 894 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 895 # define LC_POINT_7_PLUS_EN (1 << 6) 896 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 897 # define LC_LINK_WIDTH_SHIFT 0 898 # define LC_LINK_WIDTH_MASK 0x7 899 # define LC_LINK_WIDTH_X0 0 900 # define LC_LINK_WIDTH_X1 1 901 # define LC_LINK_WIDTH_X2 2 902 # define LC_LINK_WIDTH_X4 3 903 # define LC_LINK_WIDTH_X8 4 904 # define LC_LINK_WIDTH_X16 6 905 # define LC_LINK_WIDTH_RD_SHIFT 4 906 # define LC_LINK_WIDTH_RD_MASK 0x70 907 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 908 # define LC_RECONFIG_NOW (1 << 8) 909 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 910 # define LC_RENEGOTIATE_EN (1 << 10) 911 # define LC_SHORT_RECONFIG_EN (1 << 11) 912 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 913 # define LC_UPCONFIGURE_DIS (1 << 13) 914 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 915 # define LC_GEN2_EN_STRAP (1 << 0) 916 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 917 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 918 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 919 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 920 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 921 # define LC_CURRENT_DATA_RATE (1 << 11) 922 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 923 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 924 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 925 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 926 #define MM_CFGREGS_CNTL 0x544c 927 # define MM_WR_TO_CFG_EN (1 << 3) 928 #define LINK_CNTL2 0x88 /* F0 */ 929 # define TARGET_LINK_SPEED_MASK (0xf << 0) 930 # define SELECTABLE_DEEMPHASIS (1 << 6) 931 932 /* Audio clocks DCE 2.0/3.0 */ 933 #define AUDIO_DTO 0x7340 934 # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) 935 # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16) 936 937 /* Audio clocks DCE 3.2 */ 938 #define DCCG_AUDIO_DTO0_PHASE 0x0514 939 #define DCCG_AUDIO_DTO0_MODULE 0x0518 940 #define DCCG_AUDIO_DTO0_LOAD 0x051c 941 # define DTO_LOAD (1 << 31) 942 #define DCCG_AUDIO_DTO0_CNTL 0x0520 943 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 944 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 945 # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 946 947 #define DCCG_AUDIO_DTO1_PHASE 0x0524 948 #define DCCG_AUDIO_DTO1_MODULE 0x0528 949 #define DCCG_AUDIO_DTO1_LOAD 0x052c 950 #define DCCG_AUDIO_DTO1_CNTL 0x0530 951 952 #define DCCG_AUDIO_DTO_SELECT 0x0534 953 954 /* digital blocks */ 955 #define TMDSA_CNTL 0x7880 956 # define TMDSA_HDMI_EN (1 << 2) 957 #define LVTMA_CNTL 0x7a80 958 # define LVTMA_HDMI_EN (1 << 2) 959 #define DDIA_CNTL 0x7200 960 # define DDIA_HDMI_EN (1 << 2) 961 #define DIG0_CNTL 0x75a0 962 # define DIG_MODE(x) (((x) & 7) << 8) 963 # define DIG_MODE_DP 0 964 # define DIG_MODE_LVDS 1 965 # define DIG_MODE_TMDS_DVI 2 966 # define DIG_MODE_TMDS_HDMI 3 967 # define DIG_MODE_SDVO 4 968 #define DIG1_CNTL 0x79a0 969 970 #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc 971 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 972 #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 973 #define SPEAKER_ALLOCATION_SHIFT 0 974 #define HDMI_CONNECTION (1 << 16) 975 #define DP_CONNECTION (1 << 17) 976 977 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 978 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 979 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 980 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 981 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 982 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 983 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 984 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 985 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 986 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 987 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 988 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 989 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 990 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 991 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 992 /* max channels minus one. 7 = 8 channels */ 993 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 994 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 995 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 996 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 997 * bit0 = 32 kHz 998 * bit1 = 44.1 kHz 999 * bit2 = 48 kHz 1000 * bit3 = 88.2 kHz 1001 * bit4 = 96 kHz 1002 * bit5 = 176.4 kHz 1003 * bit6 = 192 kHz 1004 */ 1005 1006 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 1007 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 1008 * different due to the new DIG blocks, but also have 2 instances. 1009 * DCE 3.0 HDMI blocks are part of each DIG encoder. 1010 */ 1011 1012 /* rs6xx/rs740/r6xx/dce3 */ 1013 #define HDMI0_CONTROL 0x7400 1014 /* rs6xx/rs740/r6xx */ 1015 # define HDMI0_ENABLE (1 << 0) 1016 # define HDMI0_STREAM(x) (((x) & 3) << 2) 1017 # define HDMI0_STREAM_TMDSA 0 1018 # define HDMI0_STREAM_LVTMA 1 1019 # define HDMI0_STREAM_DVOA 2 1020 # define HDMI0_STREAM_DDIA 3 1021 /* rs6xx/r6xx/dce3 */ 1022 # define HDMI0_ERROR_ACK (1 << 8) 1023 # define HDMI0_ERROR_MASK (1 << 9) 1024 #define HDMI0_STATUS 0x7404 1025 # define HDMI0_ACTIVE_AVMUTE (1 << 0) 1026 # define HDMI0_AUDIO_ENABLE (1 << 4) 1027 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 1028 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 1029 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 1030 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 1031 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 1032 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 1033 # define HDMI0_AUDIO_TEST_EN (1 << 12) 1034 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 1035 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 1036 # define HDMI0_60958_CS_UPDATE (1 << 26) 1037 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 1038 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 1039 #define HDMI0_AUDIO_CRC_CONTROL 0x740c 1040 # define HDMI0_AUDIO_CRC_EN (1 << 0) 1041 #define HDMI0_VBI_PACKET_CONTROL 0x7410 1042 # define HDMI0_NULL_SEND (1 << 0) 1043 # define HDMI0_GC_SEND (1 << 4) 1044 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 1045 #define HDMI0_INFOFRAME_CONTROL0 0x7414 1046 # define HDMI0_AVI_INFO_SEND (1 << 0) 1047 # define HDMI0_AVI_INFO_CONT (1 << 1) 1048 # define HDMI0_AUDIO_INFO_SEND (1 << 4) 1049 # define HDMI0_AUDIO_INFO_CONT (1 << 5) 1050 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ 1051 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 1052 # define HDMI0_MPEG_INFO_SEND (1 << 8) 1053 # define HDMI0_MPEG_INFO_CONT (1 << 9) 1054 # define HDMI0_MPEG_INFO_UPDATE (1 << 10) 1055 #define HDMI0_INFOFRAME_CONTROL1 0x7418 1056 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 1057 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 1058 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 1059 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c 1060 # define HDMI0_GENERIC0_SEND (1 << 0) 1061 # define HDMI0_GENERIC0_CONT (1 << 1) 1062 # define HDMI0_GENERIC0_UPDATE (1 << 2) 1063 # define HDMI0_GENERIC1_SEND (1 << 4) 1064 # define HDMI0_GENERIC1_CONT (1 << 5) 1065 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1066 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1067 #define HDMI0_GC 0x7428 1068 # define HDMI0_GC_AVMUTE (1 << 0) 1069 #define HDMI0_AVI_INFO0 0x7454 1070 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1071 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1072 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1073 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1074 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1075 # define HDMI0_AVI_INFO_Y_RGB 0 1076 # define HDMI0_AVI_INFO_Y_YCBCR422 1 1077 # define HDMI0_AVI_INFO_Y_YCBCR444 2 1078 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1079 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1080 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1081 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1082 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1083 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1084 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1085 #define HDMI0_AVI_INFO1 0x7458 1086 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1087 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1088 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1089 #define HDMI0_AVI_INFO2 0x745c 1090 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1091 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1092 #define HDMI0_AVI_INFO3 0x7460 1093 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1094 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1095 #define HDMI0_MPEG_INFO0 0x7464 1096 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1097 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1098 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1099 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1100 #define HDMI0_MPEG_INFO1 0x7468 1101 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1102 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1103 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1104 #define HDMI0_GENERIC0_HDR 0x746c 1105 #define HDMI0_GENERIC0_0 0x7470 1106 #define HDMI0_GENERIC0_1 0x7474 1107 #define HDMI0_GENERIC0_2 0x7478 1108 #define HDMI0_GENERIC0_3 0x747c 1109 #define HDMI0_GENERIC0_4 0x7480 1110 #define HDMI0_GENERIC0_5 0x7484 1111 #define HDMI0_GENERIC0_6 0x7488 1112 #define HDMI0_GENERIC1_HDR 0x748c 1113 #define HDMI0_GENERIC1_0 0x7490 1114 #define HDMI0_GENERIC1_1 0x7494 1115 #define HDMI0_GENERIC1_2 0x7498 1116 #define HDMI0_GENERIC1_3 0x749c 1117 #define HDMI0_GENERIC1_4 0x74a0 1118 #define HDMI0_GENERIC1_5 0x74a4 1119 #define HDMI0_GENERIC1_6 0x74a8 1120 #define HDMI0_ACR_32_0 0x74ac 1121 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1122 #define HDMI0_ACR_32_1 0x74b0 1123 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1124 #define HDMI0_ACR_44_0 0x74b4 1125 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1126 #define HDMI0_ACR_44_1 0x74b8 1127 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1128 #define HDMI0_ACR_48_0 0x74bc 1129 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1130 #define HDMI0_ACR_48_1 0x74c0 1131 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1132 #define HDMI0_ACR_STATUS_0 0x74c4 1133 #define HDMI0_ACR_STATUS_1 0x74c8 1134 #define HDMI0_AUDIO_INFO0 0x74cc 1135 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1136 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1137 #define HDMI0_AUDIO_INFO1 0x74d0 1138 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1139 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1140 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1141 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1142 #define HDMI0_60958_0 0x74d4 1143 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1144 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1145 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1146 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1147 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1148 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1149 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1150 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1151 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1152 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1153 #define HDMI0_60958_1 0x74d8 1154 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1155 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1156 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1157 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1158 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1159 #define HDMI0_ACR_PACKET_CONTROL 0x74dc 1160 # define HDMI0_ACR_SEND (1 << 0) 1161 # define HDMI0_ACR_CONT (1 << 1) 1162 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1163 # define HDMI0_ACR_HW 0 1164 # define HDMI0_ACR_32 1 1165 # define HDMI0_ACR_44 2 1166 # define HDMI0_ACR_48 3 1167 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1168 # define HDMI0_ACR_AUTO_SEND (1 << 12) 1169 #define HDMI0_RAMP_CONTROL0 0x74e0 1170 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1171 #define HDMI0_RAMP_CONTROL1 0x74e4 1172 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1173 #define HDMI0_RAMP_CONTROL2 0x74e8 1174 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1175 #define HDMI0_RAMP_CONTROL3 0x74ec 1176 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1177 /* HDMI0_60958_2 is r7xx only */ 1178 #define HDMI0_60958_2 0x74f0 1179 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1180 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1181 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1182 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1183 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1184 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1185 /* r6xx only; second instance starts at 0x7700 */ 1186 #define HDMI1_CONTROL 0x7700 1187 #define HDMI1_STATUS 0x7704 1188 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1189 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1190 #define DCE3_HDMI1_CONTROL 0x7800 1191 #define DCE3_HDMI1_STATUS 0x7804 1192 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1193 /* DCE3.2 (for interrupts) */ 1194 #define AFMT_STATUS 0x7600 1195 # define AFMT_AUDIO_ENABLE (1 << 4) 1196 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1197 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1198 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1199 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 1200 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1201 # define AFMT_AUDIO_TEST_EN (1 << 12) 1202 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1203 # define AFMT_60958_CS_UPDATE (1 << 26) 1204 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1205 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1206 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1207 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1208 1209 /* DCE3 FMT blocks */ 1210 #define FMT_CONTROL 0x6700 1211 # define FMT_PIXEL_ENCODING (1 << 16) 1212 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 1213 #define FMT_BIT_DEPTH_CONTROL 0x6710 1214 # define FMT_TRUNCATE_EN (1 << 0) 1215 # define FMT_TRUNCATE_DEPTH (1 << 4) 1216 # define FMT_SPATIAL_DITHER_EN (1 << 8) 1217 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1218 # define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1219 # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1220 # define FMT_RGB_RANDOM_ENABLE (1 << 14) 1221 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1222 # define FMT_TEMPORAL_DITHER_EN (1 << 16) 1223 # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1224 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1225 # define FMT_TEMPORAL_LEVEL (1 << 24) 1226 # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1227 # define FMT_25FRC_SEL(x) ((x) << 26) 1228 # define FMT_50FRC_SEL(x) ((x) << 28) 1229 # define FMT_75FRC_SEL(x) ((x) << 30) 1230 #define FMT_CLAMP_CONTROL 0x672c 1231 # define FMT_CLAMP_DATA_EN (1 << 0) 1232 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1233 # define FMT_CLAMP_6BPC 0 1234 # define FMT_CLAMP_8BPC 1 1235 # define FMT_CLAMP_10BPC 2 1236 1237 /* Power management */ 1238 #define CG_SPLL_FUNC_CNTL 0x600 1239 # define SPLL_RESET (1 << 0) 1240 # define SPLL_SLEEP (1 << 1) 1241 # define SPLL_REF_DIV(x) ((x) << 2) 1242 # define SPLL_REF_DIV_MASK (7 << 2) 1243 # define SPLL_FB_DIV(x) ((x) << 5) 1244 # define SPLL_FB_DIV_MASK (0xff << 5) 1245 # define SPLL_PULSEEN (1 << 13) 1246 # define SPLL_PULSENUM(x) ((x) << 14) 1247 # define SPLL_PULSENUM_MASK (3 << 14) 1248 # define SPLL_SW_HILEN(x) ((x) << 16) 1249 # define SPLL_SW_HILEN_MASK (0xf << 16) 1250 # define SPLL_SW_LOLEN(x) ((x) << 20) 1251 # define SPLL_SW_LOLEN_MASK (0xf << 20) 1252 # define SPLL_DIVEN (1 << 24) 1253 # define SPLL_BYPASS_EN (1 << 25) 1254 # define SPLL_CHG_STATUS (1 << 29) 1255 # define SPLL_CTLREQ (1 << 30) 1256 # define SPLL_CTLACK (1 << 31) 1257 1258 #define GENERAL_PWRMGT 0x618 1259 # define GLOBAL_PWRMGT_EN (1 << 0) 1260 # define STATIC_PM_EN (1 << 1) 1261 # define MOBILE_SU (1 << 2) 1262 # define THERMAL_PROTECTION_DIS (1 << 3) 1263 # define THERMAL_PROTECTION_TYPE (1 << 4) 1264 # define ENABLE_GEN2PCIE (1 << 5) 1265 # define SW_GPIO_INDEX(x) ((x) << 6) 1266 # define SW_GPIO_INDEX_MASK (3 << 6) 1267 # define LOW_VOLT_D2_ACPI (1 << 8) 1268 # define LOW_VOLT_D3_ACPI (1 << 9) 1269 # define VOLT_PWRMGT_EN (1 << 10) 1270 #define CG_TPC 0x61c 1271 # define TPCC(x) ((x) << 0) 1272 # define TPCC_MASK (0x7fffff << 0) 1273 # define TPU(x) ((x) << 23) 1274 # define TPU_MASK (0x1f << 23) 1275 #define SCLK_PWRMGT_CNTL 0x620 1276 # define SCLK_PWRMGT_OFF (1 << 0) 1277 # define SCLK_TURNOFF (1 << 1) 1278 # define SPLL_TURNOFF (1 << 2) 1279 # define SU_SCLK_USE_BCLK (1 << 3) 1280 # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4) 1281 # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5) 1282 # define CLK_TURN_ON_STAGGER (1 << 6) 1283 # define CLK_TURN_OFF_STAGGER (1 << 7) 1284 # define FIR_FORCE_TREND_SEL (1 << 8) 1285 # define FIR_TREND_MODE (1 << 9) 1286 # define DYN_GFX_CLK_OFF_EN (1 << 10) 1287 # define VDDC3D_TURNOFF_D1 (1 << 11) 1288 # define VDDC3D_TURNOFF_D2 (1 << 12) 1289 # define VDDC3D_TURNOFF_D3 (1 << 13) 1290 # define SPLL_TURNOFF_D2 (1 << 14) 1291 # define SCLK_LOW_D1 (1 << 15) 1292 # define DYN_GFX_CLK_OFF_MC_EN (1 << 16) 1293 #define MCLK_PWRMGT_CNTL 0x624 1294 # define MPLL_PWRMGT_OFF (1 << 0) 1295 # define YCLK_TURNOFF (1 << 1) 1296 # define MPLL_TURNOFF (1 << 2) 1297 # define SU_MCLK_USE_BCLK (1 << 3) 1298 # define DLL_READY (1 << 4) 1299 # define MC_BUSY (1 << 5) 1300 # define MC_INT_CNTL (1 << 7) 1301 # define MRDCKA_SLEEP (1 << 8) 1302 # define MRDCKB_SLEEP (1 << 9) 1303 # define MRDCKC_SLEEP (1 << 10) 1304 # define MRDCKD_SLEEP (1 << 11) 1305 # define MRDCKE_SLEEP (1 << 12) 1306 # define MRDCKF_SLEEP (1 << 13) 1307 # define MRDCKG_SLEEP (1 << 14) 1308 # define MRDCKH_SLEEP (1 << 15) 1309 # define MRDCKA_RESET (1 << 16) 1310 # define MRDCKB_RESET (1 << 17) 1311 # define MRDCKC_RESET (1 << 18) 1312 # define MRDCKD_RESET (1 << 19) 1313 # define MRDCKE_RESET (1 << 20) 1314 # define MRDCKF_RESET (1 << 21) 1315 # define MRDCKG_RESET (1 << 22) 1316 # define MRDCKH_RESET (1 << 23) 1317 # define DLL_READY_READ (1 << 24) 1318 # define USE_DISPLAY_GAP (1 << 25) 1319 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 1320 # define USE_DISPLAY_GAP_CTXSW (1 << 27) 1321 # define MPLL_TURNOFF_D2 (1 << 28) 1322 # define USE_DISPLAY_URGENT_CTXSW (1 << 29) 1323 1324 #define MPLL_TIME 0x634 1325 # define MPLL_LOCK_TIME(x) ((x) << 0) 1326 # define MPLL_LOCK_TIME_MASK (0xffff << 0) 1327 # define MPLL_RESET_TIME(x) ((x) << 16) 1328 # define MPLL_RESET_TIME_MASK (0xffff << 16) 1329 1330 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 1331 # define STEP_0_SPLL_POST_DIV(x) ((x) << 0) 1332 # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0) 1333 # define STEP_0_SPLL_FB_DIV(x) ((x) << 8) 1334 # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) 1335 # define STEP_0_SPLL_REF_DIV(x) ((x) << 16) 1336 # define STEP_0_SPLL_REF_DIV_MASK (7 << 16) 1337 # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19) 1338 # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19) 1339 #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c 1340 # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0) 1341 # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0) 1342 # define STEP_0_POST_DIV_EN (1 << 9) 1343 # define STEP_0_SPLL_STEP_ENABLE (1 << 30) 1344 # define STEP_0_SPLL_ENTRY_VALID (1 << 31) 1345 1346 #define VID_RT 0x6f8 1347 # define VID_CRT(x) ((x) << 0) 1348 # define VID_CRT_MASK (0x1fff << 0) 1349 # define VID_CRTU(x) ((x) << 13) 1350 # define VID_CRTU_MASK (7 << 13) 1351 # define SSTU(x) ((x) << 16) 1352 # define SSTU_MASK (7 << 16) 1353 #define CTXSW_PROFILE_INDEX 0x6fc 1354 # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0) 1355 # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0) 1356 # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0 1357 # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2) 1358 # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2) 1359 # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2 1360 # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4) 1361 # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4) 1362 # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4 1363 # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9) 1364 # define CTXSW_FREQ_STATE_ENABLE (1 << 10) 1365 # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11) 1366 # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12) 1367 1368 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 1369 # define TARGET_PROFILE_INDEX_MASK (3 << 0) 1370 # define TARGET_PROFILE_INDEX_SHIFT 0 1371 # define CURRENT_PROFILE_INDEX_MASK (3 << 2) 1372 # define CURRENT_PROFILE_INDEX_SHIFT 2 1373 # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 1374 # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 1375 # define DYN_PWR_ENTER_INDEX_SHIFT 4 1376 # define CURR_MCLK_INDEX_MASK (3 << 6) 1377 # define CURR_MCLK_INDEX_SHIFT 6 1378 # define CURR_SCLK_INDEX_MASK (0x1f << 8) 1379 # define CURR_SCLK_INDEX_SHIFT 8 1380 # define CURR_VID_INDEX_MASK (3 << 13) 1381 # define CURR_VID_INDEX_SHIFT 13 1382 1383 #define LOWER_GPIO_ENABLE 0x710 1384 #define UPPER_GPIO_ENABLE 0x714 1385 #define CTXSW_VID_LOWER_GPIO_CNTL 0x718 1386 1387 #define VID_UPPER_GPIO_CNTL 0x740 1388 #define CG_CTX_CGTT3D_R 0x744 1389 # define PHC(x) ((x) << 0) 1390 # define PHC_MASK (0x1ff << 0) 1391 # define SDC(x) ((x) << 9) 1392 # define SDC_MASK (0x3fff << 9) 1393 #define CG_VDDC3D_OOR 0x748 1394 # define SU(x) ((x) << 23) 1395 # define SU_MASK (0xf << 23) 1396 #define CG_FTV 0x74c 1397 #define CG_FFCT_0 0x750 1398 # define UTC_0(x) ((x) << 0) 1399 # define UTC_0_MASK (0x3ff << 0) 1400 # define DTC_0(x) ((x) << 10) 1401 # define DTC_0_MASK (0x3ff << 10) 1402 1403 #define CG_BSP 0x78c 1404 # define BSP(x) ((x) << 0) 1405 # define BSP_MASK (0xffff << 0) 1406 # define BSU(x) ((x) << 16) 1407 # define BSU_MASK (0xf << 16) 1408 #define CG_RT 0x790 1409 # define FLS(x) ((x) << 0) 1410 # define FLS_MASK (0xffff << 0) 1411 # define FMS(x) ((x) << 16) 1412 # define FMS_MASK (0xffff << 16) 1413 #define CG_LT 0x794 1414 # define FHS(x) ((x) << 0) 1415 # define FHS_MASK (0xffff << 0) 1416 #define CG_GIT 0x798 1417 # define CG_GICST(x) ((x) << 0) 1418 # define CG_GICST_MASK (0xffff << 0) 1419 # define CG_GIPOT(x) ((x) << 16) 1420 # define CG_GIPOT_MASK (0xffff << 16) 1421 1422 #define CG_SSP 0x7a8 1423 # define CG_SST(x) ((x) << 0) 1424 # define CG_SST_MASK (0xffff << 0) 1425 # define CG_SSTU(x) ((x) << 16) 1426 # define CG_SSTU_MASK (0xf << 16) 1427 1428 #define CG_RLC_REQ_AND_RSP 0x7c4 1429 # define RLC_CG_REQ_TYPE_MASK 0xf 1430 # define RLC_CG_REQ_TYPE_SHIFT 0 1431 # define CG_RLC_RSP_TYPE_MASK 0xf0 1432 # define CG_RLC_RSP_TYPE_SHIFT 4 1433 1434 #define CG_FC_T 0x7cc 1435 # define FC_T(x) ((x) << 0) 1436 # define FC_T_MASK (0xffff << 0) 1437 # define FC_TU(x) ((x) << 16) 1438 # define FC_TU_MASK (0x1f << 16) 1439 1440 #define GPIOPAD_MASK 0x1798 1441 #define GPIOPAD_A 0x179c 1442 #define GPIOPAD_EN 0x17a0 1443 1444 #define GRBM_PWR_CNTL 0x800c 1445 # define REQ_TYPE_MASK 0xf 1446 # define REQ_TYPE_SHIFT 0 1447 # define RSP_TYPE_MASK 0xf0 1448 # define RSP_TYPE_SHIFT 4 1449 1450 /* 1451 * UVD 1452 */ 1453 #define UVD_SEMA_ADDR_LOW 0xef00 1454 #define UVD_SEMA_ADDR_HIGH 0xef04 1455 #define UVD_SEMA_CMD 0xef08 1456 1457 #define UVD_GPCOM_VCPU_CMD 0xef0c 1458 #define UVD_GPCOM_VCPU_DATA0 0xef10 1459 #define UVD_GPCOM_VCPU_DATA1 0xef14 1460 #define UVD_ENGINE_CNTL 0xef18 1461 1462 #define UVD_SEMA_CNTL 0xf400 1463 #define UVD_RB_ARB_CTRL 0xf480 1464 1465 #define UVD_LMI_EXT40_ADDR 0xf498 1466 #define UVD_CGC_GATE 0xf4a8 1467 #define UVD_LMI_CTRL2 0xf4f4 1468 #define UVD_MASTINT_EN 0xf500 1469 #define UVD_LMI_ADDR_EXT 0xf594 1470 #define UVD_LMI_CTRL 0xf598 1471 #define UVD_LMI_SWAP_CNTL 0xf5b4 1472 #define UVD_MP_SWAP_CNTL 0xf5bC 1473 #define UVD_MPC_CNTL 0xf5dC 1474 #define UVD_MPC_SET_MUXA0 0xf5e4 1475 #define UVD_MPC_SET_MUXA1 0xf5e8 1476 #define UVD_MPC_SET_MUXB0 0xf5eC 1477 #define UVD_MPC_SET_MUXB1 0xf5f0 1478 #define UVD_MPC_SET_MUX 0xf5f4 1479 #define UVD_MPC_SET_ALU 0xf5f8 1480 1481 #define UVD_VCPU_CNTL 0xf660 1482 #define UVD_SOFT_RESET 0xf680 1483 #define RBC_SOFT_RESET (1<<0) 1484 #define LBSI_SOFT_RESET (1<<1) 1485 #define LMI_SOFT_RESET (1<<2) 1486 #define VCPU_SOFT_RESET (1<<3) 1487 #define CSM_SOFT_RESET (1<<5) 1488 #define CXW_SOFT_RESET (1<<6) 1489 #define TAP_SOFT_RESET (1<<7) 1490 #define LMI_UMC_SOFT_RESET (1<<13) 1491 #define UVD_RBC_IB_BASE 0xf684 1492 #define UVD_RBC_IB_SIZE 0xf688 1493 #define UVD_RBC_RB_BASE 0xf68c 1494 #define UVD_RBC_RB_RPTR 0xf690 1495 #define UVD_RBC_RB_WPTR 0xf694 1496 #define UVD_RBC_RB_WPTR_CNTL 0xf698 1497 1498 #define UVD_STATUS 0xf6bc 1499 1500 #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0 1501 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4 1502 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8 1503 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc 1504 1505 #define UVD_RBC_RB_CNTL 0xf6a4 1506 #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 1507 1508 #define UVD_CONTEXT_ID 0xf6f4 1509 1510 # define UPLL_CTLREQ_MASK 0x00000008 1511 # define UPLL_CTLACK_MASK 0x40000000 1512 # define UPLL_CTLACK2_MASK 0x80000000 1513 1514 /* 1515 * PM4 1516 */ 1517 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1518 (((reg) >> 2) & 0xFFFF) | \ 1519 ((n) & 0x3FFF) << 16) 1520 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1521 (((op) & 0xFF) << 8) | \ 1522 ((n) & 0x3FFF) << 16) 1523 1524 /* Packet 3 types */ 1525 #define PACKET3_NOP 0x10 1526 #define PACKET3_INDIRECT_BUFFER_END 0x17 1527 #define PACKET3_SET_PREDICATION 0x20 1528 #define PACKET3_REG_RMW 0x21 1529 #define PACKET3_COND_EXEC 0x22 1530 #define PACKET3_PRED_EXEC 0x23 1531 #define PACKET3_START_3D_CMDBUF 0x24 1532 #define PACKET3_DRAW_INDEX_2 0x27 1533 #define PACKET3_CONTEXT_CONTROL 0x28 1534 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1535 #define PACKET3_INDEX_TYPE 0x2A 1536 #define PACKET3_DRAW_INDEX 0x2B 1537 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1538 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1539 #define PACKET3_NUM_INSTANCES 0x2F 1540 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1541 #define PACKET3_INDIRECT_BUFFER_MP 0x38 1542 #define PACKET3_MEM_SEMAPHORE 0x39 1543 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1544 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1545 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1546 #define PACKET3_MPEG_INDEX 0x3A 1547 #define PACKET3_COPY_DW 0x3B 1548 #define PACKET3_WAIT_REG_MEM 0x3C 1549 #define PACKET3_MEM_WRITE 0x3D 1550 #define PACKET3_INDIRECT_BUFFER 0x32 1551 #define PACKET3_CP_DMA 0x41 1552 /* 1. header 1553 * 2. SRC_ADDR_LO [31:0] 1554 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1555 * 4. DST_ADDR_LO [31:0] 1556 * 5. DST_ADDR_HI [7:0] 1557 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1558 */ 1559 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1560 /* COMMAND */ 1561 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1562 /* 0 - none 1563 * 1 - 8 in 16 1564 * 2 - 8 in 32 1565 * 3 - 8 in 64 1566 */ 1567 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1568 /* 0 - none 1569 * 1 - 8 in 16 1570 * 2 - 8 in 32 1571 * 3 - 8 in 64 1572 */ 1573 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1574 /* 0 - memory 1575 * 1 - register 1576 */ 1577 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1578 /* 0 - memory 1579 * 1 - register 1580 */ 1581 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1582 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1583 #define PACKET3_SURFACE_SYNC 0x43 1584 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1585 # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ 1586 # define PACKET3_TC_ACTION_ENA (1 << 23) 1587 # define PACKET3_VC_ACTION_ENA (1 << 24) 1588 # define PACKET3_CB_ACTION_ENA (1 << 25) 1589 # define PACKET3_DB_ACTION_ENA (1 << 26) 1590 # define PACKET3_SH_ACTION_ENA (1 << 27) 1591 # define PACKET3_SMX_ACTION_ENA (1 << 28) 1592 #define PACKET3_ME_INITIALIZE 0x44 1593 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1594 #define PACKET3_COND_WRITE 0x45 1595 #define PACKET3_EVENT_WRITE 0x46 1596 #define EVENT_TYPE(x) ((x) << 0) 1597 #define EVENT_INDEX(x) ((x) << 8) 1598 /* 0 - any non-TS event 1599 * 1 - ZPASS_DONE 1600 * 2 - SAMPLE_PIPELINESTAT 1601 * 3 - SAMPLE_STREAMOUTSTAT* 1602 * 4 - *S_PARTIAL_FLUSH 1603 * 5 - TS events 1604 */ 1605 #define PACKET3_EVENT_WRITE_EOP 0x47 1606 #define DATA_SEL(x) ((x) << 29) 1607 /* 0 - discard 1608 * 1 - send low 32bit data 1609 * 2 - send 64bit data 1610 * 3 - send 64bit counter value 1611 */ 1612 #define INT_SEL(x) ((x) << 24) 1613 /* 0 - none 1614 * 1 - interrupt only (DATA_SEL = 0) 1615 * 2 - interrupt when data write is confirmed 1616 */ 1617 #define PACKET3_ONE_REG_WRITE 0x57 1618 #define PACKET3_SET_CONFIG_REG 0x68 1619 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1620 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1621 #define PACKET3_SET_CONTEXT_REG 0x69 1622 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1623 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1624 #define PACKET3_SET_ALU_CONST 0x6A 1625 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1626 #define PACKET3_SET_ALU_CONST_END 0x00032000 1627 #define PACKET3_SET_BOOL_CONST 0x6B 1628 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1629 #define PACKET3_SET_BOOL_CONST_END 0x00040000 1630 #define PACKET3_SET_LOOP_CONST 0x6C 1631 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1632 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 1633 #define PACKET3_SET_RESOURCE 0x6D 1634 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1635 #define PACKET3_SET_RESOURCE_END 0x0003c000 1636 #define PACKET3_SET_SAMPLER 0x6E 1637 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1638 #define PACKET3_SET_SAMPLER_END 0x0003cff0 1639 #define PACKET3_SET_CTL_CONST 0x6F 1640 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1641 #define PACKET3_SET_CTL_CONST_END 0x0003e200 1642 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1643 #define PACKET3_SURFACE_BASE_UPDATE 0x73 1644 1645 #define R_000011_K8_FB_LOCATION 0x11 1646 #define R_000012_MC_MISC_UMA_CNTL 0x12 1647 #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) 1648 #define R_0028F8_MC_INDEX 0x28F8 1649 #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) 1650 #define C_0028F8_MC_IND_ADDR 0xFFFFFE00 1651 #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9) 1652 #define R_0028FC_MC_DATA 0x28FC 1653 1654 #define R_008020_GRBM_SOFT_RESET 0x8020 1655 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1656 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1657 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1658 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1659 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1660 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1661 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1662 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1663 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1664 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1665 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1666 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1667 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1668 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1669 #define R_008010_GRBM_STATUS 0x8010 1670 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1671 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1672 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1673 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1674 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1675 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1676 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1677 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1678 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1679 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1680 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1681 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1682 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1683 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1684 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1685 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1686 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1687 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1688 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1689 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1690 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1691 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1692 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1693 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1694 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1695 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1696 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1697 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1698 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1699 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1700 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1701 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1702 #define G_008010_TA_BUSY(x) (((x) >> 14) & 1) 1703 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1704 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1705 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1706 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1707 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1708 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1709 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1710 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1711 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1712 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1713 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1714 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1715 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1716 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1717 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1718 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1719 #define R_008014_GRBM_STATUS2 0x8014 1720 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1721 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1722 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1723 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1724 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1725 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1726 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1727 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1728 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1729 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1730 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1731 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1732 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1733 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1734 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1735 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1736 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1737 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1738 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1739 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1740 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1741 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1742 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1743 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1744 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1745 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1746 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1747 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1748 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1749 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1750 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1751 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1752 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1753 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1754 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1755 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1756 #define R_000E50_SRBM_STATUS 0x0E50 1757 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1758 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1759 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1760 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1761 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1762 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1763 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1764 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1765 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1766 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1767 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1768 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1769 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1770 #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) 1771 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1772 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1773 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1774 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1775 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1776 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1777 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1778 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1779 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1780 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1781 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1782 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1783 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1784 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1785 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1786 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1787 1788 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1789 1790 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1791 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1792 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1793 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1794 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1795 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1796 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1797 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1798 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1799 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1800 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1801 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1802 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1803 #define C_0280E0_BASE_256B 0x00000000 1804 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1805 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1806 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1807 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1808 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1809 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1810 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1811 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1812 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1813 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1814 #define C_0280C0_BASE_256B 0x00000000 1815 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1816 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1817 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1818 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1819 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1820 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1821 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1822 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1823 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1824 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1825 #define C_0280A0_ENDIAN 0xFFFFFFFC 1826 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1827 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1828 #define C_0280A0_FORMAT 0xFFFFFF03 1829 #define V_0280A0_COLOR_INVALID 0x00000000 1830 #define V_0280A0_COLOR_8 0x00000001 1831 #define V_0280A0_COLOR_4_4 0x00000002 1832 #define V_0280A0_COLOR_3_3_2 0x00000003 1833 #define V_0280A0_COLOR_16 0x00000005 1834 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1835 #define V_0280A0_COLOR_8_8 0x00000007 1836 #define V_0280A0_COLOR_5_6_5 0x00000008 1837 #define V_0280A0_COLOR_6_5_5 0x00000009 1838 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1839 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1840 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1841 #define V_0280A0_COLOR_32 0x0000000D 1842 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1843 #define V_0280A0_COLOR_16_16 0x0000000F 1844 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1845 #define V_0280A0_COLOR_8_24 0x00000011 1846 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1847 #define V_0280A0_COLOR_24_8 0x00000013 1848 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1849 #define V_0280A0_COLOR_10_11_11 0x00000015 1850 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1851 #define V_0280A0_COLOR_11_11_10 0x00000017 1852 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1853 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1854 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1855 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1856 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1857 #define V_0280A0_COLOR_32_32 0x0000001D 1858 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1859 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1860 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1861 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1862 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1863 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1864 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1865 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1866 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1867 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1868 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1869 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1870 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1871 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1872 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1873 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1874 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1875 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1876 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1877 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1878 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1879 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1880 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1881 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1882 #define V_0280A0_TILE_DISABLE 0 1883 #define V_0280A0_CLEAR_ENABLE 1 1884 #define V_0280A0_FRAG_ENABLE 2 1885 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1886 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1887 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1888 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1889 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1890 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1891 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1892 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1893 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1894 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1895 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1896 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1897 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1898 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1899 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1900 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1901 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1902 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1903 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1904 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1905 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1906 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1907 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1908 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1909 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1910 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1911 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1912 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1913 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1914 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1915 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1916 #define R_028060_CB_COLOR0_SIZE 0x028060 1917 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1918 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1919 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1920 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1921 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1922 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1923 #define R_028064_CB_COLOR1_SIZE 0x028064 1924 #define R_028068_CB_COLOR2_SIZE 0x028068 1925 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1926 #define R_028070_CB_COLOR4_SIZE 0x028070 1927 #define R_028074_CB_COLOR5_SIZE 0x028074 1928 #define R_028078_CB_COLOR6_SIZE 0x028078 1929 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1930 #define R_028238_CB_TARGET_MASK 0x028238 1931 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1932 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1933 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1934 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1935 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1936 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1937 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1938 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1939 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1940 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1941 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1942 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1943 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1944 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1945 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1946 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1947 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1948 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1949 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1950 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1951 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1952 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1953 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1954 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1955 #define R_02823C_CB_SHADER_MASK 0x02823C 1956 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1957 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1958 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1959 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1960 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1961 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1962 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1963 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1964 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1965 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1966 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1967 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1968 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1969 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1970 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1971 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1972 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1973 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1974 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1975 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1976 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1977 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1978 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1979 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1980 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1981 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1982 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1983 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1984 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1985 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1986 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1987 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1988 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1989 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1990 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1991 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1992 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1993 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1994 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1995 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1996 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1997 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1998 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1999 #define C_028B20_SIZE 0x00000000 2000 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 2001 #define S_038000_DIM(x) (((x) & 0x7) << 0) 2002 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 2003 #define C_038000_DIM 0xFFFFFFF8 2004 #define V_038000_SQ_TEX_DIM_1D 0x00000000 2005 #define V_038000_SQ_TEX_DIM_2D 0x00000001 2006 #define V_038000_SQ_TEX_DIM_3D 0x00000002 2007 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 2008 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 2009 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 2010 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 2011 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 2012 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 2013 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 2014 #define C_038000_TILE_MODE 0xFFFFFF87 2015 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 2016 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 2017 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 2018 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 2019 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 2020 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 2021 #define C_038000_TILE_TYPE 0xFFFFFF7F 2022 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 2023 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 2024 #define C_038000_PITCH 0xFFF800FF 2025 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 2026 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 2027 #define C_038000_TEX_WIDTH 0x0007FFFF 2028 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 2029 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 2030 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 2031 #define C_038004_TEX_HEIGHT 0xFFFFE000 2032 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 2033 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 2034 #define C_038004_TEX_DEPTH 0xFC001FFF 2035 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 2036 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 2037 #define C_038004_DATA_FORMAT 0x03FFFFFF 2038 #define V_038004_COLOR_INVALID 0x00000000 2039 #define V_038004_COLOR_8 0x00000001 2040 #define V_038004_COLOR_4_4 0x00000002 2041 #define V_038004_COLOR_3_3_2 0x00000003 2042 #define V_038004_COLOR_16 0x00000005 2043 #define V_038004_COLOR_16_FLOAT 0x00000006 2044 #define V_038004_COLOR_8_8 0x00000007 2045 #define V_038004_COLOR_5_6_5 0x00000008 2046 #define V_038004_COLOR_6_5_5 0x00000009 2047 #define V_038004_COLOR_1_5_5_5 0x0000000A 2048 #define V_038004_COLOR_4_4_4_4 0x0000000B 2049 #define V_038004_COLOR_5_5_5_1 0x0000000C 2050 #define V_038004_COLOR_32 0x0000000D 2051 #define V_038004_COLOR_32_FLOAT 0x0000000E 2052 #define V_038004_COLOR_16_16 0x0000000F 2053 #define V_038004_COLOR_16_16_FLOAT 0x00000010 2054 #define V_038004_COLOR_8_24 0x00000011 2055 #define V_038004_COLOR_8_24_FLOAT 0x00000012 2056 #define V_038004_COLOR_24_8 0x00000013 2057 #define V_038004_COLOR_24_8_FLOAT 0x00000014 2058 #define V_038004_COLOR_10_11_11 0x00000015 2059 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 2060 #define V_038004_COLOR_11_11_10 0x00000017 2061 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 2062 #define V_038004_COLOR_2_10_10_10 0x00000019 2063 #define V_038004_COLOR_8_8_8_8 0x0000001A 2064 #define V_038004_COLOR_10_10_10_2 0x0000001B 2065 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 2066 #define V_038004_COLOR_32_32 0x0000001D 2067 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 2068 #define V_038004_COLOR_16_16_16_16 0x0000001F 2069 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 2070 #define V_038004_COLOR_32_32_32_32 0x00000022 2071 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 2072 #define V_038004_FMT_1 0x00000025 2073 #define V_038004_FMT_GB_GR 0x00000027 2074 #define V_038004_FMT_BG_RG 0x00000028 2075 #define V_038004_FMT_32_AS_8 0x00000029 2076 #define V_038004_FMT_32_AS_8_8 0x0000002A 2077 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 2078 #define V_038004_FMT_8_8_8 0x0000002C 2079 #define V_038004_FMT_16_16_16 0x0000002D 2080 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 2081 #define V_038004_FMT_32_32_32 0x0000002F 2082 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 2083 #define V_038004_FMT_BC1 0x00000031 2084 #define V_038004_FMT_BC2 0x00000032 2085 #define V_038004_FMT_BC3 0x00000033 2086 #define V_038004_FMT_BC4 0x00000034 2087 #define V_038004_FMT_BC5 0x00000035 2088 #define V_038004_FMT_BC6 0x00000036 2089 #define V_038004_FMT_BC7 0x00000037 2090 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 2091 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 2092 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 2093 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 2094 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 2095 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 2096 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 2097 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 2098 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 2099 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 2100 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 2101 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 2102 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 2103 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 2104 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 2105 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 2106 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 2107 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 2108 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 2109 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 2110 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 2111 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 2112 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 2113 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 2114 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 2115 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 2116 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 2117 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 2118 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 2119 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 2120 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 2121 #define C_038010_DST_SEL_X 0xFFF8FFFF 2122 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 2123 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 2124 #define C_038010_DST_SEL_Y 0xFFC7FFFF 2125 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 2126 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 2127 #define C_038010_DST_SEL_Z 0xFE3FFFFF 2128 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 2129 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 2130 #define C_038010_DST_SEL_W 0xF1FFFFFF 2131 # define SQ_SEL_X 0 2132 # define SQ_SEL_Y 1 2133 # define SQ_SEL_Z 2 2134 # define SQ_SEL_W 3 2135 # define SQ_SEL_0 4 2136 # define SQ_SEL_1 5 2137 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 2138 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 2139 #define C_038010_BASE_LEVEL 0x0FFFFFFF 2140 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 2141 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 2142 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 2143 #define C_038014_LAST_LEVEL 0xFFFFFFF0 2144 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 2145 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 2146 #define C_038014_BASE_ARRAY 0xFFFE000F 2147 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 2148 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 2149 #define C_038014_LAST_ARRAY 0xC001FFFF 2150 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 2151 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2152 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2153 #define C_0288A8_ITEMSIZE 0xFFFF8000 2154 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 2155 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2156 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2157 #define C_008C44_MEM_SIZE 0x00000000 2158 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 2159 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2160 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2161 #define C_0288B0_ITEMSIZE 0xFFFF8000 2162 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 2163 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2164 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2165 #define C_008C54_MEM_SIZE 0x00000000 2166 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 2167 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2168 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2169 #define C_0288C0_ITEMSIZE 0xFFFF8000 2170 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 2171 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2172 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2173 #define C_008C74_MEM_SIZE 0x00000000 2174 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 2175 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2176 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2177 #define C_0288B4_ITEMSIZE 0xFFFF8000 2178 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 2179 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2180 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2181 #define C_008C5C_MEM_SIZE 0x00000000 2182 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 2183 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2184 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2185 #define C_0288AC_ITEMSIZE 0xFFFF8000 2186 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 2187 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2188 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2189 #define C_008C4C_MEM_SIZE 0x00000000 2190 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 2191 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2192 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2193 #define C_0288BC_ITEMSIZE 0xFFFF8000 2194 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 2195 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2196 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2197 #define C_008C6C_MEM_SIZE 0x00000000 2198 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 2199 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2200 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2201 #define C_0288C4_ITEMSIZE 0xFFFF8000 2202 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 2203 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2204 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2205 #define C_008C7C_MEM_SIZE 0x00000000 2206 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 2207 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2208 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2209 #define C_0288B8_ITEMSIZE 0xFFFF8000 2210 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 2211 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2212 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2213 #define C_008C64_MEM_SIZE 0x00000000 2214 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 2215 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2216 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2217 #define C_0288C8_ITEMSIZE 0xFFFF8000 2218 #define R_028010_DB_DEPTH_INFO 0x028010 2219 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 2220 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 2221 #define C_028010_FORMAT 0xFFFFFFF8 2222 #define V_028010_DEPTH_INVALID 0x00000000 2223 #define V_028010_DEPTH_16 0x00000001 2224 #define V_028010_DEPTH_X8_24 0x00000002 2225 #define V_028010_DEPTH_8_24 0x00000003 2226 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 2227 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 2228 #define V_028010_DEPTH_32_FLOAT 0x00000006 2229 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 2230 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 2231 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 2232 #define C_028010_READ_SIZE 0xFFFFFFF7 2233 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 2234 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 2235 #define C_028010_ARRAY_MODE 0xFFF87FFF 2236 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 2237 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 2238 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 2239 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 2240 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 2241 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 2242 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 2243 #define C_028010_TILE_COMPACT 0xFBFFFFFF 2244 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 2245 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 2246 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 2247 #define R_028000_DB_DEPTH_SIZE 0x028000 2248 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 2249 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 2250 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 2251 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 2252 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 2253 #define C_028000_SLICE_TILE_MAX 0xC00003FF 2254 #define R_028004_DB_DEPTH_VIEW 0x028004 2255 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 2256 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 2257 #define C_028004_SLICE_START 0xFFFFF800 2258 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 2259 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 2260 #define C_028004_SLICE_MAX 0xFF001FFF 2261 #define R_028800_DB_DEPTH_CONTROL 0x028800 2262 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 2263 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 2264 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 2265 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 2266 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 2267 #define C_028800_Z_ENABLE 0xFFFFFFFD 2268 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 2269 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 2270 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 2271 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 2272 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 2273 #define C_028800_ZFUNC 0xFFFFFF8F 2274 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 2275 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 2276 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 2277 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 2278 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 2279 #define C_028800_STENCILFUNC 0xFFFFF8FF 2280 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 2281 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 2282 #define C_028800_STENCILFAIL 0xFFFFC7FF 2283 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 2284 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 2285 #define C_028800_STENCILZPASS 0xFFFE3FFF 2286 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 2287 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 2288 #define C_028800_STENCILZFAIL 0xFFF1FFFF 2289 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 2290 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 2291 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 2292 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 2293 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 2294 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 2295 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 2296 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 2297 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 2298 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 2299 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 2300 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 2301 2302 #endif 2303
Indexes created Wed Oct 01 15:09:59 GMT 2025