radeon.h revision 1.1.1.3
1 /* $NetBSD: radeon.h,v 1.1.1.3 2021/12/18 20:15:45 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <linux/atomic.h> 66 #include <linux/wait.h> 67 #include <linux/list.h> 68 #include <linux/kref.h> 69 #include <linux/interval_tree.h> 70 #include <linux/hashtable.h> 71 #include <linux/dma-fence.h> 72 73 #ifdef CONFIG_MMU_NOTIFIER 74 #include <linux/mmu_notifier.h> 75 #endif 76 77 #include <drm/ttm/ttm_bo_api.h> 78 #include <drm/ttm/ttm_bo_driver.h> 79 #include <drm/ttm/ttm_placement.h> 80 #include <drm/ttm/ttm_module.h> 81 #include <drm/ttm/ttm_execbuf_util.h> 82 83 #include <drm/drm_gem.h> 84 85 #include "radeon_family.h" 86 #include "radeon_mode.h" 87 #include "radeon_reg.h" 88 89 /* 90 * Modules parameters. 91 */ 92 extern int radeon_no_wb; 93 extern int radeon_modeset; 94 extern int radeon_dynclks; 95 extern int radeon_r4xx_atom; 96 extern int radeon_agpmode; 97 extern int radeon_vram_limit; 98 extern int radeon_gart_size; 99 extern int radeon_benchmarking; 100 extern int radeon_testing; 101 extern int radeon_connector_table; 102 extern int radeon_tv; 103 extern int radeon_audio; 104 extern int radeon_disp_priority; 105 extern int radeon_hw_i2c; 106 extern int radeon_pcie_gen2; 107 extern int radeon_msi; 108 extern int radeon_lockup_timeout; 109 extern int radeon_fastfb; 110 extern int radeon_dpm; 111 extern int radeon_aspm; 112 extern int radeon_runtime_pm; 113 extern int radeon_hard_reset; 114 extern int radeon_vm_size; 115 extern int radeon_vm_block_size; 116 extern int radeon_deep_color; 117 extern int radeon_use_pflipirq; 118 extern int radeon_bapm; 119 extern int radeon_backlight; 120 extern int radeon_auxch; 121 extern int radeon_mst; 122 extern int radeon_uvd; 123 extern int radeon_vce; 124 extern int radeon_si_support; 125 extern int radeon_cik_support; 126 127 /* 128 * Copy from radeon_drv.h so we don't have to include both and have conflicting 129 * symbol; 130 */ 131 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 132 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 133 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 134 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 135 #define RADEON_IB_POOL_SIZE 16 136 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 137 #define RADEONFB_CONN_LIMIT 4 138 #define RADEON_BIOS_NUM_SCRATCH 8 139 140 /* internal ring indices */ 141 /* r1xx+ has gfx CP ring */ 142 #define RADEON_RING_TYPE_GFX_INDEX 0 143 144 /* cayman has 2 compute CP rings */ 145 #define CAYMAN_RING_TYPE_CP1_INDEX 1 146 #define CAYMAN_RING_TYPE_CP2_INDEX 2 147 148 /* R600+ has an async dma ring */ 149 #define R600_RING_TYPE_DMA_INDEX 3 150 /* cayman add a second async dma ring */ 151 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 152 153 /* R600+ */ 154 #define R600_RING_TYPE_UVD_INDEX 5 155 156 /* TN+ */ 157 #define TN_RING_TYPE_VCE1_INDEX 6 158 #define TN_RING_TYPE_VCE2_INDEX 7 159 160 /* max number of rings */ 161 #define RADEON_NUM_RINGS 8 162 163 /* number of hw syncs before falling back on blocking */ 164 #define RADEON_NUM_SYNCS 4 165 166 /* hardcode those limit for now */ 167 #define RADEON_VA_IB_OFFSET (1 << 20) 168 #define RADEON_VA_RESERVED_SIZE (8 << 20) 169 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 170 171 /* hard reset data */ 172 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 173 174 /* reset flags */ 175 #define RADEON_RESET_GFX (1 << 0) 176 #define RADEON_RESET_COMPUTE (1 << 1) 177 #define RADEON_RESET_DMA (1 << 2) 178 #define RADEON_RESET_CP (1 << 3) 179 #define RADEON_RESET_GRBM (1 << 4) 180 #define RADEON_RESET_DMA1 (1 << 5) 181 #define RADEON_RESET_RLC (1 << 6) 182 #define RADEON_RESET_SEM (1 << 7) 183 #define RADEON_RESET_IH (1 << 8) 184 #define RADEON_RESET_VMC (1 << 9) 185 #define RADEON_RESET_MC (1 << 10) 186 #define RADEON_RESET_DISPLAY (1 << 11) 187 188 /* CG block flags */ 189 #define RADEON_CG_BLOCK_GFX (1 << 0) 190 #define RADEON_CG_BLOCK_MC (1 << 1) 191 #define RADEON_CG_BLOCK_SDMA (1 << 2) 192 #define RADEON_CG_BLOCK_UVD (1 << 3) 193 #define RADEON_CG_BLOCK_VCE (1 << 4) 194 #define RADEON_CG_BLOCK_HDP (1 << 5) 195 #define RADEON_CG_BLOCK_BIF (1 << 6) 196 197 /* CG flags */ 198 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 199 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 200 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 201 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 202 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 203 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 204 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 205 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 206 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 207 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 208 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 209 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 210 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 211 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 212 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 213 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 214 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 215 216 /* PG flags */ 217 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 218 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 219 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 220 #define RADEON_PG_SUPPORT_UVD (1 << 3) 221 #define RADEON_PG_SUPPORT_VCE (1 << 4) 222 #define RADEON_PG_SUPPORT_CP (1 << 5) 223 #define RADEON_PG_SUPPORT_GDS (1 << 6) 224 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 225 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 226 #define RADEON_PG_SUPPORT_ACP (1 << 9) 227 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 228 229 /* max cursor sizes (in pixels) */ 230 #define CURSOR_WIDTH 64 231 #define CURSOR_HEIGHT 64 232 233 #define CIK_CURSOR_WIDTH 128 234 #define CIK_CURSOR_HEIGHT 128 235 236 /* 237 * Errata workarounds. 238 */ 239 enum radeon_pll_errata { 240 CHIP_ERRATA_R300_CG = 0x00000001, 241 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 242 CHIP_ERRATA_PLL_DELAY = 0x00000004 243 }; 244 245 246 struct radeon_device; 247 248 249 /* 250 * BIOS. 251 */ 252 bool radeon_get_bios(struct radeon_device *rdev); 253 254 /* 255 * Dummy page 256 */ 257 struct radeon_dummy_page { 258 uint64_t entry; 259 struct page *page; 260 dma_addr_t addr; 261 }; 262 int radeon_dummy_page_init(struct radeon_device *rdev); 263 void radeon_dummy_page_fini(struct radeon_device *rdev); 264 265 266 /* 267 * Clocks 268 */ 269 struct radeon_clock { 270 struct radeon_pll p1pll; 271 struct radeon_pll p2pll; 272 struct radeon_pll dcpll; 273 struct radeon_pll spll; 274 struct radeon_pll mpll; 275 /* 10 Khz units */ 276 uint32_t default_mclk; 277 uint32_t default_sclk; 278 uint32_t default_dispclk; 279 uint32_t current_dispclk; 280 uint32_t dp_extclk; 281 uint32_t max_pixel_clock; 282 uint32_t vco_freq; 283 }; 284 285 /* 286 * Power management 287 */ 288 int radeon_pm_init(struct radeon_device *rdev); 289 int radeon_pm_late_init(struct radeon_device *rdev); 290 void radeon_pm_fini(struct radeon_device *rdev); 291 void radeon_pm_compute_clocks(struct radeon_device *rdev); 292 void radeon_pm_suspend(struct radeon_device *rdev); 293 void radeon_pm_resume(struct radeon_device *rdev); 294 void radeon_combios_get_power_modes(struct radeon_device *rdev); 295 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 296 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 297 u8 clock_type, 298 u32 clock, 299 bool strobe_mode, 300 struct atom_clock_dividers *dividers); 301 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 302 u32 clock, 303 bool strobe_mode, 304 struct atom_mpll_param *mpll_param); 305 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 306 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 307 u16 voltage_level, u8 voltage_type, 308 u32 *gpio_value, u32 *gpio_mask); 309 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 310 u32 eng_clock, u32 mem_clock); 311 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 312 u8 voltage_type, u16 *voltage_step); 313 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 314 u16 voltage_id, u16 *voltage); 315 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 316 u16 *voltage, 317 u16 leakage_idx); 318 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 319 u16 *leakage_id); 320 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 321 u16 *vddc, u16 *vddci, 322 u16 virtual_voltage_id, 323 u16 vbios_voltage_id); 324 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 325 u16 virtual_voltage_id, 326 u16 *voltage); 327 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 328 u8 voltage_type, 329 u16 nominal_voltage, 330 u16 *true_voltage); 331 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 332 u8 voltage_type, u16 *min_voltage); 333 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 334 u8 voltage_type, u16 *max_voltage); 335 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode, 337 struct atom_voltage_table *voltage_table); 338 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 339 u8 voltage_type, u8 voltage_mode); 340 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 341 u8 voltage_type, 342 u8 *svd_gpio_id, u8 *svc_gpio_id); 343 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 344 u32 mem_clock); 345 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 346 u32 mem_clock); 347 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 348 u8 module_index, 349 struct atom_mc_reg_table *reg_table); 350 int radeon_atom_get_memory_info(struct radeon_device *rdev, 351 u8 module_index, struct atom_memory_info *mem_info); 352 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 353 bool gddr5, u8 module_index, 354 struct atom_memory_clock_range_table *mclk_range_table); 355 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 356 u16 voltage_id, u16 *voltage); 357 void rs690_pm_info(struct radeon_device *rdev); 358 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 359 unsigned *bankh, unsigned *mtaspect, 360 unsigned *tile_split); 361 362 /* 363 * Fences. 364 */ 365 struct radeon_fence_driver { 366 struct radeon_device *rdev; 367 uint32_t scratch_reg; 368 uint64_t gpu_addr; 369 volatile uint32_t *cpu_addr; 370 /* sync_seq is protected by ring emission lock */ 371 uint64_t sync_seq[RADEON_NUM_RINGS]; 372 atomic64_t last_seq; 373 bool initialized, delayed_irq; 374 struct delayed_work lockup_work; 375 }; 376 377 struct radeon_fence { 378 struct dma_fence base; 379 380 struct radeon_device *rdev; 381 uint64_t seq; 382 /* RB, DMA, etc. */ 383 unsigned ring; 384 bool is_vm_update; 385 386 wait_queue_entry_t fence_wake; 387 }; 388 389 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 390 int radeon_fence_driver_init(struct radeon_device *rdev); 391 void radeon_fence_driver_fini(struct radeon_device *rdev); 392 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 393 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 394 void radeon_fence_process(struct radeon_device *rdev, int ring); 395 bool radeon_fence_signaled(struct radeon_fence *fence); 396 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 397 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 398 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 399 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 400 int radeon_fence_wait_any(struct radeon_device *rdev, 401 struct radeon_fence **fences, 402 bool intr); 403 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 404 void radeon_fence_unref(struct radeon_fence **fence); 405 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 406 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 407 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 408 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 409 struct radeon_fence *b) 410 { 411 if (!a) { 412 return b; 413 } 414 415 if (!b) { 416 return a; 417 } 418 419 BUG_ON(a->ring != b->ring); 420 421 if (a->seq > b->seq) { 422 return a; 423 } else { 424 return b; 425 } 426 } 427 428 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 429 struct radeon_fence *b) 430 { 431 if (!a) { 432 return false; 433 } 434 435 if (!b) { 436 return true; 437 } 438 439 BUG_ON(a->ring != b->ring); 440 441 return a->seq < b->seq; 442 } 443 444 /* 445 * Tiling registers 446 */ 447 struct radeon_surface_reg { 448 struct radeon_bo *bo; 449 }; 450 451 #define RADEON_GEM_MAX_SURFACES 8 452 453 /* 454 * TTM. 455 */ 456 struct radeon_mman { 457 struct ttm_bo_device bdev; 458 bool initialized; 459 460 #if defined(CONFIG_DEBUG_FS) 461 struct dentry *vram; 462 struct dentry *gtt; 463 #endif 464 }; 465 466 struct radeon_bo_list { 467 struct radeon_bo *robj; 468 struct ttm_validate_buffer tv; 469 uint64_t gpu_offset; 470 unsigned preferred_domains; 471 unsigned allowed_domains; 472 uint32_t tiling_flags; 473 }; 474 475 /* bo virtual address in a specific vm */ 476 struct radeon_bo_va { 477 /* protected by bo being reserved */ 478 struct list_head bo_list; 479 uint32_t flags; 480 struct radeon_fence *last_pt_update; 481 unsigned ref_count; 482 483 /* protected by vm mutex */ 484 struct interval_tree_node it; 485 struct list_head vm_status; 486 487 /* constant after initialization */ 488 struct radeon_vm *vm; 489 struct radeon_bo *bo; 490 }; 491 492 struct radeon_bo { 493 /* Protected by gem.mutex */ 494 struct list_head list; 495 /* Protected by tbo.reserved */ 496 u32 initial_domain; 497 struct ttm_place placements[4]; 498 struct ttm_placement placement; 499 struct ttm_buffer_object tbo; 500 struct ttm_bo_kmap_obj kmap; 501 u32 flags; 502 unsigned pin_count; 503 void *kptr; 504 u32 tiling_flags; 505 u32 pitch; 506 int surface_reg; 507 unsigned prime_shared_count; 508 /* list of all virtual address to which this bo 509 * is associated to 510 */ 511 struct list_head va; 512 /* Constant after initialization */ 513 struct radeon_device *rdev; 514 515 struct ttm_bo_kmap_obj dma_buf_vmap; 516 pid_t pid; 517 518 #ifdef CONFIG_MMU_NOTIFIER 519 struct mmu_interval_notifier notifier; 520 #endif 521 }; 522 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 523 524 int radeon_gem_debugfs_init(struct radeon_device *rdev); 525 526 /* sub-allocation manager, it has to be protected by another lock. 527 * By conception this is an helper for other part of the driver 528 * like the indirect buffer or semaphore, which both have their 529 * locking. 530 * 531 * Principe is simple, we keep a list of sub allocation in offset 532 * order (first entry has offset == 0, last entry has the highest 533 * offset). 534 * 535 * When allocating new object we first check if there is room at 536 * the end total_size - (last_object_offset + last_object_size) >= 537 * alloc_size. If so we allocate new object there. 538 * 539 * When there is not enough room at the end, we start waiting for 540 * each sub object until we reach object_offset+object_size >= 541 * alloc_size, this object then become the sub object we return. 542 * 543 * Alignment can't be bigger than page size. 544 * 545 * Hole are not considered for allocation to keep things simple. 546 * Assumption is that there won't be hole (all object on same 547 * alignment). 548 */ 549 struct radeon_sa_manager { 550 wait_queue_head_t wq; 551 struct radeon_bo *bo; 552 struct list_head *hole; 553 struct list_head flist[RADEON_NUM_RINGS]; 554 struct list_head olist; 555 unsigned size; 556 uint64_t gpu_addr; 557 void *cpu_ptr; 558 uint32_t domain; 559 uint32_t align; 560 }; 561 562 struct radeon_sa_bo; 563 564 /* sub-allocation buffer */ 565 struct radeon_sa_bo { 566 struct list_head olist; 567 struct list_head flist; 568 struct radeon_sa_manager *manager; 569 unsigned soffset; 570 unsigned eoffset; 571 struct radeon_fence *fence; 572 }; 573 574 /* 575 * GEM objects. 576 */ 577 struct radeon_gem { 578 struct mutex mutex; 579 struct list_head objects; 580 }; 581 582 int radeon_gem_init(struct radeon_device *rdev); 583 void radeon_gem_fini(struct radeon_device *rdev); 584 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 585 int alignment, int initial_domain, 586 u32 flags, bool kernel, 587 struct drm_gem_object **obj); 588 589 int radeon_mode_dumb_create(struct drm_file *file_priv, 590 struct drm_device *dev, 591 struct drm_mode_create_dumb *args); 592 int radeon_mode_dumb_mmap(struct drm_file *filp, 593 struct drm_device *dev, 594 uint32_t handle, uint64_t *offset_p); 595 596 /* 597 * Semaphores. 598 */ 599 struct radeon_semaphore { 600 struct radeon_sa_bo *sa_bo; 601 signed waiters; 602 uint64_t gpu_addr; 603 }; 604 605 int radeon_semaphore_create(struct radeon_device *rdev, 606 struct radeon_semaphore **semaphore); 607 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 608 struct radeon_semaphore *semaphore); 609 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 610 struct radeon_semaphore *semaphore); 611 void radeon_semaphore_free(struct radeon_device *rdev, 612 struct radeon_semaphore **semaphore, 613 struct radeon_fence *fence); 614 615 /* 616 * Synchronization 617 */ 618 struct radeon_sync { 619 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 620 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 621 struct radeon_fence *last_vm_update; 622 }; 623 624 void radeon_sync_create(struct radeon_sync *sync); 625 void radeon_sync_fence(struct radeon_sync *sync, 626 struct radeon_fence *fence); 627 int radeon_sync_resv(struct radeon_device *rdev, 628 struct radeon_sync *sync, 629 struct dma_resv *resv, 630 bool shared); 631 int radeon_sync_rings(struct radeon_device *rdev, 632 struct radeon_sync *sync, 633 int waiting_ring); 634 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 635 struct radeon_fence *fence); 636 637 /* 638 * GART structures, functions & helpers 639 */ 640 struct radeon_mc; 641 642 #define RADEON_GPU_PAGE_SIZE 4096 643 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 644 #define RADEON_GPU_PAGE_SHIFT 12 645 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 646 647 #define RADEON_GART_PAGE_DUMMY 0 648 #define RADEON_GART_PAGE_VALID (1 << 0) 649 #define RADEON_GART_PAGE_READ (1 << 1) 650 #define RADEON_GART_PAGE_WRITE (1 << 2) 651 #define RADEON_GART_PAGE_SNOOP (1 << 3) 652 653 struct radeon_gart { 654 dma_addr_t table_addr; 655 struct radeon_bo *robj; 656 void *ptr; 657 unsigned num_gpu_pages; 658 unsigned num_cpu_pages; 659 unsigned table_size; 660 struct page **pages; 661 uint64_t *pages_entry; 662 bool ready; 663 }; 664 665 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 666 void radeon_gart_table_ram_free(struct radeon_device *rdev); 667 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 668 void radeon_gart_table_vram_free(struct radeon_device *rdev); 669 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 670 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 671 int radeon_gart_init(struct radeon_device *rdev); 672 void radeon_gart_fini(struct radeon_device *rdev); 673 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 674 int pages); 675 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 676 int pages, struct page **pagelist, 677 dma_addr_t *dma_addr, uint32_t flags); 678 679 680 /* 681 * GPU MC structures, functions & helpers 682 */ 683 struct radeon_mc { 684 resource_size_t aper_size; 685 resource_size_t aper_base; 686 resource_size_t agp_base; 687 /* for some chips with <= 32MB we need to lie 688 * about vram size near mc fb location */ 689 u64 mc_vram_size; 690 u64 visible_vram_size; 691 u64 gtt_size; 692 u64 gtt_start; 693 u64 gtt_end; 694 u64 vram_start; 695 u64 vram_end; 696 unsigned vram_width; 697 u64 real_vram_size; 698 int vram_mtrr; 699 bool vram_is_ddr; 700 bool igp_sideport_enabled; 701 u64 gtt_base_align; 702 u64 mc_mask; 703 }; 704 705 bool radeon_combios_sideport_present(struct radeon_device *rdev); 706 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 707 708 /* 709 * GPU scratch registers structures, functions & helpers 710 */ 711 struct radeon_scratch { 712 unsigned num_reg; 713 uint32_t reg_base; 714 bool free[32]; 715 uint32_t reg[32]; 716 }; 717 718 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 719 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 720 721 /* 722 * GPU doorbell structures, functions & helpers 723 */ 724 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 725 726 struct radeon_doorbell { 727 /* doorbell mmio */ 728 resource_size_t base; 729 resource_size_t size; 730 u32 __iomem *ptr; 731 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 732 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 733 }; 734 735 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 736 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 737 738 /* 739 * IRQS. 740 */ 741 742 struct radeon_flip_work { 743 struct work_struct flip_work; 744 struct work_struct unpin_work; 745 struct radeon_device *rdev; 746 int crtc_id; 747 u32 target_vblank; 748 uint64_t base; 749 struct drm_pending_vblank_event *event; 750 struct radeon_bo *old_rbo; 751 struct dma_fence *fence; 752 bool async; 753 }; 754 755 struct r500_irq_stat_regs { 756 u32 disp_int; 757 u32 hdmi0_status; 758 }; 759 760 struct r600_irq_stat_regs { 761 u32 disp_int; 762 u32 disp_int_cont; 763 u32 disp_int_cont2; 764 u32 d1grph_int; 765 u32 d2grph_int; 766 u32 hdmi0_status; 767 u32 hdmi1_status; 768 }; 769 770 struct evergreen_irq_stat_regs { 771 u32 disp_int[6]; 772 u32 grph_int[6]; 773 u32 afmt_status[6]; 774 }; 775 776 struct cik_irq_stat_regs { 777 u32 disp_int; 778 u32 disp_int_cont; 779 u32 disp_int_cont2; 780 u32 disp_int_cont3; 781 u32 disp_int_cont4; 782 u32 disp_int_cont5; 783 u32 disp_int_cont6; 784 u32 d1grph_int; 785 u32 d2grph_int; 786 u32 d3grph_int; 787 u32 d4grph_int; 788 u32 d5grph_int; 789 u32 d6grph_int; 790 }; 791 792 union radeon_irq_stat_regs { 793 struct r500_irq_stat_regs r500; 794 struct r600_irq_stat_regs r600; 795 struct evergreen_irq_stat_regs evergreen; 796 struct cik_irq_stat_regs cik; 797 }; 798 799 struct radeon_irq { 800 bool installed; 801 spinlock_t lock; 802 atomic_t ring_int[RADEON_NUM_RINGS]; 803 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 804 atomic_t pflip[RADEON_MAX_CRTCS]; 805 wait_queue_head_t vblank_queue; 806 bool hpd[RADEON_MAX_HPD_PINS]; 807 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 808 union radeon_irq_stat_regs stat_regs; 809 bool dpm_thermal; 810 }; 811 812 int radeon_irq_kms_init(struct radeon_device *rdev); 813 void radeon_irq_kms_fini(struct radeon_device *rdev); 814 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 815 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 816 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 817 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 818 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 819 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 820 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 821 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 822 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 823 824 /* 825 * CP & rings. 826 */ 827 828 struct radeon_ib { 829 struct radeon_sa_bo *sa_bo; 830 uint32_t length_dw; 831 uint64_t gpu_addr; 832 uint32_t *ptr; 833 int ring; 834 struct radeon_fence *fence; 835 struct radeon_vm *vm; 836 bool is_const_ib; 837 struct radeon_sync sync; 838 }; 839 840 struct radeon_ring { 841 struct radeon_bo *ring_obj; 842 volatile uint32_t *ring; 843 unsigned rptr_offs; 844 unsigned rptr_save_reg; 845 u64 next_rptr_gpu_addr; 846 volatile u32 *next_rptr_cpu_addr; 847 unsigned wptr; 848 unsigned wptr_old; 849 unsigned ring_size; 850 unsigned ring_free_dw; 851 int count_dw; 852 atomic_t last_rptr; 853 atomic64_t last_activity; 854 uint64_t gpu_addr; 855 uint32_t align_mask; 856 uint32_t ptr_mask; 857 bool ready; 858 u32 nop; 859 u32 idx; 860 u64 last_semaphore_signal_addr; 861 u64 last_semaphore_wait_addr; 862 /* for CIK queues */ 863 u32 me; 864 u32 pipe; 865 u32 queue; 866 struct radeon_bo *mqd_obj; 867 u32 doorbell_index; 868 unsigned wptr_offs; 869 }; 870 871 struct radeon_mec { 872 struct radeon_bo *hpd_eop_obj; 873 u64 hpd_eop_gpu_addr; 874 u32 num_pipe; 875 u32 num_mec; 876 u32 num_queue; 877 }; 878 879 /* 880 * VM 881 */ 882 883 /* maximum number of VMIDs */ 884 #define RADEON_NUM_VM 16 885 886 /* number of entries in page table */ 887 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 888 889 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 890 #define RADEON_VM_PTB_ALIGN_SIZE 32768 891 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 892 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 893 894 #define R600_PTE_VALID (1 << 0) 895 #define R600_PTE_SYSTEM (1 << 1) 896 #define R600_PTE_SNOOPED (1 << 2) 897 #define R600_PTE_READABLE (1 << 5) 898 #define R600_PTE_WRITEABLE (1 << 6) 899 900 /* PTE (Page Table Entry) fragment field for different page sizes */ 901 #define R600_PTE_FRAG_4KB (0 << 7) 902 #define R600_PTE_FRAG_64KB (4 << 7) 903 #define R600_PTE_FRAG_256KB (6 << 7) 904 905 /* flags needed to be set so we can copy directly from the GART table */ 906 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 907 R600_PTE_SYSTEM | R600_PTE_VALID ) 908 909 struct radeon_vm_pt { 910 struct radeon_bo *bo; 911 uint64_t addr; 912 }; 913 914 struct radeon_vm_id { 915 unsigned id; 916 uint64_t pd_gpu_addr; 917 /* last flushed PD/PT update */ 918 struct radeon_fence *flushed_updates; 919 /* last use of vmid */ 920 struct radeon_fence *last_id_use; 921 }; 922 923 struct radeon_vm { 924 struct mutex mutex; 925 926 struct rb_root_cached va; 927 928 /* protecting invalidated and freed */ 929 spinlock_t status_lock; 930 931 /* BOs moved, but not yet updated in the PT */ 932 struct list_head invalidated; 933 934 /* BOs freed, but not yet updated in the PT */ 935 struct list_head freed; 936 937 /* BOs cleared in the PT */ 938 struct list_head cleared; 939 940 /* contains the page directory */ 941 struct radeon_bo *page_directory; 942 unsigned max_pde_used; 943 944 /* array of page tables, one for each page directory entry */ 945 struct radeon_vm_pt *page_tables; 946 947 struct radeon_bo_va *ib_bo_va; 948 949 /* for id and flush management per ring */ 950 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 951 }; 952 953 struct radeon_vm_manager { 954 struct radeon_fence *active[RADEON_NUM_VM]; 955 uint32_t max_pfn; 956 /* number of VMIDs */ 957 unsigned nvm; 958 /* vram base address for page table entry */ 959 u64 vram_base_offset; 960 /* is vm enabled? */ 961 bool enabled; 962 /* for hw to save the PD addr on suspend/resume */ 963 uint32_t saved_table_addr[RADEON_NUM_VM]; 964 }; 965 966 /* 967 * file private structure 968 */ 969 struct radeon_fpriv { 970 struct radeon_vm vm; 971 }; 972 973 /* 974 * R6xx+ IH ring 975 */ 976 struct r600_ih { 977 struct radeon_bo *ring_obj; 978 volatile uint32_t *ring; 979 unsigned rptr; 980 unsigned ring_size; 981 uint64_t gpu_addr; 982 uint32_t ptr_mask; 983 atomic_t lock; 984 bool enabled; 985 }; 986 987 /* 988 * RLC stuff 989 */ 990 #include "clearstate_defs.h" 991 992 struct radeon_rlc { 993 /* for power gating */ 994 struct radeon_bo *save_restore_obj; 995 uint64_t save_restore_gpu_addr; 996 volatile uint32_t *sr_ptr; 997 const u32 *reg_list; 998 u32 reg_list_size; 999 /* for clear state */ 1000 struct radeon_bo *clear_state_obj; 1001 uint64_t clear_state_gpu_addr; 1002 volatile uint32_t *cs_ptr; 1003 const struct cs_section_def *cs_data; 1004 u32 clear_state_size; 1005 /* for cp tables */ 1006 struct radeon_bo *cp_table_obj; 1007 uint64_t cp_table_gpu_addr; 1008 volatile uint32_t *cp_table_ptr; 1009 u32 cp_table_size; 1010 }; 1011 1012 int radeon_ib_get(struct radeon_device *rdev, int ring, 1013 struct radeon_ib *ib, struct radeon_vm *vm, 1014 unsigned size); 1015 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1016 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1017 struct radeon_ib *const_ib, bool hdp_flush); 1018 int radeon_ib_pool_init(struct radeon_device *rdev); 1019 void radeon_ib_pool_fini(struct radeon_device *rdev); 1020 int radeon_ib_ring_tests(struct radeon_device *rdev); 1021 /* Ring access between begin & end cannot sleep */ 1022 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1023 struct radeon_ring *ring); 1024 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1025 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1026 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1027 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1028 bool hdp_flush); 1029 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1030 bool hdp_flush); 1031 void radeon_ring_undo(struct radeon_ring *ring); 1032 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1033 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1034 void radeon_ring_lockup_update(struct radeon_device *rdev, 1035 struct radeon_ring *ring); 1036 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1037 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1038 uint32_t **data); 1039 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1040 unsigned size, uint32_t *data); 1041 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1042 unsigned rptr_offs, u32 nop); 1043 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1044 1045 1046 /* r600 async dma */ 1047 void r600_dma_stop(struct radeon_device *rdev); 1048 int r600_dma_resume(struct radeon_device *rdev); 1049 void r600_dma_fini(struct radeon_device *rdev); 1050 1051 void cayman_dma_stop(struct radeon_device *rdev); 1052 int cayman_dma_resume(struct radeon_device *rdev); 1053 void cayman_dma_fini(struct radeon_device *rdev); 1054 1055 /* 1056 * CS. 1057 */ 1058 struct radeon_cs_chunk { 1059 uint32_t length_dw; 1060 uint32_t *kdata; 1061 void __user *user_ptr; 1062 }; 1063 1064 struct radeon_cs_parser { 1065 struct device *dev; 1066 struct radeon_device *rdev; 1067 struct drm_file *filp; 1068 /* chunks */ 1069 unsigned nchunks; 1070 struct radeon_cs_chunk *chunks; 1071 uint64_t *chunks_array; 1072 /* IB */ 1073 unsigned idx; 1074 /* relocations */ 1075 unsigned nrelocs; 1076 struct radeon_bo_list *relocs; 1077 struct radeon_bo_list *vm_bos; 1078 struct list_head validated; 1079 unsigned dma_reloc_idx; 1080 /* indices of various chunks */ 1081 struct radeon_cs_chunk *chunk_ib; 1082 struct radeon_cs_chunk *chunk_relocs; 1083 struct radeon_cs_chunk *chunk_flags; 1084 struct radeon_cs_chunk *chunk_const_ib; 1085 struct radeon_ib ib; 1086 struct radeon_ib const_ib; 1087 void *track; 1088 unsigned family; 1089 int parser_error; 1090 u32 cs_flags; 1091 u32 ring; 1092 s32 priority; 1093 struct ww_acquire_ctx ticket; 1094 }; 1095 1096 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1097 { 1098 struct radeon_cs_chunk *ibc = p->chunk_ib; 1099 1100 if (ibc->kdata) 1101 return ibc->kdata[idx]; 1102 return p->ib.ptr[idx]; 1103 } 1104 1105 1106 struct radeon_cs_packet { 1107 unsigned idx; 1108 unsigned type; 1109 unsigned reg; 1110 unsigned opcode; 1111 int count; 1112 unsigned one_reg_wr; 1113 }; 1114 1115 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1116 struct radeon_cs_packet *pkt, 1117 unsigned idx, unsigned reg); 1118 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1119 struct radeon_cs_packet *pkt); 1120 1121 1122 /* 1123 * AGP 1124 */ 1125 int radeon_agp_init(struct radeon_device *rdev); 1126 void radeon_agp_resume(struct radeon_device *rdev); 1127 void radeon_agp_suspend(struct radeon_device *rdev); 1128 void radeon_agp_fini(struct radeon_device *rdev); 1129 1130 1131 /* 1132 * Writeback 1133 */ 1134 struct radeon_wb { 1135 struct radeon_bo *wb_obj; 1136 volatile uint32_t *wb; 1137 uint64_t gpu_addr; 1138 bool enabled; 1139 bool use_event; 1140 }; 1141 1142 #define RADEON_WB_SCRATCH_OFFSET 0 1143 #define RADEON_WB_RING0_NEXT_RPTR 256 1144 #define RADEON_WB_CP_RPTR_OFFSET 1024 1145 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1146 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1147 #define R600_WB_DMA_RPTR_OFFSET 1792 1148 #define R600_WB_IH_WPTR_OFFSET 2048 1149 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1150 #define R600_WB_EVENT_OFFSET 3072 1151 #define CIK_WB_CP1_WPTR_OFFSET 3328 1152 #define CIK_WB_CP2_WPTR_OFFSET 3584 1153 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1154 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1155 1156 /** 1157 * struct radeon_pm - power management datas 1158 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1159 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1160 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1161 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1162 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1163 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1164 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1165 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1166 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1167 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1168 * @needed_bandwidth: current bandwidth needs 1169 * 1170 * It keeps track of various data needed to take powermanagement decision. 1171 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1172 * Equation between gpu/memory clock and available bandwidth is hw dependent 1173 * (type of memory, bus size, efficiency, ...) 1174 */ 1175 1176 enum radeon_pm_method { 1177 PM_METHOD_PROFILE, 1178 PM_METHOD_DYNPM, 1179 PM_METHOD_DPM, 1180 }; 1181 1182 enum radeon_dynpm_state { 1183 DYNPM_STATE_DISABLED, 1184 DYNPM_STATE_MINIMUM, 1185 DYNPM_STATE_PAUSED, 1186 DYNPM_STATE_ACTIVE, 1187 DYNPM_STATE_SUSPENDED, 1188 }; 1189 enum radeon_dynpm_action { 1190 DYNPM_ACTION_NONE, 1191 DYNPM_ACTION_MINIMUM, 1192 DYNPM_ACTION_DOWNCLOCK, 1193 DYNPM_ACTION_UPCLOCK, 1194 DYNPM_ACTION_DEFAULT 1195 }; 1196 1197 enum radeon_voltage_type { 1198 VOLTAGE_NONE = 0, 1199 VOLTAGE_GPIO, 1200 VOLTAGE_VDDC, 1201 VOLTAGE_SW 1202 }; 1203 1204 enum radeon_pm_state_type { 1205 /* not used for dpm */ 1206 POWER_STATE_TYPE_DEFAULT, 1207 POWER_STATE_TYPE_POWERSAVE, 1208 /* user selectable states */ 1209 POWER_STATE_TYPE_BATTERY, 1210 POWER_STATE_TYPE_BALANCED, 1211 POWER_STATE_TYPE_PERFORMANCE, 1212 /* internal states */ 1213 POWER_STATE_TYPE_INTERNAL_UVD, 1214 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1215 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1216 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1217 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1218 POWER_STATE_TYPE_INTERNAL_BOOT, 1219 POWER_STATE_TYPE_INTERNAL_THERMAL, 1220 POWER_STATE_TYPE_INTERNAL_ACPI, 1221 POWER_STATE_TYPE_INTERNAL_ULV, 1222 POWER_STATE_TYPE_INTERNAL_3DPERF, 1223 }; 1224 1225 enum radeon_pm_profile_type { 1226 PM_PROFILE_DEFAULT, 1227 PM_PROFILE_AUTO, 1228 PM_PROFILE_LOW, 1229 PM_PROFILE_MID, 1230 PM_PROFILE_HIGH, 1231 }; 1232 1233 #define PM_PROFILE_DEFAULT_IDX 0 1234 #define PM_PROFILE_LOW_SH_IDX 1 1235 #define PM_PROFILE_MID_SH_IDX 2 1236 #define PM_PROFILE_HIGH_SH_IDX 3 1237 #define PM_PROFILE_LOW_MH_IDX 4 1238 #define PM_PROFILE_MID_MH_IDX 5 1239 #define PM_PROFILE_HIGH_MH_IDX 6 1240 #define PM_PROFILE_MAX 7 1241 1242 struct radeon_pm_profile { 1243 int dpms_off_ps_idx; 1244 int dpms_on_ps_idx; 1245 int dpms_off_cm_idx; 1246 int dpms_on_cm_idx; 1247 }; 1248 1249 enum radeon_int_thermal_type { 1250 THERMAL_TYPE_NONE, 1251 THERMAL_TYPE_EXTERNAL, 1252 THERMAL_TYPE_EXTERNAL_GPIO, 1253 THERMAL_TYPE_RV6XX, 1254 THERMAL_TYPE_RV770, 1255 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1256 THERMAL_TYPE_EVERGREEN, 1257 THERMAL_TYPE_SUMO, 1258 THERMAL_TYPE_NI, 1259 THERMAL_TYPE_SI, 1260 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1261 THERMAL_TYPE_CI, 1262 THERMAL_TYPE_KV, 1263 }; 1264 1265 struct radeon_voltage { 1266 enum radeon_voltage_type type; 1267 /* gpio voltage */ 1268 struct radeon_gpio_rec gpio; 1269 u32 delay; /* delay in usec from voltage drop to sclk change */ 1270 bool active_high; /* voltage drop is active when bit is high */ 1271 /* VDDC voltage */ 1272 u8 vddc_id; /* index into vddc voltage table */ 1273 u8 vddci_id; /* index into vddci voltage table */ 1274 bool vddci_enabled; 1275 /* r6xx+ sw */ 1276 u16 voltage; 1277 /* evergreen+ vddci */ 1278 u16 vddci; 1279 }; 1280 1281 /* clock mode flags */ 1282 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1283 1284 struct radeon_pm_clock_info { 1285 /* memory clock */ 1286 u32 mclk; 1287 /* engine clock */ 1288 u32 sclk; 1289 /* voltage info */ 1290 struct radeon_voltage voltage; 1291 /* standardized clock flags */ 1292 u32 flags; 1293 }; 1294 1295 /* state flags */ 1296 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1297 1298 struct radeon_power_state { 1299 enum radeon_pm_state_type type; 1300 struct radeon_pm_clock_info *clock_info; 1301 /* number of valid clock modes in this power state */ 1302 int num_clock_modes; 1303 struct radeon_pm_clock_info *default_clock_mode; 1304 /* standardized state flags */ 1305 u32 flags; 1306 u32 misc; /* vbios specific flags */ 1307 u32 misc2; /* vbios specific flags */ 1308 int pcie_lanes; /* pcie lanes */ 1309 }; 1310 1311 /* 1312 * Some modes are overclocked by very low value, accept them 1313 */ 1314 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1315 1316 enum radeon_dpm_auto_throttle_src { 1317 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1318 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1319 }; 1320 1321 enum radeon_dpm_event_src { 1322 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1323 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1324 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1325 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1326 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1327 }; 1328 1329 #define RADEON_MAX_VCE_LEVELS 6 1330 1331 enum radeon_vce_level { 1332 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1333 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1334 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1335 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1336 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1337 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1338 }; 1339 1340 struct radeon_ps { 1341 u32 caps; /* vbios flags */ 1342 u32 class; /* vbios flags */ 1343 u32 class2; /* vbios flags */ 1344 /* UVD clocks */ 1345 u32 vclk; 1346 u32 dclk; 1347 /* VCE clocks */ 1348 u32 evclk; 1349 u32 ecclk; 1350 bool vce_active; 1351 enum radeon_vce_level vce_level; 1352 /* asic priv */ 1353 void *ps_priv; 1354 }; 1355 1356 struct radeon_dpm_thermal { 1357 /* thermal interrupt work */ 1358 struct work_struct work; 1359 /* low temperature threshold */ 1360 int min_temp; 1361 /* high temperature threshold */ 1362 int max_temp; 1363 /* was interrupt low to high or high to low */ 1364 bool high_to_low; 1365 }; 1366 1367 enum radeon_clk_action 1368 { 1369 RADEON_SCLK_UP = 1, 1370 RADEON_SCLK_DOWN 1371 }; 1372 1373 struct radeon_blacklist_clocks 1374 { 1375 u32 sclk; 1376 u32 mclk; 1377 enum radeon_clk_action action; 1378 }; 1379 1380 struct radeon_clock_and_voltage_limits { 1381 u32 sclk; 1382 u32 mclk; 1383 u16 vddc; 1384 u16 vddci; 1385 }; 1386 1387 struct radeon_clock_array { 1388 u32 count; 1389 u32 *values; 1390 }; 1391 1392 struct radeon_clock_voltage_dependency_entry { 1393 u32 clk; 1394 u16 v; 1395 }; 1396 1397 struct radeon_clock_voltage_dependency_table { 1398 u32 count; 1399 struct radeon_clock_voltage_dependency_entry *entries; 1400 }; 1401 1402 union radeon_cac_leakage_entry { 1403 struct { 1404 u16 vddc; 1405 u32 leakage; 1406 }; 1407 struct { 1408 u16 vddc1; 1409 u16 vddc2; 1410 u16 vddc3; 1411 }; 1412 }; 1413 1414 struct radeon_cac_leakage_table { 1415 u32 count; 1416 union radeon_cac_leakage_entry *entries; 1417 }; 1418 1419 struct radeon_phase_shedding_limits_entry { 1420 u16 voltage; 1421 u32 sclk; 1422 u32 mclk; 1423 }; 1424 1425 struct radeon_phase_shedding_limits_table { 1426 u32 count; 1427 struct radeon_phase_shedding_limits_entry *entries; 1428 }; 1429 1430 struct radeon_uvd_clock_voltage_dependency_entry { 1431 u32 vclk; 1432 u32 dclk; 1433 u16 v; 1434 }; 1435 1436 struct radeon_uvd_clock_voltage_dependency_table { 1437 u8 count; 1438 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1439 }; 1440 1441 struct radeon_vce_clock_voltage_dependency_entry { 1442 u32 ecclk; 1443 u32 evclk; 1444 u16 v; 1445 }; 1446 1447 struct radeon_vce_clock_voltage_dependency_table { 1448 u8 count; 1449 struct radeon_vce_clock_voltage_dependency_entry *entries; 1450 }; 1451 1452 struct radeon_ppm_table { 1453 u8 ppm_design; 1454 u16 cpu_core_number; 1455 u32 platform_tdp; 1456 u32 small_ac_platform_tdp; 1457 u32 platform_tdc; 1458 u32 small_ac_platform_tdc; 1459 u32 apu_tdp; 1460 u32 dgpu_tdp; 1461 u32 dgpu_ulv_power; 1462 u32 tj_max; 1463 }; 1464 1465 struct radeon_cac_tdp_table { 1466 u16 tdp; 1467 u16 configurable_tdp; 1468 u16 tdc; 1469 u16 battery_power_limit; 1470 u16 small_power_limit; 1471 u16 low_cac_leakage; 1472 u16 high_cac_leakage; 1473 u16 maximum_power_delivery_limit; 1474 }; 1475 1476 struct radeon_dpm_dynamic_state { 1477 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1478 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1479 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1480 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1481 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1482 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1483 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1484 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1485 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1486 struct radeon_clock_array valid_sclk_values; 1487 struct radeon_clock_array valid_mclk_values; 1488 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1489 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1490 u32 mclk_sclk_ratio; 1491 u32 sclk_mclk_delta; 1492 u16 vddc_vddci_delta; 1493 u16 min_vddc_for_pcie_gen2; 1494 struct radeon_cac_leakage_table cac_leakage_table; 1495 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1496 struct radeon_ppm_table *ppm_table; 1497 struct radeon_cac_tdp_table *cac_tdp_table; 1498 }; 1499 1500 struct radeon_dpm_fan { 1501 u16 t_min; 1502 u16 t_med; 1503 u16 t_high; 1504 u16 pwm_min; 1505 u16 pwm_med; 1506 u16 pwm_high; 1507 u8 t_hyst; 1508 u32 cycle_delay; 1509 u16 t_max; 1510 u8 control_mode; 1511 u16 default_max_fan_pwm; 1512 u16 default_fan_output_sensitivity; 1513 u16 fan_output_sensitivity; 1514 bool ucode_fan_control; 1515 }; 1516 1517 enum radeon_pcie_gen { 1518 RADEON_PCIE_GEN1 = 0, 1519 RADEON_PCIE_GEN2 = 1, 1520 RADEON_PCIE_GEN3 = 2, 1521 RADEON_PCIE_GEN_INVALID = 0xffff 1522 }; 1523 1524 enum radeon_dpm_forced_level { 1525 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1526 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1527 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1528 }; 1529 1530 struct radeon_vce_state { 1531 /* vce clocks */ 1532 u32 evclk; 1533 u32 ecclk; 1534 /* gpu clocks */ 1535 u32 sclk; 1536 u32 mclk; 1537 u8 clk_idx; 1538 u8 pstate; 1539 }; 1540 1541 struct radeon_dpm { 1542 struct radeon_ps *ps; 1543 /* number of valid power states */ 1544 int num_ps; 1545 /* current power state that is active */ 1546 struct radeon_ps *current_ps; 1547 /* requested power state */ 1548 struct radeon_ps *requested_ps; 1549 /* boot up power state */ 1550 struct radeon_ps *boot_ps; 1551 /* default uvd power state */ 1552 struct radeon_ps *uvd_ps; 1553 /* vce requirements */ 1554 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1555 enum radeon_vce_level vce_level; 1556 enum radeon_pm_state_type state; 1557 enum radeon_pm_state_type user_state; 1558 u32 platform_caps; 1559 u32 voltage_response_time; 1560 u32 backbias_response_time; 1561 void *priv; 1562 u32 new_active_crtcs; 1563 int new_active_crtc_count; 1564 u32 current_active_crtcs; 1565 int current_active_crtc_count; 1566 bool single_display; 1567 struct radeon_dpm_dynamic_state dyn_state; 1568 struct radeon_dpm_fan fan; 1569 u32 tdp_limit; 1570 u32 near_tdp_limit; 1571 u32 near_tdp_limit_adjusted; 1572 u32 sq_ramping_threshold; 1573 u32 cac_leakage; 1574 u16 tdp_od_limit; 1575 u32 tdp_adjustment; 1576 u16 load_line_slope; 1577 bool power_control; 1578 bool ac_power; 1579 /* special states active */ 1580 bool thermal_active; 1581 bool uvd_active; 1582 bool vce_active; 1583 /* thermal handling */ 1584 struct radeon_dpm_thermal thermal; 1585 /* forced levels */ 1586 enum radeon_dpm_forced_level forced_level; 1587 /* track UVD streams */ 1588 unsigned sd; 1589 unsigned hd; 1590 }; 1591 1592 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1593 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1594 1595 struct radeon_pm { 1596 struct mutex mutex; 1597 /* write locked while reprogramming mclk */ 1598 struct rw_semaphore mclk_lock; 1599 u32 active_crtcs; 1600 int active_crtc_count; 1601 int req_vblank; 1602 bool vblank_sync; 1603 fixed20_12 max_bandwidth; 1604 fixed20_12 igp_sideport_mclk; 1605 fixed20_12 igp_system_mclk; 1606 fixed20_12 igp_ht_link_clk; 1607 fixed20_12 igp_ht_link_width; 1608 fixed20_12 k8_bandwidth; 1609 fixed20_12 sideport_bandwidth; 1610 fixed20_12 ht_bandwidth; 1611 fixed20_12 core_bandwidth; 1612 fixed20_12 sclk; 1613 fixed20_12 mclk; 1614 fixed20_12 needed_bandwidth; 1615 struct radeon_power_state *power_state; 1616 /* number of valid power states */ 1617 int num_power_states; 1618 int current_power_state_index; 1619 int current_clock_mode_index; 1620 int requested_power_state_index; 1621 int requested_clock_mode_index; 1622 int default_power_state_index; 1623 u32 current_sclk; 1624 u32 current_mclk; 1625 u16 current_vddc; 1626 u16 current_vddci; 1627 u32 default_sclk; 1628 u32 default_mclk; 1629 u16 default_vddc; 1630 u16 default_vddci; 1631 struct radeon_i2c_chan *i2c_bus; 1632 /* selected pm method */ 1633 enum radeon_pm_method pm_method; 1634 /* dynpm power management */ 1635 struct delayed_work dynpm_idle_work; 1636 enum radeon_dynpm_state dynpm_state; 1637 enum radeon_dynpm_action dynpm_planned_action; 1638 unsigned long dynpm_action_timeout; 1639 bool dynpm_can_upclock; 1640 bool dynpm_can_downclock; 1641 /* profile-based power management */ 1642 enum radeon_pm_profile_type profile; 1643 int profile_index; 1644 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1645 /* internal thermal controller on rv6xx+ */ 1646 enum radeon_int_thermal_type int_thermal_type; 1647 struct device *int_hwmon_dev; 1648 /* fan control parameters */ 1649 bool no_fan; 1650 u8 fan_pulses_per_revolution; 1651 u8 fan_min_rpm; 1652 u8 fan_max_rpm; 1653 /* dpm */ 1654 bool dpm_enabled; 1655 bool sysfs_initialized; 1656 struct radeon_dpm dpm; 1657 }; 1658 1659 #define RADEON_PCIE_SPEED_25 1 1660 #define RADEON_PCIE_SPEED_50 2 1661 #define RADEON_PCIE_SPEED_80 4 1662 1663 int radeon_pm_get_type_index(struct radeon_device *rdev, 1664 enum radeon_pm_state_type ps_type, 1665 int instance); 1666 /* 1667 * UVD 1668 */ 1669 #define RADEON_DEFAULT_UVD_HANDLES 10 1670 #define RADEON_MAX_UVD_HANDLES 30 1671 #define RADEON_UVD_STACK_SIZE (200*1024) 1672 #define RADEON_UVD_HEAP_SIZE (256*1024) 1673 #define RADEON_UVD_SESSION_SIZE (50*1024) 1674 1675 struct radeon_uvd { 1676 bool fw_header_present; 1677 struct radeon_bo *vcpu_bo; 1678 void *cpu_addr; 1679 uint64_t gpu_addr; 1680 unsigned max_handles; 1681 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1682 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1683 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1684 struct delayed_work idle_work; 1685 }; 1686 1687 int radeon_uvd_init(struct radeon_device *rdev); 1688 void radeon_uvd_fini(struct radeon_device *rdev); 1689 int radeon_uvd_suspend(struct radeon_device *rdev); 1690 int radeon_uvd_resume(struct radeon_device *rdev); 1691 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1692 uint32_t handle, struct radeon_fence **fence); 1693 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1694 uint32_t handle, struct radeon_fence **fence); 1695 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1696 uint32_t allowed_domains); 1697 void radeon_uvd_free_handles(struct radeon_device *rdev, 1698 struct drm_file *filp); 1699 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1700 void radeon_uvd_note_usage(struct radeon_device *rdev); 1701 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1702 unsigned vclk, unsigned dclk, 1703 unsigned vco_min, unsigned vco_max, 1704 unsigned fb_factor, unsigned fb_mask, 1705 unsigned pd_min, unsigned pd_max, 1706 unsigned pd_even, 1707 unsigned *optimal_fb_div, 1708 unsigned *optimal_vclk_div, 1709 unsigned *optimal_dclk_div); 1710 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1711 unsigned cg_upll_func_cntl); 1712 1713 /* 1714 * VCE 1715 */ 1716 #define RADEON_MAX_VCE_HANDLES 16 1717 1718 struct radeon_vce { 1719 struct radeon_bo *vcpu_bo; 1720 uint64_t gpu_addr; 1721 unsigned fw_version; 1722 unsigned fb_version; 1723 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1724 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1725 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1726 struct delayed_work idle_work; 1727 uint32_t keyselect; 1728 }; 1729 1730 int radeon_vce_init(struct radeon_device *rdev); 1731 void radeon_vce_fini(struct radeon_device *rdev); 1732 int radeon_vce_suspend(struct radeon_device *rdev); 1733 int radeon_vce_resume(struct radeon_device *rdev); 1734 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1735 uint32_t handle, struct radeon_fence **fence); 1736 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1737 uint32_t handle, struct radeon_fence **fence); 1738 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1739 void radeon_vce_note_usage(struct radeon_device *rdev); 1740 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1741 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1742 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1743 struct radeon_ring *ring, 1744 struct radeon_semaphore *semaphore, 1745 bool emit_wait); 1746 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1747 void radeon_vce_fence_emit(struct radeon_device *rdev, 1748 struct radeon_fence *fence); 1749 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1750 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1751 1752 struct r600_audio_pin { 1753 int channels; 1754 int rate; 1755 int bits_per_sample; 1756 u8 status_bits; 1757 u8 category_code; 1758 u32 offset; 1759 bool connected; 1760 u32 id; 1761 }; 1762 1763 struct r600_audio { 1764 bool enabled; 1765 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1766 int num_pins; 1767 struct radeon_audio_funcs *hdmi_funcs; 1768 struct radeon_audio_funcs *dp_funcs; 1769 struct radeon_audio_basic_funcs *funcs; 1770 }; 1771 1772 /* 1773 * Benchmarking 1774 */ 1775 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1776 1777 1778 /* 1779 * Testing 1780 */ 1781 void radeon_test_moves(struct radeon_device *rdev); 1782 void radeon_test_ring_sync(struct radeon_device *rdev, 1783 struct radeon_ring *cpA, 1784 struct radeon_ring *cpB); 1785 void radeon_test_syncing(struct radeon_device *rdev); 1786 1787 /* 1788 * MMU Notifier 1789 */ 1790 #if defined(CONFIG_MMU_NOTIFIER) 1791 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1792 void radeon_mn_unregister(struct radeon_bo *bo); 1793 #else 1794 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1795 { 1796 return -ENODEV; 1797 } 1798 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1799 #endif 1800 1801 /* 1802 * Debugfs 1803 */ 1804 struct radeon_debugfs { 1805 struct drm_info_list *files; 1806 unsigned num_files; 1807 }; 1808 1809 int radeon_debugfs_add_files(struct radeon_device *rdev, 1810 struct drm_info_list *files, 1811 unsigned nfiles); 1812 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1813 1814 /* 1815 * ASIC ring specific functions. 1816 */ 1817 struct radeon_asic_ring { 1818 /* ring read/write ptr handling */ 1819 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1820 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1821 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1822 1823 /* validating and patching of IBs */ 1824 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1825 int (*cs_parse)(struct radeon_cs_parser *p); 1826 1827 /* command emmit functions */ 1828 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1829 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1830 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1831 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1832 struct radeon_semaphore *semaphore, bool emit_wait); 1833 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1834 unsigned vm_id, uint64_t pd_addr); 1835 1836 /* testing functions */ 1837 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1838 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1839 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1840 1841 /* deprecated */ 1842 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1843 }; 1844 1845 /* 1846 * ASIC specific functions. 1847 */ 1848 struct radeon_asic { 1849 int (*init)(struct radeon_device *rdev); 1850 void (*fini)(struct radeon_device *rdev); 1851 int (*resume)(struct radeon_device *rdev); 1852 int (*suspend)(struct radeon_device *rdev); 1853 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1854 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1855 /* Flush the HDP cache via MMIO */ 1856 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1857 /* check if 3D engine is idle */ 1858 bool (*gui_idle)(struct radeon_device *rdev); 1859 /* wait for mc_idle */ 1860 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1861 /* get the reference clock */ 1862 u32 (*get_xclk)(struct radeon_device *rdev); 1863 /* get the gpu clock counter */ 1864 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1865 /* get register for info ioctl */ 1866 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1867 /* gart */ 1868 struct { 1869 void (*tlb_flush)(struct radeon_device *rdev); 1870 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1871 void (*set_page)(struct radeon_device *rdev, unsigned i, 1872 uint64_t entry); 1873 } gart; 1874 struct { 1875 int (*init)(struct radeon_device *rdev); 1876 void (*fini)(struct radeon_device *rdev); 1877 void (*copy_pages)(struct radeon_device *rdev, 1878 struct radeon_ib *ib, 1879 uint64_t pe, uint64_t src, 1880 unsigned count); 1881 void (*write_pages)(struct radeon_device *rdev, 1882 struct radeon_ib *ib, 1883 uint64_t pe, 1884 uint64_t addr, unsigned count, 1885 uint32_t incr, uint32_t flags); 1886 void (*set_pages)(struct radeon_device *rdev, 1887 struct radeon_ib *ib, 1888 uint64_t pe, 1889 uint64_t addr, unsigned count, 1890 uint32_t incr, uint32_t flags); 1891 void (*pad_ib)(struct radeon_ib *ib); 1892 } vm; 1893 /* ring specific callbacks */ 1894 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1895 /* irqs */ 1896 struct { 1897 int (*set)(struct radeon_device *rdev); 1898 int (*process)(struct radeon_device *rdev); 1899 } irq; 1900 /* displays */ 1901 struct { 1902 /* display watermarks */ 1903 void (*bandwidth_update)(struct radeon_device *rdev); 1904 /* get frame count */ 1905 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1906 /* wait for vblank */ 1907 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1908 /* set backlight level */ 1909 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1910 /* get backlight level */ 1911 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1912 /* audio callbacks */ 1913 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1914 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1915 } display; 1916 /* copy functions for bo handling */ 1917 struct { 1918 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1919 uint64_t src_offset, 1920 uint64_t dst_offset, 1921 unsigned num_gpu_pages, 1922 struct dma_resv *resv); 1923 u32 blit_ring_index; 1924 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1925 uint64_t src_offset, 1926 uint64_t dst_offset, 1927 unsigned num_gpu_pages, 1928 struct dma_resv *resv); 1929 u32 dma_ring_index; 1930 /* method used for bo copy */ 1931 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1932 uint64_t src_offset, 1933 uint64_t dst_offset, 1934 unsigned num_gpu_pages, 1935 struct dma_resv *resv); 1936 /* ring used for bo copies */ 1937 u32 copy_ring_index; 1938 } copy; 1939 /* surfaces */ 1940 struct { 1941 int (*set_reg)(struct radeon_device *rdev, int reg, 1942 uint32_t tiling_flags, uint32_t pitch, 1943 uint32_t offset, uint32_t obj_size); 1944 void (*clear_reg)(struct radeon_device *rdev, int reg); 1945 } surface; 1946 /* hotplug detect */ 1947 struct { 1948 void (*init)(struct radeon_device *rdev); 1949 void (*fini)(struct radeon_device *rdev); 1950 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1951 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1952 } hpd; 1953 /* static power management */ 1954 struct { 1955 void (*misc)(struct radeon_device *rdev); 1956 void (*prepare)(struct radeon_device *rdev); 1957 void (*finish)(struct radeon_device *rdev); 1958 void (*init_profile)(struct radeon_device *rdev); 1959 void (*get_dynpm_state)(struct radeon_device *rdev); 1960 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1961 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1962 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1963 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1964 int (*get_pcie_lanes)(struct radeon_device *rdev); 1965 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1966 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1967 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1968 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1969 int (*get_temperature)(struct radeon_device *rdev); 1970 } pm; 1971 /* dynamic power management */ 1972 struct { 1973 int (*init)(struct radeon_device *rdev); 1974 void (*setup_asic)(struct radeon_device *rdev); 1975 int (*enable)(struct radeon_device *rdev); 1976 int (*late_enable)(struct radeon_device *rdev); 1977 void (*disable)(struct radeon_device *rdev); 1978 int (*pre_set_power_state)(struct radeon_device *rdev); 1979 int (*set_power_state)(struct radeon_device *rdev); 1980 void (*post_set_power_state)(struct radeon_device *rdev); 1981 void (*display_configuration_changed)(struct radeon_device *rdev); 1982 void (*fini)(struct radeon_device *rdev); 1983 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1984 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1985 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1986 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1987 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1988 bool (*vblank_too_short)(struct radeon_device *rdev); 1989 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1990 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1991 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1992 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1993 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1994 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1995 u32 (*get_current_sclk)(struct radeon_device *rdev); 1996 u32 (*get_current_mclk)(struct radeon_device *rdev); 1997 } dpm; 1998 /* pageflipping */ 1999 struct { 2000 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2001 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2002 } pflip; 2003 }; 2004 2005 /* 2006 * Asic structures 2007 */ 2008 struct r100_asic { 2009 const unsigned *reg_safe_bm; 2010 unsigned reg_safe_bm_size; 2011 u32 hdp_cntl; 2012 }; 2013 2014 struct r300_asic { 2015 const unsigned *reg_safe_bm; 2016 unsigned reg_safe_bm_size; 2017 u32 resync_scratch; 2018 u32 hdp_cntl; 2019 }; 2020 2021 struct r600_asic { 2022 unsigned max_pipes; 2023 unsigned max_tile_pipes; 2024 unsigned max_simds; 2025 unsigned max_backends; 2026 unsigned max_gprs; 2027 unsigned max_threads; 2028 unsigned max_stack_entries; 2029 unsigned max_hw_contexts; 2030 unsigned max_gs_threads; 2031 unsigned sx_max_export_size; 2032 unsigned sx_max_export_pos_size; 2033 unsigned sx_max_export_smx_size; 2034 unsigned sq_num_cf_insts; 2035 unsigned tiling_nbanks; 2036 unsigned tiling_npipes; 2037 unsigned tiling_group_size; 2038 unsigned tile_config; 2039 unsigned backend_map; 2040 unsigned active_simds; 2041 }; 2042 2043 struct rv770_asic { 2044 unsigned max_pipes; 2045 unsigned max_tile_pipes; 2046 unsigned max_simds; 2047 unsigned max_backends; 2048 unsigned max_gprs; 2049 unsigned max_threads; 2050 unsigned max_stack_entries; 2051 unsigned max_hw_contexts; 2052 unsigned max_gs_threads; 2053 unsigned sx_max_export_size; 2054 unsigned sx_max_export_pos_size; 2055 unsigned sx_max_export_smx_size; 2056 unsigned sq_num_cf_insts; 2057 unsigned sx_num_of_sets; 2058 unsigned sc_prim_fifo_size; 2059 unsigned sc_hiz_tile_fifo_size; 2060 unsigned sc_earlyz_tile_fifo_fize; 2061 unsigned tiling_nbanks; 2062 unsigned tiling_npipes; 2063 unsigned tiling_group_size; 2064 unsigned tile_config; 2065 unsigned backend_map; 2066 unsigned active_simds; 2067 }; 2068 2069 struct evergreen_asic { 2070 unsigned num_ses; 2071 unsigned max_pipes; 2072 unsigned max_tile_pipes; 2073 unsigned max_simds; 2074 unsigned max_backends; 2075 unsigned max_gprs; 2076 unsigned max_threads; 2077 unsigned max_stack_entries; 2078 unsigned max_hw_contexts; 2079 unsigned max_gs_threads; 2080 unsigned sx_max_export_size; 2081 unsigned sx_max_export_pos_size; 2082 unsigned sx_max_export_smx_size; 2083 unsigned sq_num_cf_insts; 2084 unsigned sx_num_of_sets; 2085 unsigned sc_prim_fifo_size; 2086 unsigned sc_hiz_tile_fifo_size; 2087 unsigned sc_earlyz_tile_fifo_size; 2088 unsigned tiling_nbanks; 2089 unsigned tiling_npipes; 2090 unsigned tiling_group_size; 2091 unsigned tile_config; 2092 unsigned backend_map; 2093 unsigned active_simds; 2094 }; 2095 2096 struct cayman_asic { 2097 unsigned max_shader_engines; 2098 unsigned max_pipes_per_simd; 2099 unsigned max_tile_pipes; 2100 unsigned max_simds_per_se; 2101 unsigned max_backends_per_se; 2102 unsigned max_texture_channel_caches; 2103 unsigned max_gprs; 2104 unsigned max_threads; 2105 unsigned max_gs_threads; 2106 unsigned max_stack_entries; 2107 unsigned sx_num_of_sets; 2108 unsigned sx_max_export_size; 2109 unsigned sx_max_export_pos_size; 2110 unsigned sx_max_export_smx_size; 2111 unsigned max_hw_contexts; 2112 unsigned sq_num_cf_insts; 2113 unsigned sc_prim_fifo_size; 2114 unsigned sc_hiz_tile_fifo_size; 2115 unsigned sc_earlyz_tile_fifo_size; 2116 2117 unsigned num_shader_engines; 2118 unsigned num_shader_pipes_per_simd; 2119 unsigned num_tile_pipes; 2120 unsigned num_simds_per_se; 2121 unsigned num_backends_per_se; 2122 unsigned backend_disable_mask_per_asic; 2123 unsigned backend_map; 2124 unsigned num_texture_channel_caches; 2125 unsigned mem_max_burst_length_bytes; 2126 unsigned mem_row_size_in_kb; 2127 unsigned shader_engine_tile_size; 2128 unsigned num_gpus; 2129 unsigned multi_gpu_tile_size; 2130 2131 unsigned tile_config; 2132 unsigned active_simds; 2133 }; 2134 2135 struct si_asic { 2136 unsigned max_shader_engines; 2137 unsigned max_tile_pipes; 2138 unsigned max_cu_per_sh; 2139 unsigned max_sh_per_se; 2140 unsigned max_backends_per_se; 2141 unsigned max_texture_channel_caches; 2142 unsigned max_gprs; 2143 unsigned max_gs_threads; 2144 unsigned max_hw_contexts; 2145 unsigned sc_prim_fifo_size_frontend; 2146 unsigned sc_prim_fifo_size_backend; 2147 unsigned sc_hiz_tile_fifo_size; 2148 unsigned sc_earlyz_tile_fifo_size; 2149 2150 unsigned num_tile_pipes; 2151 unsigned backend_enable_mask; 2152 unsigned backend_disable_mask_per_asic; 2153 unsigned backend_map; 2154 unsigned num_texture_channel_caches; 2155 unsigned mem_max_burst_length_bytes; 2156 unsigned mem_row_size_in_kb; 2157 unsigned shader_engine_tile_size; 2158 unsigned num_gpus; 2159 unsigned multi_gpu_tile_size; 2160 2161 unsigned tile_config; 2162 uint32_t tile_mode_array[32]; 2163 uint32_t active_cus; 2164 }; 2165 2166 struct cik_asic { 2167 unsigned max_shader_engines; 2168 unsigned max_tile_pipes; 2169 unsigned max_cu_per_sh; 2170 unsigned max_sh_per_se; 2171 unsigned max_backends_per_se; 2172 unsigned max_texture_channel_caches; 2173 unsigned max_gprs; 2174 unsigned max_gs_threads; 2175 unsigned max_hw_contexts; 2176 unsigned sc_prim_fifo_size_frontend; 2177 unsigned sc_prim_fifo_size_backend; 2178 unsigned sc_hiz_tile_fifo_size; 2179 unsigned sc_earlyz_tile_fifo_size; 2180 2181 unsigned num_tile_pipes; 2182 unsigned backend_enable_mask; 2183 unsigned backend_disable_mask_per_asic; 2184 unsigned backend_map; 2185 unsigned num_texture_channel_caches; 2186 unsigned mem_max_burst_length_bytes; 2187 unsigned mem_row_size_in_kb; 2188 unsigned shader_engine_tile_size; 2189 unsigned num_gpus; 2190 unsigned multi_gpu_tile_size; 2191 2192 unsigned tile_config; 2193 uint32_t tile_mode_array[32]; 2194 uint32_t macrotile_mode_array[16]; 2195 uint32_t active_cus; 2196 }; 2197 2198 union radeon_asic_config { 2199 struct r300_asic r300; 2200 struct r100_asic r100; 2201 struct r600_asic r600; 2202 struct rv770_asic rv770; 2203 struct evergreen_asic evergreen; 2204 struct cayman_asic cayman; 2205 struct si_asic si; 2206 struct cik_asic cik; 2207 }; 2208 2209 /* 2210 * asic initizalization from radeon_asic.c 2211 */ 2212 void radeon_agp_disable(struct radeon_device *rdev); 2213 int radeon_asic_init(struct radeon_device *rdev); 2214 2215 2216 /* 2217 * IOCTL. 2218 */ 2219 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2220 struct drm_file *filp); 2221 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2222 struct drm_file *filp); 2223 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2224 struct drm_file *filp); 2225 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2226 struct drm_file *file_priv); 2227 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2228 struct drm_file *file_priv); 2229 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2230 struct drm_file *file_priv); 2231 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *file_priv); 2233 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2234 struct drm_file *filp); 2235 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2236 struct drm_file *filp); 2237 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2238 struct drm_file *filp); 2239 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *filp); 2241 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2242 struct drm_file *filp); 2243 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2244 struct drm_file *filp); 2245 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2246 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2247 struct drm_file *filp); 2248 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2249 struct drm_file *filp); 2250 2251 /* VRAM scratch page for HDP bug, default vram page */ 2252 struct r600_vram_scratch { 2253 struct radeon_bo *robj; 2254 volatile uint32_t *ptr; 2255 u64 gpu_addr; 2256 }; 2257 2258 /* 2259 * ACPI 2260 */ 2261 struct radeon_atif_notification_cfg { 2262 bool enabled; 2263 int command_code; 2264 }; 2265 2266 struct radeon_atif_notifications { 2267 bool display_switch; 2268 bool expansion_mode_change; 2269 bool thermal_state; 2270 bool forced_power_state; 2271 bool system_power_state; 2272 bool display_conf_change; 2273 bool px_gfx_switch; 2274 bool brightness_change; 2275 bool dgpu_display_event; 2276 }; 2277 2278 struct radeon_atif_functions { 2279 bool system_params; 2280 bool sbios_requests; 2281 bool select_active_disp; 2282 bool lid_state; 2283 bool get_tv_standard; 2284 bool set_tv_standard; 2285 bool get_panel_expansion_mode; 2286 bool set_panel_expansion_mode; 2287 bool temperature_change; 2288 bool graphics_device_types; 2289 }; 2290 2291 struct radeon_atif { 2292 struct radeon_atif_notifications notifications; 2293 struct radeon_atif_functions functions; 2294 struct radeon_atif_notification_cfg notification_cfg; 2295 struct radeon_encoder *encoder_for_bl; 2296 }; 2297 2298 struct radeon_atcs_functions { 2299 bool get_ext_state; 2300 bool pcie_perf_req; 2301 bool pcie_dev_rdy; 2302 bool pcie_bus_width; 2303 }; 2304 2305 struct radeon_atcs { 2306 struct radeon_atcs_functions functions; 2307 }; 2308 2309 /* 2310 * Core structure, functions and helpers. 2311 */ 2312 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2313 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2314 2315 struct radeon_device { 2316 struct device *dev; 2317 struct drm_device *ddev; 2318 struct pci_dev *pdev; 2319 struct rw_semaphore exclusive_lock; 2320 /* ASIC */ 2321 union radeon_asic_config config; 2322 enum radeon_family family; 2323 unsigned long flags; 2324 int usec_timeout; 2325 enum radeon_pll_errata pll_errata; 2326 int num_gb_pipes; 2327 int num_z_pipes; 2328 int disp_priority; 2329 /* BIOS */ 2330 uint8_t *bios; 2331 bool is_atom_bios; 2332 uint16_t bios_header_start; 2333 struct radeon_bo *stolen_vga_memory; 2334 /* Register mmio */ 2335 resource_size_t rmmio_base; 2336 resource_size_t rmmio_size; 2337 /* protects concurrent MM_INDEX/DATA based register access */ 2338 spinlock_t mmio_idx_lock; 2339 /* protects concurrent SMC based register access */ 2340 spinlock_t smc_idx_lock; 2341 /* protects concurrent PLL register access */ 2342 spinlock_t pll_idx_lock; 2343 /* protects concurrent MC register access */ 2344 spinlock_t mc_idx_lock; 2345 /* protects concurrent PCIE register access */ 2346 spinlock_t pcie_idx_lock; 2347 /* protects concurrent PCIE_PORT register access */ 2348 spinlock_t pciep_idx_lock; 2349 /* protects concurrent PIF register access */ 2350 spinlock_t pif_idx_lock; 2351 /* protects concurrent CG register access */ 2352 spinlock_t cg_idx_lock; 2353 /* protects concurrent UVD register access */ 2354 spinlock_t uvd_idx_lock; 2355 /* protects concurrent RCU register access */ 2356 spinlock_t rcu_idx_lock; 2357 /* protects concurrent DIDT register access */ 2358 spinlock_t didt_idx_lock; 2359 /* protects concurrent ENDPOINT (audio) register access */ 2360 spinlock_t end_idx_lock; 2361 void __iomem *rmmio; 2362 radeon_rreg_t mc_rreg; 2363 radeon_wreg_t mc_wreg; 2364 radeon_rreg_t pll_rreg; 2365 radeon_wreg_t pll_wreg; 2366 uint32_t pcie_reg_mask; 2367 radeon_rreg_t pciep_rreg; 2368 radeon_wreg_t pciep_wreg; 2369 /* io port */ 2370 void __iomem *rio_mem; 2371 resource_size_t rio_mem_size; 2372 struct radeon_clock clock; 2373 struct radeon_mc mc; 2374 struct radeon_gart gart; 2375 struct radeon_mode_info mode_info; 2376 struct radeon_scratch scratch; 2377 struct radeon_doorbell doorbell; 2378 struct radeon_mman mman; 2379 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2380 wait_queue_head_t fence_queue; 2381 u64 fence_context; 2382 struct mutex ring_lock; 2383 struct radeon_ring ring[RADEON_NUM_RINGS]; 2384 bool ib_pool_ready; 2385 struct radeon_sa_manager ring_tmp_bo; 2386 struct radeon_irq irq; 2387 struct radeon_asic *asic; 2388 struct radeon_gem gem; 2389 struct radeon_pm pm; 2390 struct radeon_uvd uvd; 2391 struct radeon_vce vce; 2392 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2393 struct radeon_wb wb; 2394 struct radeon_dummy_page dummy_page; 2395 bool shutdown; 2396 bool need_swiotlb; 2397 bool accel_working; 2398 bool fastfb_working; /* IGP feature*/ 2399 bool needs_reset, in_reset; 2400 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2401 const struct firmware *me_fw; /* all family ME firmware */ 2402 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2403 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2404 const struct firmware *mc_fw; /* NI MC firmware */ 2405 const struct firmware *ce_fw; /* SI CE firmware */ 2406 const struct firmware *mec_fw; /* CIK MEC firmware */ 2407 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2408 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2409 const struct firmware *smc_fw; /* SMC firmware */ 2410 const struct firmware *uvd_fw; /* UVD firmware */ 2411 const struct firmware *vce_fw; /* VCE firmware */ 2412 bool new_fw; 2413 struct r600_vram_scratch vram_scratch; 2414 int msi_enabled; /* msi enabled */ 2415 struct r600_ih ih; /* r6/700 interrupt ring */ 2416 struct radeon_rlc rlc; 2417 struct radeon_mec mec; 2418 struct delayed_work hotplug_work; 2419 struct work_struct dp_work; 2420 struct work_struct audio_work; 2421 int num_crtc; /* number of crtcs */ 2422 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2423 bool has_uvd; 2424 bool has_vce; 2425 struct r600_audio audio; /* audio stuff */ 2426 struct notifier_block acpi_nb; 2427 /* only one userspace can use Hyperz features or CMASK at a time */ 2428 struct drm_file *hyperz_filp; 2429 struct drm_file *cmask_filp; 2430 /* i2c buses */ 2431 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2432 /* debugfs */ 2433 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2434 unsigned debugfs_count; 2435 /* virtual memory */ 2436 struct radeon_vm_manager vm_manager; 2437 struct mutex gpu_clock_mutex; 2438 /* memory stats */ 2439 atomic64_t vram_usage; 2440 atomic64_t gtt_usage; 2441 atomic64_t num_bytes_moved; 2442 atomic_t gpu_reset_counter; 2443 /* ACPI interface */ 2444 struct radeon_atif atif; 2445 struct radeon_atcs atcs; 2446 /* srbm instance registers */ 2447 struct mutex srbm_mutex; 2448 /* clock, powergating flags */ 2449 u32 cg_flags; 2450 u32 pg_flags; 2451 2452 struct dev_pm_domain vga_pm_domain; 2453 bool have_disp_power_ref; 2454 u32 px_quirk_flags; 2455 2456 /* tracking pinned memory */ 2457 u64 vram_pin_size; 2458 u64 gart_pin_size; 2459 }; 2460 2461 bool radeon_is_px(struct drm_device *dev); 2462 int radeon_device_init(struct radeon_device *rdev, 2463 struct drm_device *ddev, 2464 struct pci_dev *pdev, 2465 uint32_t flags); 2466 void radeon_device_fini(struct radeon_device *rdev); 2467 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2468 2469 #define RADEON_MIN_MMIO_SIZE 0x10000 2470 2471 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2472 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2473 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2474 bool always_indirect) 2475 { 2476 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2477 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2478 return readl(((void __iomem *)rdev->rmmio) + reg); 2479 else 2480 return r100_mm_rreg_slow(rdev, reg); 2481 } 2482 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2483 bool always_indirect) 2484 { 2485 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2486 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2487 else 2488 r100_mm_wreg_slow(rdev, reg, v); 2489 } 2490 2491 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2492 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2493 2494 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2495 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2496 2497 /* 2498 * Cast helper 2499 */ 2500 extern const struct dma_fence_ops radeon_fence_ops; 2501 2502 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2503 { 2504 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2505 2506 if (__f->base.ops == &radeon_fence_ops) 2507 return __f; 2508 2509 return NULL; 2510 } 2511 2512 /* 2513 * Registers read & write functions. 2514 */ 2515 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2516 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2517 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2518 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2519 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2520 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2521 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2522 r100_mm_rreg(rdev, (reg), false)) 2523 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2524 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2525 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2526 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2527 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2528 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2529 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2530 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2531 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2532 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2533 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2534 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2535 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2536 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2537 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2538 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2539 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2540 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2541 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2542 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2543 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2544 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2545 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2546 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2547 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2548 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2549 #define WREG32_P(reg, val, mask) \ 2550 do { \ 2551 uint32_t tmp_ = RREG32(reg); \ 2552 tmp_ &= (mask); \ 2553 tmp_ |= ((val) & ~(mask)); \ 2554 WREG32(reg, tmp_); \ 2555 } while (0) 2556 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2557 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2558 #define WREG32_PLL_P(reg, val, mask) \ 2559 do { \ 2560 uint32_t tmp_ = RREG32_PLL(reg); \ 2561 tmp_ &= (mask); \ 2562 tmp_ |= ((val) & ~(mask)); \ 2563 WREG32_PLL(reg, tmp_); \ 2564 } while (0) 2565 #define WREG32_SMC_P(reg, val, mask) \ 2566 do { \ 2567 uint32_t tmp_ = RREG32_SMC(reg); \ 2568 tmp_ &= (mask); \ 2569 tmp_ |= ((val) & ~(mask)); \ 2570 WREG32_SMC(reg, tmp_); \ 2571 } while (0) 2572 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2573 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2574 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2575 2576 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2577 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2578 2579 /* 2580 * Indirect registers accessors. 2581 * They used to be inlined, but this increases code size by ~65 kbytes. 2582 * Since each performs a pair of MMIO ops 2583 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2584 * the cost of call+ret is almost negligible. MMIO and locking 2585 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2586 */ 2587 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2588 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2589 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2590 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2591 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2592 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2593 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2594 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2595 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2596 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2597 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2598 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2599 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2600 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2601 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2602 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2603 2604 void r100_pll_errata_after_index(struct radeon_device *rdev); 2605 2606 2607 /* 2608 * ASICs helpers. 2609 */ 2610 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2611 (rdev->pdev->device == 0x5969)) 2612 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2613 (rdev->family == CHIP_RV200) || \ 2614 (rdev->family == CHIP_RS100) || \ 2615 (rdev->family == CHIP_RS200) || \ 2616 (rdev->family == CHIP_RV250) || \ 2617 (rdev->family == CHIP_RV280) || \ 2618 (rdev->family == CHIP_RS300)) 2619 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2620 (rdev->family == CHIP_RV350) || \ 2621 (rdev->family == CHIP_R350) || \ 2622 (rdev->family == CHIP_RV380) || \ 2623 (rdev->family == CHIP_R420) || \ 2624 (rdev->family == CHIP_R423) || \ 2625 (rdev->family == CHIP_RV410) || \ 2626 (rdev->family == CHIP_RS400) || \ 2627 (rdev->family == CHIP_RS480)) 2628 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2629 (rdev->ddev->pdev->device == 0x9443) || \ 2630 (rdev->ddev->pdev->device == 0x944B) || \ 2631 (rdev->ddev->pdev->device == 0x9506) || \ 2632 (rdev->ddev->pdev->device == 0x9509) || \ 2633 (rdev->ddev->pdev->device == 0x950F) || \ 2634 (rdev->ddev->pdev->device == 0x689C) || \ 2635 (rdev->ddev->pdev->device == 0x689D)) 2636 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2637 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2638 (rdev->family == CHIP_RS690) || \ 2639 (rdev->family == CHIP_RS740) || \ 2640 (rdev->family >= CHIP_R600)) 2641 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2642 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2643 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2644 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2645 (rdev->flags & RADEON_IS_IGP)) 2646 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2647 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2648 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2649 (rdev->flags & RADEON_IS_IGP)) 2650 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2651 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2652 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2653 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2654 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2655 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2656 (rdev->family == CHIP_MULLINS)) 2657 2658 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2659 (rdev->ddev->pdev->device == 0x6850) || \ 2660 (rdev->ddev->pdev->device == 0x6858) || \ 2661 (rdev->ddev->pdev->device == 0x6859) || \ 2662 (rdev->ddev->pdev->device == 0x6840) || \ 2663 (rdev->ddev->pdev->device == 0x6841) || \ 2664 (rdev->ddev->pdev->device == 0x6842) || \ 2665 (rdev->ddev->pdev->device == 0x6843)) 2666 2667 /* 2668 * BIOS helpers. 2669 */ 2670 #define RBIOS8(i) (rdev->bios[i]) 2671 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2672 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2673 2674 int radeon_combios_init(struct radeon_device *rdev); 2675 void radeon_combios_fini(struct radeon_device *rdev); 2676 int radeon_atombios_init(struct radeon_device *rdev); 2677 void radeon_atombios_fini(struct radeon_device *rdev); 2678 2679 2680 /* 2681 * RING helpers. 2682 */ 2683 2684 /** 2685 * radeon_ring_write - write a value to the ring 2686 * 2687 * @ring: radeon_ring structure holding ring information 2688 * @v: dword (dw) value to write 2689 * 2690 * Write a value to the requested ring buffer (all asics). 2691 */ 2692 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2693 { 2694 if (ring->count_dw <= 0) 2695 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2696 2697 ring->ring[ring->wptr++] = v; 2698 ring->wptr &= ring->ptr_mask; 2699 ring->count_dw--; 2700 ring->ring_free_dw--; 2701 } 2702 2703 /* 2704 * ASICs macro. 2705 */ 2706 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2707 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2708 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2709 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2710 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2711 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2712 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2713 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2714 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2715 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2716 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2717 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2718 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2719 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2720 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2721 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2722 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2723 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2724 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2725 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2726 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2727 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2728 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2729 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2730 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2731 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2732 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2733 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2734 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2735 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2736 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2737 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2738 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2739 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2740 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2741 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2742 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2743 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2744 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2745 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2746 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2747 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2748 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2749 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2750 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2751 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2752 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2753 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2754 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2755 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2756 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2757 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2758 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2759 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2760 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2761 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2762 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2763 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2764 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2765 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2766 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2767 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2768 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2769 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2770 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2771 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2772 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2773 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2774 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2775 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2776 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2777 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2778 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2779 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2780 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2781 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2782 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2783 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2784 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2785 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2786 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2787 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2788 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2789 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2790 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2791 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2792 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2793 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2794 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2795 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2796 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2797 2798 /* Common functions */ 2799 /* AGP */ 2800 extern int radeon_gpu_reset(struct radeon_device *rdev); 2801 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2802 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2803 extern void radeon_agp_disable(struct radeon_device *rdev); 2804 extern int radeon_modeset_init(struct radeon_device *rdev); 2805 extern void radeon_modeset_fini(struct radeon_device *rdev); 2806 extern bool radeon_card_posted(struct radeon_device *rdev); 2807 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2808 extern void radeon_update_display_priority(struct radeon_device *rdev); 2809 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2810 extern void radeon_scratch_init(struct radeon_device *rdev); 2811 extern void radeon_wb_fini(struct radeon_device *rdev); 2812 extern int radeon_wb_init(struct radeon_device *rdev); 2813 extern void radeon_wb_disable(struct radeon_device *rdev); 2814 extern void radeon_surface_init(struct radeon_device *rdev); 2815 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2816 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2817 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2818 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2819 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2820 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2821 uint32_t flags); 2822 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2823 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2824 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2825 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2826 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2827 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2828 bool fbcon, bool freeze); 2829 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2830 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2831 const u32 *registers, 2832 const u32 array_size); 2833 2834 /* 2835 * vm 2836 */ 2837 int radeon_vm_manager_init(struct radeon_device *rdev); 2838 void radeon_vm_manager_fini(struct radeon_device *rdev); 2839 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2840 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2841 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2842 struct radeon_vm *vm, 2843 struct list_head *head); 2844 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2845 struct radeon_vm *vm, int ring); 2846 void radeon_vm_flush(struct radeon_device *rdev, 2847 struct radeon_vm *vm, 2848 int ring, struct radeon_fence *fence); 2849 void radeon_vm_fence(struct radeon_device *rdev, 2850 struct radeon_vm *vm, 2851 struct radeon_fence *fence); 2852 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2853 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2854 struct radeon_vm *vm); 2855 int radeon_vm_clear_freed(struct radeon_device *rdev, 2856 struct radeon_vm *vm); 2857 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2858 struct radeon_vm *vm); 2859 int radeon_vm_bo_update(struct radeon_device *rdev, 2860 struct radeon_bo_va *bo_va, 2861 struct ttm_mem_reg *mem); 2862 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2863 struct radeon_bo *bo); 2864 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2865 struct radeon_bo *bo); 2866 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2867 struct radeon_vm *vm, 2868 struct radeon_bo *bo); 2869 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2870 struct radeon_bo_va *bo_va, 2871 uint64_t offset, 2872 uint32_t flags); 2873 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2874 struct radeon_bo_va *bo_va); 2875 2876 /* audio */ 2877 void r600_audio_update_hdmi(struct work_struct *work); 2878 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2879 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2880 void r600_audio_enable(struct radeon_device *rdev, 2881 struct r600_audio_pin *pin, 2882 u8 enable_mask); 2883 void dce6_audio_enable(struct radeon_device *rdev, 2884 struct r600_audio_pin *pin, 2885 u8 enable_mask); 2886 2887 /* 2888 * R600 vram scratch functions 2889 */ 2890 int r600_vram_scratch_init(struct radeon_device *rdev); 2891 void r600_vram_scratch_fini(struct radeon_device *rdev); 2892 2893 /* 2894 * r600 cs checking helper 2895 */ 2896 unsigned r600_mip_minify(unsigned size, unsigned level); 2897 bool r600_fmt_is_valid_color(u32 format); 2898 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2899 int r600_fmt_get_blocksize(u32 format); 2900 int r600_fmt_get_nblocksx(u32 format, u32 w); 2901 int r600_fmt_get_nblocksy(u32 format, u32 h); 2902 2903 /* 2904 * r600 functions used by radeon_encoder.c 2905 */ 2906 struct radeon_hdmi_acr { 2907 u32 clock; 2908 2909 int n_32khz; 2910 int cts_32khz; 2911 2912 int n_44_1khz; 2913 int cts_44_1khz; 2914 2915 int n_48khz; 2916 int cts_48khz; 2917 2918 }; 2919 2920 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2921 2922 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2923 u32 tiling_pipe_num, 2924 u32 max_rb_num, 2925 u32 total_max_rb_num, 2926 u32 enabled_rb_mask); 2927 2928 /* 2929 * evergreen functions used by radeon_encoder.c 2930 */ 2931 2932 extern int ni_init_microcode(struct radeon_device *rdev); 2933 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2934 2935 /* radeon_acpi.c */ 2936 #if defined(CONFIG_ACPI) 2937 extern int radeon_acpi_init(struct radeon_device *rdev); 2938 extern void radeon_acpi_fini(struct radeon_device *rdev); 2939 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2940 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2941 u8 perf_req, bool advertise); 2942 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2943 #else 2944 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2945 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2946 #endif 2947 2948 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2949 struct radeon_cs_packet *pkt, 2950 unsigned idx); 2951 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2952 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2953 struct radeon_cs_packet *pkt); 2954 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2955 struct radeon_bo_list **cs_reloc, 2956 int nomm); 2957 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2958 uint32_t *vline_start_end, 2959 uint32_t *vline_status); 2960 2961 /* interrupt control register helpers */ 2962 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2963 u32 reg, u32 mask, 2964 bool enable, const char *name, 2965 unsigned n); 2966 2967 #include "radeon_object.h" 2968 2969 #endif 2970
Indexes created Mon Oct 27 17:09:47 GMT 2025