radeon.h revision 1.10
1 /* $NetBSD: radeon.h,v 1.10 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <linux/atomic.h> 66 #include <linux/wait.h> 67 #include <linux/list.h> 68 #include <linux/kref.h> 69 #include <linux/interval_tree.h> 70 #include <linux/hashtable.h> 71 #include <linux/dma-fence.h> 72 73 #ifdef CONFIG_MMU_NOTIFIER 74 #include <linux/mmu_notifier.h> 75 #endif 76 77 #include <drm/ttm/ttm_bo_api.h> 78 #include <drm/ttm/ttm_bo_driver.h> 79 #include <drm/ttm/ttm_placement.h> 80 #include <drm/ttm/ttm_module.h> 81 #include <drm/ttm/ttm_execbuf_util.h> 82 83 #include <drm/drm_gem.h> 84 85 #include "radeon_family.h" 86 #include "radeon_mode.h" 87 #include "radeon_reg.h" 88 89 /* 90 * Modules parameters. 91 */ 92 extern int radeon_no_wb; 93 extern int radeon_modeset; 94 extern int radeon_dynclks; 95 extern int radeon_r4xx_atom; 96 extern int radeon_agpmode; 97 extern int radeon_vram_limit; 98 extern int radeon_gart_size; 99 extern int radeon_benchmarking; 100 extern int radeon_testing; 101 extern int radeon_connector_table; 102 extern int radeon_tv; 103 extern int radeon_audio; 104 extern int radeon_disp_priority; 105 extern int radeon_hw_i2c; 106 extern int radeon_pcie_gen2; 107 extern int radeon_msi; 108 extern int radeon_lockup_timeout; 109 extern int radeon_fastfb; 110 extern int radeon_dpm; 111 extern int radeon_aspm; 112 extern int radeon_runtime_pm; 113 extern int radeon_hard_reset; 114 extern int radeon_vm_size; 115 extern int radeon_vm_block_size; 116 extern int radeon_deep_color; 117 extern int radeon_use_pflipirq; 118 extern int radeon_bapm; 119 extern int radeon_backlight; 120 extern int radeon_auxch; 121 extern int radeon_mst; 122 extern int radeon_uvd; 123 extern int radeon_vce; 124 extern int radeon_si_support; 125 extern int radeon_cik_support; 126 127 /* 128 * Copy from radeon_drv.h so we don't have to include both and have conflicting 129 * symbol; 130 */ 131 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 132 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 133 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 134 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 135 #define RADEON_IB_POOL_SIZE 16 136 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 137 #define RADEONFB_CONN_LIMIT 4 138 #define RADEON_BIOS_NUM_SCRATCH 8 139 140 /* internal ring indices */ 141 /* r1xx+ has gfx CP ring */ 142 #define RADEON_RING_TYPE_GFX_INDEX 0 143 144 /* cayman has 2 compute CP rings */ 145 #define CAYMAN_RING_TYPE_CP1_INDEX 1 146 #define CAYMAN_RING_TYPE_CP2_INDEX 2 147 148 /* R600+ has an async dma ring */ 149 #define R600_RING_TYPE_DMA_INDEX 3 150 /* cayman add a second async dma ring */ 151 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 152 153 /* R600+ */ 154 #define R600_RING_TYPE_UVD_INDEX 5 155 156 /* TN+ */ 157 #define TN_RING_TYPE_VCE1_INDEX 6 158 #define TN_RING_TYPE_VCE2_INDEX 7 159 160 /* max number of rings */ 161 #define RADEON_NUM_RINGS 8 162 163 /* number of hw syncs before falling back on blocking */ 164 #define RADEON_NUM_SYNCS 4 165 166 /* hardcode those limit for now */ 167 #define RADEON_VA_IB_OFFSET (1 << 20) 168 #define RADEON_VA_RESERVED_SIZE (8 << 20) 169 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 170 171 /* hard reset data */ 172 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 173 174 /* reset flags */ 175 #define RADEON_RESET_GFX (1 << 0) 176 #define RADEON_RESET_COMPUTE (1 << 1) 177 #define RADEON_RESET_DMA (1 << 2) 178 #define RADEON_RESET_CP (1 << 3) 179 #define RADEON_RESET_GRBM (1 << 4) 180 #define RADEON_RESET_DMA1 (1 << 5) 181 #define RADEON_RESET_RLC (1 << 6) 182 #define RADEON_RESET_SEM (1 << 7) 183 #define RADEON_RESET_IH (1 << 8) 184 #define RADEON_RESET_VMC (1 << 9) 185 #define RADEON_RESET_MC (1 << 10) 186 #define RADEON_RESET_DISPLAY (1 << 11) 187 188 /* CG block flags */ 189 #define RADEON_CG_BLOCK_GFX (1 << 0) 190 #define RADEON_CG_BLOCK_MC (1 << 1) 191 #define RADEON_CG_BLOCK_SDMA (1 << 2) 192 #define RADEON_CG_BLOCK_UVD (1 << 3) 193 #define RADEON_CG_BLOCK_VCE (1 << 4) 194 #define RADEON_CG_BLOCK_HDP (1 << 5) 195 #define RADEON_CG_BLOCK_BIF (1 << 6) 196 197 /* CG flags */ 198 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 199 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 200 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 201 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 202 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 203 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 204 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 205 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 206 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 207 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 208 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 209 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 210 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 211 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 212 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 213 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 214 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 215 216 /* PG flags */ 217 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 218 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 219 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 220 #define RADEON_PG_SUPPORT_UVD (1 << 3) 221 #define RADEON_PG_SUPPORT_VCE (1 << 4) 222 #define RADEON_PG_SUPPORT_CP (1 << 5) 223 #define RADEON_PG_SUPPORT_GDS (1 << 6) 224 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 225 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 226 #define RADEON_PG_SUPPORT_ACP (1 << 9) 227 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 228 229 /* max cursor sizes (in pixels) */ 230 #define CURSOR_WIDTH 64 231 #define CURSOR_HEIGHT 64 232 233 #define CIK_CURSOR_WIDTH 128 234 #define CIK_CURSOR_HEIGHT 128 235 236 /* 237 * Errata workarounds. 238 */ 239 enum radeon_pll_errata { 240 CHIP_ERRATA_R300_CG = 0x00000001, 241 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 242 CHIP_ERRATA_PLL_DELAY = 0x00000004 243 }; 244 245 246 struct radeon_device; 247 248 #ifdef __NetBSD__ 249 extern struct radeon_device *radeon_device_private(device_t); 250 #endif 251 252 /* 253 * BIOS. 254 */ 255 bool radeon_get_bios(struct radeon_device *rdev); 256 257 /* 258 * Dummy page 259 */ 260 struct radeon_dummy_page { 261 uint64_t entry; 262 #ifdef __NetBSD__ 263 bus_dma_segment_t rdp_seg; 264 bus_dmamap_t rdp_map; 265 void *rdp_addr; 266 #else 267 struct page *page; 268 #endif 269 dma_addr_t addr; 270 }; 271 int radeon_dummy_page_init(struct radeon_device *rdev); 272 void radeon_dummy_page_fini(struct radeon_device *rdev); 273 274 275 /* 276 * Clocks 277 */ 278 struct radeon_clock { 279 struct radeon_pll p1pll; 280 struct radeon_pll p2pll; 281 struct radeon_pll dcpll; 282 struct radeon_pll spll; 283 struct radeon_pll mpll; 284 /* 10 Khz units */ 285 uint32_t default_mclk; 286 uint32_t default_sclk; 287 uint32_t default_dispclk; 288 uint32_t current_dispclk; 289 uint32_t dp_extclk; 290 uint32_t max_pixel_clock; 291 uint32_t vco_freq; 292 }; 293 294 /* 295 * Power management 296 */ 297 int radeon_pm_init(struct radeon_device *rdev); 298 int radeon_pm_late_init(struct radeon_device *rdev); 299 void radeon_pm_fini(struct radeon_device *rdev); 300 void radeon_pm_compute_clocks(struct radeon_device *rdev); 301 void radeon_pm_suspend(struct radeon_device *rdev); 302 void radeon_pm_resume(struct radeon_device *rdev); 303 void radeon_combios_get_power_modes(struct radeon_device *rdev); 304 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 305 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 306 u8 clock_type, 307 u32 clock, 308 bool strobe_mode, 309 struct atom_clock_dividers *dividers); 310 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 311 u32 clock, 312 bool strobe_mode, 313 struct atom_mpll_param *mpll_param); 314 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 315 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 316 u16 voltage_level, u8 voltage_type, 317 u32 *gpio_value, u32 *gpio_mask); 318 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 319 u32 eng_clock, u32 mem_clock); 320 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 321 u8 voltage_type, u16 *voltage_step); 322 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 323 u16 voltage_id, u16 *voltage); 324 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 325 u16 *voltage, 326 u16 leakage_idx); 327 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 328 u16 *leakage_id); 329 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 330 u16 *vddc, u16 *vddci, 331 u16 virtual_voltage_id, 332 u16 vbios_voltage_id); 333 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 334 u16 virtual_voltage_id, 335 u16 *voltage); 336 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 337 u8 voltage_type, 338 u16 nominal_voltage, 339 u16 *true_voltage); 340 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 341 u8 voltage_type, u16 *min_voltage); 342 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 343 u8 voltage_type, u16 *max_voltage); 344 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 345 u8 voltage_type, u8 voltage_mode, 346 struct atom_voltage_table *voltage_table); 347 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 348 u8 voltage_type, u8 voltage_mode); 349 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 350 u8 voltage_type, 351 u8 *svd_gpio_id, u8 *svc_gpio_id); 352 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 353 u32 mem_clock); 354 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 355 u32 mem_clock); 356 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 357 u8 module_index, 358 struct atom_mc_reg_table *reg_table); 359 int radeon_atom_get_memory_info(struct radeon_device *rdev, 360 u8 module_index, struct atom_memory_info *mem_info); 361 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 362 bool gddr5, u8 module_index, 363 struct atom_memory_clock_range_table *mclk_range_table); 364 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 365 u16 voltage_id, u16 *voltage); 366 void rs690_pm_info(struct radeon_device *rdev); 367 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 368 unsigned *bankh, unsigned *mtaspect, 369 unsigned *tile_split); 370 371 /* 372 * Fences. 373 */ 374 struct radeon_fence_driver { 375 struct radeon_device *rdev; 376 uint32_t scratch_reg; 377 uint64_t gpu_addr; 378 volatile uint32_t *cpu_addr; 379 /* sync_seq is protected by ring emission lock */ 380 uint64_t sync_seq[RADEON_NUM_RINGS]; 381 atomic64_t last_seq; 382 bool initialized, delayed_irq; 383 struct delayed_work lockup_work; 384 }; 385 386 struct radeon_fence { 387 struct dma_fence base; 388 389 struct radeon_device *rdev; 390 uint64_t seq; 391 /* RB, DMA, etc. */ 392 unsigned ring; 393 bool is_vm_update; 394 395 #ifdef __NetBSD__ 396 TAILQ_ENTRY(radeon_fence) fence_check; 397 #else 398 wait_queue_entry_t fence_wake; 399 #endif 400 }; 401 402 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 403 int radeon_fence_driver_init(struct radeon_device *rdev); 404 void radeon_fence_driver_fini(struct radeon_device *rdev); 405 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 406 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 407 void radeon_fence_wakeup_locked(struct radeon_device *rdev); 408 void radeon_fence_process(struct radeon_device *rdev, int ring); 409 bool radeon_fence_signaled(struct radeon_fence *fence); 410 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 411 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 412 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 413 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 414 int radeon_fence_wait_any(struct radeon_device *rdev, 415 struct radeon_fence **fences, 416 bool intr); 417 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 418 void radeon_fence_unref(struct radeon_fence **fence); 419 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 420 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 421 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 422 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 423 struct radeon_fence *b) 424 { 425 if (!a) { 426 return b; 427 } 428 429 if (!b) { 430 return a; 431 } 432 433 BUG_ON(a->ring != b->ring); 434 435 if (a->seq > b->seq) { 436 return a; 437 } else { 438 return b; 439 } 440 } 441 442 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 443 struct radeon_fence *b) 444 { 445 if (!a) { 446 return false; 447 } 448 449 if (!b) { 450 return true; 451 } 452 453 BUG_ON(a->ring != b->ring); 454 455 return a->seq < b->seq; 456 } 457 458 /* 459 * Tiling registers 460 */ 461 struct radeon_surface_reg { 462 struct radeon_bo *bo; 463 }; 464 465 #define RADEON_GEM_MAX_SURFACES 8 466 467 /* 468 * TTM. 469 */ 470 struct radeon_mman { 471 struct ttm_bo_device bdev; 472 bool initialized; 473 474 #if defined(CONFIG_DEBUG_FS) 475 struct dentry *vram; 476 struct dentry *gtt; 477 #endif 478 }; 479 480 struct radeon_bo_list { 481 struct radeon_bo *robj; 482 struct ttm_validate_buffer tv; 483 uint64_t gpu_offset; 484 unsigned preferred_domains; 485 unsigned allowed_domains; 486 uint32_t tiling_flags; 487 }; 488 489 /* bo virtual address in a specific vm */ 490 struct radeon_bo_va { 491 /* protected by bo being reserved */ 492 struct list_head bo_list; 493 uint32_t flags; 494 struct radeon_fence *last_pt_update; 495 unsigned ref_count; 496 497 /* protected by vm mutex */ 498 struct interval_tree_node it; 499 struct list_head vm_status; 500 501 /* constant after initialization */ 502 struct radeon_vm *vm; 503 struct radeon_bo *bo; 504 }; 505 506 struct radeon_bo { 507 /* Protected by gem.mutex */ 508 struct list_head list; 509 /* Protected by tbo.reserved */ 510 u32 initial_domain; 511 struct ttm_place placements[4]; 512 struct ttm_placement placement; 513 struct ttm_buffer_object tbo; 514 struct ttm_bo_kmap_obj kmap; 515 u32 flags; 516 unsigned pin_count; 517 void *kptr; 518 u32 tiling_flags; 519 u32 pitch; 520 int surface_reg; 521 unsigned prime_shared_count; 522 /* list of all virtual address to which this bo 523 * is associated to 524 */ 525 struct list_head va; 526 /* Constant after initialization */ 527 struct radeon_device *rdev; 528 529 struct ttm_bo_kmap_obj dma_buf_vmap; 530 #ifndef __NetBSD__ /* XXX pid??? */ 531 pid_t pid; 532 #endif 533 534 #ifdef CONFIG_MMU_NOTIFIER 535 struct mmu_interval_notifier notifier; 536 #endif 537 }; 538 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 539 540 int radeon_gem_debugfs_init(struct radeon_device *rdev); 541 542 /* sub-allocation manager, it has to be protected by another lock. 543 * By conception this is an helper for other part of the driver 544 * like the indirect buffer or semaphore, which both have their 545 * locking. 546 * 547 * Principe is simple, we keep a list of sub allocation in offset 548 * order (first entry has offset == 0, last entry has the highest 549 * offset). 550 * 551 * When allocating new object we first check if there is room at 552 * the end total_size - (last_object_offset + last_object_size) >= 553 * alloc_size. If so we allocate new object there. 554 * 555 * When there is not enough room at the end, we start waiting for 556 * each sub object until we reach object_offset+object_size >= 557 * alloc_size, this object then become the sub object we return. 558 * 559 * Alignment can't be bigger than page size. 560 * 561 * Hole are not considered for allocation to keep things simple. 562 * Assumption is that there won't be hole (all object on same 563 * alignment). 564 */ 565 struct radeon_sa_manager { 566 #ifdef __NetBSD__ 567 spinlock_t wq_lock; 568 drm_waitqueue_t wq; 569 #else 570 wait_queue_head_t wq; 571 #endif 572 struct radeon_bo *bo; 573 struct list_head *hole; 574 struct list_head flist[RADEON_NUM_RINGS]; 575 struct list_head olist; 576 unsigned size; 577 uint64_t gpu_addr; 578 void *cpu_ptr; 579 uint32_t domain; 580 uint32_t align; 581 }; 582 583 struct radeon_sa_bo; 584 585 /* sub-allocation buffer */ 586 struct radeon_sa_bo { 587 struct list_head olist; 588 struct list_head flist; 589 struct radeon_sa_manager *manager; 590 unsigned soffset; 591 unsigned eoffset; 592 struct radeon_fence *fence; 593 }; 594 595 /* 596 * GEM objects. 597 */ 598 struct radeon_gem { 599 struct mutex mutex; 600 struct list_head objects; 601 }; 602 603 int radeon_gem_init(struct radeon_device *rdev); 604 void radeon_gem_fini(struct radeon_device *rdev); 605 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 606 int alignment, int initial_domain, 607 u32 flags, bool kernel, 608 struct drm_gem_object **obj); 609 610 int radeon_mode_dumb_create(struct drm_file *file_priv, 611 struct drm_device *dev, 612 struct drm_mode_create_dumb *args); 613 int radeon_mode_dumb_mmap(struct drm_file *filp, 614 struct drm_device *dev, 615 uint32_t handle, uint64_t *offset_p); 616 617 /* 618 * Semaphores. 619 */ 620 struct radeon_semaphore { 621 struct radeon_sa_bo *sa_bo; 622 signed waiters; 623 uint64_t gpu_addr; 624 }; 625 626 int radeon_semaphore_create(struct radeon_device *rdev, 627 struct radeon_semaphore **semaphore); 628 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 629 struct radeon_semaphore *semaphore); 630 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 631 struct radeon_semaphore *semaphore); 632 void radeon_semaphore_free(struct radeon_device *rdev, 633 struct radeon_semaphore **semaphore, 634 struct radeon_fence *fence); 635 636 /* 637 * Synchronization 638 */ 639 struct radeon_sync { 640 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 641 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 642 struct radeon_fence *last_vm_update; 643 }; 644 645 void radeon_sync_create(struct radeon_sync *sync); 646 void radeon_sync_fence(struct radeon_sync *sync, 647 struct radeon_fence *fence); 648 int radeon_sync_resv(struct radeon_device *rdev, 649 struct radeon_sync *sync, 650 struct dma_resv *resv, 651 bool shared); 652 int radeon_sync_rings(struct radeon_device *rdev, 653 struct radeon_sync *sync, 654 int waiting_ring); 655 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 656 struct radeon_fence *fence); 657 658 /* 659 * GART structures, functions & helpers 660 */ 661 struct radeon_mc; 662 663 #define RADEON_GPU_PAGE_SIZE 4096 664 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 665 #define RADEON_GPU_PAGE_SHIFT 12 666 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 667 668 #define RADEON_GART_PAGE_DUMMY 0 669 #define RADEON_GART_PAGE_VALID (1 << 0) 670 #define RADEON_GART_PAGE_READ (1 << 1) 671 #define RADEON_GART_PAGE_WRITE (1 << 2) 672 #define RADEON_GART_PAGE_SNOOP (1 << 3) 673 674 struct radeon_gart { 675 #ifdef __NetBSD__ 676 bus_dma_segment_t rg_table_seg; 677 bus_dmamap_t rg_table_map; 678 #endif 679 dma_addr_t table_addr; 680 struct radeon_bo *robj; 681 void *ptr; 682 unsigned num_gpu_pages; 683 unsigned num_cpu_pages; 684 unsigned table_size; 685 struct page **pages; 686 uint64_t *pages_entry; 687 bool ready; 688 }; 689 690 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 691 void radeon_gart_table_ram_free(struct radeon_device *rdev); 692 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 693 void radeon_gart_table_vram_free(struct radeon_device *rdev); 694 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 695 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 696 int radeon_gart_init(struct radeon_device *rdev); 697 void radeon_gart_fini(struct radeon_device *rdev); 698 #ifdef __NetBSD__ 699 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 700 unsigned npages); 701 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 702 unsigned npages, struct page **pages, 703 bus_dmamap_t dmamap, uint32_t flags); 704 #else 705 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 706 int pages); 707 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 708 int pages, struct page **pagelist, 709 dma_addr_t *dma_addr, uint32_t flags); 710 #endif 711 712 713 /* 714 * GPU MC structures, functions & helpers 715 */ 716 struct radeon_mc { 717 resource_size_t aper_size; 718 resource_size_t aper_base; 719 resource_size_t agp_base; 720 /* for some chips with <= 32MB we need to lie 721 * about vram size near mc fb location */ 722 u64 mc_vram_size; 723 u64 visible_vram_size; 724 u64 gtt_size; 725 u64 gtt_start; 726 u64 gtt_end; 727 u64 vram_start; 728 u64 vram_end; 729 unsigned vram_width; 730 u64 real_vram_size; 731 int vram_mtrr; 732 bool vram_is_ddr; 733 bool igp_sideport_enabled; 734 u64 gtt_base_align; 735 u64 mc_mask; 736 }; 737 738 bool radeon_combios_sideport_present(struct radeon_device *rdev); 739 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 740 741 /* 742 * GPU scratch registers structures, functions & helpers 743 */ 744 struct radeon_scratch { 745 unsigned num_reg; 746 uint32_t reg_base; 747 bool free[32]; 748 uint32_t reg[32]; 749 }; 750 751 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 752 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 753 754 /* 755 * GPU doorbell structures, functions & helpers 756 */ 757 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 758 759 struct radeon_doorbell { 760 /* doorbell mmio */ 761 resource_size_t base; 762 resource_size_t size; 763 #ifdef __NetBSD__ 764 bus_space_tag_t bst; 765 bus_space_handle_t bsh; 766 #else 767 u32 __iomem *ptr; 768 #endif 769 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 770 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 771 }; 772 773 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 774 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 775 776 /* 777 * IRQS. 778 */ 779 780 struct radeon_flip_work { 781 struct work_struct flip_work; 782 struct work_struct unpin_work; 783 struct radeon_device *rdev; 784 int crtc_id; 785 u32 target_vblank; 786 uint64_t base; 787 struct drm_pending_vblank_event *event; 788 struct radeon_bo *old_rbo; 789 struct dma_fence *fence; 790 bool async; 791 }; 792 793 struct r500_irq_stat_regs { 794 u32 disp_int; 795 u32 hdmi0_status; 796 }; 797 798 struct r600_irq_stat_regs { 799 u32 disp_int; 800 u32 disp_int_cont; 801 u32 disp_int_cont2; 802 u32 d1grph_int; 803 u32 d2grph_int; 804 u32 hdmi0_status; 805 u32 hdmi1_status; 806 }; 807 808 struct evergreen_irq_stat_regs { 809 u32 disp_int[6]; 810 u32 grph_int[6]; 811 u32 afmt_status[6]; 812 }; 813 814 struct cik_irq_stat_regs { 815 u32 disp_int; 816 u32 disp_int_cont; 817 u32 disp_int_cont2; 818 u32 disp_int_cont3; 819 u32 disp_int_cont4; 820 u32 disp_int_cont5; 821 u32 disp_int_cont6; 822 u32 d1grph_int; 823 u32 d2grph_int; 824 u32 d3grph_int; 825 u32 d4grph_int; 826 u32 d5grph_int; 827 u32 d6grph_int; 828 }; 829 830 union radeon_irq_stat_regs { 831 struct r500_irq_stat_regs r500; 832 struct r600_irq_stat_regs r600; 833 struct evergreen_irq_stat_regs evergreen; 834 struct cik_irq_stat_regs cik; 835 }; 836 837 struct radeon_irq { 838 bool installed; 839 spinlock_t lock; 840 atomic_t ring_int[RADEON_NUM_RINGS]; 841 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 842 atomic_t pflip[RADEON_MAX_CRTCS]; 843 #ifdef __NetBSD__ 844 spinlock_t vblank_lock; 845 drm_waitqueue_t vblank_queue; 846 #else 847 wait_queue_head_t vblank_queue; 848 #endif 849 bool hpd[RADEON_MAX_HPD_PINS]; 850 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 851 union radeon_irq_stat_regs stat_regs; 852 bool dpm_thermal; 853 }; 854 855 int radeon_irq_kms_init(struct radeon_device *rdev); 856 void radeon_irq_kms_fini(struct radeon_device *rdev); 857 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 858 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 859 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 860 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 861 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 862 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 863 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 864 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 865 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 866 867 /* 868 * CP & rings. 869 */ 870 871 struct radeon_ib { 872 struct radeon_sa_bo *sa_bo; 873 uint32_t length_dw; 874 uint64_t gpu_addr; 875 uint32_t *ptr; 876 int ring; 877 struct radeon_fence *fence; 878 struct radeon_vm *vm; 879 bool is_const_ib; 880 struct radeon_sync sync; 881 }; 882 883 struct radeon_ring { 884 struct radeon_bo *ring_obj; 885 volatile uint32_t *ring; 886 unsigned rptr_offs; 887 unsigned rptr_save_reg; 888 u64 next_rptr_gpu_addr; 889 volatile u32 *next_rptr_cpu_addr; 890 unsigned wptr; 891 unsigned wptr_old; 892 unsigned ring_size; 893 unsigned ring_free_dw; 894 int count_dw; 895 atomic_t last_rptr; 896 atomic64_t last_activity; 897 uint64_t gpu_addr; 898 uint32_t align_mask; 899 uint32_t ptr_mask; 900 bool ready; 901 u32 nop; 902 u32 idx; 903 u64 last_semaphore_signal_addr; 904 u64 last_semaphore_wait_addr; 905 /* for CIK queues */ 906 u32 me; 907 u32 pipe; 908 u32 queue; 909 struct radeon_bo *mqd_obj; 910 u32 doorbell_index; 911 unsigned wptr_offs; 912 }; 913 914 struct radeon_mec { 915 struct radeon_bo *hpd_eop_obj; 916 u64 hpd_eop_gpu_addr; 917 u32 num_pipe; 918 u32 num_mec; 919 u32 num_queue; 920 }; 921 922 /* 923 * VM 924 */ 925 926 /* maximum number of VMIDs */ 927 #define RADEON_NUM_VM 16 928 929 /* number of entries in page table */ 930 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 931 932 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 933 #define RADEON_VM_PTB_ALIGN_SIZE 32768 934 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 935 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 936 937 #define R600_PTE_VALID (1 << 0) 938 #define R600_PTE_SYSTEM (1 << 1) 939 #define R600_PTE_SNOOPED (1 << 2) 940 #define R600_PTE_READABLE (1 << 5) 941 #define R600_PTE_WRITEABLE (1 << 6) 942 943 /* PTE (Page Table Entry) fragment field for different page sizes */ 944 #define R600_PTE_FRAG_4KB (0 << 7) 945 #define R600_PTE_FRAG_64KB (4 << 7) 946 #define R600_PTE_FRAG_256KB (6 << 7) 947 948 /* flags needed to be set so we can copy directly from the GART table */ 949 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 950 R600_PTE_SYSTEM | R600_PTE_VALID ) 951 952 struct radeon_vm_pt { 953 struct radeon_bo *bo; 954 uint64_t addr; 955 }; 956 957 struct radeon_vm_id { 958 unsigned id; 959 uint64_t pd_gpu_addr; 960 /* last flushed PD/PT update */ 961 struct radeon_fence *flushed_updates; 962 /* last use of vmid */ 963 struct radeon_fence *last_id_use; 964 }; 965 966 struct radeon_vm { 967 struct mutex mutex; 968 969 struct rb_root_cached va; 970 971 /* protecting invalidated and freed */ 972 spinlock_t status_lock; 973 974 /* BOs moved, but not yet updated in the PT */ 975 struct list_head invalidated; 976 977 /* BOs freed, but not yet updated in the PT */ 978 struct list_head freed; 979 980 /* BOs cleared in the PT */ 981 struct list_head cleared; 982 983 /* contains the page directory */ 984 struct radeon_bo *page_directory; 985 unsigned max_pde_used; 986 987 /* array of page tables, one for each page directory entry */ 988 struct radeon_vm_pt *page_tables; 989 990 struct radeon_bo_va *ib_bo_va; 991 992 /* for id and flush management per ring */ 993 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 994 }; 995 996 struct radeon_vm_manager { 997 struct radeon_fence *active[RADEON_NUM_VM]; 998 uint32_t max_pfn; 999 /* number of VMIDs */ 1000 unsigned nvm; 1001 /* vram base address for page table entry */ 1002 u64 vram_base_offset; 1003 /* is vm enabled? */ 1004 bool enabled; 1005 /* for hw to save the PD addr on suspend/resume */ 1006 uint32_t saved_table_addr[RADEON_NUM_VM]; 1007 }; 1008 1009 /* 1010 * file private structure 1011 */ 1012 struct radeon_fpriv { 1013 struct radeon_vm vm; 1014 }; 1015 1016 /* 1017 * R6xx+ IH ring 1018 */ 1019 struct r600_ih { 1020 struct radeon_bo *ring_obj; 1021 volatile uint32_t *ring; 1022 unsigned rptr; 1023 unsigned ring_size; 1024 uint64_t gpu_addr; 1025 uint32_t ptr_mask; 1026 atomic_t lock; 1027 bool enabled; 1028 }; 1029 1030 /* 1031 * RLC stuff 1032 */ 1033 #include "clearstate_defs.h" 1034 1035 struct radeon_rlc { 1036 /* for power gating */ 1037 struct radeon_bo *save_restore_obj; 1038 uint64_t save_restore_gpu_addr; 1039 volatile uint32_t *sr_ptr; 1040 const u32 *reg_list; 1041 u32 reg_list_size; 1042 /* for clear state */ 1043 struct radeon_bo *clear_state_obj; 1044 uint64_t clear_state_gpu_addr; 1045 volatile uint32_t *cs_ptr; 1046 const struct cs_section_def *cs_data; 1047 u32 clear_state_size; 1048 /* for cp tables */ 1049 struct radeon_bo *cp_table_obj; 1050 uint64_t cp_table_gpu_addr; 1051 volatile uint32_t *cp_table_ptr; 1052 u32 cp_table_size; 1053 }; 1054 1055 int radeon_ib_get(struct radeon_device *rdev, int ring, 1056 struct radeon_ib *ib, struct radeon_vm *vm, 1057 unsigned size); 1058 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1059 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1060 struct radeon_ib *const_ib, bool hdp_flush); 1061 int radeon_ib_pool_init(struct radeon_device *rdev); 1062 void radeon_ib_pool_fini(struct radeon_device *rdev); 1063 int radeon_ib_ring_tests(struct radeon_device *rdev); 1064 /* Ring access between begin & end cannot sleep */ 1065 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1066 struct radeon_ring *ring); 1067 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1068 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1069 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1070 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1071 bool hdp_flush); 1072 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1073 bool hdp_flush); 1074 void radeon_ring_undo(struct radeon_ring *ring); 1075 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1076 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1077 void radeon_ring_lockup_update(struct radeon_device *rdev, 1078 struct radeon_ring *ring); 1079 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1080 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1081 uint32_t **data); 1082 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1083 unsigned size, uint32_t *data); 1084 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1085 unsigned rptr_offs, u32 nop); 1086 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1087 1088 1089 /* r600 async dma */ 1090 void r600_dma_stop(struct radeon_device *rdev); 1091 int r600_dma_resume(struct radeon_device *rdev); 1092 void r600_dma_fini(struct radeon_device *rdev); 1093 1094 void cayman_dma_stop(struct radeon_device *rdev); 1095 int cayman_dma_resume(struct radeon_device *rdev); 1096 void cayman_dma_fini(struct radeon_device *rdev); 1097 1098 /* 1099 * CS. 1100 */ 1101 struct radeon_cs_chunk { 1102 uint32_t length_dw; 1103 uint32_t *kdata; 1104 void __user *user_ptr; 1105 }; 1106 1107 struct radeon_cs_parser { 1108 struct device *dev; 1109 struct radeon_device *rdev; 1110 struct drm_file *filp; 1111 /* chunks */ 1112 unsigned nchunks; 1113 struct radeon_cs_chunk *chunks; 1114 uint64_t *chunks_array; 1115 /* IB */ 1116 unsigned idx; 1117 /* relocations */ 1118 unsigned nrelocs; 1119 struct radeon_bo_list *relocs; 1120 struct radeon_bo_list *vm_bos; 1121 struct list_head validated; 1122 unsigned dma_reloc_idx; 1123 /* indices of various chunks */ 1124 struct radeon_cs_chunk *chunk_ib; 1125 struct radeon_cs_chunk *chunk_relocs; 1126 struct radeon_cs_chunk *chunk_flags; 1127 struct radeon_cs_chunk *chunk_const_ib; 1128 struct radeon_ib ib; 1129 struct radeon_ib const_ib; 1130 void *track; 1131 unsigned family; 1132 int parser_error; 1133 u32 cs_flags; 1134 u32 ring; 1135 s32 priority; 1136 struct ww_acquire_ctx ticket; 1137 }; 1138 1139 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1140 { 1141 struct radeon_cs_chunk *ibc = p->chunk_ib; 1142 1143 if (ibc->kdata) 1144 return ibc->kdata[idx]; 1145 return p->ib.ptr[idx]; 1146 } 1147 1148 1149 struct radeon_cs_packet { 1150 unsigned idx; 1151 unsigned type; 1152 unsigned reg; 1153 unsigned opcode; 1154 int count; 1155 unsigned one_reg_wr; 1156 }; 1157 1158 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1159 struct radeon_cs_packet *pkt, 1160 unsigned idx, unsigned reg); 1161 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1162 struct radeon_cs_packet *pkt); 1163 1164 1165 /* 1166 * AGP 1167 */ 1168 int radeon_agp_init(struct radeon_device *rdev); 1169 void radeon_agp_resume(struct radeon_device *rdev); 1170 void radeon_agp_suspend(struct radeon_device *rdev); 1171 void radeon_agp_fini(struct radeon_device *rdev); 1172 1173 1174 /* 1175 * Writeback 1176 */ 1177 struct radeon_wb { 1178 struct radeon_bo *wb_obj; 1179 volatile uint32_t *wb; 1180 uint64_t gpu_addr; 1181 bool enabled; 1182 bool use_event; 1183 }; 1184 1185 #define RADEON_WB_SCRATCH_OFFSET 0 1186 #define RADEON_WB_RING0_NEXT_RPTR 256 1187 #define RADEON_WB_CP_RPTR_OFFSET 1024 1188 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1189 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1190 #define R600_WB_DMA_RPTR_OFFSET 1792 1191 #define R600_WB_IH_WPTR_OFFSET 2048 1192 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1193 #define R600_WB_EVENT_OFFSET 3072 1194 #define CIK_WB_CP1_WPTR_OFFSET 3328 1195 #define CIK_WB_CP2_WPTR_OFFSET 3584 1196 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1197 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1198 1199 /** 1200 * struct radeon_pm - power management datas 1201 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1202 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1203 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1204 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1205 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1206 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1207 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1208 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1209 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1210 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1211 * @needed_bandwidth: current bandwidth needs 1212 * 1213 * It keeps track of various data needed to take powermanagement decision. 1214 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1215 * Equation between gpu/memory clock and available bandwidth is hw dependent 1216 * (type of memory, bus size, efficiency, ...) 1217 */ 1218 1219 enum radeon_pm_method { 1220 PM_METHOD_PROFILE, 1221 PM_METHOD_DYNPM, 1222 PM_METHOD_DPM, 1223 }; 1224 1225 enum radeon_dynpm_state { 1226 DYNPM_STATE_DISABLED, 1227 DYNPM_STATE_MINIMUM, 1228 DYNPM_STATE_PAUSED, 1229 DYNPM_STATE_ACTIVE, 1230 DYNPM_STATE_SUSPENDED, 1231 }; 1232 enum radeon_dynpm_action { 1233 DYNPM_ACTION_NONE, 1234 DYNPM_ACTION_MINIMUM, 1235 DYNPM_ACTION_DOWNCLOCK, 1236 DYNPM_ACTION_UPCLOCK, 1237 DYNPM_ACTION_DEFAULT 1238 }; 1239 1240 enum radeon_voltage_type { 1241 VOLTAGE_NONE = 0, 1242 VOLTAGE_GPIO, 1243 VOLTAGE_VDDC, 1244 VOLTAGE_SW 1245 }; 1246 1247 enum radeon_pm_state_type { 1248 /* not used for dpm */ 1249 POWER_STATE_TYPE_DEFAULT, 1250 POWER_STATE_TYPE_POWERSAVE, 1251 /* user selectable states */ 1252 POWER_STATE_TYPE_BATTERY, 1253 POWER_STATE_TYPE_BALANCED, 1254 POWER_STATE_TYPE_PERFORMANCE, 1255 /* internal states */ 1256 POWER_STATE_TYPE_INTERNAL_UVD, 1257 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1258 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1259 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1260 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1261 POWER_STATE_TYPE_INTERNAL_BOOT, 1262 POWER_STATE_TYPE_INTERNAL_THERMAL, 1263 POWER_STATE_TYPE_INTERNAL_ACPI, 1264 POWER_STATE_TYPE_INTERNAL_ULV, 1265 POWER_STATE_TYPE_INTERNAL_3DPERF, 1266 }; 1267 1268 enum radeon_pm_profile_type { 1269 PM_PROFILE_DEFAULT, 1270 PM_PROFILE_AUTO, 1271 PM_PROFILE_LOW, 1272 PM_PROFILE_MID, 1273 PM_PROFILE_HIGH, 1274 }; 1275 1276 #define PM_PROFILE_DEFAULT_IDX 0 1277 #define PM_PROFILE_LOW_SH_IDX 1 1278 #define PM_PROFILE_MID_SH_IDX 2 1279 #define PM_PROFILE_HIGH_SH_IDX 3 1280 #define PM_PROFILE_LOW_MH_IDX 4 1281 #define PM_PROFILE_MID_MH_IDX 5 1282 #define PM_PROFILE_HIGH_MH_IDX 6 1283 #define PM_PROFILE_MAX 7 1284 1285 struct radeon_pm_profile { 1286 int dpms_off_ps_idx; 1287 int dpms_on_ps_idx; 1288 int dpms_off_cm_idx; 1289 int dpms_on_cm_idx; 1290 }; 1291 1292 enum radeon_int_thermal_type { 1293 THERMAL_TYPE_NONE, 1294 THERMAL_TYPE_EXTERNAL, 1295 THERMAL_TYPE_EXTERNAL_GPIO, 1296 THERMAL_TYPE_RV6XX, 1297 THERMAL_TYPE_RV770, 1298 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1299 THERMAL_TYPE_EVERGREEN, 1300 THERMAL_TYPE_SUMO, 1301 THERMAL_TYPE_NI, 1302 THERMAL_TYPE_SI, 1303 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1304 THERMAL_TYPE_CI, 1305 THERMAL_TYPE_KV, 1306 }; 1307 1308 struct radeon_voltage { 1309 enum radeon_voltage_type type; 1310 /* gpio voltage */ 1311 struct radeon_gpio_rec gpio; 1312 u32 delay; /* delay in usec from voltage drop to sclk change */ 1313 bool active_high; /* voltage drop is active when bit is high */ 1314 /* VDDC voltage */ 1315 u8 vddc_id; /* index into vddc voltage table */ 1316 u8 vddci_id; /* index into vddci voltage table */ 1317 bool vddci_enabled; 1318 /* r6xx+ sw */ 1319 u16 voltage; 1320 /* evergreen+ vddci */ 1321 u16 vddci; 1322 }; 1323 1324 /* clock mode flags */ 1325 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1326 1327 struct radeon_pm_clock_info { 1328 /* memory clock */ 1329 u32 mclk; 1330 /* engine clock */ 1331 u32 sclk; 1332 /* voltage info */ 1333 struct radeon_voltage voltage; 1334 /* standardized clock flags */ 1335 u32 flags; 1336 }; 1337 1338 /* state flags */ 1339 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1340 1341 struct radeon_power_state { 1342 enum radeon_pm_state_type type; 1343 struct radeon_pm_clock_info *clock_info; 1344 /* number of valid clock modes in this power state */ 1345 int num_clock_modes; 1346 struct radeon_pm_clock_info *default_clock_mode; 1347 /* standardized state flags */ 1348 u32 flags; 1349 u32 misc; /* vbios specific flags */ 1350 u32 misc2; /* vbios specific flags */ 1351 int pcie_lanes; /* pcie lanes */ 1352 }; 1353 1354 /* 1355 * Some modes are overclocked by very low value, accept them 1356 */ 1357 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1358 1359 enum radeon_dpm_auto_throttle_src { 1360 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1361 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1362 }; 1363 1364 enum radeon_dpm_event_src { 1365 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1366 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1367 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1368 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1369 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1370 }; 1371 1372 #define RADEON_MAX_VCE_LEVELS 6 1373 1374 enum radeon_vce_level { 1375 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1376 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1377 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1378 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1379 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1380 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1381 }; 1382 1383 struct radeon_ps { 1384 u32 caps; /* vbios flags */ 1385 u32 class; /* vbios flags */ 1386 u32 class2; /* vbios flags */ 1387 /* UVD clocks */ 1388 u32 vclk; 1389 u32 dclk; 1390 /* VCE clocks */ 1391 u32 evclk; 1392 u32 ecclk; 1393 bool vce_active; 1394 enum radeon_vce_level vce_level; 1395 /* asic priv */ 1396 void *ps_priv; 1397 }; 1398 1399 struct radeon_dpm_thermal { 1400 /* thermal interrupt work */ 1401 struct work_struct work; 1402 /* low temperature threshold */ 1403 int min_temp; 1404 /* high temperature threshold */ 1405 int max_temp; 1406 /* was interrupt low to high or high to low */ 1407 bool high_to_low; 1408 }; 1409 1410 enum radeon_clk_action 1411 { 1412 RADEON_SCLK_UP = 1, 1413 RADEON_SCLK_DOWN 1414 }; 1415 1416 struct radeon_blacklist_clocks 1417 { 1418 u32 sclk; 1419 u32 mclk; 1420 enum radeon_clk_action action; 1421 }; 1422 1423 struct radeon_clock_and_voltage_limits { 1424 u32 sclk; 1425 u32 mclk; 1426 u16 vddc; 1427 u16 vddci; 1428 }; 1429 1430 struct radeon_clock_array { 1431 u32 count; 1432 u32 *values; 1433 }; 1434 1435 struct radeon_clock_voltage_dependency_entry { 1436 u32 clk; 1437 u16 v; 1438 }; 1439 1440 struct radeon_clock_voltage_dependency_table { 1441 u32 count; 1442 struct radeon_clock_voltage_dependency_entry *entries; 1443 }; 1444 1445 union radeon_cac_leakage_entry { 1446 struct { 1447 u16 vddc; 1448 u32 leakage; 1449 }; 1450 struct { 1451 u16 vddc1; 1452 u16 vddc2; 1453 u16 vddc3; 1454 }; 1455 }; 1456 1457 struct radeon_cac_leakage_table { 1458 u32 count; 1459 union radeon_cac_leakage_entry *entries; 1460 }; 1461 1462 struct radeon_phase_shedding_limits_entry { 1463 u16 voltage; 1464 u32 sclk; 1465 u32 mclk; 1466 }; 1467 1468 struct radeon_phase_shedding_limits_table { 1469 u32 count; 1470 struct radeon_phase_shedding_limits_entry *entries; 1471 }; 1472 1473 struct radeon_uvd_clock_voltage_dependency_entry { 1474 u32 vclk; 1475 u32 dclk; 1476 u16 v; 1477 }; 1478 1479 struct radeon_uvd_clock_voltage_dependency_table { 1480 u8 count; 1481 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1482 }; 1483 1484 struct radeon_vce_clock_voltage_dependency_entry { 1485 u32 ecclk; 1486 u32 evclk; 1487 u16 v; 1488 }; 1489 1490 struct radeon_vce_clock_voltage_dependency_table { 1491 u8 count; 1492 struct radeon_vce_clock_voltage_dependency_entry *entries; 1493 }; 1494 1495 struct radeon_ppm_table { 1496 u8 ppm_design; 1497 u16 cpu_core_number; 1498 u32 platform_tdp; 1499 u32 small_ac_platform_tdp; 1500 u32 platform_tdc; 1501 u32 small_ac_platform_tdc; 1502 u32 apu_tdp; 1503 u32 dgpu_tdp; 1504 u32 dgpu_ulv_power; 1505 u32 tj_max; 1506 }; 1507 1508 struct radeon_cac_tdp_table { 1509 u16 tdp; 1510 u16 configurable_tdp; 1511 u16 tdc; 1512 u16 battery_power_limit; 1513 u16 small_power_limit; 1514 u16 low_cac_leakage; 1515 u16 high_cac_leakage; 1516 u16 maximum_power_delivery_limit; 1517 }; 1518 1519 struct radeon_dpm_dynamic_state { 1520 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1521 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1522 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1523 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1524 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1525 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1526 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1527 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1528 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1529 struct radeon_clock_array valid_sclk_values; 1530 struct radeon_clock_array valid_mclk_values; 1531 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1532 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1533 u32 mclk_sclk_ratio; 1534 u32 sclk_mclk_delta; 1535 u16 vddc_vddci_delta; 1536 u16 min_vddc_for_pcie_gen2; 1537 struct radeon_cac_leakage_table cac_leakage_table; 1538 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1539 struct radeon_ppm_table *ppm_table; 1540 struct radeon_cac_tdp_table *cac_tdp_table; 1541 }; 1542 1543 struct radeon_dpm_fan { 1544 u16 t_min; 1545 u16 t_med; 1546 u16 t_high; 1547 u16 pwm_min; 1548 u16 pwm_med; 1549 u16 pwm_high; 1550 u8 t_hyst; 1551 u32 cycle_delay; 1552 u16 t_max; 1553 u8 control_mode; 1554 u16 default_max_fan_pwm; 1555 u16 default_fan_output_sensitivity; 1556 u16 fan_output_sensitivity; 1557 bool ucode_fan_control; 1558 }; 1559 1560 enum radeon_pcie_gen { 1561 RADEON_PCIE_GEN1 = 0, 1562 RADEON_PCIE_GEN2 = 1, 1563 RADEON_PCIE_GEN3 = 2, 1564 RADEON_PCIE_GEN_INVALID = 0xffff 1565 }; 1566 1567 enum radeon_dpm_forced_level { 1568 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1569 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1570 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1571 }; 1572 1573 struct radeon_vce_state { 1574 /* vce clocks */ 1575 u32 evclk; 1576 u32 ecclk; 1577 /* gpu clocks */ 1578 u32 sclk; 1579 u32 mclk; 1580 u8 clk_idx; 1581 u8 pstate; 1582 }; 1583 1584 struct radeon_dpm { 1585 struct radeon_ps *ps; 1586 /* number of valid power states */ 1587 int num_ps; 1588 /* current power state that is active */ 1589 struct radeon_ps *current_ps; 1590 /* requested power state */ 1591 struct radeon_ps *requested_ps; 1592 /* boot up power state */ 1593 struct radeon_ps *boot_ps; 1594 /* default uvd power state */ 1595 struct radeon_ps *uvd_ps; 1596 /* vce requirements */ 1597 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1598 enum radeon_vce_level vce_level; 1599 enum radeon_pm_state_type state; 1600 enum radeon_pm_state_type user_state; 1601 u32 platform_caps; 1602 u32 voltage_response_time; 1603 u32 backbias_response_time; 1604 void *priv; 1605 u32 new_active_crtcs; 1606 int new_active_crtc_count; 1607 u32 current_active_crtcs; 1608 int current_active_crtc_count; 1609 bool single_display; 1610 struct radeon_dpm_dynamic_state dyn_state; 1611 struct radeon_dpm_fan fan; 1612 u32 tdp_limit; 1613 u32 near_tdp_limit; 1614 u32 near_tdp_limit_adjusted; 1615 u32 sq_ramping_threshold; 1616 u32 cac_leakage; 1617 u16 tdp_od_limit; 1618 u32 tdp_adjustment; 1619 u16 load_line_slope; 1620 bool power_control; 1621 bool ac_power; 1622 /* special states active */ 1623 bool thermal_active; 1624 bool uvd_active; 1625 bool vce_active; 1626 /* thermal handling */ 1627 struct radeon_dpm_thermal thermal; 1628 /* forced levels */ 1629 enum radeon_dpm_forced_level forced_level; 1630 /* track UVD streams */ 1631 unsigned sd; 1632 unsigned hd; 1633 }; 1634 1635 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1636 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1637 1638 struct radeon_pm { 1639 struct mutex mutex; 1640 /* write locked while reprogramming mclk */ 1641 struct rw_semaphore mclk_lock; 1642 u32 active_crtcs; 1643 int active_crtc_count; 1644 int req_vblank; 1645 bool vblank_sync; 1646 fixed20_12 max_bandwidth; 1647 fixed20_12 igp_sideport_mclk; 1648 fixed20_12 igp_system_mclk; 1649 fixed20_12 igp_ht_link_clk; 1650 fixed20_12 igp_ht_link_width; 1651 fixed20_12 k8_bandwidth; 1652 fixed20_12 sideport_bandwidth; 1653 fixed20_12 ht_bandwidth; 1654 fixed20_12 core_bandwidth; 1655 fixed20_12 sclk; 1656 fixed20_12 mclk; 1657 fixed20_12 needed_bandwidth; 1658 struct radeon_power_state *power_state; 1659 /* number of valid power states */ 1660 int num_power_states; 1661 int current_power_state_index; 1662 int current_clock_mode_index; 1663 int requested_power_state_index; 1664 int requested_clock_mode_index; 1665 int default_power_state_index; 1666 u32 current_sclk; 1667 u32 current_mclk; 1668 u16 current_vddc; 1669 u16 current_vddci; 1670 u32 default_sclk; 1671 u32 default_mclk; 1672 u16 default_vddc; 1673 u16 default_vddci; 1674 struct radeon_i2c_chan *i2c_bus; 1675 /* selected pm method */ 1676 enum radeon_pm_method pm_method; 1677 /* dynpm power management */ 1678 struct delayed_work dynpm_idle_work; 1679 enum radeon_dynpm_state dynpm_state; 1680 enum radeon_dynpm_action dynpm_planned_action; 1681 unsigned long dynpm_action_timeout; 1682 bool dynpm_can_upclock; 1683 bool dynpm_can_downclock; 1684 /* profile-based power management */ 1685 enum radeon_pm_profile_type profile; 1686 int profile_index; 1687 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1688 /* internal thermal controller on rv6xx+ */ 1689 enum radeon_int_thermal_type int_thermal_type; 1690 struct device *int_hwmon_dev; 1691 /* fan control parameters */ 1692 bool no_fan; 1693 u8 fan_pulses_per_revolution; 1694 u8 fan_min_rpm; 1695 u8 fan_max_rpm; 1696 /* dpm */ 1697 bool dpm_enabled; 1698 bool sysfs_initialized; 1699 struct radeon_dpm dpm; 1700 }; 1701 1702 #define RADEON_PCIE_SPEED_25 1 1703 #define RADEON_PCIE_SPEED_50 2 1704 #define RADEON_PCIE_SPEED_80 4 1705 1706 int radeon_pm_get_type_index(struct radeon_device *rdev, 1707 enum radeon_pm_state_type ps_type, 1708 int instance); 1709 /* 1710 * UVD 1711 */ 1712 #define RADEON_DEFAULT_UVD_HANDLES 10 1713 #define RADEON_MAX_UVD_HANDLES 30 1714 #define RADEON_UVD_STACK_SIZE (200*1024) 1715 #define RADEON_UVD_HEAP_SIZE (256*1024) 1716 #define RADEON_UVD_SESSION_SIZE (50*1024) 1717 1718 struct radeon_uvd { 1719 bool fw_header_present; 1720 struct radeon_bo *vcpu_bo; 1721 void *cpu_addr; 1722 uint64_t gpu_addr; 1723 unsigned max_handles; 1724 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1725 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1726 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1727 struct delayed_work idle_work; 1728 }; 1729 1730 int radeon_uvd_init(struct radeon_device *rdev); 1731 void radeon_uvd_fini(struct radeon_device *rdev); 1732 int radeon_uvd_suspend(struct radeon_device *rdev); 1733 int radeon_uvd_resume(struct radeon_device *rdev); 1734 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1735 uint32_t handle, struct radeon_fence **fence); 1736 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1737 uint32_t handle, struct radeon_fence **fence); 1738 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1739 uint32_t allowed_domains); 1740 void radeon_uvd_free_handles(struct radeon_device *rdev, 1741 struct drm_file *filp); 1742 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1743 void radeon_uvd_note_usage(struct radeon_device *rdev); 1744 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1745 unsigned vclk, unsigned dclk, 1746 unsigned vco_min, unsigned vco_max, 1747 unsigned fb_factor, unsigned fb_mask, 1748 unsigned pd_min, unsigned pd_max, 1749 unsigned pd_even, 1750 unsigned *optimal_fb_div, 1751 unsigned *optimal_vclk_div, 1752 unsigned *optimal_dclk_div); 1753 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1754 unsigned cg_upll_func_cntl); 1755 1756 /* 1757 * VCE 1758 */ 1759 #define RADEON_MAX_VCE_HANDLES 16 1760 1761 struct radeon_vce { 1762 struct radeon_bo *vcpu_bo; 1763 uint64_t gpu_addr; 1764 unsigned fw_version; 1765 unsigned fb_version; 1766 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1767 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1768 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1769 struct delayed_work idle_work; 1770 uint32_t keyselect; 1771 }; 1772 1773 int radeon_vce_init(struct radeon_device *rdev); 1774 void radeon_vce_fini(struct radeon_device *rdev); 1775 int radeon_vce_suspend(struct radeon_device *rdev); 1776 int radeon_vce_resume(struct radeon_device *rdev); 1777 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1778 uint32_t handle, struct radeon_fence **fence); 1779 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1780 uint32_t handle, struct radeon_fence **fence); 1781 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1782 void radeon_vce_note_usage(struct radeon_device *rdev); 1783 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1784 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1785 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1786 struct radeon_ring *ring, 1787 struct radeon_semaphore *semaphore, 1788 bool emit_wait); 1789 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1790 void radeon_vce_fence_emit(struct radeon_device *rdev, 1791 struct radeon_fence *fence); 1792 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1793 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1794 1795 struct r600_audio_pin { 1796 int channels; 1797 int rate; 1798 int bits_per_sample; 1799 u8 status_bits; 1800 u8 category_code; 1801 u32 offset; 1802 bool connected; 1803 u32 id; 1804 }; 1805 1806 struct r600_audio { 1807 bool enabled; 1808 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1809 int num_pins; 1810 struct radeon_audio_funcs *hdmi_funcs; 1811 struct radeon_audio_funcs *dp_funcs; 1812 struct radeon_audio_basic_funcs *funcs; 1813 }; 1814 1815 /* 1816 * Benchmarking 1817 */ 1818 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1819 1820 1821 /* 1822 * Testing 1823 */ 1824 void radeon_test_moves(struct radeon_device *rdev); 1825 void radeon_test_ring_sync(struct radeon_device *rdev, 1826 struct radeon_ring *cpA, 1827 struct radeon_ring *cpB); 1828 void radeon_test_syncing(struct radeon_device *rdev); 1829 1830 /* 1831 * MMU Notifier 1832 */ 1833 #if defined(CONFIG_MMU_NOTIFIER) 1834 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1835 void radeon_mn_unregister(struct radeon_bo *bo); 1836 #else 1837 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1838 { 1839 return -ENODEV; 1840 } 1841 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1842 #endif 1843 1844 /* 1845 * Debugfs 1846 */ 1847 struct radeon_debugfs { 1848 struct drm_info_list *files; 1849 unsigned num_files; 1850 }; 1851 1852 int radeon_debugfs_add_files(struct radeon_device *rdev, 1853 struct drm_info_list *files, 1854 unsigned nfiles); 1855 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1856 1857 /* 1858 * ASIC ring specific functions. 1859 */ 1860 struct radeon_asic_ring { 1861 /* ring read/write ptr handling */ 1862 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1863 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1864 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1865 1866 /* validating and patching of IBs */ 1867 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1868 int (*cs_parse)(struct radeon_cs_parser *p); 1869 1870 /* command emmit functions */ 1871 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1872 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1873 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1874 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1875 struct radeon_semaphore *semaphore, bool emit_wait); 1876 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1877 unsigned vm_id, uint64_t pd_addr); 1878 1879 /* testing functions */ 1880 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1881 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1882 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1883 1884 /* deprecated */ 1885 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1886 }; 1887 1888 /* 1889 * ASIC specific functions. 1890 */ 1891 struct radeon_asic { 1892 int (*init)(struct radeon_device *rdev); 1893 void (*fini)(struct radeon_device *rdev); 1894 int (*resume)(struct radeon_device *rdev); 1895 int (*suspend)(struct radeon_device *rdev); 1896 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1897 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1898 /* Flush the HDP cache via MMIO */ 1899 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1900 /* check if 3D engine is idle */ 1901 bool (*gui_idle)(struct radeon_device *rdev); 1902 /* wait for mc_idle */ 1903 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1904 /* get the reference clock */ 1905 u32 (*get_xclk)(struct radeon_device *rdev); 1906 /* get the gpu clock counter */ 1907 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1908 /* get register for info ioctl */ 1909 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1910 /* gart */ 1911 struct { 1912 void (*tlb_flush)(struct radeon_device *rdev); 1913 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1914 void (*set_page)(struct radeon_device *rdev, unsigned i, 1915 uint64_t entry); 1916 } gart; 1917 struct { 1918 int (*init)(struct radeon_device *rdev); 1919 void (*fini)(struct radeon_device *rdev); 1920 void (*copy_pages)(struct radeon_device *rdev, 1921 struct radeon_ib *ib, 1922 uint64_t pe, uint64_t src, 1923 unsigned count); 1924 void (*write_pages)(struct radeon_device *rdev, 1925 struct radeon_ib *ib, 1926 uint64_t pe, 1927 uint64_t addr, unsigned count, 1928 uint32_t incr, uint32_t flags); 1929 void (*set_pages)(struct radeon_device *rdev, 1930 struct radeon_ib *ib, 1931 uint64_t pe, 1932 uint64_t addr, unsigned count, 1933 uint32_t incr, uint32_t flags); 1934 void (*pad_ib)(struct radeon_ib *ib); 1935 } vm; 1936 /* ring specific callbacks */ 1937 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1938 /* irqs */ 1939 struct { 1940 int (*set)(struct radeon_device *rdev); 1941 int (*process)(struct radeon_device *rdev); 1942 } irq; 1943 /* displays */ 1944 struct { 1945 /* display watermarks */ 1946 void (*bandwidth_update)(struct radeon_device *rdev); 1947 /* get frame count */ 1948 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1949 /* wait for vblank */ 1950 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1951 /* set backlight level */ 1952 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1953 /* get backlight level */ 1954 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1955 /* audio callbacks */ 1956 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1957 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1958 } display; 1959 /* copy functions for bo handling */ 1960 struct { 1961 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1962 uint64_t src_offset, 1963 uint64_t dst_offset, 1964 unsigned num_gpu_pages, 1965 struct dma_resv *resv); 1966 u32 blit_ring_index; 1967 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1968 uint64_t src_offset, 1969 uint64_t dst_offset, 1970 unsigned num_gpu_pages, 1971 struct dma_resv *resv); 1972 u32 dma_ring_index; 1973 /* method used for bo copy */ 1974 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1975 uint64_t src_offset, 1976 uint64_t dst_offset, 1977 unsigned num_gpu_pages, 1978 struct dma_resv *resv); 1979 /* ring used for bo copies */ 1980 u32 copy_ring_index; 1981 } copy; 1982 /* surfaces */ 1983 struct { 1984 int (*set_reg)(struct radeon_device *rdev, int reg, 1985 uint32_t tiling_flags, uint32_t pitch, 1986 uint32_t offset, uint32_t obj_size); 1987 void (*clear_reg)(struct radeon_device *rdev, int reg); 1988 } surface; 1989 /* hotplug detect */ 1990 struct { 1991 void (*init)(struct radeon_device *rdev); 1992 void (*fini)(struct radeon_device *rdev); 1993 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1994 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1995 } hpd; 1996 /* static power management */ 1997 struct { 1998 void (*misc)(struct radeon_device *rdev); 1999 void (*prepare)(struct radeon_device *rdev); 2000 void (*finish)(struct radeon_device *rdev); 2001 void (*init_profile)(struct radeon_device *rdev); 2002 void (*get_dynpm_state)(struct radeon_device *rdev); 2003 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 2004 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 2005 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 2006 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 2007 int (*get_pcie_lanes)(struct radeon_device *rdev); 2008 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 2009 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 2010 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 2011 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 2012 int (*get_temperature)(struct radeon_device *rdev); 2013 } pm; 2014 /* dynamic power management */ 2015 struct { 2016 int (*init)(struct radeon_device *rdev); 2017 void (*setup_asic)(struct radeon_device *rdev); 2018 int (*enable)(struct radeon_device *rdev); 2019 int (*late_enable)(struct radeon_device *rdev); 2020 void (*disable)(struct radeon_device *rdev); 2021 int (*pre_set_power_state)(struct radeon_device *rdev); 2022 int (*set_power_state)(struct radeon_device *rdev); 2023 void (*post_set_power_state)(struct radeon_device *rdev); 2024 void (*display_configuration_changed)(struct radeon_device *rdev); 2025 void (*fini)(struct radeon_device *rdev); 2026 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2027 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2028 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2029 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2030 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2031 bool (*vblank_too_short)(struct radeon_device *rdev); 2032 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2033 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2034 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2035 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2036 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2037 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2038 u32 (*get_current_sclk)(struct radeon_device *rdev); 2039 u32 (*get_current_mclk)(struct radeon_device *rdev); 2040 } dpm; 2041 /* pageflipping */ 2042 struct { 2043 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2044 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2045 } pflip; 2046 }; 2047 2048 /* 2049 * Asic structures 2050 */ 2051 struct r100_asic { 2052 const unsigned *reg_safe_bm; 2053 unsigned reg_safe_bm_size; 2054 u32 hdp_cntl; 2055 }; 2056 2057 struct r300_asic { 2058 const unsigned *reg_safe_bm; 2059 unsigned reg_safe_bm_size; 2060 u32 resync_scratch; 2061 u32 hdp_cntl; 2062 }; 2063 2064 struct r600_asic { 2065 unsigned max_pipes; 2066 unsigned max_tile_pipes; 2067 unsigned max_simds; 2068 unsigned max_backends; 2069 unsigned max_gprs; 2070 unsigned max_threads; 2071 unsigned max_stack_entries; 2072 unsigned max_hw_contexts; 2073 unsigned max_gs_threads; 2074 unsigned sx_max_export_size; 2075 unsigned sx_max_export_pos_size; 2076 unsigned sx_max_export_smx_size; 2077 unsigned sq_num_cf_insts; 2078 unsigned tiling_nbanks; 2079 unsigned tiling_npipes; 2080 unsigned tiling_group_size; 2081 unsigned tile_config; 2082 unsigned backend_map; 2083 unsigned active_simds; 2084 }; 2085 2086 struct rv770_asic { 2087 unsigned max_pipes; 2088 unsigned max_tile_pipes; 2089 unsigned max_simds; 2090 unsigned max_backends; 2091 unsigned max_gprs; 2092 unsigned max_threads; 2093 unsigned max_stack_entries; 2094 unsigned max_hw_contexts; 2095 unsigned max_gs_threads; 2096 unsigned sx_max_export_size; 2097 unsigned sx_max_export_pos_size; 2098 unsigned sx_max_export_smx_size; 2099 unsigned sq_num_cf_insts; 2100 unsigned sx_num_of_sets; 2101 unsigned sc_prim_fifo_size; 2102 unsigned sc_hiz_tile_fifo_size; 2103 unsigned sc_earlyz_tile_fifo_fize; 2104 unsigned tiling_nbanks; 2105 unsigned tiling_npipes; 2106 unsigned tiling_group_size; 2107 unsigned tile_config; 2108 unsigned backend_map; 2109 unsigned active_simds; 2110 }; 2111 2112 struct evergreen_asic { 2113 unsigned num_ses; 2114 unsigned max_pipes; 2115 unsigned max_tile_pipes; 2116 unsigned max_simds; 2117 unsigned max_backends; 2118 unsigned max_gprs; 2119 unsigned max_threads; 2120 unsigned max_stack_entries; 2121 unsigned max_hw_contexts; 2122 unsigned max_gs_threads; 2123 unsigned sx_max_export_size; 2124 unsigned sx_max_export_pos_size; 2125 unsigned sx_max_export_smx_size; 2126 unsigned sq_num_cf_insts; 2127 unsigned sx_num_of_sets; 2128 unsigned sc_prim_fifo_size; 2129 unsigned sc_hiz_tile_fifo_size; 2130 unsigned sc_earlyz_tile_fifo_size; 2131 unsigned tiling_nbanks; 2132 unsigned tiling_npipes; 2133 unsigned tiling_group_size; 2134 unsigned tile_config; 2135 unsigned backend_map; 2136 unsigned active_simds; 2137 }; 2138 2139 struct cayman_asic { 2140 unsigned max_shader_engines; 2141 unsigned max_pipes_per_simd; 2142 unsigned max_tile_pipes; 2143 unsigned max_simds_per_se; 2144 unsigned max_backends_per_se; 2145 unsigned max_texture_channel_caches; 2146 unsigned max_gprs; 2147 unsigned max_threads; 2148 unsigned max_gs_threads; 2149 unsigned max_stack_entries; 2150 unsigned sx_num_of_sets; 2151 unsigned sx_max_export_size; 2152 unsigned sx_max_export_pos_size; 2153 unsigned sx_max_export_smx_size; 2154 unsigned max_hw_contexts; 2155 unsigned sq_num_cf_insts; 2156 unsigned sc_prim_fifo_size; 2157 unsigned sc_hiz_tile_fifo_size; 2158 unsigned sc_earlyz_tile_fifo_size; 2159 2160 unsigned num_shader_engines; 2161 unsigned num_shader_pipes_per_simd; 2162 unsigned num_tile_pipes; 2163 unsigned num_simds_per_se; 2164 unsigned num_backends_per_se; 2165 unsigned backend_disable_mask_per_asic; 2166 unsigned backend_map; 2167 unsigned num_texture_channel_caches; 2168 unsigned mem_max_burst_length_bytes; 2169 unsigned mem_row_size_in_kb; 2170 unsigned shader_engine_tile_size; 2171 unsigned num_gpus; 2172 unsigned multi_gpu_tile_size; 2173 2174 unsigned tile_config; 2175 unsigned active_simds; 2176 }; 2177 2178 struct si_asic { 2179 unsigned max_shader_engines; 2180 unsigned max_tile_pipes; 2181 unsigned max_cu_per_sh; 2182 unsigned max_sh_per_se; 2183 unsigned max_backends_per_se; 2184 unsigned max_texture_channel_caches; 2185 unsigned max_gprs; 2186 unsigned max_gs_threads; 2187 unsigned max_hw_contexts; 2188 unsigned sc_prim_fifo_size_frontend; 2189 unsigned sc_prim_fifo_size_backend; 2190 unsigned sc_hiz_tile_fifo_size; 2191 unsigned sc_earlyz_tile_fifo_size; 2192 2193 unsigned num_tile_pipes; 2194 unsigned backend_enable_mask; 2195 unsigned backend_disable_mask_per_asic; 2196 unsigned backend_map; 2197 unsigned num_texture_channel_caches; 2198 unsigned mem_max_burst_length_bytes; 2199 unsigned mem_row_size_in_kb; 2200 unsigned shader_engine_tile_size; 2201 unsigned num_gpus; 2202 unsigned multi_gpu_tile_size; 2203 2204 unsigned tile_config; 2205 uint32_t tile_mode_array[32]; 2206 uint32_t active_cus; 2207 }; 2208 2209 struct cik_asic { 2210 unsigned max_shader_engines; 2211 unsigned max_tile_pipes; 2212 unsigned max_cu_per_sh; 2213 unsigned max_sh_per_se; 2214 unsigned max_backends_per_se; 2215 unsigned max_texture_channel_caches; 2216 unsigned max_gprs; 2217 unsigned max_gs_threads; 2218 unsigned max_hw_contexts; 2219 unsigned sc_prim_fifo_size_frontend; 2220 unsigned sc_prim_fifo_size_backend; 2221 unsigned sc_hiz_tile_fifo_size; 2222 unsigned sc_earlyz_tile_fifo_size; 2223 2224 unsigned num_tile_pipes; 2225 unsigned backend_enable_mask; 2226 unsigned backend_disable_mask_per_asic; 2227 unsigned backend_map; 2228 unsigned num_texture_channel_caches; 2229 unsigned mem_max_burst_length_bytes; 2230 unsigned mem_row_size_in_kb; 2231 unsigned shader_engine_tile_size; 2232 unsigned num_gpus; 2233 unsigned multi_gpu_tile_size; 2234 2235 unsigned tile_config; 2236 uint32_t tile_mode_array[32]; 2237 uint32_t macrotile_mode_array[16]; 2238 uint32_t active_cus; 2239 }; 2240 2241 union radeon_asic_config { 2242 struct r300_asic r300; 2243 struct r100_asic r100; 2244 struct r600_asic r600; 2245 struct rv770_asic rv770; 2246 struct evergreen_asic evergreen; 2247 struct cayman_asic cayman; 2248 struct si_asic si; 2249 struct cik_asic cik; 2250 }; 2251 2252 /* 2253 * asic initizalization from radeon_asic.c 2254 */ 2255 void radeon_agp_disable(struct radeon_device *rdev); 2256 int radeon_asic_init(struct radeon_device *rdev); 2257 2258 2259 /* 2260 * IOCTL. 2261 */ 2262 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2263 struct drm_file *filp); 2264 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2265 struct drm_file *filp); 2266 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2267 struct drm_file *filp); 2268 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2269 struct drm_file *file_priv); 2270 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2271 struct drm_file *file_priv); 2272 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2273 struct drm_file *file_priv); 2274 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2275 struct drm_file *file_priv); 2276 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2277 struct drm_file *filp); 2278 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2279 struct drm_file *filp); 2280 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2281 struct drm_file *filp); 2282 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2283 struct drm_file *filp); 2284 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2285 struct drm_file *filp); 2286 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2287 struct drm_file *filp); 2288 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2289 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2290 struct drm_file *filp); 2291 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2292 struct drm_file *filp); 2293 2294 /* VRAM scratch page for HDP bug, default vram page */ 2295 struct r600_vram_scratch { 2296 struct radeon_bo *robj; 2297 volatile uint32_t *ptr; 2298 u64 gpu_addr; 2299 }; 2300 2301 /* 2302 * ACPI 2303 */ 2304 struct radeon_atif_notification_cfg { 2305 bool enabled; 2306 int command_code; 2307 }; 2308 2309 struct radeon_atif_notifications { 2310 bool display_switch; 2311 bool expansion_mode_change; 2312 bool thermal_state; 2313 bool forced_power_state; 2314 bool system_power_state; 2315 bool display_conf_change; 2316 bool px_gfx_switch; 2317 bool brightness_change; 2318 bool dgpu_display_event; 2319 }; 2320 2321 struct radeon_atif_functions { 2322 bool system_params; 2323 bool sbios_requests; 2324 bool select_active_disp; 2325 bool lid_state; 2326 bool get_tv_standard; 2327 bool set_tv_standard; 2328 bool get_panel_expansion_mode; 2329 bool set_panel_expansion_mode; 2330 bool temperature_change; 2331 bool graphics_device_types; 2332 }; 2333 2334 struct radeon_atif { 2335 struct radeon_atif_notifications notifications; 2336 struct radeon_atif_functions functions; 2337 struct radeon_atif_notification_cfg notification_cfg; 2338 struct radeon_encoder *encoder_for_bl; 2339 }; 2340 2341 struct radeon_atcs_functions { 2342 bool get_ext_state; 2343 bool pcie_perf_req; 2344 bool pcie_dev_rdy; 2345 bool pcie_bus_width; 2346 }; 2347 2348 struct radeon_atcs { 2349 struct radeon_atcs_functions functions; 2350 }; 2351 2352 /* 2353 * Core structure, functions and helpers. 2354 */ 2355 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2356 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2357 2358 struct radeon_device { 2359 struct device *dev; 2360 struct drm_device *ddev; 2361 struct pci_dev *pdev; 2362 struct rw_semaphore exclusive_lock; 2363 /* ASIC */ 2364 union radeon_asic_config config; 2365 enum radeon_family family; 2366 unsigned long flags; 2367 int usec_timeout; 2368 enum radeon_pll_errata pll_errata; 2369 int num_gb_pipes; 2370 int num_z_pipes; 2371 int disp_priority; 2372 /* BIOS */ 2373 uint8_t *bios; 2374 bool is_atom_bios; 2375 uint16_t bios_header_start; 2376 struct radeon_bo *stolen_vga_memory; 2377 /* Register mmio */ 2378 #ifndef __NetBSD__ 2379 resource_size_t rmmio_base; 2380 resource_size_t rmmio_size; 2381 #endif 2382 /* protects concurrent MM_INDEX/DATA based register access */ 2383 spinlock_t mmio_idx_lock; 2384 /* protects concurrent SMC based register access */ 2385 spinlock_t smc_idx_lock; 2386 /* protects concurrent PLL register access */ 2387 spinlock_t pll_idx_lock; 2388 /* protects concurrent MC register access */ 2389 spinlock_t mc_idx_lock; 2390 /* protects concurrent PCIE register access */ 2391 spinlock_t pcie_idx_lock; 2392 /* protects concurrent PCIE_PORT register access */ 2393 spinlock_t pciep_idx_lock; 2394 /* protects concurrent PIF register access */ 2395 spinlock_t pif_idx_lock; 2396 /* protects concurrent CG register access */ 2397 spinlock_t cg_idx_lock; 2398 /* protects concurrent UVD register access */ 2399 spinlock_t uvd_idx_lock; 2400 /* protects concurrent RCU register access */ 2401 spinlock_t rcu_idx_lock; 2402 /* protects concurrent DIDT register access */ 2403 spinlock_t didt_idx_lock; 2404 /* protects concurrent ENDPOINT (audio) register access */ 2405 spinlock_t end_idx_lock; 2406 #ifdef __NetBSD__ 2407 bus_space_tag_t rmmio_bst; 2408 bus_space_handle_t rmmio_bsh; 2409 bus_addr_t rmmio_addr; 2410 bus_size_t rmmio_size; 2411 #else 2412 void __iomem *rmmio; 2413 #endif 2414 radeon_rreg_t mc_rreg; 2415 radeon_wreg_t mc_wreg; 2416 radeon_rreg_t pll_rreg; 2417 radeon_wreg_t pll_wreg; 2418 uint32_t pcie_reg_mask; 2419 radeon_rreg_t pciep_rreg; 2420 radeon_wreg_t pciep_wreg; 2421 /* io port */ 2422 #ifdef __NetBSD__ 2423 bus_space_tag_t rio_mem_bst; 2424 bus_space_handle_t rio_mem_bsh; 2425 bus_size_t rio_mem_size; 2426 #else 2427 void __iomem *rio_mem; 2428 resource_size_t rio_mem_size; 2429 #endif 2430 struct radeon_clock clock; 2431 struct radeon_mc mc; 2432 struct radeon_gart gart; 2433 struct radeon_mode_info mode_info; 2434 struct radeon_scratch scratch; 2435 struct radeon_doorbell doorbell; 2436 struct radeon_mman mman; 2437 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2438 #ifdef __NetBSD__ 2439 spinlock_t fence_lock; 2440 drm_waitqueue_t fence_queue; 2441 TAILQ_HEAD(, radeon_fence) fence_check; 2442 #else 2443 wait_queue_head_t fence_queue; 2444 #endif 2445 u64 fence_context; 2446 struct mutex ring_lock; 2447 struct radeon_ring ring[RADEON_NUM_RINGS]; 2448 bool ib_pool_ready; 2449 struct radeon_sa_manager ring_tmp_bo; 2450 struct radeon_irq irq; 2451 struct radeon_asic *asic; 2452 struct radeon_gem gem; 2453 struct radeon_pm pm; 2454 struct radeon_uvd uvd; 2455 struct radeon_vce vce; 2456 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2457 struct radeon_wb wb; 2458 struct radeon_dummy_page dummy_page; 2459 bool shutdown; 2460 bool need_swiotlb; 2461 bool accel_working; 2462 bool fastfb_working; /* IGP feature*/ 2463 bool needs_reset, in_reset; 2464 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2465 const struct firmware *me_fw; /* all family ME firmware */ 2466 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2467 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2468 const struct firmware *mc_fw; /* NI MC firmware */ 2469 const struct firmware *ce_fw; /* SI CE firmware */ 2470 const struct firmware *mec_fw; /* CIK MEC firmware */ 2471 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2472 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2473 const struct firmware *smc_fw; /* SMC firmware */ 2474 const struct firmware *uvd_fw; /* UVD firmware */ 2475 const struct firmware *vce_fw; /* VCE firmware */ 2476 bool new_fw; 2477 struct r600_vram_scratch vram_scratch; 2478 int msi_enabled; /* msi enabled */ 2479 struct r600_ih ih; /* r6/700 interrupt ring */ 2480 struct radeon_rlc rlc; 2481 struct radeon_mec mec; 2482 struct delayed_work hotplug_work; 2483 struct work_struct dp_work; 2484 struct work_struct audio_work; 2485 int num_crtc; /* number of crtcs */ 2486 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2487 bool has_uvd; 2488 bool has_vce; 2489 struct r600_audio audio; /* audio stuff */ 2490 struct notifier_block acpi_nb; 2491 /* only one userspace can use Hyperz features or CMASK at a time */ 2492 struct drm_file *hyperz_filp; 2493 struct drm_file *cmask_filp; 2494 /* i2c buses */ 2495 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2496 /* debugfs */ 2497 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2498 unsigned debugfs_count; 2499 /* virtual memory */ 2500 struct radeon_vm_manager vm_manager; 2501 struct mutex gpu_clock_mutex; 2502 /* memory stats */ 2503 atomic64_t vram_usage; 2504 atomic64_t gtt_usage; 2505 atomic64_t num_bytes_moved; 2506 atomic_t gpu_reset_counter; 2507 /* ACPI interface */ 2508 struct radeon_atif atif; 2509 struct radeon_atcs atcs; 2510 /* srbm instance registers */ 2511 struct mutex srbm_mutex; 2512 /* clock, powergating flags */ 2513 u32 cg_flags; 2514 u32 pg_flags; 2515 2516 struct dev_pm_domain vga_pm_domain; 2517 bool have_disp_power_ref; 2518 u32 px_quirk_flags; 2519 2520 /* tracking pinned memory */ 2521 u64 vram_pin_size; 2522 u64 gart_pin_size; 2523 }; 2524 2525 bool radeon_is_px(struct drm_device *dev); 2526 int radeon_device_init(struct radeon_device *rdev, 2527 struct drm_device *ddev, 2528 struct pci_dev *pdev, 2529 uint32_t flags); 2530 void radeon_device_fini(struct radeon_device *rdev); 2531 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2532 2533 #define RADEON_MIN_MMIO_SIZE 0x10000 2534 2535 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2536 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2537 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2538 bool always_indirect) 2539 { 2540 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2541 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2542 #ifdef __NetBSD__ 2543 return bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg); 2544 #else 2545 return readl(((void __iomem *)rdev->rmmio) + reg); 2546 #endif 2547 else 2548 return r100_mm_rreg_slow(rdev, reg); 2549 } 2550 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2551 bool always_indirect) 2552 { 2553 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2554 #ifdef __NetBSD__ 2555 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg, v); 2556 #else 2557 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2558 #endif 2559 else 2560 r100_mm_wreg_slow(rdev, reg, v); 2561 } 2562 2563 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2564 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2565 2566 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2567 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2568 2569 /* 2570 * Cast helper 2571 */ 2572 extern const struct dma_fence_ops radeon_fence_ops; 2573 2574 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2575 { 2576 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2577 2578 if (__f->base.ops == &radeon_fence_ops) 2579 return __f; 2580 2581 return NULL; 2582 } 2583 2584 /* 2585 * Registers read & write functions. 2586 */ 2587 #ifdef __NetBSD__ 2588 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2589 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2590 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2591 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2592 #else 2593 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2594 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2595 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2596 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2597 #endif 2598 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2599 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2600 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2601 r100_mm_rreg(rdev, (reg), false)) 2602 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2603 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2604 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2605 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2606 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2607 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2608 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2609 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2610 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2611 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2612 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2613 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2614 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2615 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2616 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2617 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2618 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2619 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2620 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2621 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2622 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2623 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2624 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2625 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2626 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2627 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2628 #define WREG32_P(reg, val, mask) \ 2629 do { \ 2630 uint32_t tmp_ = RREG32(reg); \ 2631 tmp_ &= (mask); \ 2632 tmp_ |= ((val) & ~(mask)); \ 2633 WREG32(reg, tmp_); \ 2634 } while (0) 2635 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2636 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2637 #define WREG32_PLL_P(reg, val, mask) \ 2638 do { \ 2639 uint32_t tmp_ = RREG32_PLL(reg); \ 2640 tmp_ &= (mask); \ 2641 tmp_ |= ((val) & ~(mask)); \ 2642 WREG32_PLL(reg, tmp_); \ 2643 } while (0) 2644 #define WREG32_SMC_P(reg, val, mask) \ 2645 do { \ 2646 uint32_t tmp_ = RREG32_SMC(reg); \ 2647 tmp_ &= (mask); \ 2648 tmp_ |= ((val) & ~(mask)); \ 2649 WREG32_SMC(reg, tmp_); \ 2650 } while (0) 2651 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2652 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2653 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2654 2655 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2656 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2657 2658 /* 2659 * Indirect registers accessors. 2660 * They used to be inlined, but this increases code size by ~65 kbytes. 2661 * Since each performs a pair of MMIO ops 2662 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2663 * the cost of call+ret is almost negligible. MMIO and locking 2664 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2665 */ 2666 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2667 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2668 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2669 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2670 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2671 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2672 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2673 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2674 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2675 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2676 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2677 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2678 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2679 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2680 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2681 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2682 2683 void r100_pll_errata_after_index(struct radeon_device *rdev); 2684 2685 2686 /* 2687 * ASICs helpers. 2688 */ 2689 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2690 (rdev->pdev->device == 0x5969)) 2691 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2692 (rdev->family == CHIP_RV200) || \ 2693 (rdev->family == CHIP_RS100) || \ 2694 (rdev->family == CHIP_RS200) || \ 2695 (rdev->family == CHIP_RV250) || \ 2696 (rdev->family == CHIP_RV280) || \ 2697 (rdev->family == CHIP_RS300)) 2698 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2699 (rdev->family == CHIP_RV350) || \ 2700 (rdev->family == CHIP_R350) || \ 2701 (rdev->family == CHIP_RV380) || \ 2702 (rdev->family == CHIP_R420) || \ 2703 (rdev->family == CHIP_R423) || \ 2704 (rdev->family == CHIP_RV410) || \ 2705 (rdev->family == CHIP_RS400) || \ 2706 (rdev->family == CHIP_RS480)) 2707 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2708 (rdev->ddev->pdev->device == 0x9443) || \ 2709 (rdev->ddev->pdev->device == 0x944B) || \ 2710 (rdev->ddev->pdev->device == 0x9506) || \ 2711 (rdev->ddev->pdev->device == 0x9509) || \ 2712 (rdev->ddev->pdev->device == 0x950F) || \ 2713 (rdev->ddev->pdev->device == 0x689C) || \ 2714 (rdev->ddev->pdev->device == 0x689D)) 2715 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2716 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2717 (rdev->family == CHIP_RS690) || \ 2718 (rdev->family == CHIP_RS740) || \ 2719 (rdev->family >= CHIP_R600)) 2720 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2721 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2722 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2723 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2724 (rdev->flags & RADEON_IS_IGP)) 2725 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2726 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2727 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2728 (rdev->flags & RADEON_IS_IGP)) 2729 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2730 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2731 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2732 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2733 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2734 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2735 (rdev->family == CHIP_MULLINS)) 2736 2737 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2738 (rdev->ddev->pdev->device == 0x6850) || \ 2739 (rdev->ddev->pdev->device == 0x6858) || \ 2740 (rdev->ddev->pdev->device == 0x6859) || \ 2741 (rdev->ddev->pdev->device == 0x6840) || \ 2742 (rdev->ddev->pdev->device == 0x6841) || \ 2743 (rdev->ddev->pdev->device == 0x6842) || \ 2744 (rdev->ddev->pdev->device == 0x6843)) 2745 2746 /* 2747 * BIOS helpers. 2748 */ 2749 #define RBIOS8(i) (rdev->bios[i]) 2750 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2751 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2752 2753 int radeon_combios_init(struct radeon_device *rdev); 2754 void radeon_combios_fini(struct radeon_device *rdev); 2755 int radeon_atombios_init(struct radeon_device *rdev); 2756 void radeon_atombios_fini(struct radeon_device *rdev); 2757 2758 2759 /* 2760 * RING helpers. 2761 */ 2762 2763 /** 2764 * radeon_ring_write - write a value to the ring 2765 * 2766 * @ring: radeon_ring structure holding ring information 2767 * @v: dword (dw) value to write 2768 * 2769 * Write a value to the requested ring buffer (all asics). 2770 */ 2771 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2772 { 2773 if (ring->count_dw <= 0) 2774 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2775 2776 ring->ring[ring->wptr++] = v; 2777 ring->wptr &= ring->ptr_mask; 2778 ring->count_dw--; 2779 ring->ring_free_dw--; 2780 } 2781 2782 /* 2783 * ASICs macro. 2784 */ 2785 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2786 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2787 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2788 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2789 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2790 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2791 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2792 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2793 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2794 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2795 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2796 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2797 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2798 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2799 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2800 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2801 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2802 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2803 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2804 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2805 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2806 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2807 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2808 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2809 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2810 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2811 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2812 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2813 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2814 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2815 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2816 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2817 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2818 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2819 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2820 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2821 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2822 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2823 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2824 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2825 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2826 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2827 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2828 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2829 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2830 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2831 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2832 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2833 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2834 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2835 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2836 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2837 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2838 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2839 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2840 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2841 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2842 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2843 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2844 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2845 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2846 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2847 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2848 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2849 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2850 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2851 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2852 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2853 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2854 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2855 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2856 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2857 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2858 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2859 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2860 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2861 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2862 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2863 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2864 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2865 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2866 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2867 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2868 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2869 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2870 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2871 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2872 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2873 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2874 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2875 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2876 2877 /* Common functions */ 2878 /* AGP */ 2879 extern int radeon_gpu_reset(struct radeon_device *rdev); 2880 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2881 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2882 extern void radeon_agp_disable(struct radeon_device *rdev); 2883 extern int radeon_modeset_init(struct radeon_device *rdev); 2884 extern void radeon_modeset_fini(struct radeon_device *rdev); 2885 extern bool radeon_card_posted(struct radeon_device *rdev); 2886 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2887 extern void radeon_update_display_priority(struct radeon_device *rdev); 2888 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2889 extern void radeon_scratch_init(struct radeon_device *rdev); 2890 extern void radeon_wb_fini(struct radeon_device *rdev); 2891 extern int radeon_wb_init(struct radeon_device *rdev); 2892 extern void radeon_wb_disable(struct radeon_device *rdev); 2893 extern void radeon_surface_init(struct radeon_device *rdev); 2894 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2895 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2896 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2897 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2898 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2899 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2900 uint32_t flags); 2901 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2902 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2903 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2904 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2905 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2906 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2907 bool fbcon, bool freeze); 2908 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2909 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2910 const u32 *registers, 2911 const u32 array_size); 2912 2913 /* 2914 * vm 2915 */ 2916 int radeon_vm_manager_init(struct radeon_device *rdev); 2917 void radeon_vm_manager_fini(struct radeon_device *rdev); 2918 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2919 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2920 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2921 struct radeon_vm *vm, 2922 struct list_head *head); 2923 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2924 struct radeon_vm *vm, int ring); 2925 void radeon_vm_flush(struct radeon_device *rdev, 2926 struct radeon_vm *vm, 2927 int ring, struct radeon_fence *fence); 2928 void radeon_vm_fence(struct radeon_device *rdev, 2929 struct radeon_vm *vm, 2930 struct radeon_fence *fence); 2931 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2932 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2933 struct radeon_vm *vm); 2934 int radeon_vm_clear_freed(struct radeon_device *rdev, 2935 struct radeon_vm *vm); 2936 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2937 struct radeon_vm *vm); 2938 int radeon_vm_bo_update(struct radeon_device *rdev, 2939 struct radeon_bo_va *bo_va, 2940 struct ttm_mem_reg *mem); 2941 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2942 struct radeon_bo *bo); 2943 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2944 struct radeon_bo *bo); 2945 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2946 struct radeon_vm *vm, 2947 struct radeon_bo *bo); 2948 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2949 struct radeon_bo_va *bo_va, 2950 uint64_t offset, 2951 uint32_t flags); 2952 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2953 struct radeon_bo_va *bo_va); 2954 2955 /* audio */ 2956 void r600_audio_update_hdmi(struct work_struct *work); 2957 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2958 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2959 void r600_audio_enable(struct radeon_device *rdev, 2960 struct r600_audio_pin *pin, 2961 u8 enable_mask); 2962 void dce6_audio_enable(struct radeon_device *rdev, 2963 struct r600_audio_pin *pin, 2964 u8 enable_mask); 2965 2966 /* 2967 * R600 vram scratch functions 2968 */ 2969 int r600_vram_scratch_init(struct radeon_device *rdev); 2970 void r600_vram_scratch_fini(struct radeon_device *rdev); 2971 2972 /* 2973 * r600 cs checking helper 2974 */ 2975 unsigned r600_mip_minify(unsigned size, unsigned level); 2976 bool r600_fmt_is_valid_color(u32 format); 2977 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2978 int r600_fmt_get_blocksize(u32 format); 2979 int r600_fmt_get_nblocksx(u32 format, u32 w); 2980 int r600_fmt_get_nblocksy(u32 format, u32 h); 2981 2982 /* 2983 * r600 functions used by radeon_encoder.c 2984 */ 2985 struct radeon_hdmi_acr { 2986 u32 clock; 2987 2988 int n_32khz; 2989 int cts_32khz; 2990 2991 int n_44_1khz; 2992 int cts_44_1khz; 2993 2994 int n_48khz; 2995 int cts_48khz; 2996 2997 }; 2998 2999 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3000 3001 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3002 u32 tiling_pipe_num, 3003 u32 max_rb_num, 3004 u32 total_max_rb_num, 3005 u32 enabled_rb_mask); 3006 3007 /* 3008 * evergreen functions used by radeon_encoder.c 3009 */ 3010 3011 extern int ni_init_microcode(struct radeon_device *rdev); 3012 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3013 3014 /* radeon_acpi.c */ 3015 #if defined(CONFIG_ACPI) 3016 extern int radeon_acpi_init(struct radeon_device *rdev); 3017 extern void radeon_acpi_fini(struct radeon_device *rdev); 3018 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3019 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3020 u8 perf_req, bool advertise); 3021 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3022 #else 3023 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3024 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3025 #endif 3026 3027 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3028 struct radeon_cs_packet *pkt, 3029 unsigned idx); 3030 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3031 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3032 struct radeon_cs_packet *pkt); 3033 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3034 struct radeon_bo_list **cs_reloc, 3035 int nomm); 3036 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3037 uint32_t *vline_start_end, 3038 uint32_t *vline_status); 3039 3040 /* interrupt control register helpers */ 3041 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 3042 u32 reg, u32 mask, 3043 bool enable, const char *name, 3044 unsigned n); 3045 3046 #include "radeon_object.h" 3047 3048 #endif 3049
Indexes created Wed Oct 01 19:09:53 GMT 2025