radeon.h revision 1.2
1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <asm/byteorder.h> 64 #include <linux/atomic.h> 65 #include <linux/wait.h> 66 #include <linux/list.h> 67 #include <linux/kref.h> 68 #include <linux/device.h> 69 #include <linux/log2.h> 70 #include <linux/notifier.h> 71 #include <linux/printk.h> 72 #include <linux/rwsem.h> 73 74 #include <ttm/ttm_bo_api.h> 75 #include <ttm/ttm_bo_driver.h> 76 #include <ttm/ttm_placement.h> 77 #include <ttm/ttm_module.h> 78 #include <ttm/ttm_execbuf_util.h> 79 80 #include "radeon_family.h" 81 #include "radeon_mode.h" 82 #include "radeon_reg.h" 83 84 /* 85 * Modules parameters. 86 */ 87 extern int radeon_no_wb; 88 extern int radeon_modeset; 89 extern int radeon_dynclks; 90 extern int radeon_r4xx_atom; 91 extern int radeon_agpmode; 92 extern int radeon_vram_limit; 93 extern int radeon_gart_size; 94 extern int radeon_benchmarking; 95 extern int radeon_testing; 96 extern int radeon_connector_table; 97 extern int radeon_tv; 98 extern int radeon_audio; 99 extern int radeon_disp_priority; 100 extern int radeon_hw_i2c; 101 extern int radeon_pcie_gen2; 102 extern int radeon_msi; 103 extern int radeon_lockup_timeout; 104 extern int radeon_fastfb; 105 extern int radeon_dpm; 106 extern int radeon_aspm; 107 extern int radeon_runtime_pm; 108 extern int radeon_hard_reset; 109 110 /* 111 * Copy from radeon_drv.h so we don't have to include both and have conflicting 112 * symbol; 113 */ 114 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 115 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 116 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 117 #define RADEON_IB_POOL_SIZE 16 118 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 119 #define RADEONFB_CONN_LIMIT 4 120 #define RADEON_BIOS_NUM_SCRATCH 8 121 122 /* fence seq are set to this number when signaled */ 123 #define RADEON_FENCE_SIGNALED_SEQ 0LL 124 125 /* internal ring indices */ 126 /* r1xx+ has gfx CP ring */ 127 #define RADEON_RING_TYPE_GFX_INDEX 0 128 129 /* cayman has 2 compute CP rings */ 130 #define CAYMAN_RING_TYPE_CP1_INDEX 1 131 #define CAYMAN_RING_TYPE_CP2_INDEX 2 132 133 /* R600+ has an async dma ring */ 134 #define R600_RING_TYPE_DMA_INDEX 3 135 /* cayman add a second async dma ring */ 136 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 137 138 /* R600+ */ 139 #define R600_RING_TYPE_UVD_INDEX 5 140 141 /* TN+ */ 142 #define TN_RING_TYPE_VCE1_INDEX 6 143 #define TN_RING_TYPE_VCE2_INDEX 7 144 145 /* max number of rings */ 146 #define RADEON_NUM_RINGS 8 147 148 /* number of hw syncs before falling back on blocking */ 149 #define RADEON_NUM_SYNCS 4 150 151 /* number of hw syncs before falling back on blocking */ 152 #define RADEON_NUM_SYNCS 4 153 154 /* hardcode those limit for now */ 155 #define RADEON_VA_IB_OFFSET (1 << 20) 156 #define RADEON_VA_RESERVED_SIZE (8 << 20) 157 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 158 159 /* hard reset data */ 160 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 161 162 /* reset flags */ 163 #define RADEON_RESET_GFX (1 << 0) 164 #define RADEON_RESET_COMPUTE (1 << 1) 165 #define RADEON_RESET_DMA (1 << 2) 166 #define RADEON_RESET_CP (1 << 3) 167 #define RADEON_RESET_GRBM (1 << 4) 168 #define RADEON_RESET_DMA1 (1 << 5) 169 #define RADEON_RESET_RLC (1 << 6) 170 #define RADEON_RESET_SEM (1 << 7) 171 #define RADEON_RESET_IH (1 << 8) 172 #define RADEON_RESET_VMC (1 << 9) 173 #define RADEON_RESET_MC (1 << 10) 174 #define RADEON_RESET_DISPLAY (1 << 11) 175 176 /* CG block flags */ 177 #define RADEON_CG_BLOCK_GFX (1 << 0) 178 #define RADEON_CG_BLOCK_MC (1 << 1) 179 #define RADEON_CG_BLOCK_SDMA (1 << 2) 180 #define RADEON_CG_BLOCK_UVD (1 << 3) 181 #define RADEON_CG_BLOCK_VCE (1 << 4) 182 #define RADEON_CG_BLOCK_HDP (1 << 5) 183 #define RADEON_CG_BLOCK_BIF (1 << 6) 184 185 /* CG flags */ 186 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 187 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 188 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 189 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 190 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 191 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 192 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 193 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 194 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 195 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 196 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 197 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 198 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 199 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 200 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 201 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 202 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 203 204 /* PG flags */ 205 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 206 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 207 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 208 #define RADEON_PG_SUPPORT_UVD (1 << 3) 209 #define RADEON_PG_SUPPORT_VCE (1 << 4) 210 #define RADEON_PG_SUPPORT_CP (1 << 5) 211 #define RADEON_PG_SUPPORT_GDS (1 << 6) 212 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 213 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 214 #define RADEON_PG_SUPPORT_ACP (1 << 9) 215 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 216 217 /* max cursor sizes (in pixels) */ 218 #define CURSOR_WIDTH 64 219 #define CURSOR_HEIGHT 64 220 221 #define CIK_CURSOR_WIDTH 128 222 #define CIK_CURSOR_HEIGHT 128 223 224 /* 225 * Errata workarounds. 226 */ 227 enum radeon_pll_errata { 228 CHIP_ERRATA_R300_CG = 0x00000001, 229 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 230 CHIP_ERRATA_PLL_DELAY = 0x00000004 231 }; 232 233 234 struct radeon_device; 235 236 237 /* 238 * BIOS. 239 */ 240 bool radeon_get_bios(struct radeon_device *rdev); 241 242 /* 243 * Dummy page 244 */ 245 struct radeon_dummy_page { 246 #ifdef __NetBSD__ 247 bus_dma_segment_t rdp_seg; 248 bus_dmamap_t rdp_map; 249 #else 250 struct page *page; 251 #endif 252 dma_addr_t addr; 253 }; 254 int radeon_dummy_page_init(struct radeon_device *rdev); 255 void radeon_dummy_page_fini(struct radeon_device *rdev); 256 257 258 /* 259 * Clocks 260 */ 261 struct radeon_clock { 262 struct radeon_pll p1pll; 263 struct radeon_pll p2pll; 264 struct radeon_pll dcpll; 265 struct radeon_pll spll; 266 struct radeon_pll mpll; 267 /* 10 Khz units */ 268 uint32_t default_mclk; 269 uint32_t default_sclk; 270 uint32_t default_dispclk; 271 uint32_t current_dispclk; 272 uint32_t dp_extclk; 273 uint32_t max_pixel_clock; 274 }; 275 276 /* 277 * Power management 278 */ 279 int radeon_pm_init(struct radeon_device *rdev); 280 int radeon_pm_late_init(struct radeon_device *rdev); 281 void radeon_pm_fini(struct radeon_device *rdev); 282 void radeon_pm_compute_clocks(struct radeon_device *rdev); 283 void radeon_pm_suspend(struct radeon_device *rdev); 284 void radeon_pm_resume(struct radeon_device *rdev); 285 void radeon_combios_get_power_modes(struct radeon_device *rdev); 286 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 287 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 288 u8 clock_type, 289 u32 clock, 290 bool strobe_mode, 291 struct atom_clock_dividers *dividers); 292 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 293 u32 clock, 294 bool strobe_mode, 295 struct atom_mpll_param *mpll_param); 296 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 297 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 298 u16 voltage_level, u8 voltage_type, 299 u32 *gpio_value, u32 *gpio_mask); 300 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 301 u32 eng_clock, u32 mem_clock); 302 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 303 u8 voltage_type, u16 *voltage_step); 304 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 305 u16 voltage_id, u16 *voltage); 306 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 307 u16 *voltage, 308 u16 leakage_idx); 309 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 310 u16 *leakage_id); 311 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 312 u16 *vddc, u16 *vddci, 313 u16 virtual_voltage_id, 314 u16 vbios_voltage_id); 315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 316 u8 voltage_type, 317 u16 nominal_voltage, 318 u16 *true_voltage); 319 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 320 u8 voltage_type, u16 *min_voltage); 321 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 322 u8 voltage_type, u16 *max_voltage); 323 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 324 u8 voltage_type, u8 voltage_mode, 325 struct atom_voltage_table *voltage_table); 326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 327 u8 voltage_type, u8 voltage_mode); 328 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 329 u32 mem_clock); 330 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 331 u32 mem_clock); 332 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 333 u8 module_index, 334 struct atom_mc_reg_table *reg_table); 335 int radeon_atom_get_memory_info(struct radeon_device *rdev, 336 u8 module_index, struct atom_memory_info *mem_info); 337 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 338 bool gddr5, u8 module_index, 339 struct atom_memory_clock_range_table *mclk_range_table); 340 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 341 u16 voltage_id, u16 *voltage); 342 void rs690_pm_info(struct radeon_device *rdev); 343 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 344 unsigned *bankh, unsigned *mtaspect, 345 unsigned *tile_split); 346 347 /* 348 * Fences. 349 */ 350 struct radeon_fence_driver { 351 uint32_t scratch_reg; 352 uint64_t gpu_addr; 353 volatile uint32_t *cpu_addr; 354 /* sync_seq is protected by ring emission lock */ 355 uint64_t sync_seq[RADEON_NUM_RINGS]; 356 atomic64_t last_seq; 357 bool initialized; 358 }; 359 360 struct radeon_fence { 361 struct radeon_device *rdev; 362 struct kref kref; 363 /* protected by radeon_fence.lock */ 364 uint64_t seq; 365 /* RB, DMA, etc. */ 366 unsigned ring; 367 }; 368 369 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 370 int radeon_fence_driver_init(struct radeon_device *rdev); 371 void radeon_fence_driver_fini(struct radeon_device *rdev); 372 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 373 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 374 void radeon_fence_process(struct radeon_device *rdev, int ring); 375 bool radeon_fence_signaled(struct radeon_fence *fence); 376 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 377 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 378 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 379 int radeon_fence_wait_any(struct radeon_device *rdev, 380 struct radeon_fence **fences, 381 bool intr); 382 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 383 void radeon_fence_unref(struct radeon_fence **fence); 384 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 385 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 386 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 387 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 388 struct radeon_fence *b) 389 { 390 if (!a) { 391 return b; 392 } 393 394 if (!b) { 395 return a; 396 } 397 398 BUG_ON(a->ring != b->ring); 399 400 if (a->seq > b->seq) { 401 return a; 402 } else { 403 return b; 404 } 405 } 406 407 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 408 struct radeon_fence *b) 409 { 410 if (!a) { 411 return false; 412 } 413 414 if (!b) { 415 return true; 416 } 417 418 BUG_ON(a->ring != b->ring); 419 420 return a->seq < b->seq; 421 } 422 423 /* 424 * Tiling registers 425 */ 426 struct radeon_surface_reg { 427 struct radeon_bo *bo; 428 }; 429 430 #define RADEON_GEM_MAX_SURFACES 8 431 432 /* 433 * TTM. 434 */ 435 struct radeon_mman { 436 struct ttm_bo_global_ref bo_global_ref; 437 struct drm_global_reference mem_global_ref; 438 struct ttm_bo_device bdev; 439 bool mem_global_referenced; 440 bool initialized; 441 442 #if defined(CONFIG_DEBUG_FS) 443 struct dentry *vram; 444 struct dentry *gtt; 445 #endif 446 }; 447 448 /* bo virtual address in a specific vm */ 449 struct radeon_bo_va { 450 /* protected by bo being reserved */ 451 struct list_head bo_list; 452 uint64_t soffset; 453 uint64_t eoffset; 454 uint32_t flags; 455 bool valid; 456 unsigned ref_count; 457 458 /* protected by vm mutex */ 459 struct list_head vm_list; 460 461 /* constant after initialization */ 462 struct radeon_vm *vm; 463 struct radeon_bo *bo; 464 }; 465 466 struct radeon_bo { 467 /* Protected by gem.mutex */ 468 struct list_head list; 469 /* Protected by tbo.reserved */ 470 u32 initial_domain; 471 u32 placements[3]; 472 struct ttm_placement placement; 473 struct ttm_buffer_object tbo; 474 struct ttm_bo_kmap_obj kmap; 475 unsigned pin_count; 476 void *kptr; 477 u32 tiling_flags; 478 u32 pitch; 479 int surface_reg; 480 /* list of all virtual address to which this bo 481 * is associated to 482 */ 483 struct list_head va; 484 /* Constant after initialization */ 485 struct radeon_device *rdev; 486 struct drm_gem_object gem_base; 487 488 struct ttm_bo_kmap_obj dma_buf_vmap; 489 #ifndef __NetBSD__ /* XXX pid??? */ 490 pid_t pid; 491 #endif 492 }; 493 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 494 495 int radeon_gem_debugfs_init(struct radeon_device *rdev); 496 497 /* sub-allocation manager, it has to be protected by another lock. 498 * By conception this is an helper for other part of the driver 499 * like the indirect buffer or semaphore, which both have their 500 * locking. 501 * 502 * Principe is simple, we keep a list of sub allocation in offset 503 * order (first entry has offset == 0, last entry has the highest 504 * offset). 505 * 506 * When allocating new object we first check if there is room at 507 * the end total_size - (last_object_offset + last_object_size) >= 508 * alloc_size. If so we allocate new object there. 509 * 510 * When there is not enough room at the end, we start waiting for 511 * each sub object until we reach object_offset+object_size >= 512 * alloc_size, this object then become the sub object we return. 513 * 514 * Alignment can't be bigger than page size. 515 * 516 * Hole are not considered for allocation to keep things simple. 517 * Assumption is that there won't be hole (all object on same 518 * alignment). 519 */ 520 struct radeon_sa_manager { 521 #ifdef __NetBSD__ 522 spinlock_t wq_lock; 523 drm_waitqueue_t wq; 524 #else 525 wait_queue_head_t wq; 526 #endif 527 struct radeon_bo *bo; 528 struct list_head *hole; 529 struct list_head flist[RADEON_NUM_RINGS]; 530 struct list_head olist; 531 unsigned size; 532 uint64_t gpu_addr; 533 void *cpu_ptr; 534 uint32_t domain; 535 uint32_t align; 536 }; 537 538 struct radeon_sa_bo; 539 540 /* sub-allocation buffer */ 541 struct radeon_sa_bo { 542 struct list_head olist; 543 struct list_head flist; 544 struct radeon_sa_manager *manager; 545 unsigned soffset; 546 unsigned eoffset; 547 struct radeon_fence *fence; 548 }; 549 550 /* 551 * GEM objects. 552 */ 553 struct radeon_gem { 554 struct mutex mutex; 555 struct list_head objects; 556 }; 557 558 int radeon_gem_init(struct radeon_device *rdev); 559 void radeon_gem_fini(struct radeon_device *rdev); 560 int radeon_gem_object_create(struct radeon_device *rdev, int size, 561 int alignment, int initial_domain, 562 bool discardable, bool kernel, 563 struct drm_gem_object **obj); 564 565 int radeon_mode_dumb_create(struct drm_file *file_priv, 566 struct drm_device *dev, 567 struct drm_mode_create_dumb *args); 568 int radeon_mode_dumb_mmap(struct drm_file *filp, 569 struct drm_device *dev, 570 uint32_t handle, uint64_t *offset_p); 571 572 /* 573 * Semaphores. 574 */ 575 struct radeon_semaphore { 576 struct radeon_sa_bo *sa_bo; 577 signed waiters; 578 uint64_t gpu_addr; 579 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 580 }; 581 582 int radeon_semaphore_create(struct radeon_device *rdev, 583 struct radeon_semaphore **semaphore); 584 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 585 struct radeon_semaphore *semaphore); 586 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 587 struct radeon_semaphore *semaphore); 588 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 589 struct radeon_fence *fence); 590 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 591 struct radeon_semaphore *semaphore, 592 int waiting_ring); 593 void radeon_semaphore_free(struct radeon_device *rdev, 594 struct radeon_semaphore **semaphore, 595 struct radeon_fence *fence); 596 597 /* 598 * GART structures, functions & helpers 599 */ 600 struct radeon_mc; 601 602 #define RADEON_GPU_PAGE_SIZE 4096 603 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 604 #define RADEON_GPU_PAGE_SHIFT 12 605 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 606 607 struct radeon_gart { 608 #ifdef __NetBSD__ 609 bus_dma_segment_t rg_table_seg; 610 bus_dmamap_t rg_table_map; 611 #endif 612 dma_addr_t table_addr; 613 struct radeon_bo *robj; 614 void *ptr; 615 unsigned num_gpu_pages; 616 unsigned num_cpu_pages; 617 unsigned table_size; 618 struct page **pages; 619 dma_addr_t *pages_addr; 620 bool ready; 621 }; 622 623 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 624 void radeon_gart_table_ram_free(struct radeon_device *rdev); 625 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 626 void radeon_gart_table_vram_free(struct radeon_device *rdev); 627 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 628 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 629 int radeon_gart_init(struct radeon_device *rdev); 630 void radeon_gart_fini(struct radeon_device *rdev); 631 #ifdef __NetBSD__ 632 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 633 unsigned npages); 634 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 635 unsigned npages, struct page **pages, 636 bus_dmamap_t dmamap); 637 #else 638 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 639 int pages); 640 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 641 int pages, struct page **pagelist, 642 dma_addr_t *dma_addr); 643 #endif 644 void radeon_gart_restore(struct radeon_device *rdev); 645 646 647 /* 648 * GPU MC structures, functions & helpers 649 */ 650 struct radeon_mc { 651 resource_size_t aper_size; 652 resource_size_t aper_base; 653 resource_size_t agp_base; 654 /* for some chips with <= 32MB we need to lie 655 * about vram size near mc fb location */ 656 u64 mc_vram_size; 657 u64 visible_vram_size; 658 u64 gtt_size; 659 u64 gtt_start; 660 u64 gtt_end; 661 u64 vram_start; 662 u64 vram_end; 663 unsigned vram_width; 664 u64 real_vram_size; 665 int vram_mtrr; 666 bool vram_is_ddr; 667 bool igp_sideport_enabled; 668 u64 gtt_base_align; 669 u64 mc_mask; 670 }; 671 672 bool radeon_combios_sideport_present(struct radeon_device *rdev); 673 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 674 675 /* 676 * GPU scratch registers structures, functions & helpers 677 */ 678 struct radeon_scratch { 679 unsigned num_reg; 680 uint32_t reg_base; 681 bool free[32]; 682 uint32_t reg[32]; 683 }; 684 685 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 686 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 687 688 /* 689 * GPU doorbell structures, functions & helpers 690 */ 691 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 692 693 struct radeon_doorbell { 694 /* doorbell mmio */ 695 resource_size_t base; 696 resource_size_t size; 697 #ifdef __NetBSD__ 698 bus_space_tag_t bst; 699 bus_space_handle_t bsh; 700 #else 701 u32 __iomem *ptr; 702 #endif 703 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 704 #ifdef __NetBSD__ 705 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, CHAR_BIT*sizeof(unsigned long))]; 706 #else 707 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 708 #endif 709 }; 710 711 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 712 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 713 714 /* 715 * IRQS. 716 */ 717 718 struct radeon_unpin_work { 719 struct work_struct work; 720 struct radeon_device *rdev; 721 int crtc_id; 722 struct radeon_fence *fence; 723 struct drm_pending_vblank_event *event; 724 struct radeon_bo *old_rbo; 725 u64 new_crtc_base; 726 }; 727 728 struct r500_irq_stat_regs { 729 u32 disp_int; 730 u32 hdmi0_status; 731 }; 732 733 struct r600_irq_stat_regs { 734 u32 disp_int; 735 u32 disp_int_cont; 736 u32 disp_int_cont2; 737 u32 d1grph_int; 738 u32 d2grph_int; 739 u32 hdmi0_status; 740 u32 hdmi1_status; 741 }; 742 743 struct evergreen_irq_stat_regs { 744 u32 disp_int; 745 u32 disp_int_cont; 746 u32 disp_int_cont2; 747 u32 disp_int_cont3; 748 u32 disp_int_cont4; 749 u32 disp_int_cont5; 750 u32 d1grph_int; 751 u32 d2grph_int; 752 u32 d3grph_int; 753 u32 d4grph_int; 754 u32 d5grph_int; 755 u32 d6grph_int; 756 u32 afmt_status1; 757 u32 afmt_status2; 758 u32 afmt_status3; 759 u32 afmt_status4; 760 u32 afmt_status5; 761 u32 afmt_status6; 762 }; 763 764 struct cik_irq_stat_regs { 765 u32 disp_int; 766 u32 disp_int_cont; 767 u32 disp_int_cont2; 768 u32 disp_int_cont3; 769 u32 disp_int_cont4; 770 u32 disp_int_cont5; 771 u32 disp_int_cont6; 772 u32 d1grph_int; 773 u32 d2grph_int; 774 u32 d3grph_int; 775 u32 d4grph_int; 776 u32 d5grph_int; 777 u32 d6grph_int; 778 }; 779 780 union radeon_irq_stat_regs { 781 struct r500_irq_stat_regs r500; 782 struct r600_irq_stat_regs r600; 783 struct evergreen_irq_stat_regs evergreen; 784 struct cik_irq_stat_regs cik; 785 }; 786 787 #define RADEON_MAX_HPD_PINS 7 788 #define RADEON_MAX_CRTCS 6 789 #define RADEON_MAX_AFMT_BLOCKS 7 790 791 struct radeon_irq { 792 bool installed; 793 spinlock_t lock; 794 atomic_t ring_int[RADEON_NUM_RINGS]; 795 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 796 atomic_t pflip[RADEON_MAX_CRTCS]; 797 #ifdef __NetBSD__ 798 spinlock_t vblank_lock; 799 drm_waitqueue_t vblank_queue; 800 #else 801 wait_queue_head_t vblank_queue; 802 #endif 803 bool hpd[RADEON_MAX_HPD_PINS]; 804 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 805 union radeon_irq_stat_regs stat_regs; 806 bool dpm_thermal; 807 }; 808 809 int radeon_irq_kms_init(struct radeon_device *rdev); 810 void radeon_irq_kms_fini(struct radeon_device *rdev); 811 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 812 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 813 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 814 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 815 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 816 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 817 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 818 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 819 820 /* 821 * CP & rings. 822 */ 823 824 struct radeon_ib { 825 struct radeon_sa_bo *sa_bo; 826 uint32_t length_dw; 827 uint64_t gpu_addr; 828 uint32_t *ptr; 829 int ring; 830 struct radeon_fence *fence; 831 struct radeon_vm *vm; 832 bool is_const_ib; 833 struct radeon_semaphore *semaphore; 834 }; 835 836 struct radeon_ring { 837 struct radeon_bo *ring_obj; 838 volatile uint32_t *ring; 839 unsigned rptr_offs; 840 unsigned rptr_save_reg; 841 u64 next_rptr_gpu_addr; 842 volatile u32 *next_rptr_cpu_addr; 843 unsigned wptr; 844 unsigned wptr_old; 845 unsigned ring_size; 846 unsigned ring_free_dw; 847 int count_dw; 848 atomic_t last_rptr; 849 atomic64_t last_activity; 850 uint64_t gpu_addr; 851 uint32_t align_mask; 852 uint32_t ptr_mask; 853 bool ready; 854 u32 nop; 855 u32 idx; 856 u64 last_semaphore_signal_addr; 857 u64 last_semaphore_wait_addr; 858 /* for CIK queues */ 859 u32 me; 860 u32 pipe; 861 u32 queue; 862 struct radeon_bo *mqd_obj; 863 u32 doorbell_index; 864 unsigned wptr_offs; 865 }; 866 867 struct radeon_mec { 868 struct radeon_bo *hpd_eop_obj; 869 u64 hpd_eop_gpu_addr; 870 u32 num_pipe; 871 u32 num_mec; 872 u32 num_queue; 873 }; 874 875 /* 876 * VM 877 */ 878 879 /* maximum number of VMIDs */ 880 #define RADEON_NUM_VM 16 881 882 /* defines number of bits in page table versus page directory, 883 * a page is 4KB so we have 12 bits offset, 9 bits in the page 884 * table and the remaining 19 bits are in the page directory */ 885 #define RADEON_VM_BLOCK_SIZE 9 886 887 /* number of entries in page table */ 888 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 889 890 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 891 #define RADEON_VM_PTB_ALIGN_SIZE 32768 892 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 893 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 894 895 #define R600_PTE_VALID (1 << 0) 896 #define R600_PTE_SYSTEM (1 << 1) 897 #define R600_PTE_SNOOPED (1 << 2) 898 #define R600_PTE_READABLE (1 << 5) 899 #define R600_PTE_WRITEABLE (1 << 6) 900 901 struct radeon_vm_pt { 902 struct radeon_bo *bo; 903 uint64_t addr; 904 }; 905 906 struct radeon_vm { 907 struct list_head va; 908 unsigned id; 909 910 /* contains the page directory */ 911 struct radeon_bo *page_directory; 912 uint64_t pd_gpu_addr; 913 unsigned max_pde_used; 914 915 /* array of page tables, one for each page directory entry */ 916 struct radeon_vm_pt *page_tables; 917 918 struct mutex mutex; 919 /* last fence for cs using this vm */ 920 struct radeon_fence *fence; 921 /* last flush or NULL if we still need to flush */ 922 struct radeon_fence *last_flush; 923 /* last use of vmid */ 924 struct radeon_fence *last_id_use; 925 }; 926 927 struct radeon_vm_manager { 928 struct radeon_fence *active[RADEON_NUM_VM]; 929 uint32_t max_pfn; 930 /* number of VMIDs */ 931 unsigned nvm; 932 /* vram base address for page table entry */ 933 u64 vram_base_offset; 934 /* is vm enabled? */ 935 bool enabled; 936 }; 937 938 /* 939 * file private structure 940 */ 941 struct radeon_fpriv { 942 struct radeon_vm vm; 943 }; 944 945 /* 946 * R6xx+ IH ring 947 */ 948 struct r600_ih { 949 struct radeon_bo *ring_obj; 950 volatile uint32_t *ring; 951 unsigned rptr; 952 unsigned ring_size; 953 uint64_t gpu_addr; 954 uint32_t ptr_mask; 955 atomic_t lock; 956 bool enabled; 957 }; 958 959 /* 960 * RLC stuff 961 */ 962 #include "clearstate_defs.h" 963 964 struct radeon_rlc { 965 /* for power gating */ 966 struct radeon_bo *save_restore_obj; 967 uint64_t save_restore_gpu_addr; 968 volatile uint32_t *sr_ptr; 969 const u32 *reg_list; 970 u32 reg_list_size; 971 /* for clear state */ 972 struct radeon_bo *clear_state_obj; 973 uint64_t clear_state_gpu_addr; 974 volatile uint32_t *cs_ptr; 975 const struct cs_section_def *cs_data; 976 u32 clear_state_size; 977 /* for cp tables */ 978 struct radeon_bo *cp_table_obj; 979 uint64_t cp_table_gpu_addr; 980 volatile uint32_t *cp_table_ptr; 981 u32 cp_table_size; 982 }; 983 984 int radeon_ib_get(struct radeon_device *rdev, int ring, 985 struct radeon_ib *ib, struct radeon_vm *vm, 986 unsigned size); 987 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 988 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 989 struct radeon_ib *const_ib); 990 int radeon_ib_pool_init(struct radeon_device *rdev); 991 void radeon_ib_pool_fini(struct radeon_device *rdev); 992 int radeon_ib_ring_tests(struct radeon_device *rdev); 993 /* Ring access between begin & end cannot sleep */ 994 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 995 struct radeon_ring *ring); 996 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 997 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 998 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 999 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 1000 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 1001 void radeon_ring_undo(struct radeon_ring *ring); 1002 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1003 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1004 void radeon_ring_lockup_update(struct radeon_device *rdev, 1005 struct radeon_ring *ring); 1006 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1007 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1008 uint32_t **data); 1009 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1010 unsigned size, uint32_t *data); 1011 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1012 unsigned rptr_offs, u32 nop); 1013 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1014 1015 1016 /* r600 async dma */ 1017 void r600_dma_stop(struct radeon_device *rdev); 1018 int r600_dma_resume(struct radeon_device *rdev); 1019 void r600_dma_fini(struct radeon_device *rdev); 1020 1021 void cayman_dma_stop(struct radeon_device *rdev); 1022 int cayman_dma_resume(struct radeon_device *rdev); 1023 void cayman_dma_fini(struct radeon_device *rdev); 1024 1025 /* 1026 * CS. 1027 */ 1028 struct radeon_cs_reloc { 1029 struct drm_gem_object *gobj; 1030 struct radeon_bo *robj; 1031 struct ttm_validate_buffer tv; 1032 uint64_t gpu_offset; 1033 unsigned domain; 1034 unsigned alt_domain; 1035 uint32_t tiling_flags; 1036 uint32_t handle; 1037 }; 1038 1039 struct radeon_cs_chunk { 1040 uint32_t chunk_id; 1041 uint32_t length_dw; 1042 uint32_t *kdata; 1043 void __user *user_ptr; 1044 }; 1045 1046 struct radeon_cs_parser { 1047 struct device *dev; 1048 struct radeon_device *rdev; 1049 struct drm_file *filp; 1050 /* chunks */ 1051 unsigned nchunks; 1052 struct radeon_cs_chunk *chunks; 1053 uint64_t *chunks_array; 1054 /* IB */ 1055 unsigned idx; 1056 /* relocations */ 1057 unsigned nrelocs; 1058 struct radeon_cs_reloc *relocs; 1059 struct radeon_cs_reloc **relocs_ptr; 1060 struct radeon_cs_reloc *vm_bos; 1061 struct list_head validated; 1062 unsigned dma_reloc_idx; 1063 /* indices of various chunks */ 1064 int chunk_ib_idx; 1065 int chunk_relocs_idx; 1066 int chunk_flags_idx; 1067 int chunk_const_ib_idx; 1068 struct radeon_ib ib; 1069 struct radeon_ib const_ib; 1070 void *track; 1071 unsigned family; 1072 int parser_error; 1073 u32 cs_flags; 1074 u32 ring; 1075 s32 priority; 1076 struct ww_acquire_ctx ticket; 1077 }; 1078 1079 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1080 { 1081 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1082 1083 if (ibc->kdata) 1084 return ibc->kdata[idx]; 1085 return p->ib.ptr[idx]; 1086 } 1087 1088 1089 struct radeon_cs_packet { 1090 unsigned idx; 1091 unsigned type; 1092 unsigned reg; 1093 unsigned opcode; 1094 int count; 1095 unsigned one_reg_wr; 1096 }; 1097 1098 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1099 struct radeon_cs_packet *pkt, 1100 unsigned idx, unsigned reg); 1101 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1102 struct radeon_cs_packet *pkt); 1103 1104 1105 /* 1106 * AGP 1107 */ 1108 int radeon_agp_init(struct radeon_device *rdev); 1109 void radeon_agp_resume(struct radeon_device *rdev); 1110 void radeon_agp_suspend(struct radeon_device *rdev); 1111 void radeon_agp_fini(struct radeon_device *rdev); 1112 1113 1114 /* 1115 * Writeback 1116 */ 1117 struct radeon_wb { 1118 struct radeon_bo *wb_obj; 1119 volatile uint32_t *wb; 1120 uint64_t gpu_addr; 1121 bool enabled; 1122 bool use_event; 1123 }; 1124 1125 #define RADEON_WB_SCRATCH_OFFSET 0 1126 #define RADEON_WB_RING0_NEXT_RPTR 256 1127 #define RADEON_WB_CP_RPTR_OFFSET 1024 1128 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1129 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1130 #define R600_WB_DMA_RPTR_OFFSET 1792 1131 #define R600_WB_IH_WPTR_OFFSET 2048 1132 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1133 #define R600_WB_EVENT_OFFSET 3072 1134 #define CIK_WB_CP1_WPTR_OFFSET 3328 1135 #define CIK_WB_CP2_WPTR_OFFSET 3584 1136 1137 /** 1138 * struct radeon_pm - power management datas 1139 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1140 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1141 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1142 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1143 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1144 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1145 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1146 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1147 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1148 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1149 * @needed_bandwidth: current bandwidth needs 1150 * 1151 * It keeps track of various data needed to take powermanagement decision. 1152 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1153 * Equation between gpu/memory clock and available bandwidth is hw dependent 1154 * (type of memory, bus size, efficiency, ...) 1155 */ 1156 1157 enum radeon_pm_method { 1158 PM_METHOD_PROFILE, 1159 PM_METHOD_DYNPM, 1160 PM_METHOD_DPM, 1161 }; 1162 1163 enum radeon_dynpm_state { 1164 DYNPM_STATE_DISABLED, 1165 DYNPM_STATE_MINIMUM, 1166 DYNPM_STATE_PAUSED, 1167 DYNPM_STATE_ACTIVE, 1168 DYNPM_STATE_SUSPENDED, 1169 }; 1170 enum radeon_dynpm_action { 1171 DYNPM_ACTION_NONE, 1172 DYNPM_ACTION_MINIMUM, 1173 DYNPM_ACTION_DOWNCLOCK, 1174 DYNPM_ACTION_UPCLOCK, 1175 DYNPM_ACTION_DEFAULT 1176 }; 1177 1178 enum radeon_voltage_type { 1179 VOLTAGE_NONE = 0, 1180 VOLTAGE_GPIO, 1181 VOLTAGE_VDDC, 1182 VOLTAGE_SW 1183 }; 1184 1185 enum radeon_pm_state_type { 1186 /* not used for dpm */ 1187 POWER_STATE_TYPE_DEFAULT, 1188 POWER_STATE_TYPE_POWERSAVE, 1189 /* user selectable states */ 1190 POWER_STATE_TYPE_BATTERY, 1191 POWER_STATE_TYPE_BALANCED, 1192 POWER_STATE_TYPE_PERFORMANCE, 1193 /* internal states */ 1194 POWER_STATE_TYPE_INTERNAL_UVD, 1195 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1196 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1197 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1198 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1199 POWER_STATE_TYPE_INTERNAL_BOOT, 1200 POWER_STATE_TYPE_INTERNAL_THERMAL, 1201 POWER_STATE_TYPE_INTERNAL_ACPI, 1202 POWER_STATE_TYPE_INTERNAL_ULV, 1203 POWER_STATE_TYPE_INTERNAL_3DPERF, 1204 }; 1205 1206 enum radeon_pm_profile_type { 1207 PM_PROFILE_DEFAULT, 1208 PM_PROFILE_AUTO, 1209 PM_PROFILE_LOW, 1210 PM_PROFILE_MID, 1211 PM_PROFILE_HIGH, 1212 }; 1213 1214 #define PM_PROFILE_DEFAULT_IDX 0 1215 #define PM_PROFILE_LOW_SH_IDX 1 1216 #define PM_PROFILE_MID_SH_IDX 2 1217 #define PM_PROFILE_HIGH_SH_IDX 3 1218 #define PM_PROFILE_LOW_MH_IDX 4 1219 #define PM_PROFILE_MID_MH_IDX 5 1220 #define PM_PROFILE_HIGH_MH_IDX 6 1221 #define PM_PROFILE_MAX 7 1222 1223 struct radeon_pm_profile { 1224 int dpms_off_ps_idx; 1225 int dpms_on_ps_idx; 1226 int dpms_off_cm_idx; 1227 int dpms_on_cm_idx; 1228 }; 1229 1230 enum radeon_int_thermal_type { 1231 THERMAL_TYPE_NONE, 1232 THERMAL_TYPE_EXTERNAL, 1233 THERMAL_TYPE_EXTERNAL_GPIO, 1234 THERMAL_TYPE_RV6XX, 1235 THERMAL_TYPE_RV770, 1236 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1237 THERMAL_TYPE_EVERGREEN, 1238 THERMAL_TYPE_SUMO, 1239 THERMAL_TYPE_NI, 1240 THERMAL_TYPE_SI, 1241 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1242 THERMAL_TYPE_CI, 1243 THERMAL_TYPE_KV, 1244 }; 1245 1246 struct radeon_voltage { 1247 enum radeon_voltage_type type; 1248 /* gpio voltage */ 1249 struct radeon_gpio_rec gpio; 1250 u32 delay; /* delay in usec from voltage drop to sclk change */ 1251 bool active_high; /* voltage drop is active when bit is high */ 1252 /* VDDC voltage */ 1253 u8 vddc_id; /* index into vddc voltage table */ 1254 u8 vddci_id; /* index into vddci voltage table */ 1255 bool vddci_enabled; 1256 /* r6xx+ sw */ 1257 u16 voltage; 1258 /* evergreen+ vddci */ 1259 u16 vddci; 1260 }; 1261 1262 /* clock mode flags */ 1263 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1264 1265 struct radeon_pm_clock_info { 1266 /* memory clock */ 1267 u32 mclk; 1268 /* engine clock */ 1269 u32 sclk; 1270 /* voltage info */ 1271 struct radeon_voltage voltage; 1272 /* standardized clock flags */ 1273 u32 flags; 1274 }; 1275 1276 /* state flags */ 1277 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1278 1279 struct radeon_power_state { 1280 enum radeon_pm_state_type type; 1281 struct radeon_pm_clock_info *clock_info; 1282 /* number of valid clock modes in this power state */ 1283 int num_clock_modes; 1284 struct radeon_pm_clock_info *default_clock_mode; 1285 /* standardized state flags */ 1286 u32 flags; 1287 u32 misc; /* vbios specific flags */ 1288 u32 misc2; /* vbios specific flags */ 1289 int pcie_lanes; /* pcie lanes */ 1290 }; 1291 1292 /* 1293 * Some modes are overclocked by very low value, accept them 1294 */ 1295 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1296 1297 enum radeon_dpm_auto_throttle_src { 1298 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1299 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1300 }; 1301 1302 enum radeon_dpm_event_src { 1303 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1304 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1305 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1306 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1307 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1308 }; 1309 1310 #define RADEON_MAX_VCE_LEVELS 6 1311 1312 enum radeon_vce_level { 1313 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1314 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1315 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1316 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1317 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1318 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1319 }; 1320 1321 struct radeon_ps { 1322 u32 caps; /* vbios flags */ 1323 u32 class; /* vbios flags */ 1324 u32 class2; /* vbios flags */ 1325 /* UVD clocks */ 1326 u32 vclk; 1327 u32 dclk; 1328 /* VCE clocks */ 1329 u32 evclk; 1330 u32 ecclk; 1331 bool vce_active; 1332 enum radeon_vce_level vce_level; 1333 /* asic priv */ 1334 void *ps_priv; 1335 }; 1336 1337 struct radeon_dpm_thermal { 1338 /* thermal interrupt work */ 1339 struct work_struct work; 1340 /* low temperature threshold */ 1341 int min_temp; 1342 /* high temperature threshold */ 1343 int max_temp; 1344 /* was interrupt low to high or high to low */ 1345 bool high_to_low; 1346 }; 1347 1348 enum radeon_clk_action 1349 { 1350 RADEON_SCLK_UP = 1, 1351 RADEON_SCLK_DOWN 1352 }; 1353 1354 struct radeon_blacklist_clocks 1355 { 1356 u32 sclk; 1357 u32 mclk; 1358 enum radeon_clk_action action; 1359 }; 1360 1361 struct radeon_clock_and_voltage_limits { 1362 u32 sclk; 1363 u32 mclk; 1364 u16 vddc; 1365 u16 vddci; 1366 }; 1367 1368 struct radeon_clock_array { 1369 u32 count; 1370 u32 *values; 1371 }; 1372 1373 struct radeon_clock_voltage_dependency_entry { 1374 u32 clk; 1375 u16 v; 1376 }; 1377 1378 struct radeon_clock_voltage_dependency_table { 1379 u32 count; 1380 struct radeon_clock_voltage_dependency_entry *entries; 1381 }; 1382 1383 union radeon_cac_leakage_entry { 1384 struct { 1385 u16 vddc; 1386 u32 leakage; 1387 }; 1388 struct { 1389 u16 vddc1; 1390 u16 vddc2; 1391 u16 vddc3; 1392 }; 1393 }; 1394 1395 struct radeon_cac_leakage_table { 1396 u32 count; 1397 union radeon_cac_leakage_entry *entries; 1398 }; 1399 1400 struct radeon_phase_shedding_limits_entry { 1401 u16 voltage; 1402 u32 sclk; 1403 u32 mclk; 1404 }; 1405 1406 struct radeon_phase_shedding_limits_table { 1407 u32 count; 1408 struct radeon_phase_shedding_limits_entry *entries; 1409 }; 1410 1411 struct radeon_uvd_clock_voltage_dependency_entry { 1412 u32 vclk; 1413 u32 dclk; 1414 u16 v; 1415 }; 1416 1417 struct radeon_uvd_clock_voltage_dependency_table { 1418 u8 count; 1419 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1420 }; 1421 1422 struct radeon_vce_clock_voltage_dependency_entry { 1423 u32 ecclk; 1424 u32 evclk; 1425 u16 v; 1426 }; 1427 1428 struct radeon_vce_clock_voltage_dependency_table { 1429 u8 count; 1430 struct radeon_vce_clock_voltage_dependency_entry *entries; 1431 }; 1432 1433 struct radeon_ppm_table { 1434 u8 ppm_design; 1435 u16 cpu_core_number; 1436 u32 platform_tdp; 1437 u32 small_ac_platform_tdp; 1438 u32 platform_tdc; 1439 u32 small_ac_platform_tdc; 1440 u32 apu_tdp; 1441 u32 dgpu_tdp; 1442 u32 dgpu_ulv_power; 1443 u32 tj_max; 1444 }; 1445 1446 struct radeon_cac_tdp_table { 1447 u16 tdp; 1448 u16 configurable_tdp; 1449 u16 tdc; 1450 u16 battery_power_limit; 1451 u16 small_power_limit; 1452 u16 low_cac_leakage; 1453 u16 high_cac_leakage; 1454 u16 maximum_power_delivery_limit; 1455 }; 1456 1457 struct radeon_dpm_dynamic_state { 1458 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1459 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1460 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1461 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1463 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1464 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1465 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1466 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1467 struct radeon_clock_array valid_sclk_values; 1468 struct radeon_clock_array valid_mclk_values; 1469 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1470 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1471 u32 mclk_sclk_ratio; 1472 u32 sclk_mclk_delta; 1473 u16 vddc_vddci_delta; 1474 u16 min_vddc_for_pcie_gen2; 1475 struct radeon_cac_leakage_table cac_leakage_table; 1476 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1477 struct radeon_ppm_table *ppm_table; 1478 struct radeon_cac_tdp_table *cac_tdp_table; 1479 }; 1480 1481 struct radeon_dpm_fan { 1482 u16 t_min; 1483 u16 t_med; 1484 u16 t_high; 1485 u16 pwm_min; 1486 u16 pwm_med; 1487 u16 pwm_high; 1488 u8 t_hyst; 1489 u32 cycle_delay; 1490 u16 t_max; 1491 bool ucode_fan_control; 1492 }; 1493 1494 enum radeon_pcie_gen { 1495 RADEON_PCIE_GEN1 = 0, 1496 RADEON_PCIE_GEN2 = 1, 1497 RADEON_PCIE_GEN3 = 2, 1498 RADEON_PCIE_GEN_INVALID = 0xffff 1499 }; 1500 1501 enum radeon_dpm_forced_level { 1502 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1503 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1504 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1505 }; 1506 1507 struct radeon_vce_state { 1508 /* vce clocks */ 1509 u32 evclk; 1510 u32 ecclk; 1511 /* gpu clocks */ 1512 u32 sclk; 1513 u32 mclk; 1514 u8 clk_idx; 1515 u8 pstate; 1516 }; 1517 1518 struct radeon_dpm { 1519 struct radeon_ps *ps; 1520 /* number of valid power states */ 1521 int num_ps; 1522 /* current power state that is active */ 1523 struct radeon_ps *current_ps; 1524 /* requested power state */ 1525 struct radeon_ps *requested_ps; 1526 /* boot up power state */ 1527 struct radeon_ps *boot_ps; 1528 /* default uvd power state */ 1529 struct radeon_ps *uvd_ps; 1530 /* vce requirements */ 1531 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1532 enum radeon_vce_level vce_level; 1533 enum radeon_pm_state_type state; 1534 enum radeon_pm_state_type user_state; 1535 u32 platform_caps; 1536 u32 voltage_response_time; 1537 u32 backbias_response_time; 1538 void *priv; 1539 u32 new_active_crtcs; 1540 int new_active_crtc_count; 1541 u32 current_active_crtcs; 1542 int current_active_crtc_count; 1543 struct radeon_dpm_dynamic_state dyn_state; 1544 struct radeon_dpm_fan fan; 1545 u32 tdp_limit; 1546 u32 near_tdp_limit; 1547 u32 near_tdp_limit_adjusted; 1548 u32 sq_ramping_threshold; 1549 u32 cac_leakage; 1550 u16 tdp_od_limit; 1551 u32 tdp_adjustment; 1552 u16 load_line_slope; 1553 bool power_control; 1554 bool ac_power; 1555 /* special states active */ 1556 bool thermal_active; 1557 bool uvd_active; 1558 bool vce_active; 1559 /* thermal handling */ 1560 struct radeon_dpm_thermal thermal; 1561 /* forced levels */ 1562 enum radeon_dpm_forced_level forced_level; 1563 /* track UVD streams */ 1564 unsigned sd; 1565 unsigned hd; 1566 }; 1567 1568 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1569 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1570 1571 struct radeon_pm { 1572 struct mutex mutex; 1573 /* write locked while reprogramming mclk */ 1574 struct rw_semaphore mclk_lock; 1575 u32 active_crtcs; 1576 int active_crtc_count; 1577 int req_vblank; 1578 bool vblank_sync; 1579 fixed20_12 max_bandwidth; 1580 fixed20_12 igp_sideport_mclk; 1581 fixed20_12 igp_system_mclk; 1582 fixed20_12 igp_ht_link_clk; 1583 fixed20_12 igp_ht_link_width; 1584 fixed20_12 k8_bandwidth; 1585 fixed20_12 sideport_bandwidth; 1586 fixed20_12 ht_bandwidth; 1587 fixed20_12 core_bandwidth; 1588 fixed20_12 sclk; 1589 fixed20_12 mclk; 1590 fixed20_12 needed_bandwidth; 1591 struct radeon_power_state *power_state; 1592 /* number of valid power states */ 1593 int num_power_states; 1594 int current_power_state_index; 1595 int current_clock_mode_index; 1596 int requested_power_state_index; 1597 int requested_clock_mode_index; 1598 int default_power_state_index; 1599 u32 current_sclk; 1600 u32 current_mclk; 1601 u16 current_vddc; 1602 u16 current_vddci; 1603 u32 default_sclk; 1604 u32 default_mclk; 1605 u16 default_vddc; 1606 u16 default_vddci; 1607 struct radeon_i2c_chan *i2c_bus; 1608 /* selected pm method */ 1609 enum radeon_pm_method pm_method; 1610 /* dynpm power management */ 1611 struct delayed_work dynpm_idle_work; 1612 enum radeon_dynpm_state dynpm_state; 1613 enum radeon_dynpm_action dynpm_planned_action; 1614 unsigned long dynpm_action_timeout; 1615 bool dynpm_can_upclock; 1616 bool dynpm_can_downclock; 1617 /* profile-based power management */ 1618 enum radeon_pm_profile_type profile; 1619 int profile_index; 1620 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1621 /* internal thermal controller on rv6xx+ */ 1622 enum radeon_int_thermal_type int_thermal_type; 1623 struct device *int_hwmon_dev; 1624 /* dpm */ 1625 bool dpm_enabled; 1626 struct radeon_dpm dpm; 1627 }; 1628 1629 int radeon_pm_get_type_index(struct radeon_device *rdev, 1630 enum radeon_pm_state_type ps_type, 1631 int instance); 1632 /* 1633 * UVD 1634 */ 1635 #define RADEON_MAX_UVD_HANDLES 10 1636 #define RADEON_UVD_STACK_SIZE (1024*1024) 1637 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1638 1639 struct radeon_uvd { 1640 struct radeon_bo *vcpu_bo; 1641 void *cpu_addr; 1642 uint64_t gpu_addr; 1643 void *saved_bo; 1644 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1645 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1646 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1647 struct delayed_work idle_work; 1648 }; 1649 1650 int radeon_uvd_init(struct radeon_device *rdev); 1651 void radeon_uvd_fini(struct radeon_device *rdev); 1652 int radeon_uvd_suspend(struct radeon_device *rdev); 1653 int radeon_uvd_resume(struct radeon_device *rdev); 1654 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1655 uint32_t handle, struct radeon_fence **fence); 1656 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1657 uint32_t handle, struct radeon_fence **fence); 1658 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1659 void radeon_uvd_free_handles(struct radeon_device *rdev, 1660 struct drm_file *filp); 1661 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1662 void radeon_uvd_note_usage(struct radeon_device *rdev); 1663 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1664 unsigned vclk, unsigned dclk, 1665 unsigned vco_min, unsigned vco_max, 1666 unsigned fb_factor, unsigned fb_mask, 1667 unsigned pd_min, unsigned pd_max, 1668 unsigned pd_even, 1669 unsigned *optimal_fb_div, 1670 unsigned *optimal_vclk_div, 1671 unsigned *optimal_dclk_div); 1672 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1673 unsigned cg_upll_func_cntl); 1674 1675 /* 1676 * VCE 1677 */ 1678 #define RADEON_MAX_VCE_HANDLES 16 1679 #define RADEON_VCE_STACK_SIZE (1024*1024) 1680 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1681 1682 struct radeon_vce { 1683 struct radeon_bo *vcpu_bo; 1684 uint64_t gpu_addr; 1685 unsigned fw_version; 1686 unsigned fb_version; 1687 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1688 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1689 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1690 struct delayed_work idle_work; 1691 }; 1692 1693 int radeon_vce_init(struct radeon_device *rdev); 1694 void radeon_vce_fini(struct radeon_device *rdev); 1695 int radeon_vce_suspend(struct radeon_device *rdev); 1696 int radeon_vce_resume(struct radeon_device *rdev); 1697 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1698 uint32_t handle, struct radeon_fence **fence); 1699 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1700 uint32_t handle, struct radeon_fence **fence); 1701 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1702 void radeon_vce_note_usage(struct radeon_device *rdev); 1703 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1704 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1705 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1706 struct radeon_ring *ring, 1707 struct radeon_semaphore *semaphore, 1708 bool emit_wait); 1709 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1710 void radeon_vce_fence_emit(struct radeon_device *rdev, 1711 struct radeon_fence *fence); 1712 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1713 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1714 1715 struct r600_audio_pin { 1716 int channels; 1717 int rate; 1718 int bits_per_sample; 1719 u8 status_bits; 1720 u8 category_code; 1721 u32 offset; 1722 bool connected; 1723 u32 id; 1724 }; 1725 1726 struct r600_audio { 1727 bool enabled; 1728 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1729 int num_pins; 1730 }; 1731 1732 /* 1733 * Benchmarking 1734 */ 1735 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1736 1737 1738 /* 1739 * Testing 1740 */ 1741 void radeon_test_moves(struct radeon_device *rdev); 1742 void radeon_test_ring_sync(struct radeon_device *rdev, 1743 struct radeon_ring *cpA, 1744 struct radeon_ring *cpB); 1745 void radeon_test_syncing(struct radeon_device *rdev); 1746 1747 1748 /* 1749 * Debugfs 1750 */ 1751 struct radeon_debugfs { 1752 struct drm_info_list *files; 1753 unsigned num_files; 1754 }; 1755 1756 int radeon_debugfs_add_files(struct radeon_device *rdev, 1757 struct drm_info_list *files, 1758 unsigned nfiles); 1759 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1760 1761 /* 1762 * ASIC ring specific functions. 1763 */ 1764 struct radeon_asic_ring { 1765 /* ring read/write ptr handling */ 1766 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1767 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1768 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1769 1770 /* validating and patching of IBs */ 1771 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1772 int (*cs_parse)(struct radeon_cs_parser *p); 1773 1774 /* command emmit functions */ 1775 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1776 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1777 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1778 struct radeon_semaphore *semaphore, bool emit_wait); 1779 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1780 1781 /* testing functions */ 1782 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1783 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1784 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1785 1786 /* deprecated */ 1787 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1788 }; 1789 1790 /* 1791 * ASIC specific functions. 1792 */ 1793 struct radeon_asic { 1794 int (*init)(struct radeon_device *rdev); 1795 void (*fini)(struct radeon_device *rdev); 1796 int (*resume)(struct radeon_device *rdev); 1797 int (*suspend)(struct radeon_device *rdev); 1798 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1799 int (*asic_reset)(struct radeon_device *rdev); 1800 /* ioctl hw specific callback. Some hw might want to perform special 1801 * operation on specific ioctl. For instance on wait idle some hw 1802 * might want to perform and HDP flush through MMIO as it seems that 1803 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1804 * through ring. 1805 */ 1806 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1807 /* check if 3D engine is idle */ 1808 bool (*gui_idle)(struct radeon_device *rdev); 1809 /* wait for mc_idle */ 1810 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1811 /* get the reference clock */ 1812 u32 (*get_xclk)(struct radeon_device *rdev); 1813 /* get the gpu clock counter */ 1814 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1815 /* gart */ 1816 struct { 1817 void (*tlb_flush)(struct radeon_device *rdev); 1818 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1819 } gart; 1820 struct { 1821 int (*init)(struct radeon_device *rdev); 1822 void (*fini)(struct radeon_device *rdev); 1823 void (*set_page)(struct radeon_device *rdev, 1824 struct radeon_ib *ib, 1825 uint64_t pe, 1826 uint64_t addr, unsigned count, 1827 uint32_t incr, uint32_t flags); 1828 } vm; 1829 /* ring specific callbacks */ 1830 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1831 /* irqs */ 1832 struct { 1833 int (*set)(struct radeon_device *rdev); 1834 int (*process)(struct radeon_device *rdev); 1835 } irq; 1836 /* displays */ 1837 struct { 1838 /* display watermarks */ 1839 void (*bandwidth_update)(struct radeon_device *rdev); 1840 /* get frame count */ 1841 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1842 /* wait for vblank */ 1843 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1844 /* set backlight level */ 1845 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1846 /* get backlight level */ 1847 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1848 /* audio callbacks */ 1849 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1850 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1851 } display; 1852 /* copy functions for bo handling */ 1853 struct { 1854 int (*blit)(struct radeon_device *rdev, 1855 uint64_t src_offset, 1856 uint64_t dst_offset, 1857 unsigned num_gpu_pages, 1858 struct radeon_fence **fence); 1859 u32 blit_ring_index; 1860 int (*dma)(struct radeon_device *rdev, 1861 uint64_t src_offset, 1862 uint64_t dst_offset, 1863 unsigned num_gpu_pages, 1864 struct radeon_fence **fence); 1865 u32 dma_ring_index; 1866 /* method used for bo copy */ 1867 int (*copy)(struct radeon_device *rdev, 1868 uint64_t src_offset, 1869 uint64_t dst_offset, 1870 unsigned num_gpu_pages, 1871 struct radeon_fence **fence); 1872 /* ring used for bo copies */ 1873 u32 copy_ring_index; 1874 } copy; 1875 /* surfaces */ 1876 struct { 1877 int (*set_reg)(struct radeon_device *rdev, int reg, 1878 uint32_t tiling_flags, uint32_t pitch, 1879 uint32_t offset, uint32_t obj_size); 1880 void (*clear_reg)(struct radeon_device *rdev, int reg); 1881 } surface; 1882 /* hotplug detect */ 1883 struct { 1884 void (*init)(struct radeon_device *rdev); 1885 void (*fini)(struct radeon_device *rdev); 1886 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1887 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1888 } hpd; 1889 /* static power management */ 1890 struct { 1891 void (*misc)(struct radeon_device *rdev); 1892 void (*prepare)(struct radeon_device *rdev); 1893 void (*finish)(struct radeon_device *rdev); 1894 void (*init_profile)(struct radeon_device *rdev); 1895 void (*get_dynpm_state)(struct radeon_device *rdev); 1896 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1897 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1898 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1899 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1900 int (*get_pcie_lanes)(struct radeon_device *rdev); 1901 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1902 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1903 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1904 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1905 int (*get_temperature)(struct radeon_device *rdev); 1906 } pm; 1907 /* dynamic power management */ 1908 struct { 1909 int (*init)(struct radeon_device *rdev); 1910 void (*setup_asic)(struct radeon_device *rdev); 1911 int (*enable)(struct radeon_device *rdev); 1912 int (*late_enable)(struct radeon_device *rdev); 1913 void (*disable)(struct radeon_device *rdev); 1914 int (*pre_set_power_state)(struct radeon_device *rdev); 1915 int (*set_power_state)(struct radeon_device *rdev); 1916 void (*post_set_power_state)(struct radeon_device *rdev); 1917 void (*display_configuration_changed)(struct radeon_device *rdev); 1918 void (*fini)(struct radeon_device *rdev); 1919 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1920 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1921 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1922 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1923 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1924 bool (*vblank_too_short)(struct radeon_device *rdev); 1925 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1926 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1927 } dpm; 1928 /* pageflipping */ 1929 struct { 1930 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1931 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1932 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1933 } pflip; 1934 }; 1935 1936 /* 1937 * Asic structures 1938 */ 1939 struct r100_asic { 1940 const unsigned *reg_safe_bm; 1941 unsigned reg_safe_bm_size; 1942 u32 hdp_cntl; 1943 }; 1944 1945 struct r300_asic { 1946 const unsigned *reg_safe_bm; 1947 unsigned reg_safe_bm_size; 1948 u32 resync_scratch; 1949 u32 hdp_cntl; 1950 }; 1951 1952 struct r600_asic { 1953 unsigned max_pipes; 1954 unsigned max_tile_pipes; 1955 unsigned max_simds; 1956 unsigned max_backends; 1957 unsigned max_gprs; 1958 unsigned max_threads; 1959 unsigned max_stack_entries; 1960 unsigned max_hw_contexts; 1961 unsigned max_gs_threads; 1962 unsigned sx_max_export_size; 1963 unsigned sx_max_export_pos_size; 1964 unsigned sx_max_export_smx_size; 1965 unsigned sq_num_cf_insts; 1966 unsigned tiling_nbanks; 1967 unsigned tiling_npipes; 1968 unsigned tiling_group_size; 1969 unsigned tile_config; 1970 unsigned backend_map; 1971 }; 1972 1973 struct rv770_asic { 1974 unsigned max_pipes; 1975 unsigned max_tile_pipes; 1976 unsigned max_simds; 1977 unsigned max_backends; 1978 unsigned max_gprs; 1979 unsigned max_threads; 1980 unsigned max_stack_entries; 1981 unsigned max_hw_contexts; 1982 unsigned max_gs_threads; 1983 unsigned sx_max_export_size; 1984 unsigned sx_max_export_pos_size; 1985 unsigned sx_max_export_smx_size; 1986 unsigned sq_num_cf_insts; 1987 unsigned sx_num_of_sets; 1988 unsigned sc_prim_fifo_size; 1989 unsigned sc_hiz_tile_fifo_size; 1990 unsigned sc_earlyz_tile_fifo_fize; 1991 unsigned tiling_nbanks; 1992 unsigned tiling_npipes; 1993 unsigned tiling_group_size; 1994 unsigned tile_config; 1995 unsigned backend_map; 1996 }; 1997 1998 struct evergreen_asic { 1999 unsigned num_ses; 2000 unsigned max_pipes; 2001 unsigned max_tile_pipes; 2002 unsigned max_simds; 2003 unsigned max_backends; 2004 unsigned max_gprs; 2005 unsigned max_threads; 2006 unsigned max_stack_entries; 2007 unsigned max_hw_contexts; 2008 unsigned max_gs_threads; 2009 unsigned sx_max_export_size; 2010 unsigned sx_max_export_pos_size; 2011 unsigned sx_max_export_smx_size; 2012 unsigned sq_num_cf_insts; 2013 unsigned sx_num_of_sets; 2014 unsigned sc_prim_fifo_size; 2015 unsigned sc_hiz_tile_fifo_size; 2016 unsigned sc_earlyz_tile_fifo_size; 2017 unsigned tiling_nbanks; 2018 unsigned tiling_npipes; 2019 unsigned tiling_group_size; 2020 unsigned tile_config; 2021 unsigned backend_map; 2022 }; 2023 2024 struct cayman_asic { 2025 unsigned max_shader_engines; 2026 unsigned max_pipes_per_simd; 2027 unsigned max_tile_pipes; 2028 unsigned max_simds_per_se; 2029 unsigned max_backends_per_se; 2030 unsigned max_texture_channel_caches; 2031 unsigned max_gprs; 2032 unsigned max_threads; 2033 unsigned max_gs_threads; 2034 unsigned max_stack_entries; 2035 unsigned sx_num_of_sets; 2036 unsigned sx_max_export_size; 2037 unsigned sx_max_export_pos_size; 2038 unsigned sx_max_export_smx_size; 2039 unsigned max_hw_contexts; 2040 unsigned sq_num_cf_insts; 2041 unsigned sc_prim_fifo_size; 2042 unsigned sc_hiz_tile_fifo_size; 2043 unsigned sc_earlyz_tile_fifo_size; 2044 2045 unsigned num_shader_engines; 2046 unsigned num_shader_pipes_per_simd; 2047 unsigned num_tile_pipes; 2048 unsigned num_simds_per_se; 2049 unsigned num_backends_per_se; 2050 unsigned backend_disable_mask_per_asic; 2051 unsigned backend_map; 2052 unsigned num_texture_channel_caches; 2053 unsigned mem_max_burst_length_bytes; 2054 unsigned mem_row_size_in_kb; 2055 unsigned shader_engine_tile_size; 2056 unsigned num_gpus; 2057 unsigned multi_gpu_tile_size; 2058 2059 unsigned tile_config; 2060 }; 2061 2062 struct si_asic { 2063 unsigned max_shader_engines; 2064 unsigned max_tile_pipes; 2065 unsigned max_cu_per_sh; 2066 unsigned max_sh_per_se; 2067 unsigned max_backends_per_se; 2068 unsigned max_texture_channel_caches; 2069 unsigned max_gprs; 2070 unsigned max_gs_threads; 2071 unsigned max_hw_contexts; 2072 unsigned sc_prim_fifo_size_frontend; 2073 unsigned sc_prim_fifo_size_backend; 2074 unsigned sc_hiz_tile_fifo_size; 2075 unsigned sc_earlyz_tile_fifo_size; 2076 2077 unsigned num_tile_pipes; 2078 unsigned backend_enable_mask; 2079 unsigned backend_disable_mask_per_asic; 2080 unsigned backend_map; 2081 unsigned num_texture_channel_caches; 2082 unsigned mem_max_burst_length_bytes; 2083 unsigned mem_row_size_in_kb; 2084 unsigned shader_engine_tile_size; 2085 unsigned num_gpus; 2086 unsigned multi_gpu_tile_size; 2087 2088 unsigned tile_config; 2089 uint32_t tile_mode_array[32]; 2090 }; 2091 2092 struct cik_asic { 2093 unsigned max_shader_engines; 2094 unsigned max_tile_pipes; 2095 unsigned max_cu_per_sh; 2096 unsigned max_sh_per_se; 2097 unsigned max_backends_per_se; 2098 unsigned max_texture_channel_caches; 2099 unsigned max_gprs; 2100 unsigned max_gs_threads; 2101 unsigned max_hw_contexts; 2102 unsigned sc_prim_fifo_size_frontend; 2103 unsigned sc_prim_fifo_size_backend; 2104 unsigned sc_hiz_tile_fifo_size; 2105 unsigned sc_earlyz_tile_fifo_size; 2106 2107 unsigned num_tile_pipes; 2108 unsigned backend_enable_mask; 2109 unsigned backend_disable_mask_per_asic; 2110 unsigned backend_map; 2111 unsigned num_texture_channel_caches; 2112 unsigned mem_max_burst_length_bytes; 2113 unsigned mem_row_size_in_kb; 2114 unsigned shader_engine_tile_size; 2115 unsigned num_gpus; 2116 unsigned multi_gpu_tile_size; 2117 2118 unsigned tile_config; 2119 uint32_t tile_mode_array[32]; 2120 uint32_t macrotile_mode_array[16]; 2121 }; 2122 2123 union radeon_asic_config { 2124 struct r300_asic r300; 2125 struct r100_asic r100; 2126 struct r600_asic r600; 2127 struct rv770_asic rv770; 2128 struct evergreen_asic evergreen; 2129 struct cayman_asic cayman; 2130 struct si_asic si; 2131 struct cik_asic cik; 2132 }; 2133 2134 /* 2135 * asic initizalization from radeon_asic.c 2136 */ 2137 void radeon_agp_disable(struct radeon_device *rdev); 2138 int radeon_asic_init(struct radeon_device *rdev); 2139 2140 2141 /* 2142 * IOCTL. 2143 */ 2144 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2145 struct drm_file *filp); 2146 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2147 struct drm_file *filp); 2148 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2149 struct drm_file *file_priv); 2150 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2151 struct drm_file *file_priv); 2152 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2153 struct drm_file *file_priv); 2154 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2155 struct drm_file *file_priv); 2156 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2157 struct drm_file *filp); 2158 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2159 struct drm_file *filp); 2160 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2161 struct drm_file *filp); 2162 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *filp); 2164 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *filp); 2166 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *filp); 2168 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2169 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2170 struct drm_file *filp); 2171 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2172 struct drm_file *filp); 2173 2174 /* VRAM scratch page for HDP bug, default vram page */ 2175 struct r600_vram_scratch { 2176 struct radeon_bo *robj; 2177 volatile uint32_t *ptr; 2178 u64 gpu_addr; 2179 }; 2180 2181 /* 2182 * ACPI 2183 */ 2184 struct radeon_atif_notification_cfg { 2185 bool enabled; 2186 int command_code; 2187 }; 2188 2189 struct radeon_atif_notifications { 2190 bool display_switch; 2191 bool expansion_mode_change; 2192 bool thermal_state; 2193 bool forced_power_state; 2194 bool system_power_state; 2195 bool display_conf_change; 2196 bool px_gfx_switch; 2197 bool brightness_change; 2198 bool dgpu_display_event; 2199 }; 2200 2201 struct radeon_atif_functions { 2202 bool system_params; 2203 bool sbios_requests; 2204 bool select_active_disp; 2205 bool lid_state; 2206 bool get_tv_standard; 2207 bool set_tv_standard; 2208 bool get_panel_expansion_mode; 2209 bool set_panel_expansion_mode; 2210 bool temperature_change; 2211 bool graphics_device_types; 2212 }; 2213 2214 struct radeon_atif { 2215 struct radeon_atif_notifications notifications; 2216 struct radeon_atif_functions functions; 2217 struct radeon_atif_notification_cfg notification_cfg; 2218 struct radeon_encoder *encoder_for_bl; 2219 }; 2220 2221 struct radeon_atcs_functions { 2222 bool get_ext_state; 2223 bool pcie_perf_req; 2224 bool pcie_dev_rdy; 2225 bool pcie_bus_width; 2226 }; 2227 2228 struct radeon_atcs { 2229 struct radeon_atcs_functions functions; 2230 }; 2231 2232 /* 2233 * Core structure, functions and helpers. 2234 */ 2235 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2236 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2237 2238 struct radeon_device { 2239 struct device *dev; 2240 struct drm_device *ddev; 2241 struct pci_dev *pdev; 2242 struct rw_semaphore exclusive_lock; 2243 /* ASIC */ 2244 union radeon_asic_config config; 2245 enum radeon_family family; 2246 unsigned long flags; 2247 int usec_timeout; 2248 enum radeon_pll_errata pll_errata; 2249 int num_gb_pipes; 2250 int num_z_pipes; 2251 int disp_priority; 2252 /* BIOS */ 2253 uint8_t *bios; 2254 bool is_atom_bios; 2255 uint16_t bios_header_start; 2256 struct radeon_bo *stollen_vga_memory; 2257 /* Register mmio */ 2258 #ifndef __NetBSD__ 2259 resource_size_t rmmio_base; 2260 resource_size_t rmmio_size; 2261 #endif 2262 /* protects concurrent MM_INDEX/DATA based register access */ 2263 spinlock_t mmio_idx_lock; 2264 /* protects concurrent SMC based register access */ 2265 spinlock_t smc_idx_lock; 2266 /* protects concurrent PLL register access */ 2267 spinlock_t pll_idx_lock; 2268 /* protects concurrent MC register access */ 2269 spinlock_t mc_idx_lock; 2270 /* protects concurrent PCIE register access */ 2271 spinlock_t pcie_idx_lock; 2272 /* protects concurrent PCIE_PORT register access */ 2273 spinlock_t pciep_idx_lock; 2274 /* protects concurrent PIF register access */ 2275 spinlock_t pif_idx_lock; 2276 /* protects concurrent CG register access */ 2277 spinlock_t cg_idx_lock; 2278 /* protects concurrent UVD register access */ 2279 spinlock_t uvd_idx_lock; 2280 /* protects concurrent RCU register access */ 2281 spinlock_t rcu_idx_lock; 2282 /* protects concurrent DIDT register access */ 2283 spinlock_t didt_idx_lock; 2284 /* protects concurrent ENDPOINT (audio) register access */ 2285 spinlock_t end_idx_lock; 2286 #ifdef __NetBSD__ 2287 bus_space_tag_t rmmio_bst; 2288 bus_space_handle_t rmmio_bsh; 2289 bus_addr_t rmmio_addr; 2290 bus_size_t rmmio_size; 2291 #else 2292 void __iomem *rmmio; 2293 #endif 2294 radeon_rreg_t mc_rreg; 2295 radeon_wreg_t mc_wreg; 2296 radeon_rreg_t pll_rreg; 2297 radeon_wreg_t pll_wreg; 2298 uint32_t pcie_reg_mask; 2299 radeon_rreg_t pciep_rreg; 2300 radeon_wreg_t pciep_wreg; 2301 /* io port */ 2302 #ifdef __NetBSD__ 2303 bus_space_tag_t rio_mem_bst; 2304 bus_space_handle_t rio_mem_bsh; 2305 bus_size_t rio_mem_size; 2306 #else 2307 void __iomem *rio_mem; 2308 resource_size_t rio_mem_size; 2309 #endif 2310 struct radeon_clock clock; 2311 struct radeon_mc mc; 2312 struct radeon_gart gart; 2313 struct radeon_mode_info mode_info; 2314 struct radeon_scratch scratch; 2315 struct radeon_doorbell doorbell; 2316 struct radeon_mman mman; 2317 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2318 #ifdef __NetBSD__ 2319 spinlock_t fence_lock; 2320 drm_waitqueue_t fence_queue; 2321 #else 2322 wait_queue_head_t fence_queue; 2323 #endif 2324 struct mutex ring_lock; 2325 struct radeon_ring ring[RADEON_NUM_RINGS]; 2326 bool ib_pool_ready; 2327 struct radeon_sa_manager ring_tmp_bo; 2328 struct radeon_irq irq; 2329 struct radeon_asic *asic; 2330 struct radeon_gem gem; 2331 struct radeon_pm pm; 2332 struct radeon_uvd uvd; 2333 struct radeon_vce vce; 2334 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2335 struct radeon_wb wb; 2336 struct radeon_dummy_page dummy_page; 2337 bool shutdown; 2338 bool suspend; 2339 bool need_dma32; 2340 bool accel_working; 2341 bool fastfb_working; /* IGP feature*/ 2342 bool needs_reset; 2343 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2344 const struct firmware *me_fw; /* all family ME firmware */ 2345 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2346 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2347 const struct firmware *mc_fw; /* NI MC firmware */ 2348 const struct firmware *ce_fw; /* SI CE firmware */ 2349 const struct firmware *mec_fw; /* CIK MEC firmware */ 2350 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2351 const struct firmware *smc_fw; /* SMC firmware */ 2352 const struct firmware *uvd_fw; /* UVD firmware */ 2353 const struct firmware *vce_fw; /* VCE firmware */ 2354 struct r600_vram_scratch vram_scratch; 2355 int msi_enabled; /* msi enabled */ 2356 struct r600_ih ih; /* r6/700 interrupt ring */ 2357 struct radeon_rlc rlc; 2358 struct radeon_mec mec; 2359 struct work_struct hotplug_work; 2360 struct work_struct audio_work; 2361 struct work_struct reset_work; 2362 int num_crtc; /* number of crtcs */ 2363 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2364 bool has_uvd; 2365 struct r600_audio audio; /* audio stuff */ 2366 struct notifier_block acpi_nb; 2367 /* only one userspace can use Hyperz features or CMASK at a time */ 2368 struct drm_file *hyperz_filp; 2369 struct drm_file *cmask_filp; 2370 /* i2c buses */ 2371 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2372 /* debugfs */ 2373 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2374 unsigned debugfs_count; 2375 /* virtual memory */ 2376 struct radeon_vm_manager vm_manager; 2377 struct mutex gpu_clock_mutex; 2378 /* memory stats */ 2379 atomic64_t vram_usage; 2380 atomic64_t gtt_usage; 2381 atomic64_t num_bytes_moved; 2382 /* ACPI interface */ 2383 struct radeon_atif atif; 2384 struct radeon_atcs atcs; 2385 /* srbm instance registers */ 2386 struct mutex srbm_mutex; 2387 /* clock, powergating flags */ 2388 u32 cg_flags; 2389 u32 pg_flags; 2390 2391 struct dev_pm_domain vga_pm_domain; 2392 bool have_disp_power_ref; 2393 }; 2394 2395 bool radeon_is_px(struct drm_device *dev); 2396 int radeon_device_init(struct radeon_device *rdev, 2397 struct drm_device *ddev, 2398 struct pci_dev *pdev, 2399 uint32_t flags); 2400 void radeon_device_fini(struct radeon_device *rdev); 2401 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2402 2403 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2404 bool always_indirect); 2405 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2406 bool always_indirect); 2407 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2408 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2409 2410 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2411 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2412 2413 /* 2414 * Cast helper 2415 */ 2416 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2417 2418 /* 2419 * Registers read & write functions. 2420 */ 2421 #ifdef __NetBSD__ 2422 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2423 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2424 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2425 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2426 #else 2427 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2428 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2429 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2430 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2431 #endif 2432 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2433 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2434 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2435 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2436 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2437 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2438 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2439 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2440 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2441 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2442 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2443 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2444 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2445 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2446 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2447 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2448 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2449 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2450 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2451 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2452 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2453 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2454 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2455 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2456 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2457 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2458 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2459 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2460 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2461 #define WREG32_P(reg, val, mask) \ 2462 do { \ 2463 uint32_t tmp_ = RREG32(reg); \ 2464 tmp_ &= (mask); \ 2465 tmp_ |= ((val) & ~(mask)); \ 2466 WREG32(reg, tmp_); \ 2467 } while (0) 2468 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2469 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2470 #define WREG32_PLL_P(reg, val, mask) \ 2471 do { \ 2472 uint32_t tmp_ = RREG32_PLL(reg); \ 2473 tmp_ &= (mask); \ 2474 tmp_ |= ((val) & ~(mask)); \ 2475 WREG32_PLL(reg, tmp_); \ 2476 } while (0) 2477 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2478 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2479 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2480 2481 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2482 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2483 2484 /* 2485 * Indirect registers accessor 2486 */ 2487 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2488 { 2489 unsigned long flags; 2490 uint32_t r; 2491 2492 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2493 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2494 r = RREG32(RADEON_PCIE_DATA); 2495 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2496 return r; 2497 } 2498 2499 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2500 { 2501 unsigned long flags; 2502 2503 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2504 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2505 WREG32(RADEON_PCIE_DATA, (v)); 2506 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2507 } 2508 2509 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2510 { 2511 unsigned long flags; 2512 u32 r; 2513 2514 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2515 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2516 r = RREG32(TN_SMC_IND_DATA_0); 2517 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2518 return r; 2519 } 2520 2521 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2522 { 2523 unsigned long flags; 2524 2525 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2526 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2527 WREG32(TN_SMC_IND_DATA_0, (v)); 2528 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2529 } 2530 2531 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2532 { 2533 unsigned long flags; 2534 u32 r; 2535 2536 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2537 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2538 r = RREG32(R600_RCU_DATA); 2539 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2540 return r; 2541 } 2542 2543 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2544 { 2545 unsigned long flags; 2546 2547 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2548 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2549 WREG32(R600_RCU_DATA, (v)); 2550 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2551 } 2552 2553 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2554 { 2555 unsigned long flags; 2556 u32 r; 2557 2558 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2559 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2560 r = RREG32(EVERGREEN_CG_IND_DATA); 2561 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2562 return r; 2563 } 2564 2565 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2566 { 2567 unsigned long flags; 2568 2569 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2570 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2571 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2572 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2573 } 2574 2575 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2576 { 2577 unsigned long flags; 2578 u32 r; 2579 2580 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2581 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2582 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2583 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2584 return r; 2585 } 2586 2587 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2588 { 2589 unsigned long flags; 2590 2591 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2592 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2593 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2594 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2595 } 2596 2597 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2598 { 2599 unsigned long flags; 2600 u32 r; 2601 2602 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2603 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2604 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2605 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2606 return r; 2607 } 2608 2609 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2610 { 2611 unsigned long flags; 2612 2613 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2614 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2615 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2616 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2617 } 2618 2619 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2620 { 2621 unsigned long flags; 2622 u32 r; 2623 2624 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2625 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2626 r = RREG32(R600_UVD_CTX_DATA); 2627 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2628 return r; 2629 } 2630 2631 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2632 { 2633 unsigned long flags; 2634 2635 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2636 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2637 WREG32(R600_UVD_CTX_DATA, (v)); 2638 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2639 } 2640 2641 2642 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2643 { 2644 unsigned long flags; 2645 u32 r; 2646 2647 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2648 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2649 r = RREG32(CIK_DIDT_IND_DATA); 2650 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2651 return r; 2652 } 2653 2654 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2655 { 2656 unsigned long flags; 2657 2658 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2659 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2660 WREG32(CIK_DIDT_IND_DATA, (v)); 2661 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2662 } 2663 2664 void r100_pll_errata_after_index(struct radeon_device *rdev); 2665 2666 2667 /* 2668 * ASICs helpers. 2669 */ 2670 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2671 (rdev->pdev->device == 0x5969)) 2672 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2673 (rdev->family == CHIP_RV200) || \ 2674 (rdev->family == CHIP_RS100) || \ 2675 (rdev->family == CHIP_RS200) || \ 2676 (rdev->family == CHIP_RV250) || \ 2677 (rdev->family == CHIP_RV280) || \ 2678 (rdev->family == CHIP_RS300)) 2679 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2680 (rdev->family == CHIP_RV350) || \ 2681 (rdev->family == CHIP_R350) || \ 2682 (rdev->family == CHIP_RV380) || \ 2683 (rdev->family == CHIP_R420) || \ 2684 (rdev->family == CHIP_R423) || \ 2685 (rdev->family == CHIP_RV410) || \ 2686 (rdev->family == CHIP_RS400) || \ 2687 (rdev->family == CHIP_RS480)) 2688 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2689 (rdev->ddev->pdev->device == 0x9443) || \ 2690 (rdev->ddev->pdev->device == 0x944B) || \ 2691 (rdev->ddev->pdev->device == 0x9506) || \ 2692 (rdev->ddev->pdev->device == 0x9509) || \ 2693 (rdev->ddev->pdev->device == 0x950F) || \ 2694 (rdev->ddev->pdev->device == 0x689C) || \ 2695 (rdev->ddev->pdev->device == 0x689D)) 2696 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2697 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2698 (rdev->family == CHIP_RS690) || \ 2699 (rdev->family == CHIP_RS740) || \ 2700 (rdev->family >= CHIP_R600)) 2701 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2702 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2703 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2704 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2705 (rdev->flags & RADEON_IS_IGP)) 2706 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2707 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2708 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2709 (rdev->flags & RADEON_IS_IGP)) 2710 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2711 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2712 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2713 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2714 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2715 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2716 (rdev->family == CHIP_MULLINS)) 2717 2718 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2719 (rdev->ddev->pdev->device == 0x6850) || \ 2720 (rdev->ddev->pdev->device == 0x6858) || \ 2721 (rdev->ddev->pdev->device == 0x6859) || \ 2722 (rdev->ddev->pdev->device == 0x6840) || \ 2723 (rdev->ddev->pdev->device == 0x6841) || \ 2724 (rdev->ddev->pdev->device == 0x6842) || \ 2725 (rdev->ddev->pdev->device == 0x6843)) 2726 2727 /* 2728 * BIOS helpers. 2729 */ 2730 #define RBIOS8(i) (rdev->bios[i]) 2731 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2732 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2733 2734 int radeon_combios_init(struct radeon_device *rdev); 2735 void radeon_combios_fini(struct radeon_device *rdev); 2736 int radeon_atombios_init(struct radeon_device *rdev); 2737 void radeon_atombios_fini(struct radeon_device *rdev); 2738 2739 2740 /* 2741 * RING helpers. 2742 */ 2743 #if DRM_DEBUG_CODE == 0 2744 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2745 { 2746 ring->ring[ring->wptr++] = v; 2747 ring->wptr &= ring->ptr_mask; 2748 ring->count_dw--; 2749 ring->ring_free_dw--; 2750 } 2751 #else 2752 /* With debugging this is just too big to inline */ 2753 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2754 #endif 2755 2756 /* 2757 * ASICs macro. 2758 */ 2759 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2760 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2761 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2762 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2763 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2764 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2765 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2766 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2767 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 2768 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2769 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2770 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2771 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2772 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2773 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2774 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2775 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2776 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2777 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2778 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2779 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2780 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2781 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2782 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2783 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2784 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2785 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2786 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2787 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2788 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2789 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2790 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2791 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2792 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2793 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2794 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2795 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2796 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2797 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2798 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2799 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2800 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2801 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2802 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2803 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2804 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2805 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2806 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2807 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2808 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2809 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2810 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2811 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2812 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2813 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2814 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2815 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2816 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2817 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2818 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2819 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 2820 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2821 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 2822 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2823 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2824 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2825 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2826 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2827 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2828 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2829 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2830 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2831 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2832 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2833 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2834 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2835 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2836 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2837 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2838 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2839 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2840 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2841 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2842 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2843 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2844 2845 /* Common functions */ 2846 /* AGP */ 2847 extern int radeon_gpu_reset(struct radeon_device *rdev); 2848 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2849 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2850 extern void radeon_agp_disable(struct radeon_device *rdev); 2851 extern int radeon_modeset_init(struct radeon_device *rdev); 2852 extern void radeon_modeset_fini(struct radeon_device *rdev); 2853 extern bool radeon_card_posted(struct radeon_device *rdev); 2854 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2855 extern void radeon_update_display_priority(struct radeon_device *rdev); 2856 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2857 extern void radeon_scratch_init(struct radeon_device *rdev); 2858 extern void radeon_wb_fini(struct radeon_device *rdev); 2859 extern int radeon_wb_init(struct radeon_device *rdev); 2860 extern void radeon_wb_disable(struct radeon_device *rdev); 2861 extern void radeon_surface_init(struct radeon_device *rdev); 2862 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2863 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2864 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2865 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2866 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2867 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2868 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2869 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2870 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2871 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2872 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2873 const u32 *registers, 2874 const u32 array_size); 2875 2876 /* 2877 * vm 2878 */ 2879 int radeon_vm_manager_init(struct radeon_device *rdev); 2880 void radeon_vm_manager_fini(struct radeon_device *rdev); 2881 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2882 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2883 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2884 struct radeon_vm *vm, 2885 struct list_head *head); 2886 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2887 struct radeon_vm *vm, int ring); 2888 void radeon_vm_flush(struct radeon_device *rdev, 2889 struct radeon_vm *vm, 2890 int ring); 2891 void radeon_vm_fence(struct radeon_device *rdev, 2892 struct radeon_vm *vm, 2893 struct radeon_fence *fence); 2894 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2895 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2896 struct radeon_vm *vm); 2897 int radeon_vm_bo_update(struct radeon_device *rdev, 2898 struct radeon_vm *vm, 2899 struct radeon_bo *bo, 2900 struct ttm_mem_reg *mem); 2901 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2902 struct radeon_bo *bo); 2903 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2904 struct radeon_bo *bo); 2905 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2906 struct radeon_vm *vm, 2907 struct radeon_bo *bo); 2908 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2909 struct radeon_bo_va *bo_va, 2910 uint64_t offset, 2911 uint32_t flags); 2912 int radeon_vm_bo_rmv(struct radeon_device *rdev, 2913 struct radeon_bo_va *bo_va); 2914 2915 /* audio */ 2916 void r600_audio_update_hdmi(struct work_struct *work); 2917 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2918 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2919 void r600_audio_enable(struct radeon_device *rdev, 2920 struct r600_audio_pin *pin, 2921 bool enable); 2922 void dce6_audio_enable(struct radeon_device *rdev, 2923 struct r600_audio_pin *pin, 2924 bool enable); 2925 2926 /* 2927 * R600 vram scratch functions 2928 */ 2929 int r600_vram_scratch_init(struct radeon_device *rdev); 2930 void r600_vram_scratch_fini(struct radeon_device *rdev); 2931 2932 /* 2933 * r600 cs checking helper 2934 */ 2935 unsigned r600_mip_minify(unsigned size, unsigned level); 2936 bool r600_fmt_is_valid_color(u32 format); 2937 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2938 int r600_fmt_get_blocksize(u32 format); 2939 int r600_fmt_get_nblocksx(u32 format, u32 w); 2940 int r600_fmt_get_nblocksy(u32 format, u32 h); 2941 2942 /* 2943 * r600 functions used by radeon_encoder.c 2944 */ 2945 struct radeon_hdmi_acr { 2946 u32 clock; 2947 2948 int n_32khz; 2949 int cts_32khz; 2950 2951 int n_44_1khz; 2952 int cts_44_1khz; 2953 2954 int n_48khz; 2955 int cts_48khz; 2956 2957 }; 2958 2959 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2960 2961 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2962 u32 tiling_pipe_num, 2963 u32 max_rb_num, 2964 u32 total_max_rb_num, 2965 u32 enabled_rb_mask); 2966 2967 /* 2968 * evergreen functions used by radeon_encoder.c 2969 */ 2970 2971 extern int ni_init_microcode(struct radeon_device *rdev); 2972 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2973 2974 /* radeon_acpi.c */ 2975 #if defined(CONFIG_ACPI) 2976 extern int radeon_acpi_init(struct radeon_device *rdev); 2977 extern void radeon_acpi_fini(struct radeon_device *rdev); 2978 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2979 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2980 u8 perf_req, bool advertise); 2981 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2982 #else 2983 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2984 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2985 #endif 2986 2987 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2988 struct radeon_cs_packet *pkt, 2989 unsigned idx); 2990 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2991 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2992 struct radeon_cs_packet *pkt); 2993 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2994 struct radeon_cs_reloc **cs_reloc, 2995 int nomm); 2996 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2997 uint32_t *vline_start_end, 2998 uint32_t *vline_status); 2999 3000 #include "radeon_object.h" 3001 3002 #endif 3003
Indexes created Wed Oct 01 07:09:59 GMT 2025