radeon.h revision 1.4
1 /* $NetBSD: radeon.h,v 1.4 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <asm/byteorder.h> 66 #include <linux/atomic.h> 67 #include <linux/wait.h> 68 #include <linux/list.h> 69 #include <linux/kref.h> 70 #include <linux/interval_tree.h> 71 #include <linux/hashtable.h> 72 #include <linux/fence.h> 73 #include <linux/device.h> 74 #include <linux/log2.h> 75 #include <linux/notifier.h> 76 #include <linux/printk.h> 77 #include <linux/rwsem.h> 78 79 #include <ttm/ttm_bo_api.h> 80 #include <ttm/ttm_bo_driver.h> 81 #include <ttm/ttm_placement.h> 82 #include <ttm/ttm_module.h> 83 #include <ttm/ttm_execbuf_util.h> 84 85 #include <drm/drm_gem.h> 86 87 #include "radeon_family.h" 88 #include "radeon_mode.h" 89 #include "radeon_reg.h" 90 91 /* 92 * Modules parameters. 93 */ 94 extern int radeon_no_wb; 95 extern int radeon_modeset; 96 extern int radeon_dynclks; 97 extern int radeon_r4xx_atom; 98 extern int radeon_agpmode; 99 extern int radeon_vram_limit; 100 extern int radeon_gart_size; 101 extern int radeon_benchmarking; 102 extern int radeon_testing; 103 extern int radeon_connector_table; 104 extern int radeon_tv; 105 extern int radeon_audio; 106 extern int radeon_disp_priority; 107 extern int radeon_hw_i2c; 108 extern int radeon_pcie_gen2; 109 extern int radeon_msi; 110 extern int radeon_lockup_timeout; 111 extern int radeon_fastfb; 112 extern int radeon_dpm; 113 extern int radeon_aspm; 114 extern int radeon_runtime_pm; 115 extern int radeon_hard_reset; 116 extern int radeon_vm_size; 117 extern int radeon_vm_block_size; 118 extern int radeon_deep_color; 119 extern int radeon_use_pflipirq; 120 extern int radeon_bapm; 121 extern int radeon_backlight; 122 extern int radeon_auxch; 123 extern int radeon_mst; 124 125 /* 126 * Copy from radeon_drv.h so we don't have to include both and have conflicting 127 * symbol; 128 */ 129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 130 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 #ifdef __NetBSD__ 246 extern struct radeon_device *radeon_device_private(device_t); 247 #endif 248 249 /* 250 * BIOS. 251 */ 252 bool radeon_get_bios(struct radeon_device *rdev); 253 254 /* 255 * Dummy page 256 */ 257 struct radeon_dummy_page { 258 uint64_t entry; 259 #ifdef __NetBSD__ 260 bus_dma_segment_t rdp_seg; 261 bus_dmamap_t rdp_map; 262 #else 263 struct page *page; 264 #endif 265 dma_addr_t addr; 266 }; 267 int radeon_dummy_page_init(struct radeon_device *rdev); 268 void radeon_dummy_page_fini(struct radeon_device *rdev); 269 270 271 /* 272 * Clocks 273 */ 274 struct radeon_clock { 275 struct radeon_pll p1pll; 276 struct radeon_pll p2pll; 277 struct radeon_pll dcpll; 278 struct radeon_pll spll; 279 struct radeon_pll mpll; 280 /* 10 Khz units */ 281 uint32_t default_mclk; 282 uint32_t default_sclk; 283 uint32_t default_dispclk; 284 uint32_t current_dispclk; 285 uint32_t dp_extclk; 286 uint32_t max_pixel_clock; 287 uint32_t vco_freq; 288 }; 289 290 /* 291 * Power management 292 */ 293 int radeon_pm_init(struct radeon_device *rdev); 294 int radeon_pm_late_init(struct radeon_device *rdev); 295 void radeon_pm_fini(struct radeon_device *rdev); 296 void radeon_pm_compute_clocks(struct radeon_device *rdev); 297 void radeon_pm_suspend(struct radeon_device *rdev); 298 void radeon_pm_resume(struct radeon_device *rdev); 299 void radeon_combios_get_power_modes(struct radeon_device *rdev); 300 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 301 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 302 u8 clock_type, 303 u32 clock, 304 bool strobe_mode, 305 struct atom_clock_dividers *dividers); 306 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 307 u32 clock, 308 bool strobe_mode, 309 struct atom_mpll_param *mpll_param); 310 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 311 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 312 u16 voltage_level, u8 voltage_type, 313 u32 *gpio_value, u32 *gpio_mask); 314 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 315 u32 eng_clock, u32 mem_clock); 316 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 317 u8 voltage_type, u16 *voltage_step); 318 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 319 u16 voltage_id, u16 *voltage); 320 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 321 u16 *voltage, 322 u16 leakage_idx); 323 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 324 u16 *leakage_id); 325 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 326 u16 *vddc, u16 *vddci, 327 u16 virtual_voltage_id, 328 u16 vbios_voltage_id); 329 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 330 u16 virtual_voltage_id, 331 u16 *voltage); 332 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 333 u8 voltage_type, 334 u16 nominal_voltage, 335 u16 *true_voltage); 336 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 337 u8 voltage_type, u16 *min_voltage); 338 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 339 u8 voltage_type, u16 *max_voltage); 340 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 341 u8 voltage_type, u8 voltage_mode, 342 struct atom_voltage_table *voltage_table); 343 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 344 u8 voltage_type, u8 voltage_mode); 345 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 346 u8 voltage_type, 347 u8 *svd_gpio_id, u8 *svc_gpio_id); 348 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 349 u32 mem_clock); 350 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 351 u32 mem_clock); 352 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 353 u8 module_index, 354 struct atom_mc_reg_table *reg_table); 355 int radeon_atom_get_memory_info(struct radeon_device *rdev, 356 u8 module_index, struct atom_memory_info *mem_info); 357 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 358 bool gddr5, u8 module_index, 359 struct atom_memory_clock_range_table *mclk_range_table); 360 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 361 u16 voltage_id, u16 *voltage); 362 void rs690_pm_info(struct radeon_device *rdev); 363 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 364 unsigned *bankh, unsigned *mtaspect, 365 unsigned *tile_split); 366 367 /* 368 * Fences. 369 */ 370 struct radeon_fence_driver { 371 struct radeon_device *rdev; 372 uint32_t scratch_reg; 373 uint64_t gpu_addr; 374 volatile uint32_t *cpu_addr; 375 /* sync_seq is protected by ring emission lock */ 376 uint64_t sync_seq[RADEON_NUM_RINGS]; 377 atomic64_t last_seq; 378 bool initialized, delayed_irq; 379 struct delayed_work lockup_work; 380 }; 381 382 struct radeon_fence { 383 struct fence base; 384 385 struct radeon_device *rdev; 386 uint64_t seq; 387 /* RB, DMA, etc. */ 388 unsigned ring; 389 bool is_vm_update; 390 391 #ifdef __NetBSD__ 392 TAILQ_ENTRY(radeon_fence) fence_check; 393 #else 394 wait_queue_t fence_wake; 395 #endif 396 }; 397 398 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 399 int radeon_fence_driver_init(struct radeon_device *rdev); 400 void radeon_fence_driver_fini(struct radeon_device *rdev); 401 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 402 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 403 void radeon_fence_process(struct radeon_device *rdev, int ring); 404 bool radeon_fence_signaled(struct radeon_fence *fence); 405 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 406 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 407 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 408 int radeon_fence_wait_any(struct radeon_device *rdev, 409 struct radeon_fence **fences, 410 bool intr); 411 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 412 void radeon_fence_unref(struct radeon_fence **fence); 413 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 414 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 415 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 416 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 417 struct radeon_fence *b) 418 { 419 if (!a) { 420 return b; 421 } 422 423 if (!b) { 424 return a; 425 } 426 427 BUG_ON(a->ring != b->ring); 428 429 if (a->seq > b->seq) { 430 return a; 431 } else { 432 return b; 433 } 434 } 435 436 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 437 struct radeon_fence *b) 438 { 439 if (!a) { 440 return false; 441 } 442 443 if (!b) { 444 return true; 445 } 446 447 BUG_ON(a->ring != b->ring); 448 449 return a->seq < b->seq; 450 } 451 452 /* 453 * Tiling registers 454 */ 455 struct radeon_surface_reg { 456 struct radeon_bo *bo; 457 }; 458 459 #define RADEON_GEM_MAX_SURFACES 8 460 461 /* 462 * TTM. 463 */ 464 struct radeon_mman { 465 struct ttm_bo_global_ref bo_global_ref; 466 struct drm_global_reference mem_global_ref; 467 struct ttm_bo_device bdev; 468 bool mem_global_referenced; 469 bool initialized; 470 471 #if defined(CONFIG_DEBUG_FS) 472 struct dentry *vram; 473 struct dentry *gtt; 474 #endif 475 }; 476 477 struct radeon_bo_list { 478 struct radeon_bo *robj; 479 struct ttm_validate_buffer tv; 480 uint64_t gpu_offset; 481 unsigned prefered_domains; 482 unsigned allowed_domains; 483 uint32_t tiling_flags; 484 }; 485 486 /* bo virtual address in a specific vm */ 487 struct radeon_bo_va { 488 /* protected by bo being reserved */ 489 struct list_head bo_list; 490 uint32_t flags; 491 struct radeon_fence *last_pt_update; 492 unsigned ref_count; 493 494 /* protected by vm mutex */ 495 struct interval_tree_node it; 496 struct list_head vm_status; 497 498 /* constant after initialization */ 499 struct radeon_vm *vm; 500 struct radeon_bo *bo; 501 }; 502 503 struct radeon_bo { 504 /* Protected by gem.mutex */ 505 struct list_head list; 506 /* Protected by tbo.reserved */ 507 u32 initial_domain; 508 struct ttm_place placements[4]; 509 struct ttm_placement placement; 510 struct ttm_buffer_object tbo; 511 struct ttm_bo_kmap_obj kmap; 512 u32 flags; 513 unsigned pin_count; 514 void *kptr; 515 u32 tiling_flags; 516 u32 pitch; 517 int surface_reg; 518 /* list of all virtual address to which this bo 519 * is associated to 520 */ 521 struct list_head va; 522 /* Constant after initialization */ 523 struct radeon_device *rdev; 524 struct drm_gem_object gem_base; 525 526 struct ttm_bo_kmap_obj dma_buf_vmap; 527 #ifndef __NetBSD__ /* XXX pid??? */ 528 pid_t pid; 529 #endif 530 531 struct radeon_mn *mn; 532 struct list_head mn_list; 533 }; 534 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 535 536 int radeon_gem_debugfs_init(struct radeon_device *rdev); 537 538 /* sub-allocation manager, it has to be protected by another lock. 539 * By conception this is an helper for other part of the driver 540 * like the indirect buffer or semaphore, which both have their 541 * locking. 542 * 543 * Principe is simple, we keep a list of sub allocation in offset 544 * order (first entry has offset == 0, last entry has the highest 545 * offset). 546 * 547 * When allocating new object we first check if there is room at 548 * the end total_size - (last_object_offset + last_object_size) >= 549 * alloc_size. If so we allocate new object there. 550 * 551 * When there is not enough room at the end, we start waiting for 552 * each sub object until we reach object_offset+object_size >= 553 * alloc_size, this object then become the sub object we return. 554 * 555 * Alignment can't be bigger than page size. 556 * 557 * Hole are not considered for allocation to keep things simple. 558 * Assumption is that there won't be hole (all object on same 559 * alignment). 560 */ 561 struct radeon_sa_manager { 562 #ifdef __NetBSD__ 563 spinlock_t wq_lock; 564 drm_waitqueue_t wq; 565 #else 566 wait_queue_head_t wq; 567 #endif 568 struct radeon_bo *bo; 569 struct list_head *hole; 570 struct list_head flist[RADEON_NUM_RINGS]; 571 struct list_head olist; 572 unsigned size; 573 uint64_t gpu_addr; 574 void *cpu_ptr; 575 uint32_t domain; 576 uint32_t align; 577 }; 578 579 struct radeon_sa_bo; 580 581 /* sub-allocation buffer */ 582 struct radeon_sa_bo { 583 struct list_head olist; 584 struct list_head flist; 585 struct radeon_sa_manager *manager; 586 unsigned soffset; 587 unsigned eoffset; 588 struct radeon_fence *fence; 589 }; 590 591 /* 592 * GEM objects. 593 */ 594 struct radeon_gem { 595 struct mutex mutex; 596 struct list_head objects; 597 }; 598 599 int radeon_gem_init(struct radeon_device *rdev); 600 void radeon_gem_fini(struct radeon_device *rdev); 601 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 602 int alignment, int initial_domain, 603 u32 flags, bool kernel, 604 struct drm_gem_object **obj); 605 606 int radeon_mode_dumb_create(struct drm_file *file_priv, 607 struct drm_device *dev, 608 struct drm_mode_create_dumb *args); 609 int radeon_mode_dumb_mmap(struct drm_file *filp, 610 struct drm_device *dev, 611 uint32_t handle, uint64_t *offset_p); 612 613 /* 614 * Semaphores. 615 */ 616 struct radeon_semaphore { 617 struct radeon_sa_bo *sa_bo; 618 signed waiters; 619 uint64_t gpu_addr; 620 }; 621 622 int radeon_semaphore_create(struct radeon_device *rdev, 623 struct radeon_semaphore **semaphore); 624 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 625 struct radeon_semaphore *semaphore); 626 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 627 struct radeon_semaphore *semaphore); 628 void radeon_semaphore_free(struct radeon_device *rdev, 629 struct radeon_semaphore **semaphore, 630 struct radeon_fence *fence); 631 632 /* 633 * Synchronization 634 */ 635 struct radeon_sync { 636 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 637 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 638 struct radeon_fence *last_vm_update; 639 }; 640 641 void radeon_sync_create(struct radeon_sync *sync); 642 void radeon_sync_fence(struct radeon_sync *sync, 643 struct radeon_fence *fence); 644 int radeon_sync_resv(struct radeon_device *rdev, 645 struct radeon_sync *sync, 646 struct reservation_object *resv, 647 bool shared); 648 int radeon_sync_rings(struct radeon_device *rdev, 649 struct radeon_sync *sync, 650 int waiting_ring); 651 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 652 struct radeon_fence *fence); 653 654 /* 655 * GART structures, functions & helpers 656 */ 657 struct radeon_mc; 658 659 #define RADEON_GPU_PAGE_SIZE 4096 660 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 661 #define RADEON_GPU_PAGE_SHIFT 12 662 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 663 664 #define RADEON_GART_PAGE_DUMMY 0 665 #define RADEON_GART_PAGE_VALID (1 << 0) 666 #define RADEON_GART_PAGE_READ (1 << 1) 667 #define RADEON_GART_PAGE_WRITE (1 << 2) 668 #define RADEON_GART_PAGE_SNOOP (1 << 3) 669 670 struct radeon_gart { 671 #ifdef __NetBSD__ 672 bus_dma_segment_t rg_table_seg; 673 bus_dmamap_t rg_table_map; 674 #endif 675 dma_addr_t table_addr; 676 struct radeon_bo *robj; 677 void *ptr; 678 unsigned num_gpu_pages; 679 unsigned num_cpu_pages; 680 unsigned table_size; 681 struct page **pages; 682 uint64_t *pages_entry; 683 bool ready; 684 }; 685 686 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 687 void radeon_gart_table_ram_free(struct radeon_device *rdev); 688 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 689 void radeon_gart_table_vram_free(struct radeon_device *rdev); 690 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 691 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 692 int radeon_gart_init(struct radeon_device *rdev); 693 void radeon_gart_fini(struct radeon_device *rdev); 694 #ifdef __NetBSD__ 695 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 696 unsigned npages); 697 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 698 unsigned npages, struct page **pages, 699 bus_dmamap_t dmamap, uint32_t flags); 700 #else 701 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 702 int pages); 703 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 704 int pages, struct page **pagelist, 705 dma_addr_t *dma_addr, uint32_t flags); 706 #endif 707 708 709 /* 710 * GPU MC structures, functions & helpers 711 */ 712 struct radeon_mc { 713 resource_size_t aper_size; 714 resource_size_t aper_base; 715 resource_size_t agp_base; 716 /* for some chips with <= 32MB we need to lie 717 * about vram size near mc fb location */ 718 u64 mc_vram_size; 719 u64 visible_vram_size; 720 u64 gtt_size; 721 u64 gtt_start; 722 u64 gtt_end; 723 u64 vram_start; 724 u64 vram_end; 725 unsigned vram_width; 726 u64 real_vram_size; 727 int vram_mtrr; 728 bool vram_is_ddr; 729 bool igp_sideport_enabled; 730 u64 gtt_base_align; 731 u64 mc_mask; 732 }; 733 734 bool radeon_combios_sideport_present(struct radeon_device *rdev); 735 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 736 737 /* 738 * GPU scratch registers structures, functions & helpers 739 */ 740 struct radeon_scratch { 741 unsigned num_reg; 742 uint32_t reg_base; 743 bool free[32]; 744 uint32_t reg[32]; 745 }; 746 747 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 748 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 749 750 /* 751 * GPU doorbell structures, functions & helpers 752 */ 753 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 754 755 struct radeon_doorbell { 756 /* doorbell mmio */ 757 resource_size_t base; 758 resource_size_t size; 759 #ifdef __NetBSD__ 760 bus_space_tag_t bst; 761 bus_space_handle_t bsh; 762 #else 763 u32 __iomem *ptr; 764 #endif 765 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 766 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 767 }; 768 769 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 770 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 771 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 772 phys_addr_t *aperture_base, 773 size_t *aperture_size, 774 size_t *start_offset); 775 776 /* 777 * IRQS. 778 */ 779 780 struct radeon_flip_work { 781 struct work_struct flip_work; 782 struct work_struct unpin_work; 783 struct radeon_device *rdev; 784 int crtc_id; 785 uint64_t base; 786 struct drm_pending_vblank_event *event; 787 struct radeon_bo *old_rbo; 788 struct fence *fence; 789 }; 790 791 struct r500_irq_stat_regs { 792 u32 disp_int; 793 u32 hdmi0_status; 794 }; 795 796 struct r600_irq_stat_regs { 797 u32 disp_int; 798 u32 disp_int_cont; 799 u32 disp_int_cont2; 800 u32 d1grph_int; 801 u32 d2grph_int; 802 u32 hdmi0_status; 803 u32 hdmi1_status; 804 }; 805 806 struct evergreen_irq_stat_regs { 807 u32 disp_int; 808 u32 disp_int_cont; 809 u32 disp_int_cont2; 810 u32 disp_int_cont3; 811 u32 disp_int_cont4; 812 u32 disp_int_cont5; 813 u32 d1grph_int; 814 u32 d2grph_int; 815 u32 d3grph_int; 816 u32 d4grph_int; 817 u32 d5grph_int; 818 u32 d6grph_int; 819 u32 afmt_status1; 820 u32 afmt_status2; 821 u32 afmt_status3; 822 u32 afmt_status4; 823 u32 afmt_status5; 824 u32 afmt_status6; 825 }; 826 827 struct cik_irq_stat_regs { 828 u32 disp_int; 829 u32 disp_int_cont; 830 u32 disp_int_cont2; 831 u32 disp_int_cont3; 832 u32 disp_int_cont4; 833 u32 disp_int_cont5; 834 u32 disp_int_cont6; 835 u32 d1grph_int; 836 u32 d2grph_int; 837 u32 d3grph_int; 838 u32 d4grph_int; 839 u32 d5grph_int; 840 u32 d6grph_int; 841 }; 842 843 union radeon_irq_stat_regs { 844 struct r500_irq_stat_regs r500; 845 struct r600_irq_stat_regs r600; 846 struct evergreen_irq_stat_regs evergreen; 847 struct cik_irq_stat_regs cik; 848 }; 849 850 struct radeon_irq { 851 bool installed; 852 spinlock_t lock; 853 atomic_t ring_int[RADEON_NUM_RINGS]; 854 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 855 atomic_t pflip[RADEON_MAX_CRTCS]; 856 #ifdef __NetBSD__ 857 spinlock_t vblank_lock; 858 drm_waitqueue_t vblank_queue; 859 #else 860 wait_queue_head_t vblank_queue; 861 #endif 862 bool hpd[RADEON_MAX_HPD_PINS]; 863 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 864 union radeon_irq_stat_regs stat_regs; 865 bool dpm_thermal; 866 }; 867 868 int radeon_irq_kms_init(struct radeon_device *rdev); 869 void radeon_irq_kms_fini(struct radeon_device *rdev); 870 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 871 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 872 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 873 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 874 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 875 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 876 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 877 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 878 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 879 880 /* 881 * CP & rings. 882 */ 883 884 struct radeon_ib { 885 struct radeon_sa_bo *sa_bo; 886 uint32_t length_dw; 887 uint64_t gpu_addr; 888 uint32_t *ptr; 889 int ring; 890 struct radeon_fence *fence; 891 struct radeon_vm *vm; 892 bool is_const_ib; 893 struct radeon_sync sync; 894 }; 895 896 struct radeon_ring { 897 struct radeon_bo *ring_obj; 898 volatile uint32_t *ring; 899 unsigned rptr_offs; 900 unsigned rptr_save_reg; 901 u64 next_rptr_gpu_addr; 902 volatile u32 *next_rptr_cpu_addr; 903 unsigned wptr; 904 unsigned wptr_old; 905 unsigned ring_size; 906 unsigned ring_free_dw; 907 int count_dw; 908 atomic_t last_rptr; 909 atomic64_t last_activity; 910 uint64_t gpu_addr; 911 uint32_t align_mask; 912 uint32_t ptr_mask; 913 bool ready; 914 u32 nop; 915 u32 idx; 916 u64 last_semaphore_signal_addr; 917 u64 last_semaphore_wait_addr; 918 /* for CIK queues */ 919 u32 me; 920 u32 pipe; 921 u32 queue; 922 struct radeon_bo *mqd_obj; 923 u32 doorbell_index; 924 unsigned wptr_offs; 925 }; 926 927 struct radeon_mec { 928 struct radeon_bo *hpd_eop_obj; 929 u64 hpd_eop_gpu_addr; 930 u32 num_pipe; 931 u32 num_mec; 932 u32 num_queue; 933 }; 934 935 /* 936 * VM 937 */ 938 939 /* maximum number of VMIDs */ 940 #define RADEON_NUM_VM 16 941 942 /* number of entries in page table */ 943 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 944 945 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 946 #define RADEON_VM_PTB_ALIGN_SIZE 32768 947 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 948 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 949 950 #define R600_PTE_VALID (1 << 0) 951 #define R600_PTE_SYSTEM (1 << 1) 952 #define R600_PTE_SNOOPED (1 << 2) 953 #define R600_PTE_READABLE (1 << 5) 954 #define R600_PTE_WRITEABLE (1 << 6) 955 956 /* PTE (Page Table Entry) fragment field for different page sizes */ 957 #define R600_PTE_FRAG_4KB (0 << 7) 958 #define R600_PTE_FRAG_64KB (4 << 7) 959 #define R600_PTE_FRAG_256KB (6 << 7) 960 961 /* flags needed to be set so we can copy directly from the GART table */ 962 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 963 R600_PTE_SYSTEM | R600_PTE_VALID ) 964 965 struct radeon_vm_pt { 966 struct radeon_bo *bo; 967 uint64_t addr; 968 }; 969 970 struct radeon_vm_id { 971 unsigned id; 972 uint64_t pd_gpu_addr; 973 /* last flushed PD/PT update */ 974 struct radeon_fence *flushed_updates; 975 /* last use of vmid */ 976 struct radeon_fence *last_id_use; 977 }; 978 979 struct radeon_vm { 980 struct mutex mutex; 981 982 struct rb_root va; 983 984 /* protecting invalidated and freed */ 985 spinlock_t status_lock; 986 987 /* BOs moved, but not yet updated in the PT */ 988 struct list_head invalidated; 989 990 /* BOs freed, but not yet updated in the PT */ 991 struct list_head freed; 992 993 /* BOs cleared in the PT */ 994 struct list_head cleared; 995 996 /* contains the page directory */ 997 struct radeon_bo *page_directory; 998 unsigned max_pde_used; 999 1000 /* array of page tables, one for each page directory entry */ 1001 struct radeon_vm_pt *page_tables; 1002 1003 struct radeon_bo_va *ib_bo_va; 1004 1005 /* for id and flush management per ring */ 1006 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 1007 }; 1008 1009 struct radeon_vm_manager { 1010 struct radeon_fence *active[RADEON_NUM_VM]; 1011 uint32_t max_pfn; 1012 /* number of VMIDs */ 1013 unsigned nvm; 1014 /* vram base address for page table entry */ 1015 u64 vram_base_offset; 1016 /* is vm enabled? */ 1017 bool enabled; 1018 /* for hw to save the PD addr on suspend/resume */ 1019 uint32_t saved_table_addr[RADEON_NUM_VM]; 1020 }; 1021 1022 /* 1023 * file private structure 1024 */ 1025 struct radeon_fpriv { 1026 struct radeon_vm vm; 1027 }; 1028 1029 /* 1030 * R6xx+ IH ring 1031 */ 1032 struct r600_ih { 1033 struct radeon_bo *ring_obj; 1034 volatile uint32_t *ring; 1035 unsigned rptr; 1036 unsigned ring_size; 1037 uint64_t gpu_addr; 1038 uint32_t ptr_mask; 1039 atomic_t lock; 1040 bool enabled; 1041 }; 1042 1043 /* 1044 * RLC stuff 1045 */ 1046 #include "clearstate_defs.h" 1047 1048 struct radeon_rlc { 1049 /* for power gating */ 1050 struct radeon_bo *save_restore_obj; 1051 uint64_t save_restore_gpu_addr; 1052 volatile uint32_t *sr_ptr; 1053 const u32 *reg_list; 1054 u32 reg_list_size; 1055 /* for clear state */ 1056 struct radeon_bo *clear_state_obj; 1057 uint64_t clear_state_gpu_addr; 1058 volatile uint32_t *cs_ptr; 1059 const struct cs_section_def *cs_data; 1060 u32 clear_state_size; 1061 /* for cp tables */ 1062 struct radeon_bo *cp_table_obj; 1063 uint64_t cp_table_gpu_addr; 1064 volatile uint32_t *cp_table_ptr; 1065 u32 cp_table_size; 1066 }; 1067 1068 int radeon_ib_get(struct radeon_device *rdev, int ring, 1069 struct radeon_ib *ib, struct radeon_vm *vm, 1070 unsigned size); 1071 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1072 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1073 struct radeon_ib *const_ib, bool hdp_flush); 1074 int radeon_ib_pool_init(struct radeon_device *rdev); 1075 void radeon_ib_pool_fini(struct radeon_device *rdev); 1076 int radeon_ib_ring_tests(struct radeon_device *rdev); 1077 /* Ring access between begin & end cannot sleep */ 1078 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1079 struct radeon_ring *ring); 1080 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1081 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1082 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1083 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1084 bool hdp_flush); 1085 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1086 bool hdp_flush); 1087 void radeon_ring_undo(struct radeon_ring *ring); 1088 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1089 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1090 void radeon_ring_lockup_update(struct radeon_device *rdev, 1091 struct radeon_ring *ring); 1092 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1093 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1094 uint32_t **data); 1095 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1096 unsigned size, uint32_t *data); 1097 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1098 unsigned rptr_offs, u32 nop); 1099 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1100 1101 1102 /* r600 async dma */ 1103 void r600_dma_stop(struct radeon_device *rdev); 1104 int r600_dma_resume(struct radeon_device *rdev); 1105 void r600_dma_fini(struct radeon_device *rdev); 1106 1107 void cayman_dma_stop(struct radeon_device *rdev); 1108 int cayman_dma_resume(struct radeon_device *rdev); 1109 void cayman_dma_fini(struct radeon_device *rdev); 1110 1111 /* 1112 * CS. 1113 */ 1114 struct radeon_cs_chunk { 1115 uint32_t length_dw; 1116 uint32_t *kdata; 1117 void __user *user_ptr; 1118 }; 1119 1120 struct radeon_cs_parser { 1121 struct device *dev; 1122 struct radeon_device *rdev; 1123 struct drm_file *filp; 1124 /* chunks */ 1125 unsigned nchunks; 1126 struct radeon_cs_chunk *chunks; 1127 uint64_t *chunks_array; 1128 /* IB */ 1129 unsigned idx; 1130 /* relocations */ 1131 unsigned nrelocs; 1132 struct radeon_bo_list *relocs; 1133 struct radeon_bo_list *vm_bos; 1134 struct list_head validated; 1135 unsigned dma_reloc_idx; 1136 /* indices of various chunks */ 1137 struct radeon_cs_chunk *chunk_ib; 1138 struct radeon_cs_chunk *chunk_relocs; 1139 struct radeon_cs_chunk *chunk_flags; 1140 struct radeon_cs_chunk *chunk_const_ib; 1141 struct radeon_ib ib; 1142 struct radeon_ib const_ib; 1143 void *track; 1144 unsigned family; 1145 int parser_error; 1146 u32 cs_flags; 1147 u32 ring; 1148 s32 priority; 1149 struct ww_acquire_ctx ticket; 1150 }; 1151 1152 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1153 { 1154 struct radeon_cs_chunk *ibc = p->chunk_ib; 1155 1156 if (ibc->kdata) 1157 return ibc->kdata[idx]; 1158 return p->ib.ptr[idx]; 1159 } 1160 1161 1162 struct radeon_cs_packet { 1163 unsigned idx; 1164 unsigned type; 1165 unsigned reg; 1166 unsigned opcode; 1167 int count; 1168 unsigned one_reg_wr; 1169 }; 1170 1171 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1172 struct radeon_cs_packet *pkt, 1173 unsigned idx, unsigned reg); 1174 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1175 struct radeon_cs_packet *pkt); 1176 1177 1178 /* 1179 * AGP 1180 */ 1181 int radeon_agp_init(struct radeon_device *rdev); 1182 void radeon_agp_resume(struct radeon_device *rdev); 1183 void radeon_agp_suspend(struct radeon_device *rdev); 1184 void radeon_agp_fini(struct radeon_device *rdev); 1185 1186 1187 /* 1188 * Writeback 1189 */ 1190 struct radeon_wb { 1191 struct radeon_bo *wb_obj; 1192 volatile uint32_t *wb; 1193 uint64_t gpu_addr; 1194 bool enabled; 1195 bool use_event; 1196 }; 1197 1198 #define RADEON_WB_SCRATCH_OFFSET 0 1199 #define RADEON_WB_RING0_NEXT_RPTR 256 1200 #define RADEON_WB_CP_RPTR_OFFSET 1024 1201 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1202 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1203 #define R600_WB_DMA_RPTR_OFFSET 1792 1204 #define R600_WB_IH_WPTR_OFFSET 2048 1205 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1206 #define R600_WB_EVENT_OFFSET 3072 1207 #define CIK_WB_CP1_WPTR_OFFSET 3328 1208 #define CIK_WB_CP2_WPTR_OFFSET 3584 1209 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1210 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1211 1212 /** 1213 * struct radeon_pm - power management datas 1214 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1215 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1216 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1217 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1218 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1219 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1220 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1221 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1222 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1223 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1224 * @needed_bandwidth: current bandwidth needs 1225 * 1226 * It keeps track of various data needed to take powermanagement decision. 1227 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1228 * Equation between gpu/memory clock and available bandwidth is hw dependent 1229 * (type of memory, bus size, efficiency, ...) 1230 */ 1231 1232 enum radeon_pm_method { 1233 PM_METHOD_PROFILE, 1234 PM_METHOD_DYNPM, 1235 PM_METHOD_DPM, 1236 }; 1237 1238 enum radeon_dynpm_state { 1239 DYNPM_STATE_DISABLED, 1240 DYNPM_STATE_MINIMUM, 1241 DYNPM_STATE_PAUSED, 1242 DYNPM_STATE_ACTIVE, 1243 DYNPM_STATE_SUSPENDED, 1244 }; 1245 enum radeon_dynpm_action { 1246 DYNPM_ACTION_NONE, 1247 DYNPM_ACTION_MINIMUM, 1248 DYNPM_ACTION_DOWNCLOCK, 1249 DYNPM_ACTION_UPCLOCK, 1250 DYNPM_ACTION_DEFAULT 1251 }; 1252 1253 enum radeon_voltage_type { 1254 VOLTAGE_NONE = 0, 1255 VOLTAGE_GPIO, 1256 VOLTAGE_VDDC, 1257 VOLTAGE_SW 1258 }; 1259 1260 enum radeon_pm_state_type { 1261 /* not used for dpm */ 1262 POWER_STATE_TYPE_DEFAULT, 1263 POWER_STATE_TYPE_POWERSAVE, 1264 /* user selectable states */ 1265 POWER_STATE_TYPE_BATTERY, 1266 POWER_STATE_TYPE_BALANCED, 1267 POWER_STATE_TYPE_PERFORMANCE, 1268 /* internal states */ 1269 POWER_STATE_TYPE_INTERNAL_UVD, 1270 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1271 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1272 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1273 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1274 POWER_STATE_TYPE_INTERNAL_BOOT, 1275 POWER_STATE_TYPE_INTERNAL_THERMAL, 1276 POWER_STATE_TYPE_INTERNAL_ACPI, 1277 POWER_STATE_TYPE_INTERNAL_ULV, 1278 POWER_STATE_TYPE_INTERNAL_3DPERF, 1279 }; 1280 1281 enum radeon_pm_profile_type { 1282 PM_PROFILE_DEFAULT, 1283 PM_PROFILE_AUTO, 1284 PM_PROFILE_LOW, 1285 PM_PROFILE_MID, 1286 PM_PROFILE_HIGH, 1287 }; 1288 1289 #define PM_PROFILE_DEFAULT_IDX 0 1290 #define PM_PROFILE_LOW_SH_IDX 1 1291 #define PM_PROFILE_MID_SH_IDX 2 1292 #define PM_PROFILE_HIGH_SH_IDX 3 1293 #define PM_PROFILE_LOW_MH_IDX 4 1294 #define PM_PROFILE_MID_MH_IDX 5 1295 #define PM_PROFILE_HIGH_MH_IDX 6 1296 #define PM_PROFILE_MAX 7 1297 1298 struct radeon_pm_profile { 1299 int dpms_off_ps_idx; 1300 int dpms_on_ps_idx; 1301 int dpms_off_cm_idx; 1302 int dpms_on_cm_idx; 1303 }; 1304 1305 enum radeon_int_thermal_type { 1306 THERMAL_TYPE_NONE, 1307 THERMAL_TYPE_EXTERNAL, 1308 THERMAL_TYPE_EXTERNAL_GPIO, 1309 THERMAL_TYPE_RV6XX, 1310 THERMAL_TYPE_RV770, 1311 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1312 THERMAL_TYPE_EVERGREEN, 1313 THERMAL_TYPE_SUMO, 1314 THERMAL_TYPE_NI, 1315 THERMAL_TYPE_SI, 1316 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1317 THERMAL_TYPE_CI, 1318 THERMAL_TYPE_KV, 1319 }; 1320 1321 struct radeon_voltage { 1322 enum radeon_voltage_type type; 1323 /* gpio voltage */ 1324 struct radeon_gpio_rec gpio; 1325 u32 delay; /* delay in usec from voltage drop to sclk change */ 1326 bool active_high; /* voltage drop is active when bit is high */ 1327 /* VDDC voltage */ 1328 u8 vddc_id; /* index into vddc voltage table */ 1329 u8 vddci_id; /* index into vddci voltage table */ 1330 bool vddci_enabled; 1331 /* r6xx+ sw */ 1332 u16 voltage; 1333 /* evergreen+ vddci */ 1334 u16 vddci; 1335 }; 1336 1337 /* clock mode flags */ 1338 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1339 1340 struct radeon_pm_clock_info { 1341 /* memory clock */ 1342 u32 mclk; 1343 /* engine clock */ 1344 u32 sclk; 1345 /* voltage info */ 1346 struct radeon_voltage voltage; 1347 /* standardized clock flags */ 1348 u32 flags; 1349 }; 1350 1351 /* state flags */ 1352 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1353 1354 struct radeon_power_state { 1355 enum radeon_pm_state_type type; 1356 struct radeon_pm_clock_info *clock_info; 1357 /* number of valid clock modes in this power state */ 1358 int num_clock_modes; 1359 struct radeon_pm_clock_info *default_clock_mode; 1360 /* standardized state flags */ 1361 u32 flags; 1362 u32 misc; /* vbios specific flags */ 1363 u32 misc2; /* vbios specific flags */ 1364 int pcie_lanes; /* pcie lanes */ 1365 }; 1366 1367 /* 1368 * Some modes are overclocked by very low value, accept them 1369 */ 1370 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1371 1372 enum radeon_dpm_auto_throttle_src { 1373 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1374 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1375 }; 1376 1377 enum radeon_dpm_event_src { 1378 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1379 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1380 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1381 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1382 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1383 }; 1384 1385 #define RADEON_MAX_VCE_LEVELS 6 1386 1387 enum radeon_vce_level { 1388 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1389 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1390 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1391 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1392 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1393 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1394 }; 1395 1396 struct radeon_ps { 1397 u32 caps; /* vbios flags */ 1398 u32 class; /* vbios flags */ 1399 u32 class2; /* vbios flags */ 1400 /* UVD clocks */ 1401 u32 vclk; 1402 u32 dclk; 1403 /* VCE clocks */ 1404 u32 evclk; 1405 u32 ecclk; 1406 bool vce_active; 1407 enum radeon_vce_level vce_level; 1408 /* asic priv */ 1409 void *ps_priv; 1410 }; 1411 1412 struct radeon_dpm_thermal { 1413 /* thermal interrupt work */ 1414 struct work_struct work; 1415 /* low temperature threshold */ 1416 int min_temp; 1417 /* high temperature threshold */ 1418 int max_temp; 1419 /* was interrupt low to high or high to low */ 1420 bool high_to_low; 1421 }; 1422 1423 enum radeon_clk_action 1424 { 1425 RADEON_SCLK_UP = 1, 1426 RADEON_SCLK_DOWN 1427 }; 1428 1429 struct radeon_blacklist_clocks 1430 { 1431 u32 sclk; 1432 u32 mclk; 1433 enum radeon_clk_action action; 1434 }; 1435 1436 struct radeon_clock_and_voltage_limits { 1437 u32 sclk; 1438 u32 mclk; 1439 u16 vddc; 1440 u16 vddci; 1441 }; 1442 1443 struct radeon_clock_array { 1444 u32 count; 1445 u32 *values; 1446 }; 1447 1448 struct radeon_clock_voltage_dependency_entry { 1449 u32 clk; 1450 u16 v; 1451 }; 1452 1453 struct radeon_clock_voltage_dependency_table { 1454 u32 count; 1455 struct radeon_clock_voltage_dependency_entry *entries; 1456 }; 1457 1458 union radeon_cac_leakage_entry { 1459 struct { 1460 u16 vddc; 1461 u32 leakage; 1462 }; 1463 struct { 1464 u16 vddc1; 1465 u16 vddc2; 1466 u16 vddc3; 1467 }; 1468 }; 1469 1470 struct radeon_cac_leakage_table { 1471 u32 count; 1472 union radeon_cac_leakage_entry *entries; 1473 }; 1474 1475 struct radeon_phase_shedding_limits_entry { 1476 u16 voltage; 1477 u32 sclk; 1478 u32 mclk; 1479 }; 1480 1481 struct radeon_phase_shedding_limits_table { 1482 u32 count; 1483 struct radeon_phase_shedding_limits_entry *entries; 1484 }; 1485 1486 struct radeon_uvd_clock_voltage_dependency_entry { 1487 u32 vclk; 1488 u32 dclk; 1489 u16 v; 1490 }; 1491 1492 struct radeon_uvd_clock_voltage_dependency_table { 1493 u8 count; 1494 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1495 }; 1496 1497 struct radeon_vce_clock_voltage_dependency_entry { 1498 u32 ecclk; 1499 u32 evclk; 1500 u16 v; 1501 }; 1502 1503 struct radeon_vce_clock_voltage_dependency_table { 1504 u8 count; 1505 struct radeon_vce_clock_voltage_dependency_entry *entries; 1506 }; 1507 1508 struct radeon_ppm_table { 1509 u8 ppm_design; 1510 u16 cpu_core_number; 1511 u32 platform_tdp; 1512 u32 small_ac_platform_tdp; 1513 u32 platform_tdc; 1514 u32 small_ac_platform_tdc; 1515 u32 apu_tdp; 1516 u32 dgpu_tdp; 1517 u32 dgpu_ulv_power; 1518 u32 tj_max; 1519 }; 1520 1521 struct radeon_cac_tdp_table { 1522 u16 tdp; 1523 u16 configurable_tdp; 1524 u16 tdc; 1525 u16 battery_power_limit; 1526 u16 small_power_limit; 1527 u16 low_cac_leakage; 1528 u16 high_cac_leakage; 1529 u16 maximum_power_delivery_limit; 1530 }; 1531 1532 struct radeon_dpm_dynamic_state { 1533 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1534 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1535 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1536 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1537 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1538 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1539 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1540 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1541 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1542 struct radeon_clock_array valid_sclk_values; 1543 struct radeon_clock_array valid_mclk_values; 1544 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1545 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1546 u32 mclk_sclk_ratio; 1547 u32 sclk_mclk_delta; 1548 u16 vddc_vddci_delta; 1549 u16 min_vddc_for_pcie_gen2; 1550 struct radeon_cac_leakage_table cac_leakage_table; 1551 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1552 struct radeon_ppm_table *ppm_table; 1553 struct radeon_cac_tdp_table *cac_tdp_table; 1554 }; 1555 1556 struct radeon_dpm_fan { 1557 u16 t_min; 1558 u16 t_med; 1559 u16 t_high; 1560 u16 pwm_min; 1561 u16 pwm_med; 1562 u16 pwm_high; 1563 u8 t_hyst; 1564 u32 cycle_delay; 1565 u16 t_max; 1566 u8 control_mode; 1567 u16 default_max_fan_pwm; 1568 u16 default_fan_output_sensitivity; 1569 u16 fan_output_sensitivity; 1570 bool ucode_fan_control; 1571 }; 1572 1573 enum radeon_pcie_gen { 1574 RADEON_PCIE_GEN1 = 0, 1575 RADEON_PCIE_GEN2 = 1, 1576 RADEON_PCIE_GEN3 = 2, 1577 RADEON_PCIE_GEN_INVALID = 0xffff 1578 }; 1579 1580 enum radeon_dpm_forced_level { 1581 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1582 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1583 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1584 }; 1585 1586 struct radeon_vce_state { 1587 /* vce clocks */ 1588 u32 evclk; 1589 u32 ecclk; 1590 /* gpu clocks */ 1591 u32 sclk; 1592 u32 mclk; 1593 u8 clk_idx; 1594 u8 pstate; 1595 }; 1596 1597 struct radeon_dpm { 1598 struct radeon_ps *ps; 1599 /* number of valid power states */ 1600 int num_ps; 1601 /* current power state that is active */ 1602 struct radeon_ps *current_ps; 1603 /* requested power state */ 1604 struct radeon_ps *requested_ps; 1605 /* boot up power state */ 1606 struct radeon_ps *boot_ps; 1607 /* default uvd power state */ 1608 struct radeon_ps *uvd_ps; 1609 /* vce requirements */ 1610 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1611 enum radeon_vce_level vce_level; 1612 enum radeon_pm_state_type state; 1613 enum radeon_pm_state_type user_state; 1614 u32 platform_caps; 1615 u32 voltage_response_time; 1616 u32 backbias_response_time; 1617 void *priv; 1618 u32 new_active_crtcs; 1619 int new_active_crtc_count; 1620 u32 current_active_crtcs; 1621 int current_active_crtc_count; 1622 bool single_display; 1623 struct radeon_dpm_dynamic_state dyn_state; 1624 struct radeon_dpm_fan fan; 1625 u32 tdp_limit; 1626 u32 near_tdp_limit; 1627 u32 near_tdp_limit_adjusted; 1628 u32 sq_ramping_threshold; 1629 u32 cac_leakage; 1630 u16 tdp_od_limit; 1631 u32 tdp_adjustment; 1632 u16 load_line_slope; 1633 bool power_control; 1634 bool ac_power; 1635 /* special states active */ 1636 bool thermal_active; 1637 bool uvd_active; 1638 bool vce_active; 1639 /* thermal handling */ 1640 struct radeon_dpm_thermal thermal; 1641 /* forced levels */ 1642 enum radeon_dpm_forced_level forced_level; 1643 /* track UVD streams */ 1644 unsigned sd; 1645 unsigned hd; 1646 }; 1647 1648 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1649 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1650 1651 struct radeon_pm { 1652 struct mutex mutex; 1653 /* write locked while reprogramming mclk */ 1654 struct rw_semaphore mclk_lock; 1655 u32 active_crtcs; 1656 int active_crtc_count; 1657 int req_vblank; 1658 bool vblank_sync; 1659 fixed20_12 max_bandwidth; 1660 fixed20_12 igp_sideport_mclk; 1661 fixed20_12 igp_system_mclk; 1662 fixed20_12 igp_ht_link_clk; 1663 fixed20_12 igp_ht_link_width; 1664 fixed20_12 k8_bandwidth; 1665 fixed20_12 sideport_bandwidth; 1666 fixed20_12 ht_bandwidth; 1667 fixed20_12 core_bandwidth; 1668 fixed20_12 sclk; 1669 fixed20_12 mclk; 1670 fixed20_12 needed_bandwidth; 1671 struct radeon_power_state *power_state; 1672 /* number of valid power states */ 1673 int num_power_states; 1674 int current_power_state_index; 1675 int current_clock_mode_index; 1676 int requested_power_state_index; 1677 int requested_clock_mode_index; 1678 int default_power_state_index; 1679 u32 current_sclk; 1680 u32 current_mclk; 1681 u16 current_vddc; 1682 u16 current_vddci; 1683 u32 default_sclk; 1684 u32 default_mclk; 1685 u16 default_vddc; 1686 u16 default_vddci; 1687 struct radeon_i2c_chan *i2c_bus; 1688 /* selected pm method */ 1689 enum radeon_pm_method pm_method; 1690 /* dynpm power management */ 1691 struct delayed_work dynpm_idle_work; 1692 enum radeon_dynpm_state dynpm_state; 1693 enum radeon_dynpm_action dynpm_planned_action; 1694 unsigned long dynpm_action_timeout; 1695 bool dynpm_can_upclock; 1696 bool dynpm_can_downclock; 1697 /* profile-based power management */ 1698 enum radeon_pm_profile_type profile; 1699 int profile_index; 1700 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1701 /* internal thermal controller on rv6xx+ */ 1702 enum radeon_int_thermal_type int_thermal_type; 1703 struct device *int_hwmon_dev; 1704 /* fan control parameters */ 1705 bool no_fan; 1706 u8 fan_pulses_per_revolution; 1707 u8 fan_min_rpm; 1708 u8 fan_max_rpm; 1709 /* dpm */ 1710 bool dpm_enabled; 1711 bool sysfs_initialized; 1712 struct radeon_dpm dpm; 1713 }; 1714 1715 int radeon_pm_get_type_index(struct radeon_device *rdev, 1716 enum radeon_pm_state_type ps_type, 1717 int instance); 1718 /* 1719 * UVD 1720 */ 1721 #define RADEON_MAX_UVD_HANDLES 10 1722 #define RADEON_UVD_STACK_SIZE (1024*1024) 1723 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1724 1725 struct radeon_uvd { 1726 struct radeon_bo *vcpu_bo; 1727 void *cpu_addr; 1728 uint64_t gpu_addr; 1729 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1730 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1731 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1732 struct delayed_work idle_work; 1733 }; 1734 1735 int radeon_uvd_init(struct radeon_device *rdev); 1736 void radeon_uvd_fini(struct radeon_device *rdev); 1737 int radeon_uvd_suspend(struct radeon_device *rdev); 1738 int radeon_uvd_resume(struct radeon_device *rdev); 1739 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1740 uint32_t handle, struct radeon_fence **fence); 1741 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1742 uint32_t handle, struct radeon_fence **fence); 1743 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1744 uint32_t allowed_domains); 1745 void radeon_uvd_free_handles(struct radeon_device *rdev, 1746 struct drm_file *filp); 1747 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1748 void radeon_uvd_note_usage(struct radeon_device *rdev); 1749 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1750 unsigned vclk, unsigned dclk, 1751 unsigned vco_min, unsigned vco_max, 1752 unsigned fb_factor, unsigned fb_mask, 1753 unsigned pd_min, unsigned pd_max, 1754 unsigned pd_even, 1755 unsigned *optimal_fb_div, 1756 unsigned *optimal_vclk_div, 1757 unsigned *optimal_dclk_div); 1758 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1759 unsigned cg_upll_func_cntl); 1760 1761 /* 1762 * VCE 1763 */ 1764 #define RADEON_MAX_VCE_HANDLES 16 1765 1766 struct radeon_vce { 1767 struct radeon_bo *vcpu_bo; 1768 uint64_t gpu_addr; 1769 unsigned fw_version; 1770 unsigned fb_version; 1771 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1772 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1773 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1774 struct delayed_work idle_work; 1775 uint32_t keyselect; 1776 }; 1777 1778 int radeon_vce_init(struct radeon_device *rdev); 1779 void radeon_vce_fini(struct radeon_device *rdev); 1780 int radeon_vce_suspend(struct radeon_device *rdev); 1781 int radeon_vce_resume(struct radeon_device *rdev); 1782 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1783 uint32_t handle, struct radeon_fence **fence); 1784 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1785 uint32_t handle, struct radeon_fence **fence); 1786 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1787 void radeon_vce_note_usage(struct radeon_device *rdev); 1788 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1789 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1790 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1791 struct radeon_ring *ring, 1792 struct radeon_semaphore *semaphore, 1793 bool emit_wait); 1794 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1795 void radeon_vce_fence_emit(struct radeon_device *rdev, 1796 struct radeon_fence *fence); 1797 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1798 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1799 1800 struct r600_audio_pin { 1801 int channels; 1802 int rate; 1803 int bits_per_sample; 1804 u8 status_bits; 1805 u8 category_code; 1806 u32 offset; 1807 bool connected; 1808 u32 id; 1809 }; 1810 1811 struct r600_audio { 1812 bool enabled; 1813 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1814 int num_pins; 1815 struct radeon_audio_funcs *hdmi_funcs; 1816 struct radeon_audio_funcs *dp_funcs; 1817 struct radeon_audio_basic_funcs *funcs; 1818 }; 1819 1820 /* 1821 * Benchmarking 1822 */ 1823 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1824 1825 1826 /* 1827 * Testing 1828 */ 1829 void radeon_test_moves(struct radeon_device *rdev); 1830 void radeon_test_ring_sync(struct radeon_device *rdev, 1831 struct radeon_ring *cpA, 1832 struct radeon_ring *cpB); 1833 void radeon_test_syncing(struct radeon_device *rdev); 1834 1835 /* 1836 * MMU Notifier 1837 */ 1838 #if defined(CONFIG_MMU_NOTIFIER) 1839 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1840 void radeon_mn_unregister(struct radeon_bo *bo); 1841 #else 1842 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1843 { 1844 return -ENODEV; 1845 } 1846 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1847 #endif 1848 1849 /* 1850 * Debugfs 1851 */ 1852 struct radeon_debugfs { 1853 struct drm_info_list *files; 1854 unsigned num_files; 1855 }; 1856 1857 int radeon_debugfs_add_files(struct radeon_device *rdev, 1858 struct drm_info_list *files, 1859 unsigned nfiles); 1860 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1861 1862 /* 1863 * ASIC ring specific functions. 1864 */ 1865 struct radeon_asic_ring { 1866 /* ring read/write ptr handling */ 1867 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1868 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1869 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1870 1871 /* validating and patching of IBs */ 1872 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1873 int (*cs_parse)(struct radeon_cs_parser *p); 1874 1875 /* command emmit functions */ 1876 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1877 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1878 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1879 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1880 struct radeon_semaphore *semaphore, bool emit_wait); 1881 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1882 unsigned vm_id, uint64_t pd_addr); 1883 1884 /* testing functions */ 1885 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1886 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1887 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1888 1889 /* deprecated */ 1890 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1891 }; 1892 1893 /* 1894 * ASIC specific functions. 1895 */ 1896 struct radeon_asic { 1897 int (*init)(struct radeon_device *rdev); 1898 void (*fini)(struct radeon_device *rdev); 1899 int (*resume)(struct radeon_device *rdev); 1900 int (*suspend)(struct radeon_device *rdev); 1901 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1902 int (*asic_reset)(struct radeon_device *rdev); 1903 /* Flush the HDP cache via MMIO */ 1904 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1905 /* check if 3D engine is idle */ 1906 bool (*gui_idle)(struct radeon_device *rdev); 1907 /* wait for mc_idle */ 1908 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1909 /* get the reference clock */ 1910 u32 (*get_xclk)(struct radeon_device *rdev); 1911 /* get the gpu clock counter */ 1912 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1913 /* get register for info ioctl */ 1914 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1915 /* gart */ 1916 struct { 1917 void (*tlb_flush)(struct radeon_device *rdev); 1918 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1919 void (*set_page)(struct radeon_device *rdev, unsigned i, 1920 uint64_t entry); 1921 } gart; 1922 struct { 1923 int (*init)(struct radeon_device *rdev); 1924 void (*fini)(struct radeon_device *rdev); 1925 void (*copy_pages)(struct radeon_device *rdev, 1926 struct radeon_ib *ib, 1927 uint64_t pe, uint64_t src, 1928 unsigned count); 1929 void (*write_pages)(struct radeon_device *rdev, 1930 struct radeon_ib *ib, 1931 uint64_t pe, 1932 uint64_t addr, unsigned count, 1933 uint32_t incr, uint32_t flags); 1934 void (*set_pages)(struct radeon_device *rdev, 1935 struct radeon_ib *ib, 1936 uint64_t pe, 1937 uint64_t addr, unsigned count, 1938 uint32_t incr, uint32_t flags); 1939 void (*pad_ib)(struct radeon_ib *ib); 1940 } vm; 1941 /* ring specific callbacks */ 1942 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1943 /* irqs */ 1944 struct { 1945 int (*set)(struct radeon_device *rdev); 1946 int (*process)(struct radeon_device *rdev); 1947 } irq; 1948 /* displays */ 1949 struct { 1950 /* display watermarks */ 1951 void (*bandwidth_update)(struct radeon_device *rdev); 1952 /* get frame count */ 1953 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1954 /* wait for vblank */ 1955 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1956 /* set backlight level */ 1957 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1958 /* get backlight level */ 1959 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1960 /* audio callbacks */ 1961 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1962 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1963 } display; 1964 /* copy functions for bo handling */ 1965 struct { 1966 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1967 uint64_t src_offset, 1968 uint64_t dst_offset, 1969 unsigned num_gpu_pages, 1970 struct reservation_object *resv); 1971 u32 blit_ring_index; 1972 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1973 uint64_t src_offset, 1974 uint64_t dst_offset, 1975 unsigned num_gpu_pages, 1976 struct reservation_object *resv); 1977 u32 dma_ring_index; 1978 /* method used for bo copy */ 1979 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1980 uint64_t src_offset, 1981 uint64_t dst_offset, 1982 unsigned num_gpu_pages, 1983 struct reservation_object *resv); 1984 /* ring used for bo copies */ 1985 u32 copy_ring_index; 1986 } copy; 1987 /* surfaces */ 1988 struct { 1989 int (*set_reg)(struct radeon_device *rdev, int reg, 1990 uint32_t tiling_flags, uint32_t pitch, 1991 uint32_t offset, uint32_t obj_size); 1992 void (*clear_reg)(struct radeon_device *rdev, int reg); 1993 } surface; 1994 /* hotplug detect */ 1995 struct { 1996 void (*init)(struct radeon_device *rdev); 1997 void (*fini)(struct radeon_device *rdev); 1998 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1999 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 2000 } hpd; 2001 /* static power management */ 2002 struct { 2003 void (*misc)(struct radeon_device *rdev); 2004 void (*prepare)(struct radeon_device *rdev); 2005 void (*finish)(struct radeon_device *rdev); 2006 void (*init_profile)(struct radeon_device *rdev); 2007 void (*get_dynpm_state)(struct radeon_device *rdev); 2008 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 2009 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 2010 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 2011 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 2012 int (*get_pcie_lanes)(struct radeon_device *rdev); 2013 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 2014 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 2015 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 2016 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 2017 int (*get_temperature)(struct radeon_device *rdev); 2018 } pm; 2019 /* dynamic power management */ 2020 struct { 2021 int (*init)(struct radeon_device *rdev); 2022 void (*setup_asic)(struct radeon_device *rdev); 2023 int (*enable)(struct radeon_device *rdev); 2024 int (*late_enable)(struct radeon_device *rdev); 2025 void (*disable)(struct radeon_device *rdev); 2026 int (*pre_set_power_state)(struct radeon_device *rdev); 2027 int (*set_power_state)(struct radeon_device *rdev); 2028 void (*post_set_power_state)(struct radeon_device *rdev); 2029 void (*display_configuration_changed)(struct radeon_device *rdev); 2030 void (*fini)(struct radeon_device *rdev); 2031 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2032 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2033 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2034 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2035 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2036 bool (*vblank_too_short)(struct radeon_device *rdev); 2037 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2038 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2039 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2040 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2041 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2042 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2043 u32 (*get_current_sclk)(struct radeon_device *rdev); 2044 u32 (*get_current_mclk)(struct radeon_device *rdev); 2045 } dpm; 2046 /* pageflipping */ 2047 struct { 2048 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 2049 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2050 } pflip; 2051 }; 2052 2053 /* 2054 * Asic structures 2055 */ 2056 struct r100_asic { 2057 const unsigned *reg_safe_bm; 2058 unsigned reg_safe_bm_size; 2059 u32 hdp_cntl; 2060 }; 2061 2062 struct r300_asic { 2063 const unsigned *reg_safe_bm; 2064 unsigned reg_safe_bm_size; 2065 u32 resync_scratch; 2066 u32 hdp_cntl; 2067 }; 2068 2069 struct r600_asic { 2070 unsigned max_pipes; 2071 unsigned max_tile_pipes; 2072 unsigned max_simds; 2073 unsigned max_backends; 2074 unsigned max_gprs; 2075 unsigned max_threads; 2076 unsigned max_stack_entries; 2077 unsigned max_hw_contexts; 2078 unsigned max_gs_threads; 2079 unsigned sx_max_export_size; 2080 unsigned sx_max_export_pos_size; 2081 unsigned sx_max_export_smx_size; 2082 unsigned sq_num_cf_insts; 2083 unsigned tiling_nbanks; 2084 unsigned tiling_npipes; 2085 unsigned tiling_group_size; 2086 unsigned tile_config; 2087 unsigned backend_map; 2088 unsigned active_simds; 2089 }; 2090 2091 struct rv770_asic { 2092 unsigned max_pipes; 2093 unsigned max_tile_pipes; 2094 unsigned max_simds; 2095 unsigned max_backends; 2096 unsigned max_gprs; 2097 unsigned max_threads; 2098 unsigned max_stack_entries; 2099 unsigned max_hw_contexts; 2100 unsigned max_gs_threads; 2101 unsigned sx_max_export_size; 2102 unsigned sx_max_export_pos_size; 2103 unsigned sx_max_export_smx_size; 2104 unsigned sq_num_cf_insts; 2105 unsigned sx_num_of_sets; 2106 unsigned sc_prim_fifo_size; 2107 unsigned sc_hiz_tile_fifo_size; 2108 unsigned sc_earlyz_tile_fifo_fize; 2109 unsigned tiling_nbanks; 2110 unsigned tiling_npipes; 2111 unsigned tiling_group_size; 2112 unsigned tile_config; 2113 unsigned backend_map; 2114 unsigned active_simds; 2115 }; 2116 2117 struct evergreen_asic { 2118 unsigned num_ses; 2119 unsigned max_pipes; 2120 unsigned max_tile_pipes; 2121 unsigned max_simds; 2122 unsigned max_backends; 2123 unsigned max_gprs; 2124 unsigned max_threads; 2125 unsigned max_stack_entries; 2126 unsigned max_hw_contexts; 2127 unsigned max_gs_threads; 2128 unsigned sx_max_export_size; 2129 unsigned sx_max_export_pos_size; 2130 unsigned sx_max_export_smx_size; 2131 unsigned sq_num_cf_insts; 2132 unsigned sx_num_of_sets; 2133 unsigned sc_prim_fifo_size; 2134 unsigned sc_hiz_tile_fifo_size; 2135 unsigned sc_earlyz_tile_fifo_size; 2136 unsigned tiling_nbanks; 2137 unsigned tiling_npipes; 2138 unsigned tiling_group_size; 2139 unsigned tile_config; 2140 unsigned backend_map; 2141 unsigned active_simds; 2142 }; 2143 2144 struct cayman_asic { 2145 unsigned max_shader_engines; 2146 unsigned max_pipes_per_simd; 2147 unsigned max_tile_pipes; 2148 unsigned max_simds_per_se; 2149 unsigned max_backends_per_se; 2150 unsigned max_texture_channel_caches; 2151 unsigned max_gprs; 2152 unsigned max_threads; 2153 unsigned max_gs_threads; 2154 unsigned max_stack_entries; 2155 unsigned sx_num_of_sets; 2156 unsigned sx_max_export_size; 2157 unsigned sx_max_export_pos_size; 2158 unsigned sx_max_export_smx_size; 2159 unsigned max_hw_contexts; 2160 unsigned sq_num_cf_insts; 2161 unsigned sc_prim_fifo_size; 2162 unsigned sc_hiz_tile_fifo_size; 2163 unsigned sc_earlyz_tile_fifo_size; 2164 2165 unsigned num_shader_engines; 2166 unsigned num_shader_pipes_per_simd; 2167 unsigned num_tile_pipes; 2168 unsigned num_simds_per_se; 2169 unsigned num_backends_per_se; 2170 unsigned backend_disable_mask_per_asic; 2171 unsigned backend_map; 2172 unsigned num_texture_channel_caches; 2173 unsigned mem_max_burst_length_bytes; 2174 unsigned mem_row_size_in_kb; 2175 unsigned shader_engine_tile_size; 2176 unsigned num_gpus; 2177 unsigned multi_gpu_tile_size; 2178 2179 unsigned tile_config; 2180 unsigned active_simds; 2181 }; 2182 2183 struct si_asic { 2184 unsigned max_shader_engines; 2185 unsigned max_tile_pipes; 2186 unsigned max_cu_per_sh; 2187 unsigned max_sh_per_se; 2188 unsigned max_backends_per_se; 2189 unsigned max_texture_channel_caches; 2190 unsigned max_gprs; 2191 unsigned max_gs_threads; 2192 unsigned max_hw_contexts; 2193 unsigned sc_prim_fifo_size_frontend; 2194 unsigned sc_prim_fifo_size_backend; 2195 unsigned sc_hiz_tile_fifo_size; 2196 unsigned sc_earlyz_tile_fifo_size; 2197 2198 unsigned num_tile_pipes; 2199 unsigned backend_enable_mask; 2200 unsigned backend_disable_mask_per_asic; 2201 unsigned backend_map; 2202 unsigned num_texture_channel_caches; 2203 unsigned mem_max_burst_length_bytes; 2204 unsigned mem_row_size_in_kb; 2205 unsigned shader_engine_tile_size; 2206 unsigned num_gpus; 2207 unsigned multi_gpu_tile_size; 2208 2209 unsigned tile_config; 2210 uint32_t tile_mode_array[32]; 2211 uint32_t active_cus; 2212 }; 2213 2214 struct cik_asic { 2215 unsigned max_shader_engines; 2216 unsigned max_tile_pipes; 2217 unsigned max_cu_per_sh; 2218 unsigned max_sh_per_se; 2219 unsigned max_backends_per_se; 2220 unsigned max_texture_channel_caches; 2221 unsigned max_gprs; 2222 unsigned max_gs_threads; 2223 unsigned max_hw_contexts; 2224 unsigned sc_prim_fifo_size_frontend; 2225 unsigned sc_prim_fifo_size_backend; 2226 unsigned sc_hiz_tile_fifo_size; 2227 unsigned sc_earlyz_tile_fifo_size; 2228 2229 unsigned num_tile_pipes; 2230 unsigned backend_enable_mask; 2231 unsigned backend_disable_mask_per_asic; 2232 unsigned backend_map; 2233 unsigned num_texture_channel_caches; 2234 unsigned mem_max_burst_length_bytes; 2235 unsigned mem_row_size_in_kb; 2236 unsigned shader_engine_tile_size; 2237 unsigned num_gpus; 2238 unsigned multi_gpu_tile_size; 2239 2240 unsigned tile_config; 2241 uint32_t tile_mode_array[32]; 2242 uint32_t macrotile_mode_array[16]; 2243 uint32_t active_cus; 2244 }; 2245 2246 union radeon_asic_config { 2247 struct r300_asic r300; 2248 struct r100_asic r100; 2249 struct r600_asic r600; 2250 struct rv770_asic rv770; 2251 struct evergreen_asic evergreen; 2252 struct cayman_asic cayman; 2253 struct si_asic si; 2254 struct cik_asic cik; 2255 }; 2256 2257 /* 2258 * asic initizalization from radeon_asic.c 2259 */ 2260 void radeon_agp_disable(struct radeon_device *rdev); 2261 int radeon_asic_init(struct radeon_device *rdev); 2262 2263 2264 /* 2265 * IOCTL. 2266 */ 2267 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2268 struct drm_file *filp); 2269 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2270 struct drm_file *filp); 2271 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2272 struct drm_file *filp); 2273 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2274 struct drm_file *file_priv); 2275 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2276 struct drm_file *file_priv); 2277 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2278 struct drm_file *file_priv); 2279 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2280 struct drm_file *file_priv); 2281 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2282 struct drm_file *filp); 2283 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2284 struct drm_file *filp); 2285 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2286 struct drm_file *filp); 2287 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2288 struct drm_file *filp); 2289 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2290 struct drm_file *filp); 2291 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2292 struct drm_file *filp); 2293 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2294 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2295 struct drm_file *filp); 2296 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2297 struct drm_file *filp); 2298 2299 /* VRAM scratch page for HDP bug, default vram page */ 2300 struct r600_vram_scratch { 2301 struct radeon_bo *robj; 2302 volatile uint32_t *ptr; 2303 u64 gpu_addr; 2304 }; 2305 2306 /* 2307 * ACPI 2308 */ 2309 struct radeon_atif_notification_cfg { 2310 bool enabled; 2311 int command_code; 2312 }; 2313 2314 struct radeon_atif_notifications { 2315 bool display_switch; 2316 bool expansion_mode_change; 2317 bool thermal_state; 2318 bool forced_power_state; 2319 bool system_power_state; 2320 bool display_conf_change; 2321 bool px_gfx_switch; 2322 bool brightness_change; 2323 bool dgpu_display_event; 2324 }; 2325 2326 struct radeon_atif_functions { 2327 bool system_params; 2328 bool sbios_requests; 2329 bool select_active_disp; 2330 bool lid_state; 2331 bool get_tv_standard; 2332 bool set_tv_standard; 2333 bool get_panel_expansion_mode; 2334 bool set_panel_expansion_mode; 2335 bool temperature_change; 2336 bool graphics_device_types; 2337 }; 2338 2339 struct radeon_atif { 2340 struct radeon_atif_notifications notifications; 2341 struct radeon_atif_functions functions; 2342 struct radeon_atif_notification_cfg notification_cfg; 2343 struct radeon_encoder *encoder_for_bl; 2344 }; 2345 2346 struct radeon_atcs_functions { 2347 bool get_ext_state; 2348 bool pcie_perf_req; 2349 bool pcie_dev_rdy; 2350 bool pcie_bus_width; 2351 }; 2352 2353 struct radeon_atcs { 2354 struct radeon_atcs_functions functions; 2355 }; 2356 2357 /* 2358 * Core structure, functions and helpers. 2359 */ 2360 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2361 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2362 2363 struct radeon_device { 2364 struct device *dev; 2365 struct drm_device *ddev; 2366 struct pci_dev *pdev; 2367 struct rw_semaphore exclusive_lock; 2368 /* ASIC */ 2369 union radeon_asic_config config; 2370 enum radeon_family family; 2371 unsigned long flags; 2372 int usec_timeout; 2373 enum radeon_pll_errata pll_errata; 2374 int num_gb_pipes; 2375 int num_z_pipes; 2376 int disp_priority; 2377 /* BIOS */ 2378 uint8_t *bios; 2379 bool is_atom_bios; 2380 uint16_t bios_header_start; 2381 struct radeon_bo *stollen_vga_memory; 2382 /* Register mmio */ 2383 #ifndef __NetBSD__ 2384 resource_size_t rmmio_base; 2385 resource_size_t rmmio_size; 2386 #endif 2387 /* protects concurrent MM_INDEX/DATA based register access */ 2388 spinlock_t mmio_idx_lock; 2389 /* protects concurrent SMC based register access */ 2390 spinlock_t smc_idx_lock; 2391 /* protects concurrent PLL register access */ 2392 spinlock_t pll_idx_lock; 2393 /* protects concurrent MC register access */ 2394 spinlock_t mc_idx_lock; 2395 /* protects concurrent PCIE register access */ 2396 spinlock_t pcie_idx_lock; 2397 /* protects concurrent PCIE_PORT register access */ 2398 spinlock_t pciep_idx_lock; 2399 /* protects concurrent PIF register access */ 2400 spinlock_t pif_idx_lock; 2401 /* protects concurrent CG register access */ 2402 spinlock_t cg_idx_lock; 2403 /* protects concurrent UVD register access */ 2404 spinlock_t uvd_idx_lock; 2405 /* protects concurrent RCU register access */ 2406 spinlock_t rcu_idx_lock; 2407 /* protects concurrent DIDT register access */ 2408 spinlock_t didt_idx_lock; 2409 /* protects concurrent ENDPOINT (audio) register access */ 2410 spinlock_t end_idx_lock; 2411 #ifdef __NetBSD__ 2412 bus_space_tag_t rmmio_bst; 2413 bus_space_handle_t rmmio_bsh; 2414 bus_addr_t rmmio_addr; 2415 bus_size_t rmmio_size; 2416 #else 2417 void __iomem *rmmio; 2418 #endif 2419 radeon_rreg_t mc_rreg; 2420 radeon_wreg_t mc_wreg; 2421 radeon_rreg_t pll_rreg; 2422 radeon_wreg_t pll_wreg; 2423 uint32_t pcie_reg_mask; 2424 radeon_rreg_t pciep_rreg; 2425 radeon_wreg_t pciep_wreg; 2426 /* io port */ 2427 #ifdef __NetBSD__ 2428 bus_space_tag_t rio_mem_bst; 2429 bus_space_handle_t rio_mem_bsh; 2430 bus_size_t rio_mem_size; 2431 #else 2432 void __iomem *rio_mem; 2433 resource_size_t rio_mem_size; 2434 #endif 2435 struct radeon_clock clock; 2436 struct radeon_mc mc; 2437 struct radeon_gart gart; 2438 struct radeon_mode_info mode_info; 2439 struct radeon_scratch scratch; 2440 struct radeon_doorbell doorbell; 2441 struct radeon_mman mman; 2442 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2443 #ifdef __NetBSD__ 2444 spinlock_t fence_lock; 2445 drm_waitqueue_t fence_queue; 2446 TAILQ_HEAD(, radeon_fence) fence_check; 2447 #else 2448 wait_queue_head_t fence_queue; 2449 #endif 2450 unsigned fence_context; 2451 struct mutex ring_lock; 2452 struct radeon_ring ring[RADEON_NUM_RINGS]; 2453 bool ib_pool_ready; 2454 struct radeon_sa_manager ring_tmp_bo; 2455 struct radeon_irq irq; 2456 struct radeon_asic *asic; 2457 struct radeon_gem gem; 2458 struct radeon_pm pm; 2459 struct radeon_uvd uvd; 2460 struct radeon_vce vce; 2461 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2462 struct radeon_wb wb; 2463 struct radeon_dummy_page dummy_page; 2464 bool shutdown; 2465 bool suspend; 2466 bool need_dma32; 2467 bool accel_working; 2468 bool fastfb_working; /* IGP feature*/ 2469 bool needs_reset, in_reset; 2470 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2471 const struct firmware *me_fw; /* all family ME firmware */ 2472 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2473 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2474 const struct firmware *mc_fw; /* NI MC firmware */ 2475 const struct firmware *ce_fw; /* SI CE firmware */ 2476 const struct firmware *mec_fw; /* CIK MEC firmware */ 2477 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2478 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2479 const struct firmware *smc_fw; /* SMC firmware */ 2480 const struct firmware *uvd_fw; /* UVD firmware */ 2481 const struct firmware *vce_fw; /* VCE firmware */ 2482 bool new_fw; 2483 struct r600_vram_scratch vram_scratch; 2484 int msi_enabled; /* msi enabled */ 2485 struct r600_ih ih; /* r6/700 interrupt ring */ 2486 struct radeon_rlc rlc; 2487 struct radeon_mec mec; 2488 struct delayed_work hotplug_work; 2489 struct work_struct dp_work; 2490 struct work_struct audio_work; 2491 int num_crtc; /* number of crtcs */ 2492 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2493 bool has_uvd; 2494 struct r600_audio audio; /* audio stuff */ 2495 struct notifier_block acpi_nb; 2496 /* only one userspace can use Hyperz features or CMASK at a time */ 2497 struct drm_file *hyperz_filp; 2498 struct drm_file *cmask_filp; 2499 /* i2c buses */ 2500 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2501 /* debugfs */ 2502 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2503 unsigned debugfs_count; 2504 /* virtual memory */ 2505 struct radeon_vm_manager vm_manager; 2506 struct mutex gpu_clock_mutex; 2507 /* memory stats */ 2508 atomic64_t vram_usage; 2509 atomic64_t gtt_usage; 2510 atomic64_t num_bytes_moved; 2511 atomic_t gpu_reset_counter; 2512 /* ACPI interface */ 2513 struct radeon_atif atif; 2514 struct radeon_atcs atcs; 2515 /* srbm instance registers */ 2516 struct mutex srbm_mutex; 2517 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2518 struct mutex grbm_idx_mutex; 2519 /* clock, powergating flags */ 2520 u32 cg_flags; 2521 u32 pg_flags; 2522 2523 struct dev_pm_domain vga_pm_domain; 2524 bool have_disp_power_ref; 2525 u32 px_quirk_flags; 2526 2527 /* tracking pinned memory */ 2528 u64 vram_pin_size; 2529 u64 gart_pin_size; 2530 2531 /* amdkfd interface */ 2532 struct kfd_dev *kfd; 2533 2534 struct mutex mn_lock; 2535 DECLARE_HASHTABLE(mn_hash, 7); 2536 }; 2537 2538 bool radeon_is_px(struct drm_device *dev); 2539 int radeon_device_init(struct radeon_device *rdev, 2540 struct drm_device *ddev, 2541 struct pci_dev *pdev, 2542 uint32_t flags); 2543 void radeon_device_fini(struct radeon_device *rdev); 2544 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2545 2546 #define RADEON_MIN_MMIO_SIZE 0x10000 2547 2548 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2549 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2550 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2551 bool always_indirect) 2552 { 2553 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2554 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2555 return readl(((void __iomem *)rdev->rmmio) + reg); 2556 else 2557 return r100_mm_rreg_slow(rdev, reg); 2558 } 2559 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2560 bool always_indirect) 2561 { 2562 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2563 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2564 else 2565 r100_mm_wreg_slow(rdev, reg, v); 2566 } 2567 2568 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2569 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2570 2571 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2572 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2573 2574 /* 2575 * Cast helper 2576 */ 2577 extern const struct fence_ops radeon_fence_ops; 2578 2579 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2580 { 2581 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2582 2583 if (__f->base.ops == &radeon_fence_ops) 2584 return __f; 2585 2586 return NULL; 2587 } 2588 2589 /* 2590 * Registers read & write functions. 2591 */ 2592 #ifdef __NetBSD__ 2593 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2594 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2595 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2596 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2597 #else 2598 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2599 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2600 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2601 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2602 #endif 2603 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2604 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2605 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2606 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2607 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2608 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2609 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2610 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2611 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2612 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2613 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2614 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2615 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2616 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2617 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2618 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2619 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2620 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2621 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2622 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2623 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2624 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2625 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2626 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2627 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2628 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2629 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2630 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2631 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2632 #define WREG32_P(reg, val, mask) \ 2633 do { \ 2634 uint32_t tmp_ = RREG32(reg); \ 2635 tmp_ &= (mask); \ 2636 tmp_ |= ((val) & ~(mask)); \ 2637 WREG32(reg, tmp_); \ 2638 } while (0) 2639 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2640 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2641 #define WREG32_PLL_P(reg, val, mask) \ 2642 do { \ 2643 uint32_t tmp_ = RREG32_PLL(reg); \ 2644 tmp_ &= (mask); \ 2645 tmp_ |= ((val) & ~(mask)); \ 2646 WREG32_PLL(reg, tmp_); \ 2647 } while (0) 2648 #define WREG32_SMC_P(reg, val, mask) \ 2649 do { \ 2650 uint32_t tmp_ = RREG32_SMC(reg); \ 2651 tmp_ &= (mask); \ 2652 tmp_ |= ((val) & ~(mask)); \ 2653 WREG32_SMC(reg, tmp_); \ 2654 } while (0) 2655 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2656 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2657 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2658 2659 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2660 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2661 2662 /* 2663 * Indirect registers accessors. 2664 * They used to be inlined, but this increases code size by ~65 kbytes. 2665 * Since each performs a pair of MMIO ops 2666 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2667 * the cost of call+ret is almost negligible. MMIO and locking 2668 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2669 */ 2670 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2671 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2672 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2673 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2674 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2675 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2676 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2677 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2678 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2679 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2680 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2681 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2682 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2683 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2684 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2685 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2686 2687 void r100_pll_errata_after_index(struct radeon_device *rdev); 2688 2689 2690 /* 2691 * ASICs helpers. 2692 */ 2693 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2694 (rdev->pdev->device == 0x5969)) 2695 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2696 (rdev->family == CHIP_RV200) || \ 2697 (rdev->family == CHIP_RS100) || \ 2698 (rdev->family == CHIP_RS200) || \ 2699 (rdev->family == CHIP_RV250) || \ 2700 (rdev->family == CHIP_RV280) || \ 2701 (rdev->family == CHIP_RS300)) 2702 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2703 (rdev->family == CHIP_RV350) || \ 2704 (rdev->family == CHIP_R350) || \ 2705 (rdev->family == CHIP_RV380) || \ 2706 (rdev->family == CHIP_R420) || \ 2707 (rdev->family == CHIP_R423) || \ 2708 (rdev->family == CHIP_RV410) || \ 2709 (rdev->family == CHIP_RS400) || \ 2710 (rdev->family == CHIP_RS480)) 2711 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2712 (rdev->ddev->pdev->device == 0x9443) || \ 2713 (rdev->ddev->pdev->device == 0x944B) || \ 2714 (rdev->ddev->pdev->device == 0x9506) || \ 2715 (rdev->ddev->pdev->device == 0x9509) || \ 2716 (rdev->ddev->pdev->device == 0x950F) || \ 2717 (rdev->ddev->pdev->device == 0x689C) || \ 2718 (rdev->ddev->pdev->device == 0x689D)) 2719 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2720 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2721 (rdev->family == CHIP_RS690) || \ 2722 (rdev->family == CHIP_RS740) || \ 2723 (rdev->family >= CHIP_R600)) 2724 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2725 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2726 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2727 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2728 (rdev->flags & RADEON_IS_IGP)) 2729 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2730 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2731 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2732 (rdev->flags & RADEON_IS_IGP)) 2733 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2734 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2735 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2736 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2737 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2738 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2739 (rdev->family == CHIP_MULLINS)) 2740 2741 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2742 (rdev->ddev->pdev->device == 0x6850) || \ 2743 (rdev->ddev->pdev->device == 0x6858) || \ 2744 (rdev->ddev->pdev->device == 0x6859) || \ 2745 (rdev->ddev->pdev->device == 0x6840) || \ 2746 (rdev->ddev->pdev->device == 0x6841) || \ 2747 (rdev->ddev->pdev->device == 0x6842) || \ 2748 (rdev->ddev->pdev->device == 0x6843)) 2749 2750 /* 2751 * BIOS helpers. 2752 */ 2753 #define RBIOS8(i) (rdev->bios[i]) 2754 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2755 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2756 2757 int radeon_combios_init(struct radeon_device *rdev); 2758 void radeon_combios_fini(struct radeon_device *rdev); 2759 int radeon_atombios_init(struct radeon_device *rdev); 2760 void radeon_atombios_fini(struct radeon_device *rdev); 2761 2762 2763 /* 2764 * RING helpers. 2765 */ 2766 2767 /** 2768 * radeon_ring_write - write a value to the ring 2769 * 2770 * @ring: radeon_ring structure holding ring information 2771 * @v: dword (dw) value to write 2772 * 2773 * Write a value to the requested ring buffer (all asics). 2774 */ 2775 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2776 { 2777 if (ring->count_dw <= 0) 2778 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2779 2780 ring->ring[ring->wptr++] = v; 2781 ring->wptr &= ring->ptr_mask; 2782 ring->count_dw--; 2783 ring->ring_free_dw--; 2784 } 2785 2786 /* 2787 * ASICs macro. 2788 */ 2789 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2790 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2791 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2792 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2793 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2794 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2795 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2796 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2797 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2798 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2799 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2800 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2801 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2802 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2803 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2804 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2805 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2806 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2807 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2808 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2809 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2810 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2811 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2812 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2813 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2814 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2815 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2816 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2817 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2818 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2819 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2820 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2821 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2822 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2823 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2824 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2825 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2826 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2827 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2828 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2829 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2830 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2831 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2832 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2833 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2834 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2835 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2836 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2837 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2838 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2839 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2840 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2841 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2842 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2843 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2844 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2845 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2846 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2847 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2848 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2849 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2850 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2851 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2852 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2853 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2854 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2855 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2856 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2857 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2858 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2859 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2860 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2861 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2862 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2863 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2864 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2865 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2866 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2867 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2868 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2869 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2870 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2871 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2872 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2873 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2874 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2875 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2876 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2877 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2878 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2879 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2880 2881 /* Common functions */ 2882 /* AGP */ 2883 extern int radeon_gpu_reset(struct radeon_device *rdev); 2884 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2885 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2886 extern void radeon_agp_disable(struct radeon_device *rdev); 2887 extern int radeon_modeset_init(struct radeon_device *rdev); 2888 extern void radeon_modeset_fini(struct radeon_device *rdev); 2889 extern bool radeon_card_posted(struct radeon_device *rdev); 2890 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2891 extern void radeon_update_display_priority(struct radeon_device *rdev); 2892 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2893 extern void radeon_scratch_init(struct radeon_device *rdev); 2894 extern void radeon_wb_fini(struct radeon_device *rdev); 2895 extern int radeon_wb_init(struct radeon_device *rdev); 2896 extern void radeon_wb_disable(struct radeon_device *rdev); 2897 extern void radeon_surface_init(struct radeon_device *rdev); 2898 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2899 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2900 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2901 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2902 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2903 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2904 uint32_t flags); 2905 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2906 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2907 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2908 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2909 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2910 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2911 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2912 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2913 const u32 *registers, 2914 const u32 array_size); 2915 2916 /* 2917 * vm 2918 */ 2919 int radeon_vm_manager_init(struct radeon_device *rdev); 2920 void radeon_vm_manager_fini(struct radeon_device *rdev); 2921 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2922 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2923 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2924 struct radeon_vm *vm, 2925 struct list_head *head); 2926 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2927 struct radeon_vm *vm, int ring); 2928 void radeon_vm_flush(struct radeon_device *rdev, 2929 struct radeon_vm *vm, 2930 int ring, struct radeon_fence *fence); 2931 void radeon_vm_fence(struct radeon_device *rdev, 2932 struct radeon_vm *vm, 2933 struct radeon_fence *fence); 2934 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2935 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2936 struct radeon_vm *vm); 2937 int radeon_vm_clear_freed(struct radeon_device *rdev, 2938 struct radeon_vm *vm); 2939 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2940 struct radeon_vm *vm); 2941 int radeon_vm_bo_update(struct radeon_device *rdev, 2942 struct radeon_bo_va *bo_va, 2943 struct ttm_mem_reg *mem); 2944 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2945 struct radeon_bo *bo); 2946 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2947 struct radeon_bo *bo); 2948 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2949 struct radeon_vm *vm, 2950 struct radeon_bo *bo); 2951 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2952 struct radeon_bo_va *bo_va, 2953 uint64_t offset, 2954 uint32_t flags); 2955 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2956 struct radeon_bo_va *bo_va); 2957 2958 /* audio */ 2959 void r600_audio_update_hdmi(struct work_struct *work); 2960 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2961 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2962 void r600_audio_enable(struct radeon_device *rdev, 2963 struct r600_audio_pin *pin, 2964 u8 enable_mask); 2965 void dce6_audio_enable(struct radeon_device *rdev, 2966 struct r600_audio_pin *pin, 2967 u8 enable_mask); 2968 2969 /* 2970 * R600 vram scratch functions 2971 */ 2972 int r600_vram_scratch_init(struct radeon_device *rdev); 2973 void r600_vram_scratch_fini(struct radeon_device *rdev); 2974 2975 /* 2976 * r600 cs checking helper 2977 */ 2978 unsigned r600_mip_minify(unsigned size, unsigned level); 2979 bool r600_fmt_is_valid_color(u32 format); 2980 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2981 int r600_fmt_get_blocksize(u32 format); 2982 int r600_fmt_get_nblocksx(u32 format, u32 w); 2983 int r600_fmt_get_nblocksy(u32 format, u32 h); 2984 2985 /* 2986 * r600 functions used by radeon_encoder.c 2987 */ 2988 struct radeon_hdmi_acr { 2989 u32 clock; 2990 2991 int n_32khz; 2992 int cts_32khz; 2993 2994 int n_44_1khz; 2995 int cts_44_1khz; 2996 2997 int n_48khz; 2998 int cts_48khz; 2999 3000 }; 3001 3002 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3003 3004 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3005 u32 tiling_pipe_num, 3006 u32 max_rb_num, 3007 u32 total_max_rb_num, 3008 u32 enabled_rb_mask); 3009 3010 /* 3011 * evergreen functions used by radeon_encoder.c 3012 */ 3013 3014 extern int ni_init_microcode(struct radeon_device *rdev); 3015 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3016 3017 /* radeon_acpi.c */ 3018 #if defined(CONFIG_ACPI) 3019 extern int radeon_acpi_init(struct radeon_device *rdev); 3020 extern void radeon_acpi_fini(struct radeon_device *rdev); 3021 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3022 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3023 u8 perf_req, bool advertise); 3024 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3025 #else 3026 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3027 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3028 #endif 3029 3030 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3031 struct radeon_cs_packet *pkt, 3032 unsigned idx); 3033 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3034 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3035 struct radeon_cs_packet *pkt); 3036 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3037 struct radeon_bo_list **cs_reloc, 3038 int nomm); 3039 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3040 uint32_t *vline_start_end, 3041 uint32_t *vline_status); 3042 3043 #include "radeon_object.h" 3044 3045 #endif 3046
Indexes created Wed Oct 01 13:09:50 GMT 2025