radeon.h revision 1.5
1 /* $NetBSD: radeon.h,v 1.5 2018/08/27 06:38:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <asm/byteorder.h> 66 #include <linux/atomic.h> 67 #include <linux/wait.h> 68 #include <linux/list.h> 69 #include <linux/kref.h> 70 #include <linux/interval_tree.h> 71 #include <linux/hashtable.h> 72 #include <linux/fence.h> 73 #include <linux/device.h> 74 #include <linux/log2.h> 75 #include <linux/notifier.h> 76 #include <linux/printk.h> 77 #include <linux/rwsem.h> 78 79 #include <ttm/ttm_bo_api.h> 80 #include <ttm/ttm_bo_driver.h> 81 #include <ttm/ttm_placement.h> 82 #include <ttm/ttm_module.h> 83 #include <ttm/ttm_execbuf_util.h> 84 85 #include <drm/drm_gem.h> 86 87 #include "radeon_family.h" 88 #include "radeon_mode.h" 89 #include "radeon_reg.h" 90 91 /* 92 * Modules parameters. 93 */ 94 extern int radeon_no_wb; 95 extern int radeon_modeset; 96 extern int radeon_dynclks; 97 extern int radeon_r4xx_atom; 98 extern int radeon_agpmode; 99 extern int radeon_vram_limit; 100 extern int radeon_gart_size; 101 extern int radeon_benchmarking; 102 extern int radeon_testing; 103 extern int radeon_connector_table; 104 extern int radeon_tv; 105 extern int radeon_audio; 106 extern int radeon_disp_priority; 107 extern int radeon_hw_i2c; 108 extern int radeon_pcie_gen2; 109 extern int radeon_msi; 110 extern int radeon_lockup_timeout; 111 extern int radeon_fastfb; 112 extern int radeon_dpm; 113 extern int radeon_aspm; 114 extern int radeon_runtime_pm; 115 extern int radeon_hard_reset; 116 extern int radeon_vm_size; 117 extern int radeon_vm_block_size; 118 extern int radeon_deep_color; 119 extern int radeon_use_pflipirq; 120 extern int radeon_bapm; 121 extern int radeon_backlight; 122 extern int radeon_auxch; 123 extern int radeon_mst; 124 125 /* 126 * Copy from radeon_drv.h so we don't have to include both and have conflicting 127 * symbol; 128 */ 129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 130 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 #ifdef __NetBSD__ 246 extern struct radeon_device *radeon_device_private(device_t); 247 #endif 248 249 /* 250 * BIOS. 251 */ 252 bool radeon_get_bios(struct radeon_device *rdev); 253 254 /* 255 * Dummy page 256 */ 257 struct radeon_dummy_page { 258 uint64_t entry; 259 #ifdef __NetBSD__ 260 bus_dma_segment_t rdp_seg; 261 bus_dmamap_t rdp_map; 262 #else 263 struct page *page; 264 #endif 265 dma_addr_t addr; 266 }; 267 int radeon_dummy_page_init(struct radeon_device *rdev); 268 void radeon_dummy_page_fini(struct radeon_device *rdev); 269 270 271 /* 272 * Clocks 273 */ 274 struct radeon_clock { 275 struct radeon_pll p1pll; 276 struct radeon_pll p2pll; 277 struct radeon_pll dcpll; 278 struct radeon_pll spll; 279 struct radeon_pll mpll; 280 /* 10 Khz units */ 281 uint32_t default_mclk; 282 uint32_t default_sclk; 283 uint32_t default_dispclk; 284 uint32_t current_dispclk; 285 uint32_t dp_extclk; 286 uint32_t max_pixel_clock; 287 uint32_t vco_freq; 288 }; 289 290 /* 291 * Power management 292 */ 293 int radeon_pm_init(struct radeon_device *rdev); 294 int radeon_pm_late_init(struct radeon_device *rdev); 295 void radeon_pm_fini(struct radeon_device *rdev); 296 void radeon_pm_compute_clocks(struct radeon_device *rdev); 297 void radeon_pm_suspend(struct radeon_device *rdev); 298 void radeon_pm_resume(struct radeon_device *rdev); 299 void radeon_combios_get_power_modes(struct radeon_device *rdev); 300 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 301 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 302 u8 clock_type, 303 u32 clock, 304 bool strobe_mode, 305 struct atom_clock_dividers *dividers); 306 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 307 u32 clock, 308 bool strobe_mode, 309 struct atom_mpll_param *mpll_param); 310 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 311 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 312 u16 voltage_level, u8 voltage_type, 313 u32 *gpio_value, u32 *gpio_mask); 314 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 315 u32 eng_clock, u32 mem_clock); 316 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 317 u8 voltage_type, u16 *voltage_step); 318 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 319 u16 voltage_id, u16 *voltage); 320 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 321 u16 *voltage, 322 u16 leakage_idx); 323 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 324 u16 *leakage_id); 325 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 326 u16 *vddc, u16 *vddci, 327 u16 virtual_voltage_id, 328 u16 vbios_voltage_id); 329 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 330 u16 virtual_voltage_id, 331 u16 *voltage); 332 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 333 u8 voltage_type, 334 u16 nominal_voltage, 335 u16 *true_voltage); 336 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 337 u8 voltage_type, u16 *min_voltage); 338 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 339 u8 voltage_type, u16 *max_voltage); 340 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 341 u8 voltage_type, u8 voltage_mode, 342 struct atom_voltage_table *voltage_table); 343 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 344 u8 voltage_type, u8 voltage_mode); 345 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 346 u8 voltage_type, 347 u8 *svd_gpio_id, u8 *svc_gpio_id); 348 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 349 u32 mem_clock); 350 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 351 u32 mem_clock); 352 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 353 u8 module_index, 354 struct atom_mc_reg_table *reg_table); 355 int radeon_atom_get_memory_info(struct radeon_device *rdev, 356 u8 module_index, struct atom_memory_info *mem_info); 357 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 358 bool gddr5, u8 module_index, 359 struct atom_memory_clock_range_table *mclk_range_table); 360 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 361 u16 voltage_id, u16 *voltage); 362 void rs690_pm_info(struct radeon_device *rdev); 363 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 364 unsigned *bankh, unsigned *mtaspect, 365 unsigned *tile_split); 366 367 /* 368 * Fences. 369 */ 370 struct radeon_fence_driver { 371 struct radeon_device *rdev; 372 uint32_t scratch_reg; 373 uint64_t gpu_addr; 374 volatile uint32_t *cpu_addr; 375 /* sync_seq is protected by ring emission lock */ 376 uint64_t sync_seq[RADEON_NUM_RINGS]; 377 atomic64_t last_seq; 378 bool initialized, delayed_irq; 379 struct delayed_work lockup_work; 380 }; 381 382 struct radeon_fence { 383 struct fence base; 384 385 struct radeon_device *rdev; 386 uint64_t seq; 387 /* RB, DMA, etc. */ 388 unsigned ring; 389 bool is_vm_update; 390 391 #ifdef __NetBSD__ 392 TAILQ_ENTRY(radeon_fence) fence_check; 393 #else 394 wait_queue_t fence_wake; 395 #endif 396 }; 397 398 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 399 int radeon_fence_driver_init(struct radeon_device *rdev); 400 void radeon_fence_driver_fini(struct radeon_device *rdev); 401 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 402 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 403 void radeon_fence_wakeup_locked(struct radeon_device *rdev); 404 void radeon_fence_process(struct radeon_device *rdev, int ring); 405 bool radeon_fence_signaled(struct radeon_fence *fence); 406 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 407 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 408 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 409 int radeon_fence_wait_any(struct radeon_device *rdev, 410 struct radeon_fence **fences, 411 bool intr); 412 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 413 void radeon_fence_unref(struct radeon_fence **fence); 414 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 415 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 416 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 417 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 418 struct radeon_fence *b) 419 { 420 if (!a) { 421 return b; 422 } 423 424 if (!b) { 425 return a; 426 } 427 428 BUG_ON(a->ring != b->ring); 429 430 if (a->seq > b->seq) { 431 return a; 432 } else { 433 return b; 434 } 435 } 436 437 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 438 struct radeon_fence *b) 439 { 440 if (!a) { 441 return false; 442 } 443 444 if (!b) { 445 return true; 446 } 447 448 BUG_ON(a->ring != b->ring); 449 450 return a->seq < b->seq; 451 } 452 453 /* 454 * Tiling registers 455 */ 456 struct radeon_surface_reg { 457 struct radeon_bo *bo; 458 }; 459 460 #define RADEON_GEM_MAX_SURFACES 8 461 462 /* 463 * TTM. 464 */ 465 struct radeon_mman { 466 struct ttm_bo_global_ref bo_global_ref; 467 struct drm_global_reference mem_global_ref; 468 struct ttm_bo_device bdev; 469 bool mem_global_referenced; 470 bool initialized; 471 472 #if defined(CONFIG_DEBUG_FS) 473 struct dentry *vram; 474 struct dentry *gtt; 475 #endif 476 }; 477 478 struct radeon_bo_list { 479 struct radeon_bo *robj; 480 struct ttm_validate_buffer tv; 481 uint64_t gpu_offset; 482 unsigned prefered_domains; 483 unsigned allowed_domains; 484 uint32_t tiling_flags; 485 }; 486 487 /* bo virtual address in a specific vm */ 488 struct radeon_bo_va { 489 /* protected by bo being reserved */ 490 struct list_head bo_list; 491 uint32_t flags; 492 struct radeon_fence *last_pt_update; 493 unsigned ref_count; 494 495 /* protected by vm mutex */ 496 struct interval_tree_node it; 497 struct list_head vm_status; 498 499 /* constant after initialization */ 500 struct radeon_vm *vm; 501 struct radeon_bo *bo; 502 }; 503 504 struct radeon_bo { 505 /* Protected by gem.mutex */ 506 struct list_head list; 507 /* Protected by tbo.reserved */ 508 u32 initial_domain; 509 struct ttm_place placements[4]; 510 struct ttm_placement placement; 511 struct ttm_buffer_object tbo; 512 struct ttm_bo_kmap_obj kmap; 513 u32 flags; 514 unsigned pin_count; 515 void *kptr; 516 u32 tiling_flags; 517 u32 pitch; 518 int surface_reg; 519 /* list of all virtual address to which this bo 520 * is associated to 521 */ 522 struct list_head va; 523 /* Constant after initialization */ 524 struct radeon_device *rdev; 525 struct drm_gem_object gem_base; 526 527 struct ttm_bo_kmap_obj dma_buf_vmap; 528 #ifndef __NetBSD__ /* XXX pid??? */ 529 pid_t pid; 530 #endif 531 532 struct radeon_mn *mn; 533 struct list_head mn_list; 534 }; 535 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 536 537 int radeon_gem_debugfs_init(struct radeon_device *rdev); 538 539 /* sub-allocation manager, it has to be protected by another lock. 540 * By conception this is an helper for other part of the driver 541 * like the indirect buffer or semaphore, which both have their 542 * locking. 543 * 544 * Principe is simple, we keep a list of sub allocation in offset 545 * order (first entry has offset == 0, last entry has the highest 546 * offset). 547 * 548 * When allocating new object we first check if there is room at 549 * the end total_size - (last_object_offset + last_object_size) >= 550 * alloc_size. If so we allocate new object there. 551 * 552 * When there is not enough room at the end, we start waiting for 553 * each sub object until we reach object_offset+object_size >= 554 * alloc_size, this object then become the sub object we return. 555 * 556 * Alignment can't be bigger than page size. 557 * 558 * Hole are not considered for allocation to keep things simple. 559 * Assumption is that there won't be hole (all object on same 560 * alignment). 561 */ 562 struct radeon_sa_manager { 563 #ifdef __NetBSD__ 564 spinlock_t wq_lock; 565 drm_waitqueue_t wq; 566 #else 567 wait_queue_head_t wq; 568 #endif 569 struct radeon_bo *bo; 570 struct list_head *hole; 571 struct list_head flist[RADEON_NUM_RINGS]; 572 struct list_head olist; 573 unsigned size; 574 uint64_t gpu_addr; 575 void *cpu_ptr; 576 uint32_t domain; 577 uint32_t align; 578 }; 579 580 struct radeon_sa_bo; 581 582 /* sub-allocation buffer */ 583 struct radeon_sa_bo { 584 struct list_head olist; 585 struct list_head flist; 586 struct radeon_sa_manager *manager; 587 unsigned soffset; 588 unsigned eoffset; 589 struct radeon_fence *fence; 590 }; 591 592 /* 593 * GEM objects. 594 */ 595 struct radeon_gem { 596 struct mutex mutex; 597 struct list_head objects; 598 }; 599 600 int radeon_gem_init(struct radeon_device *rdev); 601 void radeon_gem_fini(struct radeon_device *rdev); 602 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 603 int alignment, int initial_domain, 604 u32 flags, bool kernel, 605 struct drm_gem_object **obj); 606 607 int radeon_mode_dumb_create(struct drm_file *file_priv, 608 struct drm_device *dev, 609 struct drm_mode_create_dumb *args); 610 int radeon_mode_dumb_mmap(struct drm_file *filp, 611 struct drm_device *dev, 612 uint32_t handle, uint64_t *offset_p); 613 614 /* 615 * Semaphores. 616 */ 617 struct radeon_semaphore { 618 struct radeon_sa_bo *sa_bo; 619 signed waiters; 620 uint64_t gpu_addr; 621 }; 622 623 int radeon_semaphore_create(struct radeon_device *rdev, 624 struct radeon_semaphore **semaphore); 625 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 626 struct radeon_semaphore *semaphore); 627 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 628 struct radeon_semaphore *semaphore); 629 void radeon_semaphore_free(struct radeon_device *rdev, 630 struct radeon_semaphore **semaphore, 631 struct radeon_fence *fence); 632 633 /* 634 * Synchronization 635 */ 636 struct radeon_sync { 637 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 638 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 639 struct radeon_fence *last_vm_update; 640 }; 641 642 void radeon_sync_create(struct radeon_sync *sync); 643 void radeon_sync_fence(struct radeon_sync *sync, 644 struct radeon_fence *fence); 645 int radeon_sync_resv(struct radeon_device *rdev, 646 struct radeon_sync *sync, 647 struct reservation_object *resv, 648 bool shared); 649 int radeon_sync_rings(struct radeon_device *rdev, 650 struct radeon_sync *sync, 651 int waiting_ring); 652 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 653 struct radeon_fence *fence); 654 655 /* 656 * GART structures, functions & helpers 657 */ 658 struct radeon_mc; 659 660 #define RADEON_GPU_PAGE_SIZE 4096 661 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 662 #define RADEON_GPU_PAGE_SHIFT 12 663 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 664 665 #define RADEON_GART_PAGE_DUMMY 0 666 #define RADEON_GART_PAGE_VALID (1 << 0) 667 #define RADEON_GART_PAGE_READ (1 << 1) 668 #define RADEON_GART_PAGE_WRITE (1 << 2) 669 #define RADEON_GART_PAGE_SNOOP (1 << 3) 670 671 struct radeon_gart { 672 #ifdef __NetBSD__ 673 bus_dma_segment_t rg_table_seg; 674 bus_dmamap_t rg_table_map; 675 #endif 676 dma_addr_t table_addr; 677 struct radeon_bo *robj; 678 void *ptr; 679 unsigned num_gpu_pages; 680 unsigned num_cpu_pages; 681 unsigned table_size; 682 struct page **pages; 683 uint64_t *pages_entry; 684 bool ready; 685 }; 686 687 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 688 void radeon_gart_table_ram_free(struct radeon_device *rdev); 689 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 690 void radeon_gart_table_vram_free(struct radeon_device *rdev); 691 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 692 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 693 int radeon_gart_init(struct radeon_device *rdev); 694 void radeon_gart_fini(struct radeon_device *rdev); 695 #ifdef __NetBSD__ 696 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 697 unsigned npages); 698 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 699 unsigned npages, struct page **pages, 700 bus_dmamap_t dmamap, uint32_t flags); 701 #else 702 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 703 int pages); 704 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 705 int pages, struct page **pagelist, 706 dma_addr_t *dma_addr, uint32_t flags); 707 #endif 708 709 710 /* 711 * GPU MC structures, functions & helpers 712 */ 713 struct radeon_mc { 714 resource_size_t aper_size; 715 resource_size_t aper_base; 716 resource_size_t agp_base; 717 /* for some chips with <= 32MB we need to lie 718 * about vram size near mc fb location */ 719 u64 mc_vram_size; 720 u64 visible_vram_size; 721 u64 gtt_size; 722 u64 gtt_start; 723 u64 gtt_end; 724 u64 vram_start; 725 u64 vram_end; 726 unsigned vram_width; 727 u64 real_vram_size; 728 int vram_mtrr; 729 bool vram_is_ddr; 730 bool igp_sideport_enabled; 731 u64 gtt_base_align; 732 u64 mc_mask; 733 }; 734 735 bool radeon_combios_sideport_present(struct radeon_device *rdev); 736 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 737 738 /* 739 * GPU scratch registers structures, functions & helpers 740 */ 741 struct radeon_scratch { 742 unsigned num_reg; 743 uint32_t reg_base; 744 bool free[32]; 745 uint32_t reg[32]; 746 }; 747 748 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 749 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 750 751 /* 752 * GPU doorbell structures, functions & helpers 753 */ 754 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 755 756 struct radeon_doorbell { 757 /* doorbell mmio */ 758 resource_size_t base; 759 resource_size_t size; 760 #ifdef __NetBSD__ 761 bus_space_tag_t bst; 762 bus_space_handle_t bsh; 763 #else 764 u32 __iomem *ptr; 765 #endif 766 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 767 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 768 }; 769 770 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 771 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 772 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 773 phys_addr_t *aperture_base, 774 size_t *aperture_size, 775 size_t *start_offset); 776 777 /* 778 * IRQS. 779 */ 780 781 struct radeon_flip_work { 782 struct work_struct flip_work; 783 struct work_struct unpin_work; 784 struct radeon_device *rdev; 785 int crtc_id; 786 uint64_t base; 787 struct drm_pending_vblank_event *event; 788 struct radeon_bo *old_rbo; 789 struct fence *fence; 790 }; 791 792 struct r500_irq_stat_regs { 793 u32 disp_int; 794 u32 hdmi0_status; 795 }; 796 797 struct r600_irq_stat_regs { 798 u32 disp_int; 799 u32 disp_int_cont; 800 u32 disp_int_cont2; 801 u32 d1grph_int; 802 u32 d2grph_int; 803 u32 hdmi0_status; 804 u32 hdmi1_status; 805 }; 806 807 struct evergreen_irq_stat_regs { 808 u32 disp_int; 809 u32 disp_int_cont; 810 u32 disp_int_cont2; 811 u32 disp_int_cont3; 812 u32 disp_int_cont4; 813 u32 disp_int_cont5; 814 u32 d1grph_int; 815 u32 d2grph_int; 816 u32 d3grph_int; 817 u32 d4grph_int; 818 u32 d5grph_int; 819 u32 d6grph_int; 820 u32 afmt_status1; 821 u32 afmt_status2; 822 u32 afmt_status3; 823 u32 afmt_status4; 824 u32 afmt_status5; 825 u32 afmt_status6; 826 }; 827 828 struct cik_irq_stat_regs { 829 u32 disp_int; 830 u32 disp_int_cont; 831 u32 disp_int_cont2; 832 u32 disp_int_cont3; 833 u32 disp_int_cont4; 834 u32 disp_int_cont5; 835 u32 disp_int_cont6; 836 u32 d1grph_int; 837 u32 d2grph_int; 838 u32 d3grph_int; 839 u32 d4grph_int; 840 u32 d5grph_int; 841 u32 d6grph_int; 842 }; 843 844 union radeon_irq_stat_regs { 845 struct r500_irq_stat_regs r500; 846 struct r600_irq_stat_regs r600; 847 struct evergreen_irq_stat_regs evergreen; 848 struct cik_irq_stat_regs cik; 849 }; 850 851 struct radeon_irq { 852 bool installed; 853 spinlock_t lock; 854 atomic_t ring_int[RADEON_NUM_RINGS]; 855 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 856 atomic_t pflip[RADEON_MAX_CRTCS]; 857 #ifdef __NetBSD__ 858 spinlock_t vblank_lock; 859 drm_waitqueue_t vblank_queue; 860 #else 861 wait_queue_head_t vblank_queue; 862 #endif 863 bool hpd[RADEON_MAX_HPD_PINS]; 864 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 865 union radeon_irq_stat_regs stat_regs; 866 bool dpm_thermal; 867 }; 868 869 int radeon_irq_kms_init(struct radeon_device *rdev); 870 void radeon_irq_kms_fini(struct radeon_device *rdev); 871 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 872 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 873 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 874 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 875 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 876 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 877 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 878 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 879 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 880 881 /* 882 * CP & rings. 883 */ 884 885 struct radeon_ib { 886 struct radeon_sa_bo *sa_bo; 887 uint32_t length_dw; 888 uint64_t gpu_addr; 889 uint32_t *ptr; 890 int ring; 891 struct radeon_fence *fence; 892 struct radeon_vm *vm; 893 bool is_const_ib; 894 struct radeon_sync sync; 895 }; 896 897 struct radeon_ring { 898 struct radeon_bo *ring_obj; 899 volatile uint32_t *ring; 900 unsigned rptr_offs; 901 unsigned rptr_save_reg; 902 u64 next_rptr_gpu_addr; 903 volatile u32 *next_rptr_cpu_addr; 904 unsigned wptr; 905 unsigned wptr_old; 906 unsigned ring_size; 907 unsigned ring_free_dw; 908 int count_dw; 909 atomic_t last_rptr; 910 atomic64_t last_activity; 911 uint64_t gpu_addr; 912 uint32_t align_mask; 913 uint32_t ptr_mask; 914 bool ready; 915 u32 nop; 916 u32 idx; 917 u64 last_semaphore_signal_addr; 918 u64 last_semaphore_wait_addr; 919 /* for CIK queues */ 920 u32 me; 921 u32 pipe; 922 u32 queue; 923 struct radeon_bo *mqd_obj; 924 u32 doorbell_index; 925 unsigned wptr_offs; 926 }; 927 928 struct radeon_mec { 929 struct radeon_bo *hpd_eop_obj; 930 u64 hpd_eop_gpu_addr; 931 u32 num_pipe; 932 u32 num_mec; 933 u32 num_queue; 934 }; 935 936 /* 937 * VM 938 */ 939 940 /* maximum number of VMIDs */ 941 #define RADEON_NUM_VM 16 942 943 /* number of entries in page table */ 944 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 945 946 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 947 #define RADEON_VM_PTB_ALIGN_SIZE 32768 948 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 949 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 950 951 #define R600_PTE_VALID (1 << 0) 952 #define R600_PTE_SYSTEM (1 << 1) 953 #define R600_PTE_SNOOPED (1 << 2) 954 #define R600_PTE_READABLE (1 << 5) 955 #define R600_PTE_WRITEABLE (1 << 6) 956 957 /* PTE (Page Table Entry) fragment field for different page sizes */ 958 #define R600_PTE_FRAG_4KB (0 << 7) 959 #define R600_PTE_FRAG_64KB (4 << 7) 960 #define R600_PTE_FRAG_256KB (6 << 7) 961 962 /* flags needed to be set so we can copy directly from the GART table */ 963 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 964 R600_PTE_SYSTEM | R600_PTE_VALID ) 965 966 struct radeon_vm_pt { 967 struct radeon_bo *bo; 968 uint64_t addr; 969 }; 970 971 struct radeon_vm_id { 972 unsigned id; 973 uint64_t pd_gpu_addr; 974 /* last flushed PD/PT update */ 975 struct radeon_fence *flushed_updates; 976 /* last use of vmid */ 977 struct radeon_fence *last_id_use; 978 }; 979 980 struct radeon_vm { 981 struct mutex mutex; 982 983 struct rb_root va; 984 985 /* protecting invalidated and freed */ 986 spinlock_t status_lock; 987 988 /* BOs moved, but not yet updated in the PT */ 989 struct list_head invalidated; 990 991 /* BOs freed, but not yet updated in the PT */ 992 struct list_head freed; 993 994 /* BOs cleared in the PT */ 995 struct list_head cleared; 996 997 /* contains the page directory */ 998 struct radeon_bo *page_directory; 999 unsigned max_pde_used; 1000 1001 /* array of page tables, one for each page directory entry */ 1002 struct radeon_vm_pt *page_tables; 1003 1004 struct radeon_bo_va *ib_bo_va; 1005 1006 /* for id and flush management per ring */ 1007 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 1008 }; 1009 1010 struct radeon_vm_manager { 1011 struct radeon_fence *active[RADEON_NUM_VM]; 1012 uint32_t max_pfn; 1013 /* number of VMIDs */ 1014 unsigned nvm; 1015 /* vram base address for page table entry */ 1016 u64 vram_base_offset; 1017 /* is vm enabled? */ 1018 bool enabled; 1019 /* for hw to save the PD addr on suspend/resume */ 1020 uint32_t saved_table_addr[RADEON_NUM_VM]; 1021 }; 1022 1023 /* 1024 * file private structure 1025 */ 1026 struct radeon_fpriv { 1027 struct radeon_vm vm; 1028 }; 1029 1030 /* 1031 * R6xx+ IH ring 1032 */ 1033 struct r600_ih { 1034 struct radeon_bo *ring_obj; 1035 volatile uint32_t *ring; 1036 unsigned rptr; 1037 unsigned ring_size; 1038 uint64_t gpu_addr; 1039 uint32_t ptr_mask; 1040 atomic_t lock; 1041 bool enabled; 1042 }; 1043 1044 /* 1045 * RLC stuff 1046 */ 1047 #include "clearstate_defs.h" 1048 1049 struct radeon_rlc { 1050 /* for power gating */ 1051 struct radeon_bo *save_restore_obj; 1052 uint64_t save_restore_gpu_addr; 1053 volatile uint32_t *sr_ptr; 1054 const u32 *reg_list; 1055 u32 reg_list_size; 1056 /* for clear state */ 1057 struct radeon_bo *clear_state_obj; 1058 uint64_t clear_state_gpu_addr; 1059 volatile uint32_t *cs_ptr; 1060 const struct cs_section_def *cs_data; 1061 u32 clear_state_size; 1062 /* for cp tables */ 1063 struct radeon_bo *cp_table_obj; 1064 uint64_t cp_table_gpu_addr; 1065 volatile uint32_t *cp_table_ptr; 1066 u32 cp_table_size; 1067 }; 1068 1069 int radeon_ib_get(struct radeon_device *rdev, int ring, 1070 struct radeon_ib *ib, struct radeon_vm *vm, 1071 unsigned size); 1072 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1073 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1074 struct radeon_ib *const_ib, bool hdp_flush); 1075 int radeon_ib_pool_init(struct radeon_device *rdev); 1076 void radeon_ib_pool_fini(struct radeon_device *rdev); 1077 int radeon_ib_ring_tests(struct radeon_device *rdev); 1078 /* Ring access between begin & end cannot sleep */ 1079 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1080 struct radeon_ring *ring); 1081 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1082 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1083 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1084 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1085 bool hdp_flush); 1086 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1087 bool hdp_flush); 1088 void radeon_ring_undo(struct radeon_ring *ring); 1089 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1090 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1091 void radeon_ring_lockup_update(struct radeon_device *rdev, 1092 struct radeon_ring *ring); 1093 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1094 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1095 uint32_t **data); 1096 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1097 unsigned size, uint32_t *data); 1098 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1099 unsigned rptr_offs, u32 nop); 1100 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1101 1102 1103 /* r600 async dma */ 1104 void r600_dma_stop(struct radeon_device *rdev); 1105 int r600_dma_resume(struct radeon_device *rdev); 1106 void r600_dma_fini(struct radeon_device *rdev); 1107 1108 void cayman_dma_stop(struct radeon_device *rdev); 1109 int cayman_dma_resume(struct radeon_device *rdev); 1110 void cayman_dma_fini(struct radeon_device *rdev); 1111 1112 /* 1113 * CS. 1114 */ 1115 struct radeon_cs_chunk { 1116 uint32_t length_dw; 1117 uint32_t *kdata; 1118 void __user *user_ptr; 1119 }; 1120 1121 struct radeon_cs_parser { 1122 struct device *dev; 1123 struct radeon_device *rdev; 1124 struct drm_file *filp; 1125 /* chunks */ 1126 unsigned nchunks; 1127 struct radeon_cs_chunk *chunks; 1128 uint64_t *chunks_array; 1129 /* IB */ 1130 unsigned idx; 1131 /* relocations */ 1132 unsigned nrelocs; 1133 struct radeon_bo_list *relocs; 1134 struct radeon_bo_list *vm_bos; 1135 struct list_head validated; 1136 unsigned dma_reloc_idx; 1137 /* indices of various chunks */ 1138 struct radeon_cs_chunk *chunk_ib; 1139 struct radeon_cs_chunk *chunk_relocs; 1140 struct radeon_cs_chunk *chunk_flags; 1141 struct radeon_cs_chunk *chunk_const_ib; 1142 struct radeon_ib ib; 1143 struct radeon_ib const_ib; 1144 void *track; 1145 unsigned family; 1146 int parser_error; 1147 u32 cs_flags; 1148 u32 ring; 1149 s32 priority; 1150 struct ww_acquire_ctx ticket; 1151 }; 1152 1153 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1154 { 1155 struct radeon_cs_chunk *ibc = p->chunk_ib; 1156 1157 if (ibc->kdata) 1158 return ibc->kdata[idx]; 1159 return p->ib.ptr[idx]; 1160 } 1161 1162 1163 struct radeon_cs_packet { 1164 unsigned idx; 1165 unsigned type; 1166 unsigned reg; 1167 unsigned opcode; 1168 int count; 1169 unsigned one_reg_wr; 1170 }; 1171 1172 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1173 struct radeon_cs_packet *pkt, 1174 unsigned idx, unsigned reg); 1175 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1176 struct radeon_cs_packet *pkt); 1177 1178 1179 /* 1180 * AGP 1181 */ 1182 int radeon_agp_init(struct radeon_device *rdev); 1183 void radeon_agp_resume(struct radeon_device *rdev); 1184 void radeon_agp_suspend(struct radeon_device *rdev); 1185 void radeon_agp_fini(struct radeon_device *rdev); 1186 1187 1188 /* 1189 * Writeback 1190 */ 1191 struct radeon_wb { 1192 struct radeon_bo *wb_obj; 1193 volatile uint32_t *wb; 1194 uint64_t gpu_addr; 1195 bool enabled; 1196 bool use_event; 1197 }; 1198 1199 #define RADEON_WB_SCRATCH_OFFSET 0 1200 #define RADEON_WB_RING0_NEXT_RPTR 256 1201 #define RADEON_WB_CP_RPTR_OFFSET 1024 1202 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1203 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1204 #define R600_WB_DMA_RPTR_OFFSET 1792 1205 #define R600_WB_IH_WPTR_OFFSET 2048 1206 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1207 #define R600_WB_EVENT_OFFSET 3072 1208 #define CIK_WB_CP1_WPTR_OFFSET 3328 1209 #define CIK_WB_CP2_WPTR_OFFSET 3584 1210 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1211 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1212 1213 /** 1214 * struct radeon_pm - power management datas 1215 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1216 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1217 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1218 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1219 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1220 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1221 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1222 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1223 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1224 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1225 * @needed_bandwidth: current bandwidth needs 1226 * 1227 * It keeps track of various data needed to take powermanagement decision. 1228 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1229 * Equation between gpu/memory clock and available bandwidth is hw dependent 1230 * (type of memory, bus size, efficiency, ...) 1231 */ 1232 1233 enum radeon_pm_method { 1234 PM_METHOD_PROFILE, 1235 PM_METHOD_DYNPM, 1236 PM_METHOD_DPM, 1237 }; 1238 1239 enum radeon_dynpm_state { 1240 DYNPM_STATE_DISABLED, 1241 DYNPM_STATE_MINIMUM, 1242 DYNPM_STATE_PAUSED, 1243 DYNPM_STATE_ACTIVE, 1244 DYNPM_STATE_SUSPENDED, 1245 }; 1246 enum radeon_dynpm_action { 1247 DYNPM_ACTION_NONE, 1248 DYNPM_ACTION_MINIMUM, 1249 DYNPM_ACTION_DOWNCLOCK, 1250 DYNPM_ACTION_UPCLOCK, 1251 DYNPM_ACTION_DEFAULT 1252 }; 1253 1254 enum radeon_voltage_type { 1255 VOLTAGE_NONE = 0, 1256 VOLTAGE_GPIO, 1257 VOLTAGE_VDDC, 1258 VOLTAGE_SW 1259 }; 1260 1261 enum radeon_pm_state_type { 1262 /* not used for dpm */ 1263 POWER_STATE_TYPE_DEFAULT, 1264 POWER_STATE_TYPE_POWERSAVE, 1265 /* user selectable states */ 1266 POWER_STATE_TYPE_BATTERY, 1267 POWER_STATE_TYPE_BALANCED, 1268 POWER_STATE_TYPE_PERFORMANCE, 1269 /* internal states */ 1270 POWER_STATE_TYPE_INTERNAL_UVD, 1271 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1272 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1273 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1274 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1275 POWER_STATE_TYPE_INTERNAL_BOOT, 1276 POWER_STATE_TYPE_INTERNAL_THERMAL, 1277 POWER_STATE_TYPE_INTERNAL_ACPI, 1278 POWER_STATE_TYPE_INTERNAL_ULV, 1279 POWER_STATE_TYPE_INTERNAL_3DPERF, 1280 }; 1281 1282 enum radeon_pm_profile_type { 1283 PM_PROFILE_DEFAULT, 1284 PM_PROFILE_AUTO, 1285 PM_PROFILE_LOW, 1286 PM_PROFILE_MID, 1287 PM_PROFILE_HIGH, 1288 }; 1289 1290 #define PM_PROFILE_DEFAULT_IDX 0 1291 #define PM_PROFILE_LOW_SH_IDX 1 1292 #define PM_PROFILE_MID_SH_IDX 2 1293 #define PM_PROFILE_HIGH_SH_IDX 3 1294 #define PM_PROFILE_LOW_MH_IDX 4 1295 #define PM_PROFILE_MID_MH_IDX 5 1296 #define PM_PROFILE_HIGH_MH_IDX 6 1297 #define PM_PROFILE_MAX 7 1298 1299 struct radeon_pm_profile { 1300 int dpms_off_ps_idx; 1301 int dpms_on_ps_idx; 1302 int dpms_off_cm_idx; 1303 int dpms_on_cm_idx; 1304 }; 1305 1306 enum radeon_int_thermal_type { 1307 THERMAL_TYPE_NONE, 1308 THERMAL_TYPE_EXTERNAL, 1309 THERMAL_TYPE_EXTERNAL_GPIO, 1310 THERMAL_TYPE_RV6XX, 1311 THERMAL_TYPE_RV770, 1312 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1313 THERMAL_TYPE_EVERGREEN, 1314 THERMAL_TYPE_SUMO, 1315 THERMAL_TYPE_NI, 1316 THERMAL_TYPE_SI, 1317 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1318 THERMAL_TYPE_CI, 1319 THERMAL_TYPE_KV, 1320 }; 1321 1322 struct radeon_voltage { 1323 enum radeon_voltage_type type; 1324 /* gpio voltage */ 1325 struct radeon_gpio_rec gpio; 1326 u32 delay; /* delay in usec from voltage drop to sclk change */ 1327 bool active_high; /* voltage drop is active when bit is high */ 1328 /* VDDC voltage */ 1329 u8 vddc_id; /* index into vddc voltage table */ 1330 u8 vddci_id; /* index into vddci voltage table */ 1331 bool vddci_enabled; 1332 /* r6xx+ sw */ 1333 u16 voltage; 1334 /* evergreen+ vddci */ 1335 u16 vddci; 1336 }; 1337 1338 /* clock mode flags */ 1339 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1340 1341 struct radeon_pm_clock_info { 1342 /* memory clock */ 1343 u32 mclk; 1344 /* engine clock */ 1345 u32 sclk; 1346 /* voltage info */ 1347 struct radeon_voltage voltage; 1348 /* standardized clock flags */ 1349 u32 flags; 1350 }; 1351 1352 /* state flags */ 1353 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1354 1355 struct radeon_power_state { 1356 enum radeon_pm_state_type type; 1357 struct radeon_pm_clock_info *clock_info; 1358 /* number of valid clock modes in this power state */ 1359 int num_clock_modes; 1360 struct radeon_pm_clock_info *default_clock_mode; 1361 /* standardized state flags */ 1362 u32 flags; 1363 u32 misc; /* vbios specific flags */ 1364 u32 misc2; /* vbios specific flags */ 1365 int pcie_lanes; /* pcie lanes */ 1366 }; 1367 1368 /* 1369 * Some modes are overclocked by very low value, accept them 1370 */ 1371 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1372 1373 enum radeon_dpm_auto_throttle_src { 1374 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1375 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1376 }; 1377 1378 enum radeon_dpm_event_src { 1379 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1380 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1381 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1382 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1383 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1384 }; 1385 1386 #define RADEON_MAX_VCE_LEVELS 6 1387 1388 enum radeon_vce_level { 1389 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1390 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1391 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1392 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1393 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1394 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1395 }; 1396 1397 struct radeon_ps { 1398 u32 caps; /* vbios flags */ 1399 u32 class; /* vbios flags */ 1400 u32 class2; /* vbios flags */ 1401 /* UVD clocks */ 1402 u32 vclk; 1403 u32 dclk; 1404 /* VCE clocks */ 1405 u32 evclk; 1406 u32 ecclk; 1407 bool vce_active; 1408 enum radeon_vce_level vce_level; 1409 /* asic priv */ 1410 void *ps_priv; 1411 }; 1412 1413 struct radeon_dpm_thermal { 1414 /* thermal interrupt work */ 1415 struct work_struct work; 1416 /* low temperature threshold */ 1417 int min_temp; 1418 /* high temperature threshold */ 1419 int max_temp; 1420 /* was interrupt low to high or high to low */ 1421 bool high_to_low; 1422 }; 1423 1424 enum radeon_clk_action 1425 { 1426 RADEON_SCLK_UP = 1, 1427 RADEON_SCLK_DOWN 1428 }; 1429 1430 struct radeon_blacklist_clocks 1431 { 1432 u32 sclk; 1433 u32 mclk; 1434 enum radeon_clk_action action; 1435 }; 1436 1437 struct radeon_clock_and_voltage_limits { 1438 u32 sclk; 1439 u32 mclk; 1440 u16 vddc; 1441 u16 vddci; 1442 }; 1443 1444 struct radeon_clock_array { 1445 u32 count; 1446 u32 *values; 1447 }; 1448 1449 struct radeon_clock_voltage_dependency_entry { 1450 u32 clk; 1451 u16 v; 1452 }; 1453 1454 struct radeon_clock_voltage_dependency_table { 1455 u32 count; 1456 struct radeon_clock_voltage_dependency_entry *entries; 1457 }; 1458 1459 union radeon_cac_leakage_entry { 1460 struct { 1461 u16 vddc; 1462 u32 leakage; 1463 }; 1464 struct { 1465 u16 vddc1; 1466 u16 vddc2; 1467 u16 vddc3; 1468 }; 1469 }; 1470 1471 struct radeon_cac_leakage_table { 1472 u32 count; 1473 union radeon_cac_leakage_entry *entries; 1474 }; 1475 1476 struct radeon_phase_shedding_limits_entry { 1477 u16 voltage; 1478 u32 sclk; 1479 u32 mclk; 1480 }; 1481 1482 struct radeon_phase_shedding_limits_table { 1483 u32 count; 1484 struct radeon_phase_shedding_limits_entry *entries; 1485 }; 1486 1487 struct radeon_uvd_clock_voltage_dependency_entry { 1488 u32 vclk; 1489 u32 dclk; 1490 u16 v; 1491 }; 1492 1493 struct radeon_uvd_clock_voltage_dependency_table { 1494 u8 count; 1495 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1496 }; 1497 1498 struct radeon_vce_clock_voltage_dependency_entry { 1499 u32 ecclk; 1500 u32 evclk; 1501 u16 v; 1502 }; 1503 1504 struct radeon_vce_clock_voltage_dependency_table { 1505 u8 count; 1506 struct radeon_vce_clock_voltage_dependency_entry *entries; 1507 }; 1508 1509 struct radeon_ppm_table { 1510 u8 ppm_design; 1511 u16 cpu_core_number; 1512 u32 platform_tdp; 1513 u32 small_ac_platform_tdp; 1514 u32 platform_tdc; 1515 u32 small_ac_platform_tdc; 1516 u32 apu_tdp; 1517 u32 dgpu_tdp; 1518 u32 dgpu_ulv_power; 1519 u32 tj_max; 1520 }; 1521 1522 struct radeon_cac_tdp_table { 1523 u16 tdp; 1524 u16 configurable_tdp; 1525 u16 tdc; 1526 u16 battery_power_limit; 1527 u16 small_power_limit; 1528 u16 low_cac_leakage; 1529 u16 high_cac_leakage; 1530 u16 maximum_power_delivery_limit; 1531 }; 1532 1533 struct radeon_dpm_dynamic_state { 1534 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1535 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1536 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1537 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1538 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1539 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1540 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1541 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1542 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1543 struct radeon_clock_array valid_sclk_values; 1544 struct radeon_clock_array valid_mclk_values; 1545 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1546 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1547 u32 mclk_sclk_ratio; 1548 u32 sclk_mclk_delta; 1549 u16 vddc_vddci_delta; 1550 u16 min_vddc_for_pcie_gen2; 1551 struct radeon_cac_leakage_table cac_leakage_table; 1552 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1553 struct radeon_ppm_table *ppm_table; 1554 struct radeon_cac_tdp_table *cac_tdp_table; 1555 }; 1556 1557 struct radeon_dpm_fan { 1558 u16 t_min; 1559 u16 t_med; 1560 u16 t_high; 1561 u16 pwm_min; 1562 u16 pwm_med; 1563 u16 pwm_high; 1564 u8 t_hyst; 1565 u32 cycle_delay; 1566 u16 t_max; 1567 u8 control_mode; 1568 u16 default_max_fan_pwm; 1569 u16 default_fan_output_sensitivity; 1570 u16 fan_output_sensitivity; 1571 bool ucode_fan_control; 1572 }; 1573 1574 enum radeon_pcie_gen { 1575 RADEON_PCIE_GEN1 = 0, 1576 RADEON_PCIE_GEN2 = 1, 1577 RADEON_PCIE_GEN3 = 2, 1578 RADEON_PCIE_GEN_INVALID = 0xffff 1579 }; 1580 1581 enum radeon_dpm_forced_level { 1582 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1583 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1584 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1585 }; 1586 1587 struct radeon_vce_state { 1588 /* vce clocks */ 1589 u32 evclk; 1590 u32 ecclk; 1591 /* gpu clocks */ 1592 u32 sclk; 1593 u32 mclk; 1594 u8 clk_idx; 1595 u8 pstate; 1596 }; 1597 1598 struct radeon_dpm { 1599 struct radeon_ps *ps; 1600 /* number of valid power states */ 1601 int num_ps; 1602 /* current power state that is active */ 1603 struct radeon_ps *current_ps; 1604 /* requested power state */ 1605 struct radeon_ps *requested_ps; 1606 /* boot up power state */ 1607 struct radeon_ps *boot_ps; 1608 /* default uvd power state */ 1609 struct radeon_ps *uvd_ps; 1610 /* vce requirements */ 1611 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1612 enum radeon_vce_level vce_level; 1613 enum radeon_pm_state_type state; 1614 enum radeon_pm_state_type user_state; 1615 u32 platform_caps; 1616 u32 voltage_response_time; 1617 u32 backbias_response_time; 1618 void *priv; 1619 u32 new_active_crtcs; 1620 int new_active_crtc_count; 1621 u32 current_active_crtcs; 1622 int current_active_crtc_count; 1623 bool single_display; 1624 struct radeon_dpm_dynamic_state dyn_state; 1625 struct radeon_dpm_fan fan; 1626 u32 tdp_limit; 1627 u32 near_tdp_limit; 1628 u32 near_tdp_limit_adjusted; 1629 u32 sq_ramping_threshold; 1630 u32 cac_leakage; 1631 u16 tdp_od_limit; 1632 u32 tdp_adjustment; 1633 u16 load_line_slope; 1634 bool power_control; 1635 bool ac_power; 1636 /* special states active */ 1637 bool thermal_active; 1638 bool uvd_active; 1639 bool vce_active; 1640 /* thermal handling */ 1641 struct radeon_dpm_thermal thermal; 1642 /* forced levels */ 1643 enum radeon_dpm_forced_level forced_level; 1644 /* track UVD streams */ 1645 unsigned sd; 1646 unsigned hd; 1647 }; 1648 1649 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1650 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1651 1652 struct radeon_pm { 1653 struct mutex mutex; 1654 /* write locked while reprogramming mclk */ 1655 struct rw_semaphore mclk_lock; 1656 u32 active_crtcs; 1657 int active_crtc_count; 1658 int req_vblank; 1659 bool vblank_sync; 1660 fixed20_12 max_bandwidth; 1661 fixed20_12 igp_sideport_mclk; 1662 fixed20_12 igp_system_mclk; 1663 fixed20_12 igp_ht_link_clk; 1664 fixed20_12 igp_ht_link_width; 1665 fixed20_12 k8_bandwidth; 1666 fixed20_12 sideport_bandwidth; 1667 fixed20_12 ht_bandwidth; 1668 fixed20_12 core_bandwidth; 1669 fixed20_12 sclk; 1670 fixed20_12 mclk; 1671 fixed20_12 needed_bandwidth; 1672 struct radeon_power_state *power_state; 1673 /* number of valid power states */ 1674 int num_power_states; 1675 int current_power_state_index; 1676 int current_clock_mode_index; 1677 int requested_power_state_index; 1678 int requested_clock_mode_index; 1679 int default_power_state_index; 1680 u32 current_sclk; 1681 u32 current_mclk; 1682 u16 current_vddc; 1683 u16 current_vddci; 1684 u32 default_sclk; 1685 u32 default_mclk; 1686 u16 default_vddc; 1687 u16 default_vddci; 1688 struct radeon_i2c_chan *i2c_bus; 1689 /* selected pm method */ 1690 enum radeon_pm_method pm_method; 1691 /* dynpm power management */ 1692 struct delayed_work dynpm_idle_work; 1693 enum radeon_dynpm_state dynpm_state; 1694 enum radeon_dynpm_action dynpm_planned_action; 1695 unsigned long dynpm_action_timeout; 1696 bool dynpm_can_upclock; 1697 bool dynpm_can_downclock; 1698 /* profile-based power management */ 1699 enum radeon_pm_profile_type profile; 1700 int profile_index; 1701 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1702 /* internal thermal controller on rv6xx+ */ 1703 enum radeon_int_thermal_type int_thermal_type; 1704 struct device *int_hwmon_dev; 1705 /* fan control parameters */ 1706 bool no_fan; 1707 u8 fan_pulses_per_revolution; 1708 u8 fan_min_rpm; 1709 u8 fan_max_rpm; 1710 /* dpm */ 1711 bool dpm_enabled; 1712 bool sysfs_initialized; 1713 struct radeon_dpm dpm; 1714 }; 1715 1716 int radeon_pm_get_type_index(struct radeon_device *rdev, 1717 enum radeon_pm_state_type ps_type, 1718 int instance); 1719 /* 1720 * UVD 1721 */ 1722 #define RADEON_MAX_UVD_HANDLES 10 1723 #define RADEON_UVD_STACK_SIZE (1024*1024) 1724 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1725 1726 struct radeon_uvd { 1727 struct radeon_bo *vcpu_bo; 1728 void *cpu_addr; 1729 uint64_t gpu_addr; 1730 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1731 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1732 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1733 struct delayed_work idle_work; 1734 }; 1735 1736 int radeon_uvd_init(struct radeon_device *rdev); 1737 void radeon_uvd_fini(struct radeon_device *rdev); 1738 int radeon_uvd_suspend(struct radeon_device *rdev); 1739 int radeon_uvd_resume(struct radeon_device *rdev); 1740 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1741 uint32_t handle, struct radeon_fence **fence); 1742 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1743 uint32_t handle, struct radeon_fence **fence); 1744 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1745 uint32_t allowed_domains); 1746 void radeon_uvd_free_handles(struct radeon_device *rdev, 1747 struct drm_file *filp); 1748 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1749 void radeon_uvd_note_usage(struct radeon_device *rdev); 1750 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1751 unsigned vclk, unsigned dclk, 1752 unsigned vco_min, unsigned vco_max, 1753 unsigned fb_factor, unsigned fb_mask, 1754 unsigned pd_min, unsigned pd_max, 1755 unsigned pd_even, 1756 unsigned *optimal_fb_div, 1757 unsigned *optimal_vclk_div, 1758 unsigned *optimal_dclk_div); 1759 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1760 unsigned cg_upll_func_cntl); 1761 1762 /* 1763 * VCE 1764 */ 1765 #define RADEON_MAX_VCE_HANDLES 16 1766 1767 struct radeon_vce { 1768 struct radeon_bo *vcpu_bo; 1769 uint64_t gpu_addr; 1770 unsigned fw_version; 1771 unsigned fb_version; 1772 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1773 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1774 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1775 struct delayed_work idle_work; 1776 uint32_t keyselect; 1777 }; 1778 1779 int radeon_vce_init(struct radeon_device *rdev); 1780 void radeon_vce_fini(struct radeon_device *rdev); 1781 int radeon_vce_suspend(struct radeon_device *rdev); 1782 int radeon_vce_resume(struct radeon_device *rdev); 1783 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1784 uint32_t handle, struct radeon_fence **fence); 1785 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1786 uint32_t handle, struct radeon_fence **fence); 1787 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1788 void radeon_vce_note_usage(struct radeon_device *rdev); 1789 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1790 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1791 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1792 struct radeon_ring *ring, 1793 struct radeon_semaphore *semaphore, 1794 bool emit_wait); 1795 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1796 void radeon_vce_fence_emit(struct radeon_device *rdev, 1797 struct radeon_fence *fence); 1798 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1799 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1800 1801 struct r600_audio_pin { 1802 int channels; 1803 int rate; 1804 int bits_per_sample; 1805 u8 status_bits; 1806 u8 category_code; 1807 u32 offset; 1808 bool connected; 1809 u32 id; 1810 }; 1811 1812 struct r600_audio { 1813 bool enabled; 1814 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1815 int num_pins; 1816 struct radeon_audio_funcs *hdmi_funcs; 1817 struct radeon_audio_funcs *dp_funcs; 1818 struct radeon_audio_basic_funcs *funcs; 1819 }; 1820 1821 /* 1822 * Benchmarking 1823 */ 1824 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1825 1826 1827 /* 1828 * Testing 1829 */ 1830 void radeon_test_moves(struct radeon_device *rdev); 1831 void radeon_test_ring_sync(struct radeon_device *rdev, 1832 struct radeon_ring *cpA, 1833 struct radeon_ring *cpB); 1834 void radeon_test_syncing(struct radeon_device *rdev); 1835 1836 /* 1837 * MMU Notifier 1838 */ 1839 #if defined(CONFIG_MMU_NOTIFIER) 1840 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1841 void radeon_mn_unregister(struct radeon_bo *bo); 1842 #else 1843 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1844 { 1845 return -ENODEV; 1846 } 1847 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1848 #endif 1849 1850 /* 1851 * Debugfs 1852 */ 1853 struct radeon_debugfs { 1854 struct drm_info_list *files; 1855 unsigned num_files; 1856 }; 1857 1858 int radeon_debugfs_add_files(struct radeon_device *rdev, 1859 struct drm_info_list *files, 1860 unsigned nfiles); 1861 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1862 1863 /* 1864 * ASIC ring specific functions. 1865 */ 1866 struct radeon_asic_ring { 1867 /* ring read/write ptr handling */ 1868 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1869 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1870 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1871 1872 /* validating and patching of IBs */ 1873 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1874 int (*cs_parse)(struct radeon_cs_parser *p); 1875 1876 /* command emmit functions */ 1877 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1878 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1879 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1880 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1881 struct radeon_semaphore *semaphore, bool emit_wait); 1882 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1883 unsigned vm_id, uint64_t pd_addr); 1884 1885 /* testing functions */ 1886 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1887 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1888 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1889 1890 /* deprecated */ 1891 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1892 }; 1893 1894 /* 1895 * ASIC specific functions. 1896 */ 1897 struct radeon_asic { 1898 int (*init)(struct radeon_device *rdev); 1899 void (*fini)(struct radeon_device *rdev); 1900 int (*resume)(struct radeon_device *rdev); 1901 int (*suspend)(struct radeon_device *rdev); 1902 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1903 int (*asic_reset)(struct radeon_device *rdev); 1904 /* Flush the HDP cache via MMIO */ 1905 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1906 /* check if 3D engine is idle */ 1907 bool (*gui_idle)(struct radeon_device *rdev); 1908 /* wait for mc_idle */ 1909 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1910 /* get the reference clock */ 1911 u32 (*get_xclk)(struct radeon_device *rdev); 1912 /* get the gpu clock counter */ 1913 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1914 /* get register for info ioctl */ 1915 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1916 /* gart */ 1917 struct { 1918 void (*tlb_flush)(struct radeon_device *rdev); 1919 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1920 void (*set_page)(struct radeon_device *rdev, unsigned i, 1921 uint64_t entry); 1922 } gart; 1923 struct { 1924 int (*init)(struct radeon_device *rdev); 1925 void (*fini)(struct radeon_device *rdev); 1926 void (*copy_pages)(struct radeon_device *rdev, 1927 struct radeon_ib *ib, 1928 uint64_t pe, uint64_t src, 1929 unsigned count); 1930 void (*write_pages)(struct radeon_device *rdev, 1931 struct radeon_ib *ib, 1932 uint64_t pe, 1933 uint64_t addr, unsigned count, 1934 uint32_t incr, uint32_t flags); 1935 void (*set_pages)(struct radeon_device *rdev, 1936 struct radeon_ib *ib, 1937 uint64_t pe, 1938 uint64_t addr, unsigned count, 1939 uint32_t incr, uint32_t flags); 1940 void (*pad_ib)(struct radeon_ib *ib); 1941 } vm; 1942 /* ring specific callbacks */ 1943 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1944 /* irqs */ 1945 struct { 1946 int (*set)(struct radeon_device *rdev); 1947 int (*process)(struct radeon_device *rdev); 1948 } irq; 1949 /* displays */ 1950 struct { 1951 /* display watermarks */ 1952 void (*bandwidth_update)(struct radeon_device *rdev); 1953 /* get frame count */ 1954 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1955 /* wait for vblank */ 1956 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1957 /* set backlight level */ 1958 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1959 /* get backlight level */ 1960 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1961 /* audio callbacks */ 1962 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1963 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1964 } display; 1965 /* copy functions for bo handling */ 1966 struct { 1967 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1968 uint64_t src_offset, 1969 uint64_t dst_offset, 1970 unsigned num_gpu_pages, 1971 struct reservation_object *resv); 1972 u32 blit_ring_index; 1973 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1974 uint64_t src_offset, 1975 uint64_t dst_offset, 1976 unsigned num_gpu_pages, 1977 struct reservation_object *resv); 1978 u32 dma_ring_index; 1979 /* method used for bo copy */ 1980 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1981 uint64_t src_offset, 1982 uint64_t dst_offset, 1983 unsigned num_gpu_pages, 1984 struct reservation_object *resv); 1985 /* ring used for bo copies */ 1986 u32 copy_ring_index; 1987 } copy; 1988 /* surfaces */ 1989 struct { 1990 int (*set_reg)(struct radeon_device *rdev, int reg, 1991 uint32_t tiling_flags, uint32_t pitch, 1992 uint32_t offset, uint32_t obj_size); 1993 void (*clear_reg)(struct radeon_device *rdev, int reg); 1994 } surface; 1995 /* hotplug detect */ 1996 struct { 1997 void (*init)(struct radeon_device *rdev); 1998 void (*fini)(struct radeon_device *rdev); 1999 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 2000 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 2001 } hpd; 2002 /* static power management */ 2003 struct { 2004 void (*misc)(struct radeon_device *rdev); 2005 void (*prepare)(struct radeon_device *rdev); 2006 void (*finish)(struct radeon_device *rdev); 2007 void (*init_profile)(struct radeon_device *rdev); 2008 void (*get_dynpm_state)(struct radeon_device *rdev); 2009 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 2010 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 2011 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 2012 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 2013 int (*get_pcie_lanes)(struct radeon_device *rdev); 2014 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 2015 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 2016 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 2017 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 2018 int (*get_temperature)(struct radeon_device *rdev); 2019 } pm; 2020 /* dynamic power management */ 2021 struct { 2022 int (*init)(struct radeon_device *rdev); 2023 void (*setup_asic)(struct radeon_device *rdev); 2024 int (*enable)(struct radeon_device *rdev); 2025 int (*late_enable)(struct radeon_device *rdev); 2026 void (*disable)(struct radeon_device *rdev); 2027 int (*pre_set_power_state)(struct radeon_device *rdev); 2028 int (*set_power_state)(struct radeon_device *rdev); 2029 void (*post_set_power_state)(struct radeon_device *rdev); 2030 void (*display_configuration_changed)(struct radeon_device *rdev); 2031 void (*fini)(struct radeon_device *rdev); 2032 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2033 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2034 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2035 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2036 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2037 bool (*vblank_too_short)(struct radeon_device *rdev); 2038 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2039 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2040 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2041 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2042 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2043 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2044 u32 (*get_current_sclk)(struct radeon_device *rdev); 2045 u32 (*get_current_mclk)(struct radeon_device *rdev); 2046 } dpm; 2047 /* pageflipping */ 2048 struct { 2049 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 2050 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2051 } pflip; 2052 }; 2053 2054 /* 2055 * Asic structures 2056 */ 2057 struct r100_asic { 2058 const unsigned *reg_safe_bm; 2059 unsigned reg_safe_bm_size; 2060 u32 hdp_cntl; 2061 }; 2062 2063 struct r300_asic { 2064 const unsigned *reg_safe_bm; 2065 unsigned reg_safe_bm_size; 2066 u32 resync_scratch; 2067 u32 hdp_cntl; 2068 }; 2069 2070 struct r600_asic { 2071 unsigned max_pipes; 2072 unsigned max_tile_pipes; 2073 unsigned max_simds; 2074 unsigned max_backends; 2075 unsigned max_gprs; 2076 unsigned max_threads; 2077 unsigned max_stack_entries; 2078 unsigned max_hw_contexts; 2079 unsigned max_gs_threads; 2080 unsigned sx_max_export_size; 2081 unsigned sx_max_export_pos_size; 2082 unsigned sx_max_export_smx_size; 2083 unsigned sq_num_cf_insts; 2084 unsigned tiling_nbanks; 2085 unsigned tiling_npipes; 2086 unsigned tiling_group_size; 2087 unsigned tile_config; 2088 unsigned backend_map; 2089 unsigned active_simds; 2090 }; 2091 2092 struct rv770_asic { 2093 unsigned max_pipes; 2094 unsigned max_tile_pipes; 2095 unsigned max_simds; 2096 unsigned max_backends; 2097 unsigned max_gprs; 2098 unsigned max_threads; 2099 unsigned max_stack_entries; 2100 unsigned max_hw_contexts; 2101 unsigned max_gs_threads; 2102 unsigned sx_max_export_size; 2103 unsigned sx_max_export_pos_size; 2104 unsigned sx_max_export_smx_size; 2105 unsigned sq_num_cf_insts; 2106 unsigned sx_num_of_sets; 2107 unsigned sc_prim_fifo_size; 2108 unsigned sc_hiz_tile_fifo_size; 2109 unsigned sc_earlyz_tile_fifo_fize; 2110 unsigned tiling_nbanks; 2111 unsigned tiling_npipes; 2112 unsigned tiling_group_size; 2113 unsigned tile_config; 2114 unsigned backend_map; 2115 unsigned active_simds; 2116 }; 2117 2118 struct evergreen_asic { 2119 unsigned num_ses; 2120 unsigned max_pipes; 2121 unsigned max_tile_pipes; 2122 unsigned max_simds; 2123 unsigned max_backends; 2124 unsigned max_gprs; 2125 unsigned max_threads; 2126 unsigned max_stack_entries; 2127 unsigned max_hw_contexts; 2128 unsigned max_gs_threads; 2129 unsigned sx_max_export_size; 2130 unsigned sx_max_export_pos_size; 2131 unsigned sx_max_export_smx_size; 2132 unsigned sq_num_cf_insts; 2133 unsigned sx_num_of_sets; 2134 unsigned sc_prim_fifo_size; 2135 unsigned sc_hiz_tile_fifo_size; 2136 unsigned sc_earlyz_tile_fifo_size; 2137 unsigned tiling_nbanks; 2138 unsigned tiling_npipes; 2139 unsigned tiling_group_size; 2140 unsigned tile_config; 2141 unsigned backend_map; 2142 unsigned active_simds; 2143 }; 2144 2145 struct cayman_asic { 2146 unsigned max_shader_engines; 2147 unsigned max_pipes_per_simd; 2148 unsigned max_tile_pipes; 2149 unsigned max_simds_per_se; 2150 unsigned max_backends_per_se; 2151 unsigned max_texture_channel_caches; 2152 unsigned max_gprs; 2153 unsigned max_threads; 2154 unsigned max_gs_threads; 2155 unsigned max_stack_entries; 2156 unsigned sx_num_of_sets; 2157 unsigned sx_max_export_size; 2158 unsigned sx_max_export_pos_size; 2159 unsigned sx_max_export_smx_size; 2160 unsigned max_hw_contexts; 2161 unsigned sq_num_cf_insts; 2162 unsigned sc_prim_fifo_size; 2163 unsigned sc_hiz_tile_fifo_size; 2164 unsigned sc_earlyz_tile_fifo_size; 2165 2166 unsigned num_shader_engines; 2167 unsigned num_shader_pipes_per_simd; 2168 unsigned num_tile_pipes; 2169 unsigned num_simds_per_se; 2170 unsigned num_backends_per_se; 2171 unsigned backend_disable_mask_per_asic; 2172 unsigned backend_map; 2173 unsigned num_texture_channel_caches; 2174 unsigned mem_max_burst_length_bytes; 2175 unsigned mem_row_size_in_kb; 2176 unsigned shader_engine_tile_size; 2177 unsigned num_gpus; 2178 unsigned multi_gpu_tile_size; 2179 2180 unsigned tile_config; 2181 unsigned active_simds; 2182 }; 2183 2184 struct si_asic { 2185 unsigned max_shader_engines; 2186 unsigned max_tile_pipes; 2187 unsigned max_cu_per_sh; 2188 unsigned max_sh_per_se; 2189 unsigned max_backends_per_se; 2190 unsigned max_texture_channel_caches; 2191 unsigned max_gprs; 2192 unsigned max_gs_threads; 2193 unsigned max_hw_contexts; 2194 unsigned sc_prim_fifo_size_frontend; 2195 unsigned sc_prim_fifo_size_backend; 2196 unsigned sc_hiz_tile_fifo_size; 2197 unsigned sc_earlyz_tile_fifo_size; 2198 2199 unsigned num_tile_pipes; 2200 unsigned backend_enable_mask; 2201 unsigned backend_disable_mask_per_asic; 2202 unsigned backend_map; 2203 unsigned num_texture_channel_caches; 2204 unsigned mem_max_burst_length_bytes; 2205 unsigned mem_row_size_in_kb; 2206 unsigned shader_engine_tile_size; 2207 unsigned num_gpus; 2208 unsigned multi_gpu_tile_size; 2209 2210 unsigned tile_config; 2211 uint32_t tile_mode_array[32]; 2212 uint32_t active_cus; 2213 }; 2214 2215 struct cik_asic { 2216 unsigned max_shader_engines; 2217 unsigned max_tile_pipes; 2218 unsigned max_cu_per_sh; 2219 unsigned max_sh_per_se; 2220 unsigned max_backends_per_se; 2221 unsigned max_texture_channel_caches; 2222 unsigned max_gprs; 2223 unsigned max_gs_threads; 2224 unsigned max_hw_contexts; 2225 unsigned sc_prim_fifo_size_frontend; 2226 unsigned sc_prim_fifo_size_backend; 2227 unsigned sc_hiz_tile_fifo_size; 2228 unsigned sc_earlyz_tile_fifo_size; 2229 2230 unsigned num_tile_pipes; 2231 unsigned backend_enable_mask; 2232 unsigned backend_disable_mask_per_asic; 2233 unsigned backend_map; 2234 unsigned num_texture_channel_caches; 2235 unsigned mem_max_burst_length_bytes; 2236 unsigned mem_row_size_in_kb; 2237 unsigned shader_engine_tile_size; 2238 unsigned num_gpus; 2239 unsigned multi_gpu_tile_size; 2240 2241 unsigned tile_config; 2242 uint32_t tile_mode_array[32]; 2243 uint32_t macrotile_mode_array[16]; 2244 uint32_t active_cus; 2245 }; 2246 2247 union radeon_asic_config { 2248 struct r300_asic r300; 2249 struct r100_asic r100; 2250 struct r600_asic r600; 2251 struct rv770_asic rv770; 2252 struct evergreen_asic evergreen; 2253 struct cayman_asic cayman; 2254 struct si_asic si; 2255 struct cik_asic cik; 2256 }; 2257 2258 /* 2259 * asic initizalization from radeon_asic.c 2260 */ 2261 void radeon_agp_disable(struct radeon_device *rdev); 2262 int radeon_asic_init(struct radeon_device *rdev); 2263 2264 2265 /* 2266 * IOCTL. 2267 */ 2268 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2269 struct drm_file *filp); 2270 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2271 struct drm_file *filp); 2272 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2273 struct drm_file *filp); 2274 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2275 struct drm_file *file_priv); 2276 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2277 struct drm_file *file_priv); 2278 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2279 struct drm_file *file_priv); 2280 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2281 struct drm_file *file_priv); 2282 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2283 struct drm_file *filp); 2284 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2285 struct drm_file *filp); 2286 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2287 struct drm_file *filp); 2288 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2289 struct drm_file *filp); 2290 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2291 struct drm_file *filp); 2292 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2293 struct drm_file *filp); 2294 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2295 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2296 struct drm_file *filp); 2297 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2298 struct drm_file *filp); 2299 2300 /* VRAM scratch page for HDP bug, default vram page */ 2301 struct r600_vram_scratch { 2302 struct radeon_bo *robj; 2303 volatile uint32_t *ptr; 2304 u64 gpu_addr; 2305 }; 2306 2307 /* 2308 * ACPI 2309 */ 2310 struct radeon_atif_notification_cfg { 2311 bool enabled; 2312 int command_code; 2313 }; 2314 2315 struct radeon_atif_notifications { 2316 bool display_switch; 2317 bool expansion_mode_change; 2318 bool thermal_state; 2319 bool forced_power_state; 2320 bool system_power_state; 2321 bool display_conf_change; 2322 bool px_gfx_switch; 2323 bool brightness_change; 2324 bool dgpu_display_event; 2325 }; 2326 2327 struct radeon_atif_functions { 2328 bool system_params; 2329 bool sbios_requests; 2330 bool select_active_disp; 2331 bool lid_state; 2332 bool get_tv_standard; 2333 bool set_tv_standard; 2334 bool get_panel_expansion_mode; 2335 bool set_panel_expansion_mode; 2336 bool temperature_change; 2337 bool graphics_device_types; 2338 }; 2339 2340 struct radeon_atif { 2341 struct radeon_atif_notifications notifications; 2342 struct radeon_atif_functions functions; 2343 struct radeon_atif_notification_cfg notification_cfg; 2344 struct radeon_encoder *encoder_for_bl; 2345 }; 2346 2347 struct radeon_atcs_functions { 2348 bool get_ext_state; 2349 bool pcie_perf_req; 2350 bool pcie_dev_rdy; 2351 bool pcie_bus_width; 2352 }; 2353 2354 struct radeon_atcs { 2355 struct radeon_atcs_functions functions; 2356 }; 2357 2358 /* 2359 * Core structure, functions and helpers. 2360 */ 2361 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2362 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2363 2364 struct radeon_device { 2365 struct device *dev; 2366 struct drm_device *ddev; 2367 struct pci_dev *pdev; 2368 struct rw_semaphore exclusive_lock; 2369 /* ASIC */ 2370 union radeon_asic_config config; 2371 enum radeon_family family; 2372 unsigned long flags; 2373 int usec_timeout; 2374 enum radeon_pll_errata pll_errata; 2375 int num_gb_pipes; 2376 int num_z_pipes; 2377 int disp_priority; 2378 /* BIOS */ 2379 uint8_t *bios; 2380 bool is_atom_bios; 2381 uint16_t bios_header_start; 2382 struct radeon_bo *stollen_vga_memory; 2383 /* Register mmio */ 2384 #ifndef __NetBSD__ 2385 resource_size_t rmmio_base; 2386 resource_size_t rmmio_size; 2387 #endif 2388 /* protects concurrent MM_INDEX/DATA based register access */ 2389 spinlock_t mmio_idx_lock; 2390 /* protects concurrent SMC based register access */ 2391 spinlock_t smc_idx_lock; 2392 /* protects concurrent PLL register access */ 2393 spinlock_t pll_idx_lock; 2394 /* protects concurrent MC register access */ 2395 spinlock_t mc_idx_lock; 2396 /* protects concurrent PCIE register access */ 2397 spinlock_t pcie_idx_lock; 2398 /* protects concurrent PCIE_PORT register access */ 2399 spinlock_t pciep_idx_lock; 2400 /* protects concurrent PIF register access */ 2401 spinlock_t pif_idx_lock; 2402 /* protects concurrent CG register access */ 2403 spinlock_t cg_idx_lock; 2404 /* protects concurrent UVD register access */ 2405 spinlock_t uvd_idx_lock; 2406 /* protects concurrent RCU register access */ 2407 spinlock_t rcu_idx_lock; 2408 /* protects concurrent DIDT register access */ 2409 spinlock_t didt_idx_lock; 2410 /* protects concurrent ENDPOINT (audio) register access */ 2411 spinlock_t end_idx_lock; 2412 #ifdef __NetBSD__ 2413 bus_space_tag_t rmmio_bst; 2414 bus_space_handle_t rmmio_bsh; 2415 bus_addr_t rmmio_addr; 2416 bus_size_t rmmio_size; 2417 #else 2418 void __iomem *rmmio; 2419 #endif 2420 radeon_rreg_t mc_rreg; 2421 radeon_wreg_t mc_wreg; 2422 radeon_rreg_t pll_rreg; 2423 radeon_wreg_t pll_wreg; 2424 uint32_t pcie_reg_mask; 2425 radeon_rreg_t pciep_rreg; 2426 radeon_wreg_t pciep_wreg; 2427 /* io port */ 2428 #ifdef __NetBSD__ 2429 bus_space_tag_t rio_mem_bst; 2430 bus_space_handle_t rio_mem_bsh; 2431 bus_size_t rio_mem_size; 2432 #else 2433 void __iomem *rio_mem; 2434 resource_size_t rio_mem_size; 2435 #endif 2436 struct radeon_clock clock; 2437 struct radeon_mc mc; 2438 struct radeon_gart gart; 2439 struct radeon_mode_info mode_info; 2440 struct radeon_scratch scratch; 2441 struct radeon_doorbell doorbell; 2442 struct radeon_mman mman; 2443 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2444 #ifdef __NetBSD__ 2445 spinlock_t fence_lock; 2446 drm_waitqueue_t fence_queue; 2447 TAILQ_HEAD(, radeon_fence) fence_check; 2448 #else 2449 wait_queue_head_t fence_queue; 2450 #endif 2451 unsigned fence_context; 2452 struct mutex ring_lock; 2453 struct radeon_ring ring[RADEON_NUM_RINGS]; 2454 bool ib_pool_ready; 2455 struct radeon_sa_manager ring_tmp_bo; 2456 struct radeon_irq irq; 2457 struct radeon_asic *asic; 2458 struct radeon_gem gem; 2459 struct radeon_pm pm; 2460 struct radeon_uvd uvd; 2461 struct radeon_vce vce; 2462 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2463 struct radeon_wb wb; 2464 struct radeon_dummy_page dummy_page; 2465 bool shutdown; 2466 bool suspend; 2467 bool need_dma32; 2468 bool accel_working; 2469 bool fastfb_working; /* IGP feature*/ 2470 bool needs_reset, in_reset; 2471 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2472 const struct firmware *me_fw; /* all family ME firmware */ 2473 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2474 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2475 const struct firmware *mc_fw; /* NI MC firmware */ 2476 const struct firmware *ce_fw; /* SI CE firmware */ 2477 const struct firmware *mec_fw; /* CIK MEC firmware */ 2478 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2479 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2480 const struct firmware *smc_fw; /* SMC firmware */ 2481 const struct firmware *uvd_fw; /* UVD firmware */ 2482 const struct firmware *vce_fw; /* VCE firmware */ 2483 bool new_fw; 2484 struct r600_vram_scratch vram_scratch; 2485 int msi_enabled; /* msi enabled */ 2486 struct r600_ih ih; /* r6/700 interrupt ring */ 2487 struct radeon_rlc rlc; 2488 struct radeon_mec mec; 2489 struct delayed_work hotplug_work; 2490 struct work_struct dp_work; 2491 struct work_struct audio_work; 2492 int num_crtc; /* number of crtcs */ 2493 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2494 bool has_uvd; 2495 struct r600_audio audio; /* audio stuff */ 2496 struct notifier_block acpi_nb; 2497 /* only one userspace can use Hyperz features or CMASK at a time */ 2498 struct drm_file *hyperz_filp; 2499 struct drm_file *cmask_filp; 2500 /* i2c buses */ 2501 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2502 /* debugfs */ 2503 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2504 unsigned debugfs_count; 2505 /* virtual memory */ 2506 struct radeon_vm_manager vm_manager; 2507 struct mutex gpu_clock_mutex; 2508 /* memory stats */ 2509 atomic64_t vram_usage; 2510 atomic64_t gtt_usage; 2511 atomic64_t num_bytes_moved; 2512 atomic_t gpu_reset_counter; 2513 /* ACPI interface */ 2514 struct radeon_atif atif; 2515 struct radeon_atcs atcs; 2516 /* srbm instance registers */ 2517 struct mutex srbm_mutex; 2518 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2519 struct mutex grbm_idx_mutex; 2520 /* clock, powergating flags */ 2521 u32 cg_flags; 2522 u32 pg_flags; 2523 2524 struct dev_pm_domain vga_pm_domain; 2525 bool have_disp_power_ref; 2526 u32 px_quirk_flags; 2527 2528 /* tracking pinned memory */ 2529 u64 vram_pin_size; 2530 u64 gart_pin_size; 2531 2532 /* amdkfd interface */ 2533 struct kfd_dev *kfd; 2534 2535 struct mutex mn_lock; 2536 DECLARE_HASHTABLE(mn_hash, 7); 2537 }; 2538 2539 bool radeon_is_px(struct drm_device *dev); 2540 int radeon_device_init(struct radeon_device *rdev, 2541 struct drm_device *ddev, 2542 struct pci_dev *pdev, 2543 uint32_t flags); 2544 void radeon_device_fini(struct radeon_device *rdev); 2545 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2546 2547 #define RADEON_MIN_MMIO_SIZE 0x10000 2548 2549 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2550 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2551 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2552 bool always_indirect) 2553 { 2554 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2555 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2556 return readl(((void __iomem *)rdev->rmmio) + reg); 2557 else 2558 return r100_mm_rreg_slow(rdev, reg); 2559 } 2560 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2561 bool always_indirect) 2562 { 2563 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2564 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2565 else 2566 r100_mm_wreg_slow(rdev, reg, v); 2567 } 2568 2569 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2570 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2571 2572 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2573 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2574 2575 /* 2576 * Cast helper 2577 */ 2578 extern const struct fence_ops radeon_fence_ops; 2579 2580 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2581 { 2582 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2583 2584 if (__f->base.ops == &radeon_fence_ops) 2585 return __f; 2586 2587 return NULL; 2588 } 2589 2590 /* 2591 * Registers read & write functions. 2592 */ 2593 #ifdef __NetBSD__ 2594 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2595 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2596 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2597 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2598 #else 2599 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2600 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2601 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2602 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2603 #endif 2604 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2605 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2606 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2607 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2608 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2609 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2610 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2611 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2612 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2613 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2614 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2615 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2616 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2617 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2618 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2619 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2620 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2621 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2622 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2623 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2624 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2625 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2626 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2627 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2628 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2629 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2630 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2631 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2632 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2633 #define WREG32_P(reg, val, mask) \ 2634 do { \ 2635 uint32_t tmp_ = RREG32(reg); \ 2636 tmp_ &= (mask); \ 2637 tmp_ |= ((val) & ~(mask)); \ 2638 WREG32(reg, tmp_); \ 2639 } while (0) 2640 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2641 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2642 #define WREG32_PLL_P(reg, val, mask) \ 2643 do { \ 2644 uint32_t tmp_ = RREG32_PLL(reg); \ 2645 tmp_ &= (mask); \ 2646 tmp_ |= ((val) & ~(mask)); \ 2647 WREG32_PLL(reg, tmp_); \ 2648 } while (0) 2649 #define WREG32_SMC_P(reg, val, mask) \ 2650 do { \ 2651 uint32_t tmp_ = RREG32_SMC(reg); \ 2652 tmp_ &= (mask); \ 2653 tmp_ |= ((val) & ~(mask)); \ 2654 WREG32_SMC(reg, tmp_); \ 2655 } while (0) 2656 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2657 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2658 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2659 2660 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2661 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2662 2663 /* 2664 * Indirect registers accessors. 2665 * They used to be inlined, but this increases code size by ~65 kbytes. 2666 * Since each performs a pair of MMIO ops 2667 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2668 * the cost of call+ret is almost negligible. MMIO and locking 2669 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2670 */ 2671 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2672 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2673 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2674 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2675 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2676 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2677 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2678 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2679 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2680 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2681 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2682 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2683 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2684 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2685 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2686 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2687 2688 void r100_pll_errata_after_index(struct radeon_device *rdev); 2689 2690 2691 /* 2692 * ASICs helpers. 2693 */ 2694 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2695 (rdev->pdev->device == 0x5969)) 2696 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2697 (rdev->family == CHIP_RV200) || \ 2698 (rdev->family == CHIP_RS100) || \ 2699 (rdev->family == CHIP_RS200) || \ 2700 (rdev->family == CHIP_RV250) || \ 2701 (rdev->family == CHIP_RV280) || \ 2702 (rdev->family == CHIP_RS300)) 2703 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2704 (rdev->family == CHIP_RV350) || \ 2705 (rdev->family == CHIP_R350) || \ 2706 (rdev->family == CHIP_RV380) || \ 2707 (rdev->family == CHIP_R420) || \ 2708 (rdev->family == CHIP_R423) || \ 2709 (rdev->family == CHIP_RV410) || \ 2710 (rdev->family == CHIP_RS400) || \ 2711 (rdev->family == CHIP_RS480)) 2712 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2713 (rdev->ddev->pdev->device == 0x9443) || \ 2714 (rdev->ddev->pdev->device == 0x944B) || \ 2715 (rdev->ddev->pdev->device == 0x9506) || \ 2716 (rdev->ddev->pdev->device == 0x9509) || \ 2717 (rdev->ddev->pdev->device == 0x950F) || \ 2718 (rdev->ddev->pdev->device == 0x689C) || \ 2719 (rdev->ddev->pdev->device == 0x689D)) 2720 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2721 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2722 (rdev->family == CHIP_RS690) || \ 2723 (rdev->family == CHIP_RS740) || \ 2724 (rdev->family >= CHIP_R600)) 2725 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2726 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2727 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2728 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2729 (rdev->flags & RADEON_IS_IGP)) 2730 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2731 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2732 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2733 (rdev->flags & RADEON_IS_IGP)) 2734 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2735 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2736 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2737 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2738 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2739 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2740 (rdev->family == CHIP_MULLINS)) 2741 2742 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2743 (rdev->ddev->pdev->device == 0x6850) || \ 2744 (rdev->ddev->pdev->device == 0x6858) || \ 2745 (rdev->ddev->pdev->device == 0x6859) || \ 2746 (rdev->ddev->pdev->device == 0x6840) || \ 2747 (rdev->ddev->pdev->device == 0x6841) || \ 2748 (rdev->ddev->pdev->device == 0x6842) || \ 2749 (rdev->ddev->pdev->device == 0x6843)) 2750 2751 /* 2752 * BIOS helpers. 2753 */ 2754 #define RBIOS8(i) (rdev->bios[i]) 2755 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2756 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2757 2758 int radeon_combios_init(struct radeon_device *rdev); 2759 void radeon_combios_fini(struct radeon_device *rdev); 2760 int radeon_atombios_init(struct radeon_device *rdev); 2761 void radeon_atombios_fini(struct radeon_device *rdev); 2762 2763 2764 /* 2765 * RING helpers. 2766 */ 2767 2768 /** 2769 * radeon_ring_write - write a value to the ring 2770 * 2771 * @ring: radeon_ring structure holding ring information 2772 * @v: dword (dw) value to write 2773 * 2774 * Write a value to the requested ring buffer (all asics). 2775 */ 2776 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2777 { 2778 if (ring->count_dw <= 0) 2779 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2780 2781 ring->ring[ring->wptr++] = v; 2782 ring->wptr &= ring->ptr_mask; 2783 ring->count_dw--; 2784 ring->ring_free_dw--; 2785 } 2786 2787 /* 2788 * ASICs macro. 2789 */ 2790 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2791 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2792 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2793 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2794 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2795 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2796 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2797 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2798 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2799 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2800 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2801 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2802 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2803 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2804 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2805 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2806 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2807 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2808 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2809 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2810 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2811 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2812 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2813 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2814 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2815 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2816 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2817 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2818 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2819 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2820 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2821 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2822 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2823 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2824 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2825 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2826 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2827 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2828 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2829 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2830 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2831 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2832 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2833 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2834 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2835 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2836 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2837 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2838 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2839 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2840 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2841 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2842 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2843 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2844 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2845 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2846 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2847 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2848 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2849 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2850 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2851 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2852 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2853 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2854 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2855 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2856 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2857 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2858 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2859 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2860 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2861 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2862 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2863 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2864 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2865 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2866 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2867 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2868 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2869 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2870 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2871 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2872 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2873 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2874 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2875 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2876 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2877 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2878 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2879 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2880 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2881 2882 /* Common functions */ 2883 /* AGP */ 2884 extern int radeon_gpu_reset(struct radeon_device *rdev); 2885 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2886 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2887 extern void radeon_agp_disable(struct radeon_device *rdev); 2888 extern int radeon_modeset_init(struct radeon_device *rdev); 2889 extern void radeon_modeset_fini(struct radeon_device *rdev); 2890 extern bool radeon_card_posted(struct radeon_device *rdev); 2891 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2892 extern void radeon_update_display_priority(struct radeon_device *rdev); 2893 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2894 extern void radeon_scratch_init(struct radeon_device *rdev); 2895 extern void radeon_wb_fini(struct radeon_device *rdev); 2896 extern int radeon_wb_init(struct radeon_device *rdev); 2897 extern void radeon_wb_disable(struct radeon_device *rdev); 2898 extern void radeon_surface_init(struct radeon_device *rdev); 2899 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2900 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2901 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2902 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2903 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2904 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2905 uint32_t flags); 2906 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2907 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2908 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2909 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2910 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2911 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2912 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2913 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2914 const u32 *registers, 2915 const u32 array_size); 2916 2917 /* 2918 * vm 2919 */ 2920 int radeon_vm_manager_init(struct radeon_device *rdev); 2921 void radeon_vm_manager_fini(struct radeon_device *rdev); 2922 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2923 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2924 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2925 struct radeon_vm *vm, 2926 struct list_head *head); 2927 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2928 struct radeon_vm *vm, int ring); 2929 void radeon_vm_flush(struct radeon_device *rdev, 2930 struct radeon_vm *vm, 2931 int ring, struct radeon_fence *fence); 2932 void radeon_vm_fence(struct radeon_device *rdev, 2933 struct radeon_vm *vm, 2934 struct radeon_fence *fence); 2935 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2936 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2937 struct radeon_vm *vm); 2938 int radeon_vm_clear_freed(struct radeon_device *rdev, 2939 struct radeon_vm *vm); 2940 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2941 struct radeon_vm *vm); 2942 int radeon_vm_bo_update(struct radeon_device *rdev, 2943 struct radeon_bo_va *bo_va, 2944 struct ttm_mem_reg *mem); 2945 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2946 struct radeon_bo *bo); 2947 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2948 struct radeon_bo *bo); 2949 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2950 struct radeon_vm *vm, 2951 struct radeon_bo *bo); 2952 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2953 struct radeon_bo_va *bo_va, 2954 uint64_t offset, 2955 uint32_t flags); 2956 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2957 struct radeon_bo_va *bo_va); 2958 2959 /* audio */ 2960 void r600_audio_update_hdmi(struct work_struct *work); 2961 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2962 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2963 void r600_audio_enable(struct radeon_device *rdev, 2964 struct r600_audio_pin *pin, 2965 u8 enable_mask); 2966 void dce6_audio_enable(struct radeon_device *rdev, 2967 struct r600_audio_pin *pin, 2968 u8 enable_mask); 2969 2970 /* 2971 * R600 vram scratch functions 2972 */ 2973 int r600_vram_scratch_init(struct radeon_device *rdev); 2974 void r600_vram_scratch_fini(struct radeon_device *rdev); 2975 2976 /* 2977 * r600 cs checking helper 2978 */ 2979 unsigned r600_mip_minify(unsigned size, unsigned level); 2980 bool r600_fmt_is_valid_color(u32 format); 2981 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2982 int r600_fmt_get_blocksize(u32 format); 2983 int r600_fmt_get_nblocksx(u32 format, u32 w); 2984 int r600_fmt_get_nblocksy(u32 format, u32 h); 2985 2986 /* 2987 * r600 functions used by radeon_encoder.c 2988 */ 2989 struct radeon_hdmi_acr { 2990 u32 clock; 2991 2992 int n_32khz; 2993 int cts_32khz; 2994 2995 int n_44_1khz; 2996 int cts_44_1khz; 2997 2998 int n_48khz; 2999 int cts_48khz; 3000 3001 }; 3002 3003 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3004 3005 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3006 u32 tiling_pipe_num, 3007 u32 max_rb_num, 3008 u32 total_max_rb_num, 3009 u32 enabled_rb_mask); 3010 3011 /* 3012 * evergreen functions used by radeon_encoder.c 3013 */ 3014 3015 extern int ni_init_microcode(struct radeon_device *rdev); 3016 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3017 3018 /* radeon_acpi.c */ 3019 #if defined(CONFIG_ACPI) 3020 extern int radeon_acpi_init(struct radeon_device *rdev); 3021 extern void radeon_acpi_fini(struct radeon_device *rdev); 3022 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3023 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3024 u8 perf_req, bool advertise); 3025 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3026 #else 3027 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3028 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3029 #endif 3030 3031 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3032 struct radeon_cs_packet *pkt, 3033 unsigned idx); 3034 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3035 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3036 struct radeon_cs_packet *pkt); 3037 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3038 struct radeon_bo_list **cs_reloc, 3039 int nomm); 3040 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3041 uint32_t *vline_start_end, 3042 uint32_t *vline_status); 3043 3044 #include "radeon_object.h" 3045 3046 #endif 3047
Indexes created Wed Oct 01 18:09:54 GMT 2025