radeon.h revision 1.8
1 /* $NetBSD: radeon.h,v 1.8 2020/02/14 04:37:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <asm/byteorder.h> 66 #include <linux/atomic.h> 67 #include <linux/wait.h> 68 #include <linux/list.h> 69 #include <linux/kref.h> 70 #include <linux/interval_tree.h> 71 #include <linux/hashtable.h> 72 #include <linux/fence.h> 73 #include <linux/device.h> 74 #include <linux/log2.h> 75 #include <linux/notifier.h> 76 #include <linux/printk.h> 77 #include <linux/rwsem.h> 78 79 #include <ttm/ttm_bo_api.h> 80 #include <ttm/ttm_bo_driver.h> 81 #include <ttm/ttm_placement.h> 82 #include <ttm/ttm_module.h> 83 #include <ttm/ttm_execbuf_util.h> 84 85 #include <drm/drm_gem.h> 86 87 #include "radeon_family.h" 88 #include "radeon_mode.h" 89 #include "radeon_reg.h" 90 91 /* 92 * Modules parameters. 93 */ 94 extern int radeon_no_wb; 95 extern int radeon_modeset; 96 extern int radeon_dynclks; 97 extern int radeon_r4xx_atom; 98 extern int radeon_agpmode; 99 extern int radeon_vram_limit; 100 extern int radeon_gart_size; 101 extern int radeon_benchmarking; 102 extern int radeon_testing; 103 extern int radeon_connector_table; 104 extern int radeon_tv; 105 extern int radeon_audio; 106 extern int radeon_disp_priority; 107 extern int radeon_hw_i2c; 108 extern int radeon_pcie_gen2; 109 extern int radeon_msi; 110 extern int radeon_lockup_timeout; 111 extern int radeon_fastfb; 112 extern int radeon_dpm; 113 extern int radeon_aspm; 114 extern int radeon_runtime_pm; 115 extern int radeon_hard_reset; 116 extern int radeon_vm_size; 117 extern int radeon_vm_block_size; 118 extern int radeon_deep_color; 119 extern int radeon_use_pflipirq; 120 extern int radeon_bapm; 121 extern int radeon_backlight; 122 extern int radeon_auxch; 123 extern int radeon_mst; 124 125 /* 126 * Copy from radeon_drv.h so we don't have to include both and have conflicting 127 * symbol; 128 */ 129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 130 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 #ifdef __NetBSD__ 246 extern struct radeon_device *radeon_device_private(device_t); 247 #endif 248 249 /* 250 * BIOS. 251 */ 252 bool radeon_get_bios(struct radeon_device *rdev); 253 254 /* 255 * Dummy page 256 */ 257 struct radeon_dummy_page { 258 uint64_t entry; 259 #ifdef __NetBSD__ 260 bus_dma_segment_t rdp_seg; 261 bus_dmamap_t rdp_map; 262 void *rdp_addr; 263 #else 264 struct page *page; 265 #endif 266 dma_addr_t addr; 267 }; 268 int radeon_dummy_page_init(struct radeon_device *rdev); 269 void radeon_dummy_page_fini(struct radeon_device *rdev); 270 271 272 /* 273 * Clocks 274 */ 275 struct radeon_clock { 276 struct radeon_pll p1pll; 277 struct radeon_pll p2pll; 278 struct radeon_pll dcpll; 279 struct radeon_pll spll; 280 struct radeon_pll mpll; 281 /* 10 Khz units */ 282 uint32_t default_mclk; 283 uint32_t default_sclk; 284 uint32_t default_dispclk; 285 uint32_t current_dispclk; 286 uint32_t dp_extclk; 287 uint32_t max_pixel_clock; 288 uint32_t vco_freq; 289 }; 290 291 /* 292 * Power management 293 */ 294 int radeon_pm_init(struct radeon_device *rdev); 295 int radeon_pm_late_init(struct radeon_device *rdev); 296 void radeon_pm_fini(struct radeon_device *rdev); 297 void radeon_pm_compute_clocks(struct radeon_device *rdev); 298 void radeon_pm_suspend(struct radeon_device *rdev); 299 void radeon_pm_resume(struct radeon_device *rdev); 300 void radeon_combios_get_power_modes(struct radeon_device *rdev); 301 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 302 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 303 u8 clock_type, 304 u32 clock, 305 bool strobe_mode, 306 struct atom_clock_dividers *dividers); 307 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 308 u32 clock, 309 bool strobe_mode, 310 struct atom_mpll_param *mpll_param); 311 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 312 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 313 u16 voltage_level, u8 voltage_type, 314 u32 *gpio_value, u32 *gpio_mask); 315 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 316 u32 eng_clock, u32 mem_clock); 317 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 318 u8 voltage_type, u16 *voltage_step); 319 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 320 u16 voltage_id, u16 *voltage); 321 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 322 u16 *voltage, 323 u16 leakage_idx); 324 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 325 u16 *leakage_id); 326 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 327 u16 *vddc, u16 *vddci, 328 u16 virtual_voltage_id, 329 u16 vbios_voltage_id); 330 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 331 u16 virtual_voltage_id, 332 u16 *voltage); 333 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 334 u8 voltage_type, 335 u16 nominal_voltage, 336 u16 *true_voltage); 337 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 338 u8 voltage_type, u16 *min_voltage); 339 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 340 u8 voltage_type, u16 *max_voltage); 341 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 342 u8 voltage_type, u8 voltage_mode, 343 struct atom_voltage_table *voltage_table); 344 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 345 u8 voltage_type, u8 voltage_mode); 346 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 347 u8 voltage_type, 348 u8 *svd_gpio_id, u8 *svc_gpio_id); 349 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 350 u32 mem_clock); 351 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 352 u32 mem_clock); 353 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 354 u8 module_index, 355 struct atom_mc_reg_table *reg_table); 356 int radeon_atom_get_memory_info(struct radeon_device *rdev, 357 u8 module_index, struct atom_memory_info *mem_info); 358 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 359 bool gddr5, u8 module_index, 360 struct atom_memory_clock_range_table *mclk_range_table); 361 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 362 u16 voltage_id, u16 *voltage); 363 void rs690_pm_info(struct radeon_device *rdev); 364 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 365 unsigned *bankh, unsigned *mtaspect, 366 unsigned *tile_split); 367 368 /* 369 * Fences. 370 */ 371 struct radeon_fence_driver { 372 struct radeon_device *rdev; 373 uint32_t scratch_reg; 374 uint64_t gpu_addr; 375 volatile uint32_t *cpu_addr; 376 /* sync_seq is protected by ring emission lock */ 377 uint64_t sync_seq[RADEON_NUM_RINGS]; 378 atomic64_t last_seq; 379 bool initialized, delayed_irq; 380 struct delayed_work lockup_work; 381 }; 382 383 struct radeon_fence { 384 struct fence base; 385 386 struct radeon_device *rdev; 387 uint64_t seq; 388 /* RB, DMA, etc. */ 389 unsigned ring; 390 bool is_vm_update; 391 392 #ifdef __NetBSD__ 393 TAILQ_ENTRY(radeon_fence) fence_check; 394 #else 395 wait_queue_t fence_wake; 396 #endif 397 }; 398 399 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 400 int radeon_fence_driver_init(struct radeon_device *rdev); 401 void radeon_fence_driver_fini(struct radeon_device *rdev); 402 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 403 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 404 void radeon_fence_wakeup_locked(struct radeon_device *rdev); 405 void radeon_fence_process(struct radeon_device *rdev, int ring); 406 bool radeon_fence_signaled(struct radeon_fence *fence); 407 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 408 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 409 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 410 int radeon_fence_wait_any(struct radeon_device *rdev, 411 struct radeon_fence **fences, 412 bool intr); 413 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 414 void radeon_fence_unref(struct radeon_fence **fence); 415 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 416 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 417 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 418 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 419 struct radeon_fence *b) 420 { 421 if (!a) { 422 return b; 423 } 424 425 if (!b) { 426 return a; 427 } 428 429 BUG_ON(a->ring != b->ring); 430 431 if (a->seq > b->seq) { 432 return a; 433 } else { 434 return b; 435 } 436 } 437 438 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 439 struct radeon_fence *b) 440 { 441 if (!a) { 442 return false; 443 } 444 445 if (!b) { 446 return true; 447 } 448 449 BUG_ON(a->ring != b->ring); 450 451 return a->seq < b->seq; 452 } 453 454 /* 455 * Tiling registers 456 */ 457 struct radeon_surface_reg { 458 struct radeon_bo *bo; 459 }; 460 461 #define RADEON_GEM_MAX_SURFACES 8 462 463 /* 464 * TTM. 465 */ 466 struct radeon_mman { 467 struct ttm_bo_global_ref bo_global_ref; 468 struct drm_global_reference mem_global_ref; 469 struct ttm_bo_device bdev; 470 bool mem_global_referenced; 471 bool initialized; 472 473 #if defined(CONFIG_DEBUG_FS) 474 struct dentry *vram; 475 struct dentry *gtt; 476 #endif 477 }; 478 479 struct radeon_bo_list { 480 struct radeon_bo *robj; 481 struct ttm_validate_buffer tv; 482 uint64_t gpu_offset; 483 unsigned prefered_domains; 484 unsigned allowed_domains; 485 uint32_t tiling_flags; 486 }; 487 488 /* bo virtual address in a specific vm */ 489 struct radeon_bo_va { 490 /* protected by bo being reserved */ 491 struct list_head bo_list; 492 uint32_t flags; 493 struct radeon_fence *last_pt_update; 494 unsigned ref_count; 495 496 /* protected by vm mutex */ 497 struct interval_tree_node it; 498 struct list_head vm_status; 499 500 /* constant after initialization */ 501 struct radeon_vm *vm; 502 struct radeon_bo *bo; 503 }; 504 505 struct radeon_bo { 506 /* Protected by gem.mutex */ 507 struct list_head list; 508 /* Protected by tbo.reserved */ 509 u32 initial_domain; 510 struct ttm_place placements[4]; 511 struct ttm_placement placement; 512 struct ttm_buffer_object tbo; 513 struct ttm_bo_kmap_obj kmap; 514 u32 flags; 515 unsigned pin_count; 516 void *kptr; 517 u32 tiling_flags; 518 u32 pitch; 519 int surface_reg; 520 /* list of all virtual address to which this bo 521 * is associated to 522 */ 523 struct list_head va; 524 /* Constant after initialization */ 525 struct radeon_device *rdev; 526 struct drm_gem_object gem_base; 527 528 struct ttm_bo_kmap_obj dma_buf_vmap; 529 #ifndef __NetBSD__ /* XXX pid??? */ 530 pid_t pid; 531 #endif 532 533 struct radeon_mn *mn; 534 struct list_head mn_list; 535 }; 536 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 537 538 int radeon_gem_debugfs_init(struct radeon_device *rdev); 539 540 /* sub-allocation manager, it has to be protected by another lock. 541 * By conception this is an helper for other part of the driver 542 * like the indirect buffer or semaphore, which both have their 543 * locking. 544 * 545 * Principe is simple, we keep a list of sub allocation in offset 546 * order (first entry has offset == 0, last entry has the highest 547 * offset). 548 * 549 * When allocating new object we first check if there is room at 550 * the end total_size - (last_object_offset + last_object_size) >= 551 * alloc_size. If so we allocate new object there. 552 * 553 * When there is not enough room at the end, we start waiting for 554 * each sub object until we reach object_offset+object_size >= 555 * alloc_size, this object then become the sub object we return. 556 * 557 * Alignment can't be bigger than page size. 558 * 559 * Hole are not considered for allocation to keep things simple. 560 * Assumption is that there won't be hole (all object on same 561 * alignment). 562 */ 563 struct radeon_sa_manager { 564 #ifdef __NetBSD__ 565 spinlock_t wq_lock; 566 drm_waitqueue_t wq; 567 #else 568 wait_queue_head_t wq; 569 #endif 570 struct radeon_bo *bo; 571 struct list_head *hole; 572 struct list_head flist[RADEON_NUM_RINGS]; 573 struct list_head olist; 574 unsigned size; 575 uint64_t gpu_addr; 576 void *cpu_ptr; 577 uint32_t domain; 578 uint32_t align; 579 }; 580 581 struct radeon_sa_bo; 582 583 /* sub-allocation buffer */ 584 struct radeon_sa_bo { 585 struct list_head olist; 586 struct list_head flist; 587 struct radeon_sa_manager *manager; 588 unsigned soffset; 589 unsigned eoffset; 590 struct radeon_fence *fence; 591 }; 592 593 /* 594 * GEM objects. 595 */ 596 struct radeon_gem { 597 struct mutex mutex; 598 struct list_head objects; 599 }; 600 601 int radeon_gem_init(struct radeon_device *rdev); 602 void radeon_gem_fini(struct radeon_device *rdev); 603 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 604 int alignment, int initial_domain, 605 u32 flags, bool kernel, 606 struct drm_gem_object **obj); 607 608 int radeon_mode_dumb_create(struct drm_file *file_priv, 609 struct drm_device *dev, 610 struct drm_mode_create_dumb *args); 611 int radeon_mode_dumb_mmap(struct drm_file *filp, 612 struct drm_device *dev, 613 uint32_t handle, uint64_t *offset_p); 614 615 /* 616 * Semaphores. 617 */ 618 struct radeon_semaphore { 619 struct radeon_sa_bo *sa_bo; 620 signed waiters; 621 uint64_t gpu_addr; 622 }; 623 624 int radeon_semaphore_create(struct radeon_device *rdev, 625 struct radeon_semaphore **semaphore); 626 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 627 struct radeon_semaphore *semaphore); 628 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 629 struct radeon_semaphore *semaphore); 630 void radeon_semaphore_free(struct radeon_device *rdev, 631 struct radeon_semaphore **semaphore, 632 struct radeon_fence *fence); 633 634 /* 635 * Synchronization 636 */ 637 struct radeon_sync { 638 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 639 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 640 struct radeon_fence *last_vm_update; 641 }; 642 643 void radeon_sync_create(struct radeon_sync *sync); 644 void radeon_sync_fence(struct radeon_sync *sync, 645 struct radeon_fence *fence); 646 int radeon_sync_resv(struct radeon_device *rdev, 647 struct radeon_sync *sync, 648 struct reservation_object *resv, 649 bool shared); 650 int radeon_sync_rings(struct radeon_device *rdev, 651 struct radeon_sync *sync, 652 int waiting_ring); 653 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 654 struct radeon_fence *fence); 655 656 /* 657 * GART structures, functions & helpers 658 */ 659 struct radeon_mc; 660 661 #define RADEON_GPU_PAGE_SIZE 4096 662 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 663 #define RADEON_GPU_PAGE_SHIFT 12 664 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 665 666 #define RADEON_GART_PAGE_DUMMY 0 667 #define RADEON_GART_PAGE_VALID (1 << 0) 668 #define RADEON_GART_PAGE_READ (1 << 1) 669 #define RADEON_GART_PAGE_WRITE (1 << 2) 670 #define RADEON_GART_PAGE_SNOOP (1 << 3) 671 672 struct radeon_gart { 673 #ifdef __NetBSD__ 674 bus_dma_segment_t rg_table_seg; 675 bus_dmamap_t rg_table_map; 676 #endif 677 dma_addr_t table_addr; 678 struct radeon_bo *robj; 679 void *ptr; 680 unsigned num_gpu_pages; 681 unsigned num_cpu_pages; 682 unsigned table_size; 683 struct page **pages; 684 uint64_t *pages_entry; 685 bool ready; 686 }; 687 688 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 689 void radeon_gart_table_ram_free(struct radeon_device *rdev); 690 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 691 void radeon_gart_table_vram_free(struct radeon_device *rdev); 692 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 693 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 694 int radeon_gart_init(struct radeon_device *rdev); 695 void radeon_gart_fini(struct radeon_device *rdev); 696 #ifdef __NetBSD__ 697 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 698 unsigned npages); 699 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 700 unsigned npages, struct page **pages, 701 bus_dmamap_t dmamap, uint32_t flags); 702 #else 703 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 704 int pages); 705 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 706 int pages, struct page **pagelist, 707 dma_addr_t *dma_addr, uint32_t flags); 708 #endif 709 710 711 /* 712 * GPU MC structures, functions & helpers 713 */ 714 struct radeon_mc { 715 resource_size_t aper_size; 716 resource_size_t aper_base; 717 resource_size_t agp_base; 718 /* for some chips with <= 32MB we need to lie 719 * about vram size near mc fb location */ 720 u64 mc_vram_size; 721 u64 visible_vram_size; 722 u64 gtt_size; 723 u64 gtt_start; 724 u64 gtt_end; 725 u64 vram_start; 726 u64 vram_end; 727 unsigned vram_width; 728 u64 real_vram_size; 729 int vram_mtrr; 730 bool vram_is_ddr; 731 bool igp_sideport_enabled; 732 u64 gtt_base_align; 733 u64 mc_mask; 734 }; 735 736 bool radeon_combios_sideport_present(struct radeon_device *rdev); 737 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 738 739 /* 740 * GPU scratch registers structures, functions & helpers 741 */ 742 struct radeon_scratch { 743 unsigned num_reg; 744 uint32_t reg_base; 745 bool free[32]; 746 uint32_t reg[32]; 747 }; 748 749 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 750 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 751 752 /* 753 * GPU doorbell structures, functions & helpers 754 */ 755 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 756 757 struct radeon_doorbell { 758 /* doorbell mmio */ 759 resource_size_t base; 760 resource_size_t size; 761 #ifdef __NetBSD__ 762 bus_space_tag_t bst; 763 bus_space_handle_t bsh; 764 #else 765 u32 __iomem *ptr; 766 #endif 767 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 768 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 769 }; 770 771 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 772 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 773 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 774 phys_addr_t *aperture_base, 775 size_t *aperture_size, 776 size_t *start_offset); 777 778 /* 779 * IRQS. 780 */ 781 782 struct radeon_flip_work { 783 struct work_struct flip_work; 784 struct work_struct unpin_work; 785 struct radeon_device *rdev; 786 int crtc_id; 787 uint64_t base; 788 struct drm_pending_vblank_event *event; 789 struct radeon_bo *old_rbo; 790 struct fence *fence; 791 }; 792 793 struct r500_irq_stat_regs { 794 u32 disp_int; 795 u32 hdmi0_status; 796 }; 797 798 struct r600_irq_stat_regs { 799 u32 disp_int; 800 u32 disp_int_cont; 801 u32 disp_int_cont2; 802 u32 d1grph_int; 803 u32 d2grph_int; 804 u32 hdmi0_status; 805 u32 hdmi1_status; 806 }; 807 808 struct evergreen_irq_stat_regs { 809 u32 disp_int; 810 u32 disp_int_cont; 811 u32 disp_int_cont2; 812 u32 disp_int_cont3; 813 u32 disp_int_cont4; 814 u32 disp_int_cont5; 815 u32 d1grph_int; 816 u32 d2grph_int; 817 u32 d3grph_int; 818 u32 d4grph_int; 819 u32 d5grph_int; 820 u32 d6grph_int; 821 u32 afmt_status1; 822 u32 afmt_status2; 823 u32 afmt_status3; 824 u32 afmt_status4; 825 u32 afmt_status5; 826 u32 afmt_status6; 827 }; 828 829 struct cik_irq_stat_regs { 830 u32 disp_int; 831 u32 disp_int_cont; 832 u32 disp_int_cont2; 833 u32 disp_int_cont3; 834 u32 disp_int_cont4; 835 u32 disp_int_cont5; 836 u32 disp_int_cont6; 837 u32 d1grph_int; 838 u32 d2grph_int; 839 u32 d3grph_int; 840 u32 d4grph_int; 841 u32 d5grph_int; 842 u32 d6grph_int; 843 }; 844 845 union radeon_irq_stat_regs { 846 struct r500_irq_stat_regs r500; 847 struct r600_irq_stat_regs r600; 848 struct evergreen_irq_stat_regs evergreen; 849 struct cik_irq_stat_regs cik; 850 }; 851 852 struct radeon_irq { 853 bool installed; 854 spinlock_t lock; 855 atomic_t ring_int[RADEON_NUM_RINGS]; 856 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 857 atomic_t pflip[RADEON_MAX_CRTCS]; 858 #ifdef __NetBSD__ 859 spinlock_t vblank_lock; 860 drm_waitqueue_t vblank_queue; 861 #else 862 wait_queue_head_t vblank_queue; 863 #endif 864 bool hpd[RADEON_MAX_HPD_PINS]; 865 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 866 union radeon_irq_stat_regs stat_regs; 867 bool dpm_thermal; 868 }; 869 870 int radeon_irq_kms_init(struct radeon_device *rdev); 871 void radeon_irq_kms_fini(struct radeon_device *rdev); 872 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 873 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 874 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 875 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 876 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 877 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 878 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 879 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 880 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 881 882 /* 883 * CP & rings. 884 */ 885 886 struct radeon_ib { 887 struct radeon_sa_bo *sa_bo; 888 uint32_t length_dw; 889 uint64_t gpu_addr; 890 uint32_t *ptr; 891 int ring; 892 struct radeon_fence *fence; 893 struct radeon_vm *vm; 894 bool is_const_ib; 895 struct radeon_sync sync; 896 }; 897 898 struct radeon_ring { 899 struct radeon_bo *ring_obj; 900 volatile uint32_t *ring; 901 unsigned rptr_offs; 902 unsigned rptr_save_reg; 903 u64 next_rptr_gpu_addr; 904 volatile u32 *next_rptr_cpu_addr; 905 unsigned wptr; 906 unsigned wptr_old; 907 unsigned ring_size; 908 unsigned ring_free_dw; 909 int count_dw; 910 atomic_t last_rptr; 911 atomic64_t last_activity; 912 uint64_t gpu_addr; 913 uint32_t align_mask; 914 uint32_t ptr_mask; 915 bool ready; 916 u32 nop; 917 u32 idx; 918 u64 last_semaphore_signal_addr; 919 u64 last_semaphore_wait_addr; 920 /* for CIK queues */ 921 u32 me; 922 u32 pipe; 923 u32 queue; 924 struct radeon_bo *mqd_obj; 925 u32 doorbell_index; 926 unsigned wptr_offs; 927 }; 928 929 struct radeon_mec { 930 struct radeon_bo *hpd_eop_obj; 931 u64 hpd_eop_gpu_addr; 932 u32 num_pipe; 933 u32 num_mec; 934 u32 num_queue; 935 }; 936 937 /* 938 * VM 939 */ 940 941 /* maximum number of VMIDs */ 942 #define RADEON_NUM_VM 16 943 944 /* number of entries in page table */ 945 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 946 947 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 948 #define RADEON_VM_PTB_ALIGN_SIZE 32768 949 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 950 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 951 952 #define R600_PTE_VALID (1 << 0) 953 #define R600_PTE_SYSTEM (1 << 1) 954 #define R600_PTE_SNOOPED (1 << 2) 955 #define R600_PTE_READABLE (1 << 5) 956 #define R600_PTE_WRITEABLE (1 << 6) 957 958 /* PTE (Page Table Entry) fragment field for different page sizes */ 959 #define R600_PTE_FRAG_4KB (0 << 7) 960 #define R600_PTE_FRAG_64KB (4 << 7) 961 #define R600_PTE_FRAG_256KB (6 << 7) 962 963 /* flags needed to be set so we can copy directly from the GART table */ 964 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 965 R600_PTE_SYSTEM | R600_PTE_VALID ) 966 967 struct radeon_vm_pt { 968 struct radeon_bo *bo; 969 uint64_t addr; 970 }; 971 972 struct radeon_vm_id { 973 unsigned id; 974 uint64_t pd_gpu_addr; 975 /* last flushed PD/PT update */ 976 struct radeon_fence *flushed_updates; 977 /* last use of vmid */ 978 struct radeon_fence *last_id_use; 979 }; 980 981 struct radeon_vm { 982 struct mutex mutex; 983 984 struct rb_root va; 985 986 /* protecting invalidated and freed */ 987 spinlock_t status_lock; 988 989 /* BOs moved, but not yet updated in the PT */ 990 struct list_head invalidated; 991 992 /* BOs freed, but not yet updated in the PT */ 993 struct list_head freed; 994 995 /* BOs cleared in the PT */ 996 struct list_head cleared; 997 998 /* contains the page directory */ 999 struct radeon_bo *page_directory; 1000 unsigned max_pde_used; 1001 1002 /* array of page tables, one for each page directory entry */ 1003 struct radeon_vm_pt *page_tables; 1004 1005 struct radeon_bo_va *ib_bo_va; 1006 1007 /* for id and flush management per ring */ 1008 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 1009 }; 1010 1011 struct radeon_vm_manager { 1012 struct radeon_fence *active[RADEON_NUM_VM]; 1013 uint32_t max_pfn; 1014 /* number of VMIDs */ 1015 unsigned nvm; 1016 /* vram base address for page table entry */ 1017 u64 vram_base_offset; 1018 /* is vm enabled? */ 1019 bool enabled; 1020 /* for hw to save the PD addr on suspend/resume */ 1021 uint32_t saved_table_addr[RADEON_NUM_VM]; 1022 }; 1023 1024 /* 1025 * file private structure 1026 */ 1027 struct radeon_fpriv { 1028 struct radeon_vm vm; 1029 }; 1030 1031 /* 1032 * R6xx+ IH ring 1033 */ 1034 struct r600_ih { 1035 struct radeon_bo *ring_obj; 1036 volatile uint32_t *ring; 1037 unsigned rptr; 1038 unsigned ring_size; 1039 uint64_t gpu_addr; 1040 uint32_t ptr_mask; 1041 atomic_t lock; 1042 bool enabled; 1043 }; 1044 1045 /* 1046 * RLC stuff 1047 */ 1048 #include "clearstate_defs.h" 1049 1050 struct radeon_rlc { 1051 /* for power gating */ 1052 struct radeon_bo *save_restore_obj; 1053 uint64_t save_restore_gpu_addr; 1054 volatile uint32_t *sr_ptr; 1055 const u32 *reg_list; 1056 u32 reg_list_size; 1057 /* for clear state */ 1058 struct radeon_bo *clear_state_obj; 1059 uint64_t clear_state_gpu_addr; 1060 volatile uint32_t *cs_ptr; 1061 const struct cs_section_def *cs_data; 1062 u32 clear_state_size; 1063 /* for cp tables */ 1064 struct radeon_bo *cp_table_obj; 1065 uint64_t cp_table_gpu_addr; 1066 volatile uint32_t *cp_table_ptr; 1067 u32 cp_table_size; 1068 }; 1069 1070 int radeon_ib_get(struct radeon_device *rdev, int ring, 1071 struct radeon_ib *ib, struct radeon_vm *vm, 1072 unsigned size); 1073 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1074 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1075 struct radeon_ib *const_ib, bool hdp_flush); 1076 int radeon_ib_pool_init(struct radeon_device *rdev); 1077 void radeon_ib_pool_fini(struct radeon_device *rdev); 1078 int radeon_ib_ring_tests(struct radeon_device *rdev); 1079 /* Ring access between begin & end cannot sleep */ 1080 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1081 struct radeon_ring *ring); 1082 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1083 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1084 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1085 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1086 bool hdp_flush); 1087 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1088 bool hdp_flush); 1089 void radeon_ring_undo(struct radeon_ring *ring); 1090 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1091 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1092 void radeon_ring_lockup_update(struct radeon_device *rdev, 1093 struct radeon_ring *ring); 1094 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1095 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1096 uint32_t **data); 1097 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1098 unsigned size, uint32_t *data); 1099 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1100 unsigned rptr_offs, u32 nop); 1101 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1102 1103 1104 /* r600 async dma */ 1105 void r600_dma_stop(struct radeon_device *rdev); 1106 int r600_dma_resume(struct radeon_device *rdev); 1107 void r600_dma_fini(struct radeon_device *rdev); 1108 1109 void cayman_dma_stop(struct radeon_device *rdev); 1110 int cayman_dma_resume(struct radeon_device *rdev); 1111 void cayman_dma_fini(struct radeon_device *rdev); 1112 1113 /* 1114 * CS. 1115 */ 1116 struct radeon_cs_chunk { 1117 uint32_t length_dw; 1118 uint32_t *kdata; 1119 void __user *user_ptr; 1120 }; 1121 1122 struct radeon_cs_parser { 1123 struct device *dev; 1124 struct radeon_device *rdev; 1125 struct drm_file *filp; 1126 /* chunks */ 1127 unsigned nchunks; 1128 struct radeon_cs_chunk *chunks; 1129 uint64_t *chunks_array; 1130 /* IB */ 1131 unsigned idx; 1132 /* relocations */ 1133 unsigned nrelocs; 1134 struct radeon_bo_list *relocs; 1135 struct radeon_bo_list *vm_bos; 1136 struct list_head validated; 1137 unsigned dma_reloc_idx; 1138 /* indices of various chunks */ 1139 struct radeon_cs_chunk *chunk_ib; 1140 struct radeon_cs_chunk *chunk_relocs; 1141 struct radeon_cs_chunk *chunk_flags; 1142 struct radeon_cs_chunk *chunk_const_ib; 1143 struct radeon_ib ib; 1144 struct radeon_ib const_ib; 1145 void *track; 1146 unsigned family; 1147 int parser_error; 1148 u32 cs_flags; 1149 u32 ring; 1150 s32 priority; 1151 struct ww_acquire_ctx ticket; 1152 }; 1153 1154 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1155 { 1156 struct radeon_cs_chunk *ibc = p->chunk_ib; 1157 1158 if (ibc->kdata) 1159 return ibc->kdata[idx]; 1160 return p->ib.ptr[idx]; 1161 } 1162 1163 1164 struct radeon_cs_packet { 1165 unsigned idx; 1166 unsigned type; 1167 unsigned reg; 1168 unsigned opcode; 1169 int count; 1170 unsigned one_reg_wr; 1171 }; 1172 1173 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1174 struct radeon_cs_packet *pkt, 1175 unsigned idx, unsigned reg); 1176 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1177 struct radeon_cs_packet *pkt); 1178 1179 1180 /* 1181 * AGP 1182 */ 1183 int radeon_agp_init(struct radeon_device *rdev); 1184 void radeon_agp_resume(struct radeon_device *rdev); 1185 void radeon_agp_suspend(struct radeon_device *rdev); 1186 void radeon_agp_fini(struct radeon_device *rdev); 1187 1188 1189 /* 1190 * Writeback 1191 */ 1192 struct radeon_wb { 1193 struct radeon_bo *wb_obj; 1194 volatile uint32_t *wb; 1195 uint64_t gpu_addr; 1196 bool enabled; 1197 bool use_event; 1198 }; 1199 1200 #define RADEON_WB_SCRATCH_OFFSET 0 1201 #define RADEON_WB_RING0_NEXT_RPTR 256 1202 #define RADEON_WB_CP_RPTR_OFFSET 1024 1203 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1204 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1205 #define R600_WB_DMA_RPTR_OFFSET 1792 1206 #define R600_WB_IH_WPTR_OFFSET 2048 1207 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1208 #define R600_WB_EVENT_OFFSET 3072 1209 #define CIK_WB_CP1_WPTR_OFFSET 3328 1210 #define CIK_WB_CP2_WPTR_OFFSET 3584 1211 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1212 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1213 1214 /** 1215 * struct radeon_pm - power management datas 1216 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1217 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1218 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1219 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1220 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1221 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1222 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1223 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1224 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1225 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1226 * @needed_bandwidth: current bandwidth needs 1227 * 1228 * It keeps track of various data needed to take powermanagement decision. 1229 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1230 * Equation between gpu/memory clock and available bandwidth is hw dependent 1231 * (type of memory, bus size, efficiency, ...) 1232 */ 1233 1234 enum radeon_pm_method { 1235 PM_METHOD_PROFILE, 1236 PM_METHOD_DYNPM, 1237 PM_METHOD_DPM, 1238 }; 1239 1240 enum radeon_dynpm_state { 1241 DYNPM_STATE_DISABLED, 1242 DYNPM_STATE_MINIMUM, 1243 DYNPM_STATE_PAUSED, 1244 DYNPM_STATE_ACTIVE, 1245 DYNPM_STATE_SUSPENDED, 1246 }; 1247 enum radeon_dynpm_action { 1248 DYNPM_ACTION_NONE, 1249 DYNPM_ACTION_MINIMUM, 1250 DYNPM_ACTION_DOWNCLOCK, 1251 DYNPM_ACTION_UPCLOCK, 1252 DYNPM_ACTION_DEFAULT 1253 }; 1254 1255 enum radeon_voltage_type { 1256 VOLTAGE_NONE = 0, 1257 VOLTAGE_GPIO, 1258 VOLTAGE_VDDC, 1259 VOLTAGE_SW 1260 }; 1261 1262 enum radeon_pm_state_type { 1263 /* not used for dpm */ 1264 POWER_STATE_TYPE_DEFAULT, 1265 POWER_STATE_TYPE_POWERSAVE, 1266 /* user selectable states */ 1267 POWER_STATE_TYPE_BATTERY, 1268 POWER_STATE_TYPE_BALANCED, 1269 POWER_STATE_TYPE_PERFORMANCE, 1270 /* internal states */ 1271 POWER_STATE_TYPE_INTERNAL_UVD, 1272 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1273 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1274 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1275 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1276 POWER_STATE_TYPE_INTERNAL_BOOT, 1277 POWER_STATE_TYPE_INTERNAL_THERMAL, 1278 POWER_STATE_TYPE_INTERNAL_ACPI, 1279 POWER_STATE_TYPE_INTERNAL_ULV, 1280 POWER_STATE_TYPE_INTERNAL_3DPERF, 1281 }; 1282 1283 enum radeon_pm_profile_type { 1284 PM_PROFILE_DEFAULT, 1285 PM_PROFILE_AUTO, 1286 PM_PROFILE_LOW, 1287 PM_PROFILE_MID, 1288 PM_PROFILE_HIGH, 1289 }; 1290 1291 #define PM_PROFILE_DEFAULT_IDX 0 1292 #define PM_PROFILE_LOW_SH_IDX 1 1293 #define PM_PROFILE_MID_SH_IDX 2 1294 #define PM_PROFILE_HIGH_SH_IDX 3 1295 #define PM_PROFILE_LOW_MH_IDX 4 1296 #define PM_PROFILE_MID_MH_IDX 5 1297 #define PM_PROFILE_HIGH_MH_IDX 6 1298 #define PM_PROFILE_MAX 7 1299 1300 struct radeon_pm_profile { 1301 int dpms_off_ps_idx; 1302 int dpms_on_ps_idx; 1303 int dpms_off_cm_idx; 1304 int dpms_on_cm_idx; 1305 }; 1306 1307 enum radeon_int_thermal_type { 1308 THERMAL_TYPE_NONE, 1309 THERMAL_TYPE_EXTERNAL, 1310 THERMAL_TYPE_EXTERNAL_GPIO, 1311 THERMAL_TYPE_RV6XX, 1312 THERMAL_TYPE_RV770, 1313 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1314 THERMAL_TYPE_EVERGREEN, 1315 THERMAL_TYPE_SUMO, 1316 THERMAL_TYPE_NI, 1317 THERMAL_TYPE_SI, 1318 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1319 THERMAL_TYPE_CI, 1320 THERMAL_TYPE_KV, 1321 }; 1322 1323 struct radeon_voltage { 1324 enum radeon_voltage_type type; 1325 /* gpio voltage */ 1326 struct radeon_gpio_rec gpio; 1327 u32 delay; /* delay in usec from voltage drop to sclk change */ 1328 bool active_high; /* voltage drop is active when bit is high */ 1329 /* VDDC voltage */ 1330 u8 vddc_id; /* index into vddc voltage table */ 1331 u8 vddci_id; /* index into vddci voltage table */ 1332 bool vddci_enabled; 1333 /* r6xx+ sw */ 1334 u16 voltage; 1335 /* evergreen+ vddci */ 1336 u16 vddci; 1337 }; 1338 1339 /* clock mode flags */ 1340 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1341 1342 struct radeon_pm_clock_info { 1343 /* memory clock */ 1344 u32 mclk; 1345 /* engine clock */ 1346 u32 sclk; 1347 /* voltage info */ 1348 struct radeon_voltage voltage; 1349 /* standardized clock flags */ 1350 u32 flags; 1351 }; 1352 1353 /* state flags */ 1354 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1355 1356 struct radeon_power_state { 1357 enum radeon_pm_state_type type; 1358 struct radeon_pm_clock_info *clock_info; 1359 /* number of valid clock modes in this power state */ 1360 int num_clock_modes; 1361 struct radeon_pm_clock_info *default_clock_mode; 1362 /* standardized state flags */ 1363 u32 flags; 1364 u32 misc; /* vbios specific flags */ 1365 u32 misc2; /* vbios specific flags */ 1366 int pcie_lanes; /* pcie lanes */ 1367 }; 1368 1369 /* 1370 * Some modes are overclocked by very low value, accept them 1371 */ 1372 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1373 1374 enum radeon_dpm_auto_throttle_src { 1375 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1376 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1377 }; 1378 1379 enum radeon_dpm_event_src { 1380 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1381 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1382 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1383 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1384 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1385 }; 1386 1387 #define RADEON_MAX_VCE_LEVELS 6 1388 1389 enum radeon_vce_level { 1390 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1391 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1392 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1393 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1394 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1395 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1396 }; 1397 1398 struct radeon_ps { 1399 u32 caps; /* vbios flags */ 1400 u32 class; /* vbios flags */ 1401 u32 class2; /* vbios flags */ 1402 /* UVD clocks */ 1403 u32 vclk; 1404 u32 dclk; 1405 /* VCE clocks */ 1406 u32 evclk; 1407 u32 ecclk; 1408 bool vce_active; 1409 enum radeon_vce_level vce_level; 1410 /* asic priv */ 1411 void *ps_priv; 1412 }; 1413 1414 struct radeon_dpm_thermal { 1415 /* thermal interrupt work */ 1416 struct work_struct work; 1417 /* low temperature threshold */ 1418 int min_temp; 1419 /* high temperature threshold */ 1420 int max_temp; 1421 /* was interrupt low to high or high to low */ 1422 bool high_to_low; 1423 }; 1424 1425 enum radeon_clk_action 1426 { 1427 RADEON_SCLK_UP = 1, 1428 RADEON_SCLK_DOWN 1429 }; 1430 1431 struct radeon_blacklist_clocks 1432 { 1433 u32 sclk; 1434 u32 mclk; 1435 enum radeon_clk_action action; 1436 }; 1437 1438 struct radeon_clock_and_voltage_limits { 1439 u32 sclk; 1440 u32 mclk; 1441 u16 vddc; 1442 u16 vddci; 1443 }; 1444 1445 struct radeon_clock_array { 1446 u32 count; 1447 u32 *values; 1448 }; 1449 1450 struct radeon_clock_voltage_dependency_entry { 1451 u32 clk; 1452 u16 v; 1453 }; 1454 1455 struct radeon_clock_voltage_dependency_table { 1456 u32 count; 1457 struct radeon_clock_voltage_dependency_entry *entries; 1458 }; 1459 1460 union radeon_cac_leakage_entry { 1461 struct { 1462 u16 vddc; 1463 u32 leakage; 1464 }; 1465 struct { 1466 u16 vddc1; 1467 u16 vddc2; 1468 u16 vddc3; 1469 }; 1470 }; 1471 1472 struct radeon_cac_leakage_table { 1473 u32 count; 1474 union radeon_cac_leakage_entry *entries; 1475 }; 1476 1477 struct radeon_phase_shedding_limits_entry { 1478 u16 voltage; 1479 u32 sclk; 1480 u32 mclk; 1481 }; 1482 1483 struct radeon_phase_shedding_limits_table { 1484 u32 count; 1485 struct radeon_phase_shedding_limits_entry *entries; 1486 }; 1487 1488 struct radeon_uvd_clock_voltage_dependency_entry { 1489 u32 vclk; 1490 u32 dclk; 1491 u16 v; 1492 }; 1493 1494 struct radeon_uvd_clock_voltage_dependency_table { 1495 u8 count; 1496 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1497 }; 1498 1499 struct radeon_vce_clock_voltage_dependency_entry { 1500 u32 ecclk; 1501 u32 evclk; 1502 u16 v; 1503 }; 1504 1505 struct radeon_vce_clock_voltage_dependency_table { 1506 u8 count; 1507 struct radeon_vce_clock_voltage_dependency_entry *entries; 1508 }; 1509 1510 struct radeon_ppm_table { 1511 u8 ppm_design; 1512 u16 cpu_core_number; 1513 u32 platform_tdp; 1514 u32 small_ac_platform_tdp; 1515 u32 platform_tdc; 1516 u32 small_ac_platform_tdc; 1517 u32 apu_tdp; 1518 u32 dgpu_tdp; 1519 u32 dgpu_ulv_power; 1520 u32 tj_max; 1521 }; 1522 1523 struct radeon_cac_tdp_table { 1524 u16 tdp; 1525 u16 configurable_tdp; 1526 u16 tdc; 1527 u16 battery_power_limit; 1528 u16 small_power_limit; 1529 u16 low_cac_leakage; 1530 u16 high_cac_leakage; 1531 u16 maximum_power_delivery_limit; 1532 }; 1533 1534 struct radeon_dpm_dynamic_state { 1535 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1536 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1537 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1538 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1539 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1540 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1541 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1542 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1543 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1544 struct radeon_clock_array valid_sclk_values; 1545 struct radeon_clock_array valid_mclk_values; 1546 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1547 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1548 u32 mclk_sclk_ratio; 1549 u32 sclk_mclk_delta; 1550 u16 vddc_vddci_delta; 1551 u16 min_vddc_for_pcie_gen2; 1552 struct radeon_cac_leakage_table cac_leakage_table; 1553 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1554 struct radeon_ppm_table *ppm_table; 1555 struct radeon_cac_tdp_table *cac_tdp_table; 1556 }; 1557 1558 struct radeon_dpm_fan { 1559 u16 t_min; 1560 u16 t_med; 1561 u16 t_high; 1562 u16 pwm_min; 1563 u16 pwm_med; 1564 u16 pwm_high; 1565 u8 t_hyst; 1566 u32 cycle_delay; 1567 u16 t_max; 1568 u8 control_mode; 1569 u16 default_max_fan_pwm; 1570 u16 default_fan_output_sensitivity; 1571 u16 fan_output_sensitivity; 1572 bool ucode_fan_control; 1573 }; 1574 1575 enum radeon_pcie_gen { 1576 RADEON_PCIE_GEN1 = 0, 1577 RADEON_PCIE_GEN2 = 1, 1578 RADEON_PCIE_GEN3 = 2, 1579 RADEON_PCIE_GEN_INVALID = 0xffff 1580 }; 1581 1582 enum radeon_dpm_forced_level { 1583 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1584 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1585 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1586 }; 1587 1588 struct radeon_vce_state { 1589 /* vce clocks */ 1590 u32 evclk; 1591 u32 ecclk; 1592 /* gpu clocks */ 1593 u32 sclk; 1594 u32 mclk; 1595 u8 clk_idx; 1596 u8 pstate; 1597 }; 1598 1599 struct radeon_dpm { 1600 struct radeon_ps *ps; 1601 /* number of valid power states */ 1602 int num_ps; 1603 /* current power state that is active */ 1604 struct radeon_ps *current_ps; 1605 /* requested power state */ 1606 struct radeon_ps *requested_ps; 1607 /* boot up power state */ 1608 struct radeon_ps *boot_ps; 1609 /* default uvd power state */ 1610 struct radeon_ps *uvd_ps; 1611 /* vce requirements */ 1612 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1613 enum radeon_vce_level vce_level; 1614 enum radeon_pm_state_type state; 1615 enum radeon_pm_state_type user_state; 1616 u32 platform_caps; 1617 u32 voltage_response_time; 1618 u32 backbias_response_time; 1619 void *priv; 1620 u32 new_active_crtcs; 1621 int new_active_crtc_count; 1622 u32 current_active_crtcs; 1623 int current_active_crtc_count; 1624 bool single_display; 1625 struct radeon_dpm_dynamic_state dyn_state; 1626 struct radeon_dpm_fan fan; 1627 u32 tdp_limit; 1628 u32 near_tdp_limit; 1629 u32 near_tdp_limit_adjusted; 1630 u32 sq_ramping_threshold; 1631 u32 cac_leakage; 1632 u16 tdp_od_limit; 1633 u32 tdp_adjustment; 1634 u16 load_line_slope; 1635 bool power_control; 1636 bool ac_power; 1637 /* special states active */ 1638 bool thermal_active; 1639 bool uvd_active; 1640 bool vce_active; 1641 /* thermal handling */ 1642 struct radeon_dpm_thermal thermal; 1643 /* forced levels */ 1644 enum radeon_dpm_forced_level forced_level; 1645 /* track UVD streams */ 1646 unsigned sd; 1647 unsigned hd; 1648 }; 1649 1650 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1651 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1652 1653 struct radeon_pm { 1654 struct mutex mutex; 1655 /* write locked while reprogramming mclk */ 1656 struct rw_semaphore mclk_lock; 1657 u32 active_crtcs; 1658 int active_crtc_count; 1659 int req_vblank; 1660 bool vblank_sync; 1661 fixed20_12 max_bandwidth; 1662 fixed20_12 igp_sideport_mclk; 1663 fixed20_12 igp_system_mclk; 1664 fixed20_12 igp_ht_link_clk; 1665 fixed20_12 igp_ht_link_width; 1666 fixed20_12 k8_bandwidth; 1667 fixed20_12 sideport_bandwidth; 1668 fixed20_12 ht_bandwidth; 1669 fixed20_12 core_bandwidth; 1670 fixed20_12 sclk; 1671 fixed20_12 mclk; 1672 fixed20_12 needed_bandwidth; 1673 struct radeon_power_state *power_state; 1674 /* number of valid power states */ 1675 int num_power_states; 1676 int current_power_state_index; 1677 int current_clock_mode_index; 1678 int requested_power_state_index; 1679 int requested_clock_mode_index; 1680 int default_power_state_index; 1681 u32 current_sclk; 1682 u32 current_mclk; 1683 u16 current_vddc; 1684 u16 current_vddci; 1685 u32 default_sclk; 1686 u32 default_mclk; 1687 u16 default_vddc; 1688 u16 default_vddci; 1689 struct radeon_i2c_chan *i2c_bus; 1690 /* selected pm method */ 1691 enum radeon_pm_method pm_method; 1692 /* dynpm power management */ 1693 struct delayed_work dynpm_idle_work; 1694 enum radeon_dynpm_state dynpm_state; 1695 enum radeon_dynpm_action dynpm_planned_action; 1696 unsigned long dynpm_action_timeout; 1697 bool dynpm_can_upclock; 1698 bool dynpm_can_downclock; 1699 /* profile-based power management */ 1700 enum radeon_pm_profile_type profile; 1701 int profile_index; 1702 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1703 /* internal thermal controller on rv6xx+ */ 1704 enum radeon_int_thermal_type int_thermal_type; 1705 struct device *int_hwmon_dev; 1706 /* fan control parameters */ 1707 bool no_fan; 1708 u8 fan_pulses_per_revolution; 1709 u8 fan_min_rpm; 1710 u8 fan_max_rpm; 1711 /* dpm */ 1712 bool dpm_enabled; 1713 bool sysfs_initialized; 1714 struct radeon_dpm dpm; 1715 }; 1716 1717 int radeon_pm_get_type_index(struct radeon_device *rdev, 1718 enum radeon_pm_state_type ps_type, 1719 int instance); 1720 /* 1721 * UVD 1722 */ 1723 #define RADEON_MAX_UVD_HANDLES 10 1724 #define RADEON_UVD_STACK_SIZE (1024*1024) 1725 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1726 1727 struct radeon_uvd { 1728 struct radeon_bo *vcpu_bo; 1729 void *cpu_addr; 1730 uint64_t gpu_addr; 1731 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1732 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1733 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1734 struct delayed_work idle_work; 1735 }; 1736 1737 int radeon_uvd_init(struct radeon_device *rdev); 1738 void radeon_uvd_fini(struct radeon_device *rdev); 1739 int radeon_uvd_suspend(struct radeon_device *rdev); 1740 int radeon_uvd_resume(struct radeon_device *rdev); 1741 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1742 uint32_t handle, struct radeon_fence **fence); 1743 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1744 uint32_t handle, struct radeon_fence **fence); 1745 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1746 uint32_t allowed_domains); 1747 void radeon_uvd_free_handles(struct radeon_device *rdev, 1748 struct drm_file *filp); 1749 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1750 void radeon_uvd_note_usage(struct radeon_device *rdev); 1751 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1752 unsigned vclk, unsigned dclk, 1753 unsigned vco_min, unsigned vco_max, 1754 unsigned fb_factor, unsigned fb_mask, 1755 unsigned pd_min, unsigned pd_max, 1756 unsigned pd_even, 1757 unsigned *optimal_fb_div, 1758 unsigned *optimal_vclk_div, 1759 unsigned *optimal_dclk_div); 1760 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1761 unsigned cg_upll_func_cntl); 1762 1763 /* 1764 * VCE 1765 */ 1766 #define RADEON_MAX_VCE_HANDLES 16 1767 1768 struct radeon_vce { 1769 struct radeon_bo *vcpu_bo; 1770 uint64_t gpu_addr; 1771 unsigned fw_version; 1772 unsigned fb_version; 1773 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1774 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1775 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1776 struct delayed_work idle_work; 1777 uint32_t keyselect; 1778 }; 1779 1780 int radeon_vce_init(struct radeon_device *rdev); 1781 void radeon_vce_fini(struct radeon_device *rdev); 1782 int radeon_vce_suspend(struct radeon_device *rdev); 1783 int radeon_vce_resume(struct radeon_device *rdev); 1784 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1785 uint32_t handle, struct radeon_fence **fence); 1786 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1787 uint32_t handle, struct radeon_fence **fence); 1788 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1789 void radeon_vce_note_usage(struct radeon_device *rdev); 1790 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1791 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1792 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1793 struct radeon_ring *ring, 1794 struct radeon_semaphore *semaphore, 1795 bool emit_wait); 1796 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1797 void radeon_vce_fence_emit(struct radeon_device *rdev, 1798 struct radeon_fence *fence); 1799 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1800 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1801 1802 struct r600_audio_pin { 1803 int channels; 1804 int rate; 1805 int bits_per_sample; 1806 u8 status_bits; 1807 u8 category_code; 1808 u32 offset; 1809 bool connected; 1810 u32 id; 1811 }; 1812 1813 struct r600_audio { 1814 bool enabled; 1815 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1816 int num_pins; 1817 struct radeon_audio_funcs *hdmi_funcs; 1818 struct radeon_audio_funcs *dp_funcs; 1819 struct radeon_audio_basic_funcs *funcs; 1820 }; 1821 1822 /* 1823 * Benchmarking 1824 */ 1825 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1826 1827 1828 /* 1829 * Testing 1830 */ 1831 void radeon_test_moves(struct radeon_device *rdev); 1832 void radeon_test_ring_sync(struct radeon_device *rdev, 1833 struct radeon_ring *cpA, 1834 struct radeon_ring *cpB); 1835 void radeon_test_syncing(struct radeon_device *rdev); 1836 1837 /* 1838 * MMU Notifier 1839 */ 1840 #if defined(CONFIG_MMU_NOTIFIER) 1841 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1842 void radeon_mn_unregister(struct radeon_bo *bo); 1843 #else 1844 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1845 { 1846 return -ENODEV; 1847 } 1848 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1849 #endif 1850 1851 /* 1852 * Debugfs 1853 */ 1854 struct radeon_debugfs { 1855 struct drm_info_list *files; 1856 unsigned num_files; 1857 }; 1858 1859 int radeon_debugfs_add_files(struct radeon_device *rdev, 1860 struct drm_info_list *files, 1861 unsigned nfiles); 1862 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1863 1864 /* 1865 * ASIC ring specific functions. 1866 */ 1867 struct radeon_asic_ring { 1868 /* ring read/write ptr handling */ 1869 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1870 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1871 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1872 1873 /* validating and patching of IBs */ 1874 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1875 int (*cs_parse)(struct radeon_cs_parser *p); 1876 1877 /* command emmit functions */ 1878 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1879 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1880 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1881 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1882 struct radeon_semaphore *semaphore, bool emit_wait); 1883 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1884 unsigned vm_id, uint64_t pd_addr); 1885 1886 /* testing functions */ 1887 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1888 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1889 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1890 1891 /* deprecated */ 1892 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1893 }; 1894 1895 /* 1896 * ASIC specific functions. 1897 */ 1898 struct radeon_asic { 1899 int (*init)(struct radeon_device *rdev); 1900 void (*fini)(struct radeon_device *rdev); 1901 int (*resume)(struct radeon_device *rdev); 1902 int (*suspend)(struct radeon_device *rdev); 1903 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1904 int (*asic_reset)(struct radeon_device *rdev); 1905 /* Flush the HDP cache via MMIO */ 1906 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1907 /* check if 3D engine is idle */ 1908 bool (*gui_idle)(struct radeon_device *rdev); 1909 /* wait for mc_idle */ 1910 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1911 /* get the reference clock */ 1912 u32 (*get_xclk)(struct radeon_device *rdev); 1913 /* get the gpu clock counter */ 1914 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1915 /* get register for info ioctl */ 1916 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1917 /* gart */ 1918 struct { 1919 void (*tlb_flush)(struct radeon_device *rdev); 1920 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1921 void (*set_page)(struct radeon_device *rdev, unsigned i, 1922 uint64_t entry); 1923 } gart; 1924 struct { 1925 int (*init)(struct radeon_device *rdev); 1926 void (*fini)(struct radeon_device *rdev); 1927 void (*copy_pages)(struct radeon_device *rdev, 1928 struct radeon_ib *ib, 1929 uint64_t pe, uint64_t src, 1930 unsigned count); 1931 void (*write_pages)(struct radeon_device *rdev, 1932 struct radeon_ib *ib, 1933 uint64_t pe, 1934 uint64_t addr, unsigned count, 1935 uint32_t incr, uint32_t flags); 1936 void (*set_pages)(struct radeon_device *rdev, 1937 struct radeon_ib *ib, 1938 uint64_t pe, 1939 uint64_t addr, unsigned count, 1940 uint32_t incr, uint32_t flags); 1941 void (*pad_ib)(struct radeon_ib *ib); 1942 } vm; 1943 /* ring specific callbacks */ 1944 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1945 /* irqs */ 1946 struct { 1947 int (*set)(struct radeon_device *rdev); 1948 int (*process)(struct radeon_device *rdev); 1949 } irq; 1950 /* displays */ 1951 struct { 1952 /* display watermarks */ 1953 void (*bandwidth_update)(struct radeon_device *rdev); 1954 /* get frame count */ 1955 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1956 /* wait for vblank */ 1957 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1958 /* set backlight level */ 1959 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1960 /* get backlight level */ 1961 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1962 /* audio callbacks */ 1963 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1964 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1965 } display; 1966 /* copy functions for bo handling */ 1967 struct { 1968 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1969 uint64_t src_offset, 1970 uint64_t dst_offset, 1971 unsigned num_gpu_pages, 1972 struct reservation_object *resv); 1973 u32 blit_ring_index; 1974 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1975 uint64_t src_offset, 1976 uint64_t dst_offset, 1977 unsigned num_gpu_pages, 1978 struct reservation_object *resv); 1979 u32 dma_ring_index; 1980 /* method used for bo copy */ 1981 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1982 uint64_t src_offset, 1983 uint64_t dst_offset, 1984 unsigned num_gpu_pages, 1985 struct reservation_object *resv); 1986 /* ring used for bo copies */ 1987 u32 copy_ring_index; 1988 } copy; 1989 /* surfaces */ 1990 struct { 1991 int (*set_reg)(struct radeon_device *rdev, int reg, 1992 uint32_t tiling_flags, uint32_t pitch, 1993 uint32_t offset, uint32_t obj_size); 1994 void (*clear_reg)(struct radeon_device *rdev, int reg); 1995 } surface; 1996 /* hotplug detect */ 1997 struct { 1998 void (*init)(struct radeon_device *rdev); 1999 void (*fini)(struct radeon_device *rdev); 2000 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 2001 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 2002 } hpd; 2003 /* static power management */ 2004 struct { 2005 void (*misc)(struct radeon_device *rdev); 2006 void (*prepare)(struct radeon_device *rdev); 2007 void (*finish)(struct radeon_device *rdev); 2008 void (*init_profile)(struct radeon_device *rdev); 2009 void (*get_dynpm_state)(struct radeon_device *rdev); 2010 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 2011 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 2012 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 2013 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 2014 int (*get_pcie_lanes)(struct radeon_device *rdev); 2015 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 2016 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 2017 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 2018 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 2019 int (*get_temperature)(struct radeon_device *rdev); 2020 } pm; 2021 /* dynamic power management */ 2022 struct { 2023 int (*init)(struct radeon_device *rdev); 2024 void (*setup_asic)(struct radeon_device *rdev); 2025 int (*enable)(struct radeon_device *rdev); 2026 int (*late_enable)(struct radeon_device *rdev); 2027 void (*disable)(struct radeon_device *rdev); 2028 int (*pre_set_power_state)(struct radeon_device *rdev); 2029 int (*set_power_state)(struct radeon_device *rdev); 2030 void (*post_set_power_state)(struct radeon_device *rdev); 2031 void (*display_configuration_changed)(struct radeon_device *rdev); 2032 void (*fini)(struct radeon_device *rdev); 2033 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2034 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2035 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2036 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2037 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2038 bool (*vblank_too_short)(struct radeon_device *rdev); 2039 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2040 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2041 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2042 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2043 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2044 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2045 u32 (*get_current_sclk)(struct radeon_device *rdev); 2046 u32 (*get_current_mclk)(struct radeon_device *rdev); 2047 } dpm; 2048 /* pageflipping */ 2049 struct { 2050 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 2051 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2052 } pflip; 2053 }; 2054 2055 /* 2056 * Asic structures 2057 */ 2058 struct r100_asic { 2059 const unsigned *reg_safe_bm; 2060 unsigned reg_safe_bm_size; 2061 u32 hdp_cntl; 2062 }; 2063 2064 struct r300_asic { 2065 const unsigned *reg_safe_bm; 2066 unsigned reg_safe_bm_size; 2067 u32 resync_scratch; 2068 u32 hdp_cntl; 2069 }; 2070 2071 struct r600_asic { 2072 unsigned max_pipes; 2073 unsigned max_tile_pipes; 2074 unsigned max_simds; 2075 unsigned max_backends; 2076 unsigned max_gprs; 2077 unsigned max_threads; 2078 unsigned max_stack_entries; 2079 unsigned max_hw_contexts; 2080 unsigned max_gs_threads; 2081 unsigned sx_max_export_size; 2082 unsigned sx_max_export_pos_size; 2083 unsigned sx_max_export_smx_size; 2084 unsigned sq_num_cf_insts; 2085 unsigned tiling_nbanks; 2086 unsigned tiling_npipes; 2087 unsigned tiling_group_size; 2088 unsigned tile_config; 2089 unsigned backend_map; 2090 unsigned active_simds; 2091 }; 2092 2093 struct rv770_asic { 2094 unsigned max_pipes; 2095 unsigned max_tile_pipes; 2096 unsigned max_simds; 2097 unsigned max_backends; 2098 unsigned max_gprs; 2099 unsigned max_threads; 2100 unsigned max_stack_entries; 2101 unsigned max_hw_contexts; 2102 unsigned max_gs_threads; 2103 unsigned sx_max_export_size; 2104 unsigned sx_max_export_pos_size; 2105 unsigned sx_max_export_smx_size; 2106 unsigned sq_num_cf_insts; 2107 unsigned sx_num_of_sets; 2108 unsigned sc_prim_fifo_size; 2109 unsigned sc_hiz_tile_fifo_size; 2110 unsigned sc_earlyz_tile_fifo_fize; 2111 unsigned tiling_nbanks; 2112 unsigned tiling_npipes; 2113 unsigned tiling_group_size; 2114 unsigned tile_config; 2115 unsigned backend_map; 2116 unsigned active_simds; 2117 }; 2118 2119 struct evergreen_asic { 2120 unsigned num_ses; 2121 unsigned max_pipes; 2122 unsigned max_tile_pipes; 2123 unsigned max_simds; 2124 unsigned max_backends; 2125 unsigned max_gprs; 2126 unsigned max_threads; 2127 unsigned max_stack_entries; 2128 unsigned max_hw_contexts; 2129 unsigned max_gs_threads; 2130 unsigned sx_max_export_size; 2131 unsigned sx_max_export_pos_size; 2132 unsigned sx_max_export_smx_size; 2133 unsigned sq_num_cf_insts; 2134 unsigned sx_num_of_sets; 2135 unsigned sc_prim_fifo_size; 2136 unsigned sc_hiz_tile_fifo_size; 2137 unsigned sc_earlyz_tile_fifo_size; 2138 unsigned tiling_nbanks; 2139 unsigned tiling_npipes; 2140 unsigned tiling_group_size; 2141 unsigned tile_config; 2142 unsigned backend_map; 2143 unsigned active_simds; 2144 }; 2145 2146 struct cayman_asic { 2147 unsigned max_shader_engines; 2148 unsigned max_pipes_per_simd; 2149 unsigned max_tile_pipes; 2150 unsigned max_simds_per_se; 2151 unsigned max_backends_per_se; 2152 unsigned max_texture_channel_caches; 2153 unsigned max_gprs; 2154 unsigned max_threads; 2155 unsigned max_gs_threads; 2156 unsigned max_stack_entries; 2157 unsigned sx_num_of_sets; 2158 unsigned sx_max_export_size; 2159 unsigned sx_max_export_pos_size; 2160 unsigned sx_max_export_smx_size; 2161 unsigned max_hw_contexts; 2162 unsigned sq_num_cf_insts; 2163 unsigned sc_prim_fifo_size; 2164 unsigned sc_hiz_tile_fifo_size; 2165 unsigned sc_earlyz_tile_fifo_size; 2166 2167 unsigned num_shader_engines; 2168 unsigned num_shader_pipes_per_simd; 2169 unsigned num_tile_pipes; 2170 unsigned num_simds_per_se; 2171 unsigned num_backends_per_se; 2172 unsigned backend_disable_mask_per_asic; 2173 unsigned backend_map; 2174 unsigned num_texture_channel_caches; 2175 unsigned mem_max_burst_length_bytes; 2176 unsigned mem_row_size_in_kb; 2177 unsigned shader_engine_tile_size; 2178 unsigned num_gpus; 2179 unsigned multi_gpu_tile_size; 2180 2181 unsigned tile_config; 2182 unsigned active_simds; 2183 }; 2184 2185 struct si_asic { 2186 unsigned max_shader_engines; 2187 unsigned max_tile_pipes; 2188 unsigned max_cu_per_sh; 2189 unsigned max_sh_per_se; 2190 unsigned max_backends_per_se; 2191 unsigned max_texture_channel_caches; 2192 unsigned max_gprs; 2193 unsigned max_gs_threads; 2194 unsigned max_hw_contexts; 2195 unsigned sc_prim_fifo_size_frontend; 2196 unsigned sc_prim_fifo_size_backend; 2197 unsigned sc_hiz_tile_fifo_size; 2198 unsigned sc_earlyz_tile_fifo_size; 2199 2200 unsigned num_tile_pipes; 2201 unsigned backend_enable_mask; 2202 unsigned backend_disable_mask_per_asic; 2203 unsigned backend_map; 2204 unsigned num_texture_channel_caches; 2205 unsigned mem_max_burst_length_bytes; 2206 unsigned mem_row_size_in_kb; 2207 unsigned shader_engine_tile_size; 2208 unsigned num_gpus; 2209 unsigned multi_gpu_tile_size; 2210 2211 unsigned tile_config; 2212 uint32_t tile_mode_array[32]; 2213 uint32_t active_cus; 2214 }; 2215 2216 struct cik_asic { 2217 unsigned max_shader_engines; 2218 unsigned max_tile_pipes; 2219 unsigned max_cu_per_sh; 2220 unsigned max_sh_per_se; 2221 unsigned max_backends_per_se; 2222 unsigned max_texture_channel_caches; 2223 unsigned max_gprs; 2224 unsigned max_gs_threads; 2225 unsigned max_hw_contexts; 2226 unsigned sc_prim_fifo_size_frontend; 2227 unsigned sc_prim_fifo_size_backend; 2228 unsigned sc_hiz_tile_fifo_size; 2229 unsigned sc_earlyz_tile_fifo_size; 2230 2231 unsigned num_tile_pipes; 2232 unsigned backend_enable_mask; 2233 unsigned backend_disable_mask_per_asic; 2234 unsigned backend_map; 2235 unsigned num_texture_channel_caches; 2236 unsigned mem_max_burst_length_bytes; 2237 unsigned mem_row_size_in_kb; 2238 unsigned shader_engine_tile_size; 2239 unsigned num_gpus; 2240 unsigned multi_gpu_tile_size; 2241 2242 unsigned tile_config; 2243 uint32_t tile_mode_array[32]; 2244 uint32_t macrotile_mode_array[16]; 2245 uint32_t active_cus; 2246 }; 2247 2248 union radeon_asic_config { 2249 struct r300_asic r300; 2250 struct r100_asic r100; 2251 struct r600_asic r600; 2252 struct rv770_asic rv770; 2253 struct evergreen_asic evergreen; 2254 struct cayman_asic cayman; 2255 struct si_asic si; 2256 struct cik_asic cik; 2257 }; 2258 2259 /* 2260 * asic initizalization from radeon_asic.c 2261 */ 2262 void radeon_agp_disable(struct radeon_device *rdev); 2263 int radeon_asic_init(struct radeon_device *rdev); 2264 2265 2266 /* 2267 * IOCTL. 2268 */ 2269 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2270 struct drm_file *filp); 2271 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2272 struct drm_file *filp); 2273 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2274 struct drm_file *filp); 2275 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2276 struct drm_file *file_priv); 2277 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2278 struct drm_file *file_priv); 2279 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2280 struct drm_file *file_priv); 2281 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2282 struct drm_file *file_priv); 2283 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2284 struct drm_file *filp); 2285 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2286 struct drm_file *filp); 2287 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2288 struct drm_file *filp); 2289 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2290 struct drm_file *filp); 2291 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2292 struct drm_file *filp); 2293 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2294 struct drm_file *filp); 2295 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2296 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2297 struct drm_file *filp); 2298 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2299 struct drm_file *filp); 2300 2301 /* VRAM scratch page for HDP bug, default vram page */ 2302 struct r600_vram_scratch { 2303 struct radeon_bo *robj; 2304 volatile uint32_t *ptr; 2305 u64 gpu_addr; 2306 }; 2307 2308 /* 2309 * ACPI 2310 */ 2311 struct radeon_atif_notification_cfg { 2312 bool enabled; 2313 int command_code; 2314 }; 2315 2316 struct radeon_atif_notifications { 2317 bool display_switch; 2318 bool expansion_mode_change; 2319 bool thermal_state; 2320 bool forced_power_state; 2321 bool system_power_state; 2322 bool display_conf_change; 2323 bool px_gfx_switch; 2324 bool brightness_change; 2325 bool dgpu_display_event; 2326 }; 2327 2328 struct radeon_atif_functions { 2329 bool system_params; 2330 bool sbios_requests; 2331 bool select_active_disp; 2332 bool lid_state; 2333 bool get_tv_standard; 2334 bool set_tv_standard; 2335 bool get_panel_expansion_mode; 2336 bool set_panel_expansion_mode; 2337 bool temperature_change; 2338 bool graphics_device_types; 2339 }; 2340 2341 struct radeon_atif { 2342 struct radeon_atif_notifications notifications; 2343 struct radeon_atif_functions functions; 2344 struct radeon_atif_notification_cfg notification_cfg; 2345 struct radeon_encoder *encoder_for_bl; 2346 }; 2347 2348 struct radeon_atcs_functions { 2349 bool get_ext_state; 2350 bool pcie_perf_req; 2351 bool pcie_dev_rdy; 2352 bool pcie_bus_width; 2353 }; 2354 2355 struct radeon_atcs { 2356 struct radeon_atcs_functions functions; 2357 }; 2358 2359 /* 2360 * Core structure, functions and helpers. 2361 */ 2362 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2363 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2364 2365 struct radeon_device { 2366 struct device *dev; 2367 struct drm_device *ddev; 2368 struct pci_dev *pdev; 2369 struct rw_semaphore exclusive_lock; 2370 /* ASIC */ 2371 union radeon_asic_config config; 2372 enum radeon_family family; 2373 unsigned long flags; 2374 int usec_timeout; 2375 enum radeon_pll_errata pll_errata; 2376 int num_gb_pipes; 2377 int num_z_pipes; 2378 int disp_priority; 2379 /* BIOS */ 2380 uint8_t *bios; 2381 bool is_atom_bios; 2382 uint16_t bios_header_start; 2383 struct radeon_bo *stollen_vga_memory; 2384 /* Register mmio */ 2385 #ifndef __NetBSD__ 2386 resource_size_t rmmio_base; 2387 resource_size_t rmmio_size; 2388 #endif 2389 /* protects concurrent MM_INDEX/DATA based register access */ 2390 spinlock_t mmio_idx_lock; 2391 /* protects concurrent SMC based register access */ 2392 spinlock_t smc_idx_lock; 2393 /* protects concurrent PLL register access */ 2394 spinlock_t pll_idx_lock; 2395 /* protects concurrent MC register access */ 2396 spinlock_t mc_idx_lock; 2397 /* protects concurrent PCIE register access */ 2398 spinlock_t pcie_idx_lock; 2399 /* protects concurrent PCIE_PORT register access */ 2400 spinlock_t pciep_idx_lock; 2401 /* protects concurrent PIF register access */ 2402 spinlock_t pif_idx_lock; 2403 /* protects concurrent CG register access */ 2404 spinlock_t cg_idx_lock; 2405 /* protects concurrent UVD register access */ 2406 spinlock_t uvd_idx_lock; 2407 /* protects concurrent RCU register access */ 2408 spinlock_t rcu_idx_lock; 2409 /* protects concurrent DIDT register access */ 2410 spinlock_t didt_idx_lock; 2411 /* protects concurrent ENDPOINT (audio) register access */ 2412 spinlock_t end_idx_lock; 2413 #ifdef __NetBSD__ 2414 bus_space_tag_t rmmio_bst; 2415 bus_space_handle_t rmmio_bsh; 2416 bus_addr_t rmmio_addr; 2417 bus_size_t rmmio_size; 2418 #else 2419 void __iomem *rmmio; 2420 #endif 2421 radeon_rreg_t mc_rreg; 2422 radeon_wreg_t mc_wreg; 2423 radeon_rreg_t pll_rreg; 2424 radeon_wreg_t pll_wreg; 2425 uint32_t pcie_reg_mask; 2426 radeon_rreg_t pciep_rreg; 2427 radeon_wreg_t pciep_wreg; 2428 /* io port */ 2429 #ifdef __NetBSD__ 2430 bus_space_tag_t rio_mem_bst; 2431 bus_space_handle_t rio_mem_bsh; 2432 bus_size_t rio_mem_size; 2433 #else 2434 void __iomem *rio_mem; 2435 resource_size_t rio_mem_size; 2436 #endif 2437 struct radeon_clock clock; 2438 struct radeon_mc mc; 2439 struct radeon_gart gart; 2440 struct radeon_mode_info mode_info; 2441 struct radeon_scratch scratch; 2442 struct radeon_doorbell doorbell; 2443 struct radeon_mman mman; 2444 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2445 #ifdef __NetBSD__ 2446 spinlock_t fence_lock; 2447 drm_waitqueue_t fence_queue; 2448 TAILQ_HEAD(, radeon_fence) fence_check; 2449 #else 2450 wait_queue_head_t fence_queue; 2451 #endif 2452 unsigned fence_context; 2453 struct mutex ring_lock; 2454 struct radeon_ring ring[RADEON_NUM_RINGS]; 2455 bool ib_pool_ready; 2456 struct radeon_sa_manager ring_tmp_bo; 2457 struct radeon_irq irq; 2458 struct radeon_asic *asic; 2459 struct radeon_gem gem; 2460 struct radeon_pm pm; 2461 struct radeon_uvd uvd; 2462 struct radeon_vce vce; 2463 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2464 struct radeon_wb wb; 2465 struct radeon_dummy_page dummy_page; 2466 bool shutdown; 2467 bool suspend; 2468 bool need_dma32; 2469 bool accel_working; 2470 bool fastfb_working; /* IGP feature*/ 2471 bool needs_reset, in_reset; 2472 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2473 const struct firmware *me_fw; /* all family ME firmware */ 2474 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2475 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2476 const struct firmware *mc_fw; /* NI MC firmware */ 2477 const struct firmware *ce_fw; /* SI CE firmware */ 2478 const struct firmware *mec_fw; /* CIK MEC firmware */ 2479 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2480 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2481 const struct firmware *smc_fw; /* SMC firmware */ 2482 const struct firmware *uvd_fw; /* UVD firmware */ 2483 const struct firmware *vce_fw; /* VCE firmware */ 2484 bool new_fw; 2485 struct r600_vram_scratch vram_scratch; 2486 int msi_enabled; /* msi enabled */ 2487 struct r600_ih ih; /* r6/700 interrupt ring */ 2488 struct radeon_rlc rlc; 2489 struct radeon_mec mec; 2490 struct delayed_work hotplug_work; 2491 struct work_struct dp_work; 2492 struct work_struct audio_work; 2493 int num_crtc; /* number of crtcs */ 2494 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2495 bool has_uvd; 2496 struct r600_audio audio; /* audio stuff */ 2497 struct notifier_block acpi_nb; 2498 /* only one userspace can use Hyperz features or CMASK at a time */ 2499 struct drm_file *hyperz_filp; 2500 struct drm_file *cmask_filp; 2501 /* i2c buses */ 2502 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2503 /* debugfs */ 2504 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2505 unsigned debugfs_count; 2506 /* virtual memory */ 2507 struct radeon_vm_manager vm_manager; 2508 struct mutex gpu_clock_mutex; 2509 /* memory stats */ 2510 atomic64_t vram_usage; 2511 atomic64_t gtt_usage; 2512 atomic64_t num_bytes_moved; 2513 atomic_t gpu_reset_counter; 2514 /* ACPI interface */ 2515 struct radeon_atif atif; 2516 struct radeon_atcs atcs; 2517 /* srbm instance registers */ 2518 struct mutex srbm_mutex; 2519 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2520 struct mutex grbm_idx_mutex; 2521 /* clock, powergating flags */ 2522 u32 cg_flags; 2523 u32 pg_flags; 2524 2525 struct dev_pm_domain vga_pm_domain; 2526 bool have_disp_power_ref; 2527 u32 px_quirk_flags; 2528 2529 /* tracking pinned memory */ 2530 u64 vram_pin_size; 2531 u64 gart_pin_size; 2532 2533 /* amdkfd interface */ 2534 struct kfd_dev *kfd; 2535 2536 struct mutex mn_lock; 2537 DECLARE_HASHTABLE(mn_hash, 7); 2538 }; 2539 2540 bool radeon_is_px(struct drm_device *dev); 2541 int radeon_device_init(struct radeon_device *rdev, 2542 struct drm_device *ddev, 2543 struct pci_dev *pdev, 2544 uint32_t flags); 2545 void radeon_device_fini(struct radeon_device *rdev); 2546 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2547 2548 #define RADEON_MIN_MMIO_SIZE 0x10000 2549 2550 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2551 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2552 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2553 bool always_indirect) 2554 { 2555 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2556 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2557 #ifdef __NetBSD__ 2558 return bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg); 2559 #else 2560 return readl(((void __iomem *)rdev->rmmio) + reg); 2561 #endif 2562 else 2563 return r100_mm_rreg_slow(rdev, reg); 2564 } 2565 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2566 bool always_indirect) 2567 { 2568 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2569 #ifdef __NetBSD__ 2570 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg, v); 2571 #else 2572 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2573 #endif 2574 else 2575 r100_mm_wreg_slow(rdev, reg, v); 2576 } 2577 2578 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2579 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2580 2581 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2582 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2583 2584 /* 2585 * Cast helper 2586 */ 2587 extern const struct fence_ops radeon_fence_ops; 2588 2589 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2590 { 2591 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2592 2593 if (__f->base.ops == &radeon_fence_ops) 2594 return __f; 2595 2596 return NULL; 2597 } 2598 2599 /* 2600 * Registers read & write functions. 2601 */ 2602 #ifdef __NetBSD__ 2603 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2604 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2605 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2606 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2607 #else 2608 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2609 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2610 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2611 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2612 #endif 2613 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2614 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2615 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2616 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2617 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2618 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2619 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2620 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2621 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2622 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2623 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2624 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2625 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2626 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2627 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2628 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2629 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2630 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2631 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2632 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2633 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2634 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2635 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2636 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2637 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2638 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2639 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2640 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2641 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2642 #define WREG32_P(reg, val, mask) \ 2643 do { \ 2644 uint32_t tmp_ = RREG32(reg); \ 2645 tmp_ &= (mask); \ 2646 tmp_ |= ((val) & ~(mask)); \ 2647 WREG32(reg, tmp_); \ 2648 } while (0) 2649 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2650 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2651 #define WREG32_PLL_P(reg, val, mask) \ 2652 do { \ 2653 uint32_t tmp_ = RREG32_PLL(reg); \ 2654 tmp_ &= (mask); \ 2655 tmp_ |= ((val) & ~(mask)); \ 2656 WREG32_PLL(reg, tmp_); \ 2657 } while (0) 2658 #define WREG32_SMC_P(reg, val, mask) \ 2659 do { \ 2660 uint32_t tmp_ = RREG32_SMC(reg); \ 2661 tmp_ &= (mask); \ 2662 tmp_ |= ((val) & ~(mask)); \ 2663 WREG32_SMC(reg, tmp_); \ 2664 } while (0) 2665 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2666 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2667 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2668 2669 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2670 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2671 2672 /* 2673 * Indirect registers accessors. 2674 * They used to be inlined, but this increases code size by ~65 kbytes. 2675 * Since each performs a pair of MMIO ops 2676 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2677 * the cost of call+ret is almost negligible. MMIO and locking 2678 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2679 */ 2680 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2681 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2682 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2683 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2684 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2685 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2686 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2687 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2688 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2689 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2690 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2691 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2692 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2693 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2694 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2695 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2696 2697 void r100_pll_errata_after_index(struct radeon_device *rdev); 2698 2699 2700 /* 2701 * ASICs helpers. 2702 */ 2703 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2704 (rdev->pdev->device == 0x5969)) 2705 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2706 (rdev->family == CHIP_RV200) || \ 2707 (rdev->family == CHIP_RS100) || \ 2708 (rdev->family == CHIP_RS200) || \ 2709 (rdev->family == CHIP_RV250) || \ 2710 (rdev->family == CHIP_RV280) || \ 2711 (rdev->family == CHIP_RS300)) 2712 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2713 (rdev->family == CHIP_RV350) || \ 2714 (rdev->family == CHIP_R350) || \ 2715 (rdev->family == CHIP_RV380) || \ 2716 (rdev->family == CHIP_R420) || \ 2717 (rdev->family == CHIP_R423) || \ 2718 (rdev->family == CHIP_RV410) || \ 2719 (rdev->family == CHIP_RS400) || \ 2720 (rdev->family == CHIP_RS480)) 2721 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2722 (rdev->ddev->pdev->device == 0x9443) || \ 2723 (rdev->ddev->pdev->device == 0x944B) || \ 2724 (rdev->ddev->pdev->device == 0x9506) || \ 2725 (rdev->ddev->pdev->device == 0x9509) || \ 2726 (rdev->ddev->pdev->device == 0x950F) || \ 2727 (rdev->ddev->pdev->device == 0x689C) || \ 2728 (rdev->ddev->pdev->device == 0x689D)) 2729 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2730 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2731 (rdev->family == CHIP_RS690) || \ 2732 (rdev->family == CHIP_RS740) || \ 2733 (rdev->family >= CHIP_R600)) 2734 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2735 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2736 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2737 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2738 (rdev->flags & RADEON_IS_IGP)) 2739 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2740 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2741 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2742 (rdev->flags & RADEON_IS_IGP)) 2743 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2744 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2745 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2746 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2747 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2748 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2749 (rdev->family == CHIP_MULLINS)) 2750 2751 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2752 (rdev->ddev->pdev->device == 0x6850) || \ 2753 (rdev->ddev->pdev->device == 0x6858) || \ 2754 (rdev->ddev->pdev->device == 0x6859) || \ 2755 (rdev->ddev->pdev->device == 0x6840) || \ 2756 (rdev->ddev->pdev->device == 0x6841) || \ 2757 (rdev->ddev->pdev->device == 0x6842) || \ 2758 (rdev->ddev->pdev->device == 0x6843)) 2759 2760 /* 2761 * BIOS helpers. 2762 */ 2763 #define RBIOS8(i) (rdev->bios[i]) 2764 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2765 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2766 2767 int radeon_combios_init(struct radeon_device *rdev); 2768 void radeon_combios_fini(struct radeon_device *rdev); 2769 int radeon_atombios_init(struct radeon_device *rdev); 2770 void radeon_atombios_fini(struct radeon_device *rdev); 2771 2772 2773 /* 2774 * RING helpers. 2775 */ 2776 2777 /** 2778 * radeon_ring_write - write a value to the ring 2779 * 2780 * @ring: radeon_ring structure holding ring information 2781 * @v: dword (dw) value to write 2782 * 2783 * Write a value to the requested ring buffer (all asics). 2784 */ 2785 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2786 { 2787 if (ring->count_dw <= 0) 2788 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2789 2790 ring->ring[ring->wptr++] = v; 2791 ring->wptr &= ring->ptr_mask; 2792 ring->count_dw--; 2793 ring->ring_free_dw--; 2794 } 2795 2796 /* 2797 * ASICs macro. 2798 */ 2799 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2800 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2801 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2802 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2803 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2804 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2805 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2806 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2807 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2808 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2809 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2810 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2811 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2812 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2813 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2814 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2815 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2816 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2817 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2818 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2819 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2820 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2821 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2822 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2823 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2824 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2825 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2826 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2827 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2828 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2829 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2830 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2831 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2832 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2833 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2834 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2835 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2836 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2837 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2838 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2839 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2840 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2841 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2842 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2843 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2844 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2845 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2846 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2847 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2848 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2849 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2850 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2851 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2852 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2853 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2854 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2855 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2856 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2857 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2858 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2859 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2860 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2861 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2862 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2863 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2864 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2865 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2866 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2867 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2868 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2869 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2870 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2871 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2872 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2873 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2874 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2875 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2876 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2877 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2878 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2879 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2880 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2881 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2882 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2883 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2884 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2885 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2886 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2887 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2888 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2889 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2890 2891 /* Common functions */ 2892 /* AGP */ 2893 extern int radeon_gpu_reset(struct radeon_device *rdev); 2894 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2895 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2896 extern void radeon_agp_disable(struct radeon_device *rdev); 2897 extern int radeon_modeset_init(struct radeon_device *rdev); 2898 extern void radeon_modeset_fini(struct radeon_device *rdev); 2899 extern bool radeon_card_posted(struct radeon_device *rdev); 2900 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2901 extern void radeon_update_display_priority(struct radeon_device *rdev); 2902 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2903 extern void radeon_scratch_init(struct radeon_device *rdev); 2904 extern void radeon_wb_fini(struct radeon_device *rdev); 2905 extern int radeon_wb_init(struct radeon_device *rdev); 2906 extern void radeon_wb_disable(struct radeon_device *rdev); 2907 extern void radeon_surface_init(struct radeon_device *rdev); 2908 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2909 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2910 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2911 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2912 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2913 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2914 uint32_t flags); 2915 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2916 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2917 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2918 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2919 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2920 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2921 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2922 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2923 const u32 *registers, 2924 const u32 array_size); 2925 2926 /* 2927 * vm 2928 */ 2929 int radeon_vm_manager_init(struct radeon_device *rdev); 2930 void radeon_vm_manager_fini(struct radeon_device *rdev); 2931 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2932 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2933 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2934 struct radeon_vm *vm, 2935 struct list_head *head); 2936 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2937 struct radeon_vm *vm, int ring); 2938 void radeon_vm_flush(struct radeon_device *rdev, 2939 struct radeon_vm *vm, 2940 int ring, struct radeon_fence *fence); 2941 void radeon_vm_fence(struct radeon_device *rdev, 2942 struct radeon_vm *vm, 2943 struct radeon_fence *fence); 2944 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2945 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2946 struct radeon_vm *vm); 2947 int radeon_vm_clear_freed(struct radeon_device *rdev, 2948 struct radeon_vm *vm); 2949 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2950 struct radeon_vm *vm); 2951 int radeon_vm_bo_update(struct radeon_device *rdev, 2952 struct radeon_bo_va *bo_va, 2953 struct ttm_mem_reg *mem); 2954 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2955 struct radeon_bo *bo); 2956 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2957 struct radeon_bo *bo); 2958 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2959 struct radeon_vm *vm, 2960 struct radeon_bo *bo); 2961 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2962 struct radeon_bo_va *bo_va, 2963 uint64_t offset, 2964 uint32_t flags); 2965 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2966 struct radeon_bo_va *bo_va); 2967 2968 /* audio */ 2969 void r600_audio_update_hdmi(struct work_struct *work); 2970 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2971 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2972 void r600_audio_enable(struct radeon_device *rdev, 2973 struct r600_audio_pin *pin, 2974 u8 enable_mask); 2975 void dce6_audio_enable(struct radeon_device *rdev, 2976 struct r600_audio_pin *pin, 2977 u8 enable_mask); 2978 2979 /* 2980 * R600 vram scratch functions 2981 */ 2982 int r600_vram_scratch_init(struct radeon_device *rdev); 2983 void r600_vram_scratch_fini(struct radeon_device *rdev); 2984 2985 /* 2986 * r600 cs checking helper 2987 */ 2988 unsigned r600_mip_minify(unsigned size, unsigned level); 2989 bool r600_fmt_is_valid_color(u32 format); 2990 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2991 int r600_fmt_get_blocksize(u32 format); 2992 int r600_fmt_get_nblocksx(u32 format, u32 w); 2993 int r600_fmt_get_nblocksy(u32 format, u32 h); 2994 2995 /* 2996 * r600 functions used by radeon_encoder.c 2997 */ 2998 struct radeon_hdmi_acr { 2999 u32 clock; 3000 3001 int n_32khz; 3002 int cts_32khz; 3003 3004 int n_44_1khz; 3005 int cts_44_1khz; 3006 3007 int n_48khz; 3008 int cts_48khz; 3009 3010 }; 3011 3012 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3013 3014 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3015 u32 tiling_pipe_num, 3016 u32 max_rb_num, 3017 u32 total_max_rb_num, 3018 u32 enabled_rb_mask); 3019 3020 /* 3021 * evergreen functions used by radeon_encoder.c 3022 */ 3023 3024 extern int ni_init_microcode(struct radeon_device *rdev); 3025 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3026 3027 /* radeon_acpi.c */ 3028 #if defined(CONFIG_ACPI) 3029 extern int radeon_acpi_init(struct radeon_device *rdev); 3030 extern void radeon_acpi_fini(struct radeon_device *rdev); 3031 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3032 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3033 u8 perf_req, bool advertise); 3034 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3035 #else 3036 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3037 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3038 #endif 3039 3040 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3041 struct radeon_cs_packet *pkt, 3042 unsigned idx); 3043 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3044 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3045 struct radeon_cs_packet *pkt); 3046 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3047 struct radeon_bo_list **cs_reloc, 3048 int nomm); 3049 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3050 uint32_t *vline_start_end, 3051 uint32_t *vline_status); 3052 3053 #include "radeon_object.h" 3054 3055 #endif 3056
Indexes created Wed Oct 01 13:09:50 GMT 2025