radeon.h revision 1.9
1 /* $NetBSD: radeon.h,v 1.9 2020/02/14 14:34:59 maya Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __RADEON_H__ 31 #define __RADEON_H__ 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <linux/atomic.h> 66 #include <linux/wait.h> 67 #include <linux/list.h> 68 #include <linux/kref.h> 69 #include <linux/interval_tree.h> 70 #include <linux/hashtable.h> 71 #include <linux/fence.h> 72 73 #include <ttm/ttm_bo_api.h> 74 #include <ttm/ttm_bo_driver.h> 75 #include <ttm/ttm_placement.h> 76 #include <ttm/ttm_module.h> 77 #include <ttm/ttm_execbuf_util.h> 78 79 #include <drm/drm_gem.h> 80 81 #include "radeon_family.h" 82 #include "radeon_mode.h" 83 #include "radeon_reg.h" 84 85 /* 86 * Modules parameters. 87 */ 88 extern int radeon_no_wb; 89 extern int radeon_modeset; 90 extern int radeon_dynclks; 91 extern int radeon_r4xx_atom; 92 extern int radeon_agpmode; 93 extern int radeon_vram_limit; 94 extern int radeon_gart_size; 95 extern int radeon_benchmarking; 96 extern int radeon_testing; 97 extern int radeon_connector_table; 98 extern int radeon_tv; 99 extern int radeon_audio; 100 extern int radeon_disp_priority; 101 extern int radeon_hw_i2c; 102 extern int radeon_pcie_gen2; 103 extern int radeon_msi; 104 extern int radeon_lockup_timeout; 105 extern int radeon_fastfb; 106 extern int radeon_dpm; 107 extern int radeon_aspm; 108 extern int radeon_runtime_pm; 109 extern int radeon_hard_reset; 110 extern int radeon_vm_size; 111 extern int radeon_vm_block_size; 112 extern int radeon_deep_color; 113 extern int radeon_use_pflipirq; 114 extern int radeon_bapm; 115 extern int radeon_backlight; 116 extern int radeon_auxch; 117 extern int radeon_mst; 118 119 /* 120 * Copy from radeon_drv.h so we don't have to include both and have conflicting 121 * symbol; 122 */ 123 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 124 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 125 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 126 #define RADEON_IB_POOL_SIZE 16 127 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 128 #define RADEONFB_CONN_LIMIT 4 129 #define RADEON_BIOS_NUM_SCRATCH 8 130 131 /* internal ring indices */ 132 /* r1xx+ has gfx CP ring */ 133 #define RADEON_RING_TYPE_GFX_INDEX 0 134 135 /* cayman has 2 compute CP rings */ 136 #define CAYMAN_RING_TYPE_CP1_INDEX 1 137 #define CAYMAN_RING_TYPE_CP2_INDEX 2 138 139 /* R600+ has an async dma ring */ 140 #define R600_RING_TYPE_DMA_INDEX 3 141 /* cayman add a second async dma ring */ 142 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 143 144 /* R600+ */ 145 #define R600_RING_TYPE_UVD_INDEX 5 146 147 /* TN+ */ 148 #define TN_RING_TYPE_VCE1_INDEX 6 149 #define TN_RING_TYPE_VCE2_INDEX 7 150 151 /* max number of rings */ 152 #define RADEON_NUM_RINGS 8 153 154 /* number of hw syncs before falling back on blocking */ 155 #define RADEON_NUM_SYNCS 4 156 157 /* hardcode those limit for now */ 158 #define RADEON_VA_IB_OFFSET (1 << 20) 159 #define RADEON_VA_RESERVED_SIZE (8 << 20) 160 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 161 162 /* hard reset data */ 163 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 164 165 /* reset flags */ 166 #define RADEON_RESET_GFX (1 << 0) 167 #define RADEON_RESET_COMPUTE (1 << 1) 168 #define RADEON_RESET_DMA (1 << 2) 169 #define RADEON_RESET_CP (1 << 3) 170 #define RADEON_RESET_GRBM (1 << 4) 171 #define RADEON_RESET_DMA1 (1 << 5) 172 #define RADEON_RESET_RLC (1 << 6) 173 #define RADEON_RESET_SEM (1 << 7) 174 #define RADEON_RESET_IH (1 << 8) 175 #define RADEON_RESET_VMC (1 << 9) 176 #define RADEON_RESET_MC (1 << 10) 177 #define RADEON_RESET_DISPLAY (1 << 11) 178 179 /* CG block flags */ 180 #define RADEON_CG_BLOCK_GFX (1 << 0) 181 #define RADEON_CG_BLOCK_MC (1 << 1) 182 #define RADEON_CG_BLOCK_SDMA (1 << 2) 183 #define RADEON_CG_BLOCK_UVD (1 << 3) 184 #define RADEON_CG_BLOCK_VCE (1 << 4) 185 #define RADEON_CG_BLOCK_HDP (1 << 5) 186 #define RADEON_CG_BLOCK_BIF (1 << 6) 187 188 /* CG flags */ 189 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 190 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 191 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 192 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 193 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 194 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 195 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 196 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 197 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 198 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 199 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 200 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 201 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 202 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 203 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 204 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 205 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 206 207 /* PG flags */ 208 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 209 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 210 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 211 #define RADEON_PG_SUPPORT_UVD (1 << 3) 212 #define RADEON_PG_SUPPORT_VCE (1 << 4) 213 #define RADEON_PG_SUPPORT_CP (1 << 5) 214 #define RADEON_PG_SUPPORT_GDS (1 << 6) 215 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 216 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 217 #define RADEON_PG_SUPPORT_ACP (1 << 9) 218 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 219 220 /* max cursor sizes (in pixels) */ 221 #define CURSOR_WIDTH 64 222 #define CURSOR_HEIGHT 64 223 224 #define CIK_CURSOR_WIDTH 128 225 #define CIK_CURSOR_HEIGHT 128 226 227 /* 228 * Errata workarounds. 229 */ 230 enum radeon_pll_errata { 231 CHIP_ERRATA_R300_CG = 0x00000001, 232 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 233 CHIP_ERRATA_PLL_DELAY = 0x00000004 234 }; 235 236 237 struct radeon_device; 238 239 #ifdef __NetBSD__ 240 extern struct radeon_device *radeon_device_private(device_t); 241 #endif 242 243 /* 244 * BIOS. 245 */ 246 bool radeon_get_bios(struct radeon_device *rdev); 247 248 /* 249 * Dummy page 250 */ 251 struct radeon_dummy_page { 252 uint64_t entry; 253 #ifdef __NetBSD__ 254 bus_dma_segment_t rdp_seg; 255 bus_dmamap_t rdp_map; 256 void *rdp_addr; 257 #else 258 struct page *page; 259 #endif 260 dma_addr_t addr; 261 }; 262 int radeon_dummy_page_init(struct radeon_device *rdev); 263 void radeon_dummy_page_fini(struct radeon_device *rdev); 264 265 266 /* 267 * Clocks 268 */ 269 struct radeon_clock { 270 struct radeon_pll p1pll; 271 struct radeon_pll p2pll; 272 struct radeon_pll dcpll; 273 struct radeon_pll spll; 274 struct radeon_pll mpll; 275 /* 10 Khz units */ 276 uint32_t default_mclk; 277 uint32_t default_sclk; 278 uint32_t default_dispclk; 279 uint32_t current_dispclk; 280 uint32_t dp_extclk; 281 uint32_t max_pixel_clock; 282 uint32_t vco_freq; 283 }; 284 285 /* 286 * Power management 287 */ 288 int radeon_pm_init(struct radeon_device *rdev); 289 int radeon_pm_late_init(struct radeon_device *rdev); 290 void radeon_pm_fini(struct radeon_device *rdev); 291 void radeon_pm_compute_clocks(struct radeon_device *rdev); 292 void radeon_pm_suspend(struct radeon_device *rdev); 293 void radeon_pm_resume(struct radeon_device *rdev); 294 void radeon_combios_get_power_modes(struct radeon_device *rdev); 295 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 296 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 297 u8 clock_type, 298 u32 clock, 299 bool strobe_mode, 300 struct atom_clock_dividers *dividers); 301 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 302 u32 clock, 303 bool strobe_mode, 304 struct atom_mpll_param *mpll_param); 305 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 306 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 307 u16 voltage_level, u8 voltage_type, 308 u32 *gpio_value, u32 *gpio_mask); 309 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 310 u32 eng_clock, u32 mem_clock); 311 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 312 u8 voltage_type, u16 *voltage_step); 313 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 314 u16 voltage_id, u16 *voltage); 315 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 316 u16 *voltage, 317 u16 leakage_idx); 318 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 319 u16 *leakage_id); 320 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 321 u16 *vddc, u16 *vddci, 322 u16 virtual_voltage_id, 323 u16 vbios_voltage_id); 324 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 325 u16 virtual_voltage_id, 326 u16 *voltage); 327 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 328 u8 voltage_type, 329 u16 nominal_voltage, 330 u16 *true_voltage); 331 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 332 u8 voltage_type, u16 *min_voltage); 333 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 334 u8 voltage_type, u16 *max_voltage); 335 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode, 337 struct atom_voltage_table *voltage_table); 338 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 339 u8 voltage_type, u8 voltage_mode); 340 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 341 u8 voltage_type, 342 u8 *svd_gpio_id, u8 *svc_gpio_id); 343 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 344 u32 mem_clock); 345 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 346 u32 mem_clock); 347 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 348 u8 module_index, 349 struct atom_mc_reg_table *reg_table); 350 int radeon_atom_get_memory_info(struct radeon_device *rdev, 351 u8 module_index, struct atom_memory_info *mem_info); 352 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 353 bool gddr5, u8 module_index, 354 struct atom_memory_clock_range_table *mclk_range_table); 355 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 356 u16 voltage_id, u16 *voltage); 357 void rs690_pm_info(struct radeon_device *rdev); 358 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 359 unsigned *bankh, unsigned *mtaspect, 360 unsigned *tile_split); 361 362 /* 363 * Fences. 364 */ 365 struct radeon_fence_driver { 366 struct radeon_device *rdev; 367 uint32_t scratch_reg; 368 uint64_t gpu_addr; 369 volatile uint32_t *cpu_addr; 370 /* sync_seq is protected by ring emission lock */ 371 uint64_t sync_seq[RADEON_NUM_RINGS]; 372 atomic64_t last_seq; 373 bool initialized, delayed_irq; 374 struct delayed_work lockup_work; 375 }; 376 377 struct radeon_fence { 378 struct fence base; 379 380 struct radeon_device *rdev; 381 uint64_t seq; 382 /* RB, DMA, etc. */ 383 unsigned ring; 384 bool is_vm_update; 385 386 #ifdef __NetBSD__ 387 TAILQ_ENTRY(radeon_fence) fence_check; 388 #else 389 wait_queue_t fence_wake; 390 #endif 391 }; 392 393 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 394 int radeon_fence_driver_init(struct radeon_device *rdev); 395 void radeon_fence_driver_fini(struct radeon_device *rdev); 396 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 397 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 398 void radeon_fence_wakeup_locked(struct radeon_device *rdev); 399 void radeon_fence_process(struct radeon_device *rdev, int ring); 400 bool radeon_fence_signaled(struct radeon_fence *fence); 401 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 402 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 403 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 404 int radeon_fence_wait_any(struct radeon_device *rdev, 405 struct radeon_fence **fences, 406 bool intr); 407 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 408 void radeon_fence_unref(struct radeon_fence **fence); 409 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 410 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 411 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 412 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 413 struct radeon_fence *b) 414 { 415 if (!a) { 416 return b; 417 } 418 419 if (!b) { 420 return a; 421 } 422 423 BUG_ON(a->ring != b->ring); 424 425 if (a->seq > b->seq) { 426 return a; 427 } else { 428 return b; 429 } 430 } 431 432 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 433 struct radeon_fence *b) 434 { 435 if (!a) { 436 return false; 437 } 438 439 if (!b) { 440 return true; 441 } 442 443 BUG_ON(a->ring != b->ring); 444 445 return a->seq < b->seq; 446 } 447 448 /* 449 * Tiling registers 450 */ 451 struct radeon_surface_reg { 452 struct radeon_bo *bo; 453 }; 454 455 #define RADEON_GEM_MAX_SURFACES 8 456 457 /* 458 * TTM. 459 */ 460 struct radeon_mman { 461 struct ttm_bo_global_ref bo_global_ref; 462 struct drm_global_reference mem_global_ref; 463 struct ttm_bo_device bdev; 464 bool mem_global_referenced; 465 bool initialized; 466 467 #if defined(CONFIG_DEBUG_FS) 468 struct dentry *vram; 469 struct dentry *gtt; 470 #endif 471 }; 472 473 struct radeon_bo_list { 474 struct radeon_bo *robj; 475 struct ttm_validate_buffer tv; 476 uint64_t gpu_offset; 477 unsigned prefered_domains; 478 unsigned allowed_domains; 479 uint32_t tiling_flags; 480 }; 481 482 /* bo virtual address in a specific vm */ 483 struct radeon_bo_va { 484 /* protected by bo being reserved */ 485 struct list_head bo_list; 486 uint32_t flags; 487 struct radeon_fence *last_pt_update; 488 unsigned ref_count; 489 490 /* protected by vm mutex */ 491 struct interval_tree_node it; 492 struct list_head vm_status; 493 494 /* constant after initialization */ 495 struct radeon_vm *vm; 496 struct radeon_bo *bo; 497 }; 498 499 struct radeon_bo { 500 /* Protected by gem.mutex */ 501 struct list_head list; 502 /* Protected by tbo.reserved */ 503 u32 initial_domain; 504 struct ttm_place placements[4]; 505 struct ttm_placement placement; 506 struct ttm_buffer_object tbo; 507 struct ttm_bo_kmap_obj kmap; 508 u32 flags; 509 unsigned pin_count; 510 void *kptr; 511 u32 tiling_flags; 512 u32 pitch; 513 int surface_reg; 514 /* list of all virtual address to which this bo 515 * is associated to 516 */ 517 struct list_head va; 518 /* Constant after initialization */ 519 struct radeon_device *rdev; 520 struct drm_gem_object gem_base; 521 522 struct ttm_bo_kmap_obj dma_buf_vmap; 523 #ifndef __NetBSD__ /* XXX pid??? */ 524 pid_t pid; 525 #endif 526 527 struct radeon_mn *mn; 528 struct list_head mn_list; 529 }; 530 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 531 532 int radeon_gem_debugfs_init(struct radeon_device *rdev); 533 534 /* sub-allocation manager, it has to be protected by another lock. 535 * By conception this is an helper for other part of the driver 536 * like the indirect buffer or semaphore, which both have their 537 * locking. 538 * 539 * Principe is simple, we keep a list of sub allocation in offset 540 * order (first entry has offset == 0, last entry has the highest 541 * offset). 542 * 543 * When allocating new object we first check if there is room at 544 * the end total_size - (last_object_offset + last_object_size) >= 545 * alloc_size. If so we allocate new object there. 546 * 547 * When there is not enough room at the end, we start waiting for 548 * each sub object until we reach object_offset+object_size >= 549 * alloc_size, this object then become the sub object we return. 550 * 551 * Alignment can't be bigger than page size. 552 * 553 * Hole are not considered for allocation to keep things simple. 554 * Assumption is that there won't be hole (all object on same 555 * alignment). 556 */ 557 struct radeon_sa_manager { 558 #ifdef __NetBSD__ 559 spinlock_t wq_lock; 560 drm_waitqueue_t wq; 561 #else 562 wait_queue_head_t wq; 563 #endif 564 struct radeon_bo *bo; 565 struct list_head *hole; 566 struct list_head flist[RADEON_NUM_RINGS]; 567 struct list_head olist; 568 unsigned size; 569 uint64_t gpu_addr; 570 void *cpu_ptr; 571 uint32_t domain; 572 uint32_t align; 573 }; 574 575 struct radeon_sa_bo; 576 577 /* sub-allocation buffer */ 578 struct radeon_sa_bo { 579 struct list_head olist; 580 struct list_head flist; 581 struct radeon_sa_manager *manager; 582 unsigned soffset; 583 unsigned eoffset; 584 struct radeon_fence *fence; 585 }; 586 587 /* 588 * GEM objects. 589 */ 590 struct radeon_gem { 591 struct mutex mutex; 592 struct list_head objects; 593 }; 594 595 int radeon_gem_init(struct radeon_device *rdev); 596 void radeon_gem_fini(struct radeon_device *rdev); 597 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 598 int alignment, int initial_domain, 599 u32 flags, bool kernel, 600 struct drm_gem_object **obj); 601 602 int radeon_mode_dumb_create(struct drm_file *file_priv, 603 struct drm_device *dev, 604 struct drm_mode_create_dumb *args); 605 int radeon_mode_dumb_mmap(struct drm_file *filp, 606 struct drm_device *dev, 607 uint32_t handle, uint64_t *offset_p); 608 609 /* 610 * Semaphores. 611 */ 612 struct radeon_semaphore { 613 struct radeon_sa_bo *sa_bo; 614 signed waiters; 615 uint64_t gpu_addr; 616 }; 617 618 int radeon_semaphore_create(struct radeon_device *rdev, 619 struct radeon_semaphore **semaphore); 620 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 621 struct radeon_semaphore *semaphore); 622 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 623 struct radeon_semaphore *semaphore); 624 void radeon_semaphore_free(struct radeon_device *rdev, 625 struct radeon_semaphore **semaphore, 626 struct radeon_fence *fence); 627 628 /* 629 * Synchronization 630 */ 631 struct radeon_sync { 632 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 633 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 634 struct radeon_fence *last_vm_update; 635 }; 636 637 void radeon_sync_create(struct radeon_sync *sync); 638 void radeon_sync_fence(struct radeon_sync *sync, 639 struct radeon_fence *fence); 640 int radeon_sync_resv(struct radeon_device *rdev, 641 struct radeon_sync *sync, 642 struct reservation_object *resv, 643 bool shared); 644 int radeon_sync_rings(struct radeon_device *rdev, 645 struct radeon_sync *sync, 646 int waiting_ring); 647 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 648 struct radeon_fence *fence); 649 650 /* 651 * GART structures, functions & helpers 652 */ 653 struct radeon_mc; 654 655 #define RADEON_GPU_PAGE_SIZE 4096 656 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 657 #define RADEON_GPU_PAGE_SHIFT 12 658 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 659 660 #define RADEON_GART_PAGE_DUMMY 0 661 #define RADEON_GART_PAGE_VALID (1 << 0) 662 #define RADEON_GART_PAGE_READ (1 << 1) 663 #define RADEON_GART_PAGE_WRITE (1 << 2) 664 #define RADEON_GART_PAGE_SNOOP (1 << 3) 665 666 struct radeon_gart { 667 #ifdef __NetBSD__ 668 bus_dma_segment_t rg_table_seg; 669 bus_dmamap_t rg_table_map; 670 #endif 671 dma_addr_t table_addr; 672 struct radeon_bo *robj; 673 void *ptr; 674 unsigned num_gpu_pages; 675 unsigned num_cpu_pages; 676 unsigned table_size; 677 struct page **pages; 678 uint64_t *pages_entry; 679 bool ready; 680 }; 681 682 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 683 void radeon_gart_table_ram_free(struct radeon_device *rdev); 684 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 685 void radeon_gart_table_vram_free(struct radeon_device *rdev); 686 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 687 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 688 int radeon_gart_init(struct radeon_device *rdev); 689 void radeon_gart_fini(struct radeon_device *rdev); 690 #ifdef __NetBSD__ 691 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start, 692 unsigned npages); 693 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start, 694 unsigned npages, struct page **pages, 695 bus_dmamap_t dmamap, uint32_t flags); 696 #else 697 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 698 int pages); 699 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 700 int pages, struct page **pagelist, 701 dma_addr_t *dma_addr, uint32_t flags); 702 #endif 703 704 705 /* 706 * GPU MC structures, functions & helpers 707 */ 708 struct radeon_mc { 709 resource_size_t aper_size; 710 resource_size_t aper_base; 711 resource_size_t agp_base; 712 /* for some chips with <= 32MB we need to lie 713 * about vram size near mc fb location */ 714 u64 mc_vram_size; 715 u64 visible_vram_size; 716 u64 gtt_size; 717 u64 gtt_start; 718 u64 gtt_end; 719 u64 vram_start; 720 u64 vram_end; 721 unsigned vram_width; 722 u64 real_vram_size; 723 int vram_mtrr; 724 bool vram_is_ddr; 725 bool igp_sideport_enabled; 726 u64 gtt_base_align; 727 u64 mc_mask; 728 }; 729 730 bool radeon_combios_sideport_present(struct radeon_device *rdev); 731 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 732 733 /* 734 * GPU scratch registers structures, functions & helpers 735 */ 736 struct radeon_scratch { 737 unsigned num_reg; 738 uint32_t reg_base; 739 bool free[32]; 740 uint32_t reg[32]; 741 }; 742 743 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 744 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 745 746 /* 747 * GPU doorbell structures, functions & helpers 748 */ 749 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 750 751 struct radeon_doorbell { 752 /* doorbell mmio */ 753 resource_size_t base; 754 resource_size_t size; 755 #ifdef __NetBSD__ 756 bus_space_tag_t bst; 757 bus_space_handle_t bsh; 758 #else 759 u32 __iomem *ptr; 760 #endif 761 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 762 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 763 }; 764 765 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 766 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 767 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 768 phys_addr_t *aperture_base, 769 size_t *aperture_size, 770 size_t *start_offset); 771 772 /* 773 * IRQS. 774 */ 775 776 struct radeon_flip_work { 777 struct work_struct flip_work; 778 struct work_struct unpin_work; 779 struct radeon_device *rdev; 780 int crtc_id; 781 uint64_t base; 782 struct drm_pending_vblank_event *event; 783 struct radeon_bo *old_rbo; 784 struct fence *fence; 785 }; 786 787 struct r500_irq_stat_regs { 788 u32 disp_int; 789 u32 hdmi0_status; 790 }; 791 792 struct r600_irq_stat_regs { 793 u32 disp_int; 794 u32 disp_int_cont; 795 u32 disp_int_cont2; 796 u32 d1grph_int; 797 u32 d2grph_int; 798 u32 hdmi0_status; 799 u32 hdmi1_status; 800 }; 801 802 struct evergreen_irq_stat_regs { 803 u32 disp_int; 804 u32 disp_int_cont; 805 u32 disp_int_cont2; 806 u32 disp_int_cont3; 807 u32 disp_int_cont4; 808 u32 disp_int_cont5; 809 u32 d1grph_int; 810 u32 d2grph_int; 811 u32 d3grph_int; 812 u32 d4grph_int; 813 u32 d5grph_int; 814 u32 d6grph_int; 815 u32 afmt_status1; 816 u32 afmt_status2; 817 u32 afmt_status3; 818 u32 afmt_status4; 819 u32 afmt_status5; 820 u32 afmt_status6; 821 }; 822 823 struct cik_irq_stat_regs { 824 u32 disp_int; 825 u32 disp_int_cont; 826 u32 disp_int_cont2; 827 u32 disp_int_cont3; 828 u32 disp_int_cont4; 829 u32 disp_int_cont5; 830 u32 disp_int_cont6; 831 u32 d1grph_int; 832 u32 d2grph_int; 833 u32 d3grph_int; 834 u32 d4grph_int; 835 u32 d5grph_int; 836 u32 d6grph_int; 837 }; 838 839 union radeon_irq_stat_regs { 840 struct r500_irq_stat_regs r500; 841 struct r600_irq_stat_regs r600; 842 struct evergreen_irq_stat_regs evergreen; 843 struct cik_irq_stat_regs cik; 844 }; 845 846 struct radeon_irq { 847 bool installed; 848 spinlock_t lock; 849 atomic_t ring_int[RADEON_NUM_RINGS]; 850 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 851 atomic_t pflip[RADEON_MAX_CRTCS]; 852 #ifdef __NetBSD__ 853 spinlock_t vblank_lock; 854 drm_waitqueue_t vblank_queue; 855 #else 856 wait_queue_head_t vblank_queue; 857 #endif 858 bool hpd[RADEON_MAX_HPD_PINS]; 859 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 860 union radeon_irq_stat_regs stat_regs; 861 bool dpm_thermal; 862 }; 863 864 int radeon_irq_kms_init(struct radeon_device *rdev); 865 void radeon_irq_kms_fini(struct radeon_device *rdev); 866 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 867 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 868 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 869 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 870 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 871 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 872 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 873 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 874 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 875 876 /* 877 * CP & rings. 878 */ 879 880 struct radeon_ib { 881 struct radeon_sa_bo *sa_bo; 882 uint32_t length_dw; 883 uint64_t gpu_addr; 884 uint32_t *ptr; 885 int ring; 886 struct radeon_fence *fence; 887 struct radeon_vm *vm; 888 bool is_const_ib; 889 struct radeon_sync sync; 890 }; 891 892 struct radeon_ring { 893 struct radeon_bo *ring_obj; 894 volatile uint32_t *ring; 895 unsigned rptr_offs; 896 unsigned rptr_save_reg; 897 u64 next_rptr_gpu_addr; 898 volatile u32 *next_rptr_cpu_addr; 899 unsigned wptr; 900 unsigned wptr_old; 901 unsigned ring_size; 902 unsigned ring_free_dw; 903 int count_dw; 904 atomic_t last_rptr; 905 atomic64_t last_activity; 906 uint64_t gpu_addr; 907 uint32_t align_mask; 908 uint32_t ptr_mask; 909 bool ready; 910 u32 nop; 911 u32 idx; 912 u64 last_semaphore_signal_addr; 913 u64 last_semaphore_wait_addr; 914 /* for CIK queues */ 915 u32 me; 916 u32 pipe; 917 u32 queue; 918 struct radeon_bo *mqd_obj; 919 u32 doorbell_index; 920 unsigned wptr_offs; 921 }; 922 923 struct radeon_mec { 924 struct radeon_bo *hpd_eop_obj; 925 u64 hpd_eop_gpu_addr; 926 u32 num_pipe; 927 u32 num_mec; 928 u32 num_queue; 929 }; 930 931 /* 932 * VM 933 */ 934 935 /* maximum number of VMIDs */ 936 #define RADEON_NUM_VM 16 937 938 /* number of entries in page table */ 939 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 940 941 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 942 #define RADEON_VM_PTB_ALIGN_SIZE 32768 943 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 944 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 945 946 #define R600_PTE_VALID (1 << 0) 947 #define R600_PTE_SYSTEM (1 << 1) 948 #define R600_PTE_SNOOPED (1 << 2) 949 #define R600_PTE_READABLE (1 << 5) 950 #define R600_PTE_WRITEABLE (1 << 6) 951 952 /* PTE (Page Table Entry) fragment field for different page sizes */ 953 #define R600_PTE_FRAG_4KB (0 << 7) 954 #define R600_PTE_FRAG_64KB (4 << 7) 955 #define R600_PTE_FRAG_256KB (6 << 7) 956 957 /* flags needed to be set so we can copy directly from the GART table */ 958 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 959 R600_PTE_SYSTEM | R600_PTE_VALID ) 960 961 struct radeon_vm_pt { 962 struct radeon_bo *bo; 963 uint64_t addr; 964 }; 965 966 struct radeon_vm_id { 967 unsigned id; 968 uint64_t pd_gpu_addr; 969 /* last flushed PD/PT update */ 970 struct radeon_fence *flushed_updates; 971 /* last use of vmid */ 972 struct radeon_fence *last_id_use; 973 }; 974 975 struct radeon_vm { 976 struct mutex mutex; 977 978 struct rb_root va; 979 980 /* protecting invalidated and freed */ 981 spinlock_t status_lock; 982 983 /* BOs moved, but not yet updated in the PT */ 984 struct list_head invalidated; 985 986 /* BOs freed, but not yet updated in the PT */ 987 struct list_head freed; 988 989 /* BOs cleared in the PT */ 990 struct list_head cleared; 991 992 /* contains the page directory */ 993 struct radeon_bo *page_directory; 994 unsigned max_pde_used; 995 996 /* array of page tables, one for each page directory entry */ 997 struct radeon_vm_pt *page_tables; 998 999 struct radeon_bo_va *ib_bo_va; 1000 1001 /* for id and flush management per ring */ 1002 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 1003 }; 1004 1005 struct radeon_vm_manager { 1006 struct radeon_fence *active[RADEON_NUM_VM]; 1007 uint32_t max_pfn; 1008 /* number of VMIDs */ 1009 unsigned nvm; 1010 /* vram base address for page table entry */ 1011 u64 vram_base_offset; 1012 /* is vm enabled? */ 1013 bool enabled; 1014 /* for hw to save the PD addr on suspend/resume */ 1015 uint32_t saved_table_addr[RADEON_NUM_VM]; 1016 }; 1017 1018 /* 1019 * file private structure 1020 */ 1021 struct radeon_fpriv { 1022 struct radeon_vm vm; 1023 }; 1024 1025 /* 1026 * R6xx+ IH ring 1027 */ 1028 struct r600_ih { 1029 struct radeon_bo *ring_obj; 1030 volatile uint32_t *ring; 1031 unsigned rptr; 1032 unsigned ring_size; 1033 uint64_t gpu_addr; 1034 uint32_t ptr_mask; 1035 atomic_t lock; 1036 bool enabled; 1037 }; 1038 1039 /* 1040 * RLC stuff 1041 */ 1042 #include "clearstate_defs.h" 1043 1044 struct radeon_rlc { 1045 /* for power gating */ 1046 struct radeon_bo *save_restore_obj; 1047 uint64_t save_restore_gpu_addr; 1048 volatile uint32_t *sr_ptr; 1049 const u32 *reg_list; 1050 u32 reg_list_size; 1051 /* for clear state */ 1052 struct radeon_bo *clear_state_obj; 1053 uint64_t clear_state_gpu_addr; 1054 volatile uint32_t *cs_ptr; 1055 const struct cs_section_def *cs_data; 1056 u32 clear_state_size; 1057 /* for cp tables */ 1058 struct radeon_bo *cp_table_obj; 1059 uint64_t cp_table_gpu_addr; 1060 volatile uint32_t *cp_table_ptr; 1061 u32 cp_table_size; 1062 }; 1063 1064 int radeon_ib_get(struct radeon_device *rdev, int ring, 1065 struct radeon_ib *ib, struct radeon_vm *vm, 1066 unsigned size); 1067 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1068 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1069 struct radeon_ib *const_ib, bool hdp_flush); 1070 int radeon_ib_pool_init(struct radeon_device *rdev); 1071 void radeon_ib_pool_fini(struct radeon_device *rdev); 1072 int radeon_ib_ring_tests(struct radeon_device *rdev); 1073 /* Ring access between begin & end cannot sleep */ 1074 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1075 struct radeon_ring *ring); 1076 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1077 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1078 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1079 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1080 bool hdp_flush); 1081 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1082 bool hdp_flush); 1083 void radeon_ring_undo(struct radeon_ring *ring); 1084 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1085 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1086 void radeon_ring_lockup_update(struct radeon_device *rdev, 1087 struct radeon_ring *ring); 1088 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1089 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1090 uint32_t **data); 1091 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1092 unsigned size, uint32_t *data); 1093 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1094 unsigned rptr_offs, u32 nop); 1095 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1096 1097 1098 /* r600 async dma */ 1099 void r600_dma_stop(struct radeon_device *rdev); 1100 int r600_dma_resume(struct radeon_device *rdev); 1101 void r600_dma_fini(struct radeon_device *rdev); 1102 1103 void cayman_dma_stop(struct radeon_device *rdev); 1104 int cayman_dma_resume(struct radeon_device *rdev); 1105 void cayman_dma_fini(struct radeon_device *rdev); 1106 1107 /* 1108 * CS. 1109 */ 1110 struct radeon_cs_chunk { 1111 uint32_t length_dw; 1112 uint32_t *kdata; 1113 void __user *user_ptr; 1114 }; 1115 1116 struct radeon_cs_parser { 1117 struct device *dev; 1118 struct radeon_device *rdev; 1119 struct drm_file *filp; 1120 /* chunks */ 1121 unsigned nchunks; 1122 struct radeon_cs_chunk *chunks; 1123 uint64_t *chunks_array; 1124 /* IB */ 1125 unsigned idx; 1126 /* relocations */ 1127 unsigned nrelocs; 1128 struct radeon_bo_list *relocs; 1129 struct radeon_bo_list *vm_bos; 1130 struct list_head validated; 1131 unsigned dma_reloc_idx; 1132 /* indices of various chunks */ 1133 struct radeon_cs_chunk *chunk_ib; 1134 struct radeon_cs_chunk *chunk_relocs; 1135 struct radeon_cs_chunk *chunk_flags; 1136 struct radeon_cs_chunk *chunk_const_ib; 1137 struct radeon_ib ib; 1138 struct radeon_ib const_ib; 1139 void *track; 1140 unsigned family; 1141 int parser_error; 1142 u32 cs_flags; 1143 u32 ring; 1144 s32 priority; 1145 struct ww_acquire_ctx ticket; 1146 }; 1147 1148 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1149 { 1150 struct radeon_cs_chunk *ibc = p->chunk_ib; 1151 1152 if (ibc->kdata) 1153 return ibc->kdata[idx]; 1154 return p->ib.ptr[idx]; 1155 } 1156 1157 1158 struct radeon_cs_packet { 1159 unsigned idx; 1160 unsigned type; 1161 unsigned reg; 1162 unsigned opcode; 1163 int count; 1164 unsigned one_reg_wr; 1165 }; 1166 1167 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1168 struct radeon_cs_packet *pkt, 1169 unsigned idx, unsigned reg); 1170 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1171 struct radeon_cs_packet *pkt); 1172 1173 1174 /* 1175 * AGP 1176 */ 1177 int radeon_agp_init(struct radeon_device *rdev); 1178 void radeon_agp_resume(struct radeon_device *rdev); 1179 void radeon_agp_suspend(struct radeon_device *rdev); 1180 void radeon_agp_fini(struct radeon_device *rdev); 1181 1182 1183 /* 1184 * Writeback 1185 */ 1186 struct radeon_wb { 1187 struct radeon_bo *wb_obj; 1188 volatile uint32_t *wb; 1189 uint64_t gpu_addr; 1190 bool enabled; 1191 bool use_event; 1192 }; 1193 1194 #define RADEON_WB_SCRATCH_OFFSET 0 1195 #define RADEON_WB_RING0_NEXT_RPTR 256 1196 #define RADEON_WB_CP_RPTR_OFFSET 1024 1197 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1198 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1199 #define R600_WB_DMA_RPTR_OFFSET 1792 1200 #define R600_WB_IH_WPTR_OFFSET 2048 1201 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1202 #define R600_WB_EVENT_OFFSET 3072 1203 #define CIK_WB_CP1_WPTR_OFFSET 3328 1204 #define CIK_WB_CP2_WPTR_OFFSET 3584 1205 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1206 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1207 1208 /** 1209 * struct radeon_pm - power management datas 1210 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1211 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1212 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1213 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1214 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1215 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1216 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1217 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1218 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1219 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1220 * @needed_bandwidth: current bandwidth needs 1221 * 1222 * It keeps track of various data needed to take powermanagement decision. 1223 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1224 * Equation between gpu/memory clock and available bandwidth is hw dependent 1225 * (type of memory, bus size, efficiency, ...) 1226 */ 1227 1228 enum radeon_pm_method { 1229 PM_METHOD_PROFILE, 1230 PM_METHOD_DYNPM, 1231 PM_METHOD_DPM, 1232 }; 1233 1234 enum radeon_dynpm_state { 1235 DYNPM_STATE_DISABLED, 1236 DYNPM_STATE_MINIMUM, 1237 DYNPM_STATE_PAUSED, 1238 DYNPM_STATE_ACTIVE, 1239 DYNPM_STATE_SUSPENDED, 1240 }; 1241 enum radeon_dynpm_action { 1242 DYNPM_ACTION_NONE, 1243 DYNPM_ACTION_MINIMUM, 1244 DYNPM_ACTION_DOWNCLOCK, 1245 DYNPM_ACTION_UPCLOCK, 1246 DYNPM_ACTION_DEFAULT 1247 }; 1248 1249 enum radeon_voltage_type { 1250 VOLTAGE_NONE = 0, 1251 VOLTAGE_GPIO, 1252 VOLTAGE_VDDC, 1253 VOLTAGE_SW 1254 }; 1255 1256 enum radeon_pm_state_type { 1257 /* not used for dpm */ 1258 POWER_STATE_TYPE_DEFAULT, 1259 POWER_STATE_TYPE_POWERSAVE, 1260 /* user selectable states */ 1261 POWER_STATE_TYPE_BATTERY, 1262 POWER_STATE_TYPE_BALANCED, 1263 POWER_STATE_TYPE_PERFORMANCE, 1264 /* internal states */ 1265 POWER_STATE_TYPE_INTERNAL_UVD, 1266 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1267 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1268 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1269 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1270 POWER_STATE_TYPE_INTERNAL_BOOT, 1271 POWER_STATE_TYPE_INTERNAL_THERMAL, 1272 POWER_STATE_TYPE_INTERNAL_ACPI, 1273 POWER_STATE_TYPE_INTERNAL_ULV, 1274 POWER_STATE_TYPE_INTERNAL_3DPERF, 1275 }; 1276 1277 enum radeon_pm_profile_type { 1278 PM_PROFILE_DEFAULT, 1279 PM_PROFILE_AUTO, 1280 PM_PROFILE_LOW, 1281 PM_PROFILE_MID, 1282 PM_PROFILE_HIGH, 1283 }; 1284 1285 #define PM_PROFILE_DEFAULT_IDX 0 1286 #define PM_PROFILE_LOW_SH_IDX 1 1287 #define PM_PROFILE_MID_SH_IDX 2 1288 #define PM_PROFILE_HIGH_SH_IDX 3 1289 #define PM_PROFILE_LOW_MH_IDX 4 1290 #define PM_PROFILE_MID_MH_IDX 5 1291 #define PM_PROFILE_HIGH_MH_IDX 6 1292 #define PM_PROFILE_MAX 7 1293 1294 struct radeon_pm_profile { 1295 int dpms_off_ps_idx; 1296 int dpms_on_ps_idx; 1297 int dpms_off_cm_idx; 1298 int dpms_on_cm_idx; 1299 }; 1300 1301 enum radeon_int_thermal_type { 1302 THERMAL_TYPE_NONE, 1303 THERMAL_TYPE_EXTERNAL, 1304 THERMAL_TYPE_EXTERNAL_GPIO, 1305 THERMAL_TYPE_RV6XX, 1306 THERMAL_TYPE_RV770, 1307 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1308 THERMAL_TYPE_EVERGREEN, 1309 THERMAL_TYPE_SUMO, 1310 THERMAL_TYPE_NI, 1311 THERMAL_TYPE_SI, 1312 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1313 THERMAL_TYPE_CI, 1314 THERMAL_TYPE_KV, 1315 }; 1316 1317 struct radeon_voltage { 1318 enum radeon_voltage_type type; 1319 /* gpio voltage */ 1320 struct radeon_gpio_rec gpio; 1321 u32 delay; /* delay in usec from voltage drop to sclk change */ 1322 bool active_high; /* voltage drop is active when bit is high */ 1323 /* VDDC voltage */ 1324 u8 vddc_id; /* index into vddc voltage table */ 1325 u8 vddci_id; /* index into vddci voltage table */ 1326 bool vddci_enabled; 1327 /* r6xx+ sw */ 1328 u16 voltage; 1329 /* evergreen+ vddci */ 1330 u16 vddci; 1331 }; 1332 1333 /* clock mode flags */ 1334 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1335 1336 struct radeon_pm_clock_info { 1337 /* memory clock */ 1338 u32 mclk; 1339 /* engine clock */ 1340 u32 sclk; 1341 /* voltage info */ 1342 struct radeon_voltage voltage; 1343 /* standardized clock flags */ 1344 u32 flags; 1345 }; 1346 1347 /* state flags */ 1348 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1349 1350 struct radeon_power_state { 1351 enum radeon_pm_state_type type; 1352 struct radeon_pm_clock_info *clock_info; 1353 /* number of valid clock modes in this power state */ 1354 int num_clock_modes; 1355 struct radeon_pm_clock_info *default_clock_mode; 1356 /* standardized state flags */ 1357 u32 flags; 1358 u32 misc; /* vbios specific flags */ 1359 u32 misc2; /* vbios specific flags */ 1360 int pcie_lanes; /* pcie lanes */ 1361 }; 1362 1363 /* 1364 * Some modes are overclocked by very low value, accept them 1365 */ 1366 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1367 1368 enum radeon_dpm_auto_throttle_src { 1369 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1370 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1371 }; 1372 1373 enum radeon_dpm_event_src { 1374 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1375 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1376 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1377 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1378 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1379 }; 1380 1381 #define RADEON_MAX_VCE_LEVELS 6 1382 1383 enum radeon_vce_level { 1384 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1385 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1386 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1387 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1388 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1389 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1390 }; 1391 1392 struct radeon_ps { 1393 u32 caps; /* vbios flags */ 1394 u32 class; /* vbios flags */ 1395 u32 class2; /* vbios flags */ 1396 /* UVD clocks */ 1397 u32 vclk; 1398 u32 dclk; 1399 /* VCE clocks */ 1400 u32 evclk; 1401 u32 ecclk; 1402 bool vce_active; 1403 enum radeon_vce_level vce_level; 1404 /* asic priv */ 1405 void *ps_priv; 1406 }; 1407 1408 struct radeon_dpm_thermal { 1409 /* thermal interrupt work */ 1410 struct work_struct work; 1411 /* low temperature threshold */ 1412 int min_temp; 1413 /* high temperature threshold */ 1414 int max_temp; 1415 /* was interrupt low to high or high to low */ 1416 bool high_to_low; 1417 }; 1418 1419 enum radeon_clk_action 1420 { 1421 RADEON_SCLK_UP = 1, 1422 RADEON_SCLK_DOWN 1423 }; 1424 1425 struct radeon_blacklist_clocks 1426 { 1427 u32 sclk; 1428 u32 mclk; 1429 enum radeon_clk_action action; 1430 }; 1431 1432 struct radeon_clock_and_voltage_limits { 1433 u32 sclk; 1434 u32 mclk; 1435 u16 vddc; 1436 u16 vddci; 1437 }; 1438 1439 struct radeon_clock_array { 1440 u32 count; 1441 u32 *values; 1442 }; 1443 1444 struct radeon_clock_voltage_dependency_entry { 1445 u32 clk; 1446 u16 v; 1447 }; 1448 1449 struct radeon_clock_voltage_dependency_table { 1450 u32 count; 1451 struct radeon_clock_voltage_dependency_entry *entries; 1452 }; 1453 1454 union radeon_cac_leakage_entry { 1455 struct { 1456 u16 vddc; 1457 u32 leakage; 1458 }; 1459 struct { 1460 u16 vddc1; 1461 u16 vddc2; 1462 u16 vddc3; 1463 }; 1464 }; 1465 1466 struct radeon_cac_leakage_table { 1467 u32 count; 1468 union radeon_cac_leakage_entry *entries; 1469 }; 1470 1471 struct radeon_phase_shedding_limits_entry { 1472 u16 voltage; 1473 u32 sclk; 1474 u32 mclk; 1475 }; 1476 1477 struct radeon_phase_shedding_limits_table { 1478 u32 count; 1479 struct radeon_phase_shedding_limits_entry *entries; 1480 }; 1481 1482 struct radeon_uvd_clock_voltage_dependency_entry { 1483 u32 vclk; 1484 u32 dclk; 1485 u16 v; 1486 }; 1487 1488 struct radeon_uvd_clock_voltage_dependency_table { 1489 u8 count; 1490 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1491 }; 1492 1493 struct radeon_vce_clock_voltage_dependency_entry { 1494 u32 ecclk; 1495 u32 evclk; 1496 u16 v; 1497 }; 1498 1499 struct radeon_vce_clock_voltage_dependency_table { 1500 u8 count; 1501 struct radeon_vce_clock_voltage_dependency_entry *entries; 1502 }; 1503 1504 struct radeon_ppm_table { 1505 u8 ppm_design; 1506 u16 cpu_core_number; 1507 u32 platform_tdp; 1508 u32 small_ac_platform_tdp; 1509 u32 platform_tdc; 1510 u32 small_ac_platform_tdc; 1511 u32 apu_tdp; 1512 u32 dgpu_tdp; 1513 u32 dgpu_ulv_power; 1514 u32 tj_max; 1515 }; 1516 1517 struct radeon_cac_tdp_table { 1518 u16 tdp; 1519 u16 configurable_tdp; 1520 u16 tdc; 1521 u16 battery_power_limit; 1522 u16 small_power_limit; 1523 u16 low_cac_leakage; 1524 u16 high_cac_leakage; 1525 u16 maximum_power_delivery_limit; 1526 }; 1527 1528 struct radeon_dpm_dynamic_state { 1529 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1530 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1531 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1532 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1533 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1534 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1535 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1536 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1537 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1538 struct radeon_clock_array valid_sclk_values; 1539 struct radeon_clock_array valid_mclk_values; 1540 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1541 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1542 u32 mclk_sclk_ratio; 1543 u32 sclk_mclk_delta; 1544 u16 vddc_vddci_delta; 1545 u16 min_vddc_for_pcie_gen2; 1546 struct radeon_cac_leakage_table cac_leakage_table; 1547 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1548 struct radeon_ppm_table *ppm_table; 1549 struct radeon_cac_tdp_table *cac_tdp_table; 1550 }; 1551 1552 struct radeon_dpm_fan { 1553 u16 t_min; 1554 u16 t_med; 1555 u16 t_high; 1556 u16 pwm_min; 1557 u16 pwm_med; 1558 u16 pwm_high; 1559 u8 t_hyst; 1560 u32 cycle_delay; 1561 u16 t_max; 1562 u8 control_mode; 1563 u16 default_max_fan_pwm; 1564 u16 default_fan_output_sensitivity; 1565 u16 fan_output_sensitivity; 1566 bool ucode_fan_control; 1567 }; 1568 1569 enum radeon_pcie_gen { 1570 RADEON_PCIE_GEN1 = 0, 1571 RADEON_PCIE_GEN2 = 1, 1572 RADEON_PCIE_GEN3 = 2, 1573 RADEON_PCIE_GEN_INVALID = 0xffff 1574 }; 1575 1576 enum radeon_dpm_forced_level { 1577 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1578 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1579 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1580 }; 1581 1582 struct radeon_vce_state { 1583 /* vce clocks */ 1584 u32 evclk; 1585 u32 ecclk; 1586 /* gpu clocks */ 1587 u32 sclk; 1588 u32 mclk; 1589 u8 clk_idx; 1590 u8 pstate; 1591 }; 1592 1593 struct radeon_dpm { 1594 struct radeon_ps *ps; 1595 /* number of valid power states */ 1596 int num_ps; 1597 /* current power state that is active */ 1598 struct radeon_ps *current_ps; 1599 /* requested power state */ 1600 struct radeon_ps *requested_ps; 1601 /* boot up power state */ 1602 struct radeon_ps *boot_ps; 1603 /* default uvd power state */ 1604 struct radeon_ps *uvd_ps; 1605 /* vce requirements */ 1606 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1607 enum radeon_vce_level vce_level; 1608 enum radeon_pm_state_type state; 1609 enum radeon_pm_state_type user_state; 1610 u32 platform_caps; 1611 u32 voltage_response_time; 1612 u32 backbias_response_time; 1613 void *priv; 1614 u32 new_active_crtcs; 1615 int new_active_crtc_count; 1616 u32 current_active_crtcs; 1617 int current_active_crtc_count; 1618 bool single_display; 1619 struct radeon_dpm_dynamic_state dyn_state; 1620 struct radeon_dpm_fan fan; 1621 u32 tdp_limit; 1622 u32 near_tdp_limit; 1623 u32 near_tdp_limit_adjusted; 1624 u32 sq_ramping_threshold; 1625 u32 cac_leakage; 1626 u16 tdp_od_limit; 1627 u32 tdp_adjustment; 1628 u16 load_line_slope; 1629 bool power_control; 1630 bool ac_power; 1631 /* special states active */ 1632 bool thermal_active; 1633 bool uvd_active; 1634 bool vce_active; 1635 /* thermal handling */ 1636 struct radeon_dpm_thermal thermal; 1637 /* forced levels */ 1638 enum radeon_dpm_forced_level forced_level; 1639 /* track UVD streams */ 1640 unsigned sd; 1641 unsigned hd; 1642 }; 1643 1644 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1645 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1646 1647 struct radeon_pm { 1648 struct mutex mutex; 1649 /* write locked while reprogramming mclk */ 1650 struct rw_semaphore mclk_lock; 1651 u32 active_crtcs; 1652 int active_crtc_count; 1653 int req_vblank; 1654 bool vblank_sync; 1655 fixed20_12 max_bandwidth; 1656 fixed20_12 igp_sideport_mclk; 1657 fixed20_12 igp_system_mclk; 1658 fixed20_12 igp_ht_link_clk; 1659 fixed20_12 igp_ht_link_width; 1660 fixed20_12 k8_bandwidth; 1661 fixed20_12 sideport_bandwidth; 1662 fixed20_12 ht_bandwidth; 1663 fixed20_12 core_bandwidth; 1664 fixed20_12 sclk; 1665 fixed20_12 mclk; 1666 fixed20_12 needed_bandwidth; 1667 struct radeon_power_state *power_state; 1668 /* number of valid power states */ 1669 int num_power_states; 1670 int current_power_state_index; 1671 int current_clock_mode_index; 1672 int requested_power_state_index; 1673 int requested_clock_mode_index; 1674 int default_power_state_index; 1675 u32 current_sclk; 1676 u32 current_mclk; 1677 u16 current_vddc; 1678 u16 current_vddci; 1679 u32 default_sclk; 1680 u32 default_mclk; 1681 u16 default_vddc; 1682 u16 default_vddci; 1683 struct radeon_i2c_chan *i2c_bus; 1684 /* selected pm method */ 1685 enum radeon_pm_method pm_method; 1686 /* dynpm power management */ 1687 struct delayed_work dynpm_idle_work; 1688 enum radeon_dynpm_state dynpm_state; 1689 enum radeon_dynpm_action dynpm_planned_action; 1690 unsigned long dynpm_action_timeout; 1691 bool dynpm_can_upclock; 1692 bool dynpm_can_downclock; 1693 /* profile-based power management */ 1694 enum radeon_pm_profile_type profile; 1695 int profile_index; 1696 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1697 /* internal thermal controller on rv6xx+ */ 1698 enum radeon_int_thermal_type int_thermal_type; 1699 struct device *int_hwmon_dev; 1700 /* fan control parameters */ 1701 bool no_fan; 1702 u8 fan_pulses_per_revolution; 1703 u8 fan_min_rpm; 1704 u8 fan_max_rpm; 1705 /* dpm */ 1706 bool dpm_enabled; 1707 bool sysfs_initialized; 1708 struct radeon_dpm dpm; 1709 }; 1710 1711 int radeon_pm_get_type_index(struct radeon_device *rdev, 1712 enum radeon_pm_state_type ps_type, 1713 int instance); 1714 /* 1715 * UVD 1716 */ 1717 #define RADEON_MAX_UVD_HANDLES 10 1718 #define RADEON_UVD_STACK_SIZE (1024*1024) 1719 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1720 1721 struct radeon_uvd { 1722 struct radeon_bo *vcpu_bo; 1723 void *cpu_addr; 1724 uint64_t gpu_addr; 1725 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1726 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1727 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1728 struct delayed_work idle_work; 1729 }; 1730 1731 int radeon_uvd_init(struct radeon_device *rdev); 1732 void radeon_uvd_fini(struct radeon_device *rdev); 1733 int radeon_uvd_suspend(struct radeon_device *rdev); 1734 int radeon_uvd_resume(struct radeon_device *rdev); 1735 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1736 uint32_t handle, struct radeon_fence **fence); 1737 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1738 uint32_t handle, struct radeon_fence **fence); 1739 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1740 uint32_t allowed_domains); 1741 void radeon_uvd_free_handles(struct radeon_device *rdev, 1742 struct drm_file *filp); 1743 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1744 void radeon_uvd_note_usage(struct radeon_device *rdev); 1745 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1746 unsigned vclk, unsigned dclk, 1747 unsigned vco_min, unsigned vco_max, 1748 unsigned fb_factor, unsigned fb_mask, 1749 unsigned pd_min, unsigned pd_max, 1750 unsigned pd_even, 1751 unsigned *optimal_fb_div, 1752 unsigned *optimal_vclk_div, 1753 unsigned *optimal_dclk_div); 1754 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1755 unsigned cg_upll_func_cntl); 1756 1757 /* 1758 * VCE 1759 */ 1760 #define RADEON_MAX_VCE_HANDLES 16 1761 1762 struct radeon_vce { 1763 struct radeon_bo *vcpu_bo; 1764 uint64_t gpu_addr; 1765 unsigned fw_version; 1766 unsigned fb_version; 1767 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1768 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1769 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1770 struct delayed_work idle_work; 1771 uint32_t keyselect; 1772 }; 1773 1774 int radeon_vce_init(struct radeon_device *rdev); 1775 void radeon_vce_fini(struct radeon_device *rdev); 1776 int radeon_vce_suspend(struct radeon_device *rdev); 1777 int radeon_vce_resume(struct radeon_device *rdev); 1778 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1779 uint32_t handle, struct radeon_fence **fence); 1780 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1781 uint32_t handle, struct radeon_fence **fence); 1782 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1783 void radeon_vce_note_usage(struct radeon_device *rdev); 1784 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1785 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1786 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1787 struct radeon_ring *ring, 1788 struct radeon_semaphore *semaphore, 1789 bool emit_wait); 1790 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1791 void radeon_vce_fence_emit(struct radeon_device *rdev, 1792 struct radeon_fence *fence); 1793 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1794 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1795 1796 struct r600_audio_pin { 1797 int channels; 1798 int rate; 1799 int bits_per_sample; 1800 u8 status_bits; 1801 u8 category_code; 1802 u32 offset; 1803 bool connected; 1804 u32 id; 1805 }; 1806 1807 struct r600_audio { 1808 bool enabled; 1809 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1810 int num_pins; 1811 struct radeon_audio_funcs *hdmi_funcs; 1812 struct radeon_audio_funcs *dp_funcs; 1813 struct radeon_audio_basic_funcs *funcs; 1814 }; 1815 1816 /* 1817 * Benchmarking 1818 */ 1819 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1820 1821 1822 /* 1823 * Testing 1824 */ 1825 void radeon_test_moves(struct radeon_device *rdev); 1826 void radeon_test_ring_sync(struct radeon_device *rdev, 1827 struct radeon_ring *cpA, 1828 struct radeon_ring *cpB); 1829 void radeon_test_syncing(struct radeon_device *rdev); 1830 1831 /* 1832 * MMU Notifier 1833 */ 1834 #if defined(CONFIG_MMU_NOTIFIER) 1835 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1836 void radeon_mn_unregister(struct radeon_bo *bo); 1837 #else 1838 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1839 { 1840 return -ENODEV; 1841 } 1842 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1843 #endif 1844 1845 /* 1846 * Debugfs 1847 */ 1848 struct radeon_debugfs { 1849 struct drm_info_list *files; 1850 unsigned num_files; 1851 }; 1852 1853 int radeon_debugfs_add_files(struct radeon_device *rdev, 1854 struct drm_info_list *files, 1855 unsigned nfiles); 1856 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1857 1858 /* 1859 * ASIC ring specific functions. 1860 */ 1861 struct radeon_asic_ring { 1862 /* ring read/write ptr handling */ 1863 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1864 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1865 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1866 1867 /* validating and patching of IBs */ 1868 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1869 int (*cs_parse)(struct radeon_cs_parser *p); 1870 1871 /* command emmit functions */ 1872 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1873 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1874 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1875 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1876 struct radeon_semaphore *semaphore, bool emit_wait); 1877 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1878 unsigned vm_id, uint64_t pd_addr); 1879 1880 /* testing functions */ 1881 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1882 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1883 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1884 1885 /* deprecated */ 1886 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1887 }; 1888 1889 /* 1890 * ASIC specific functions. 1891 */ 1892 struct radeon_asic { 1893 int (*init)(struct radeon_device *rdev); 1894 void (*fini)(struct radeon_device *rdev); 1895 int (*resume)(struct radeon_device *rdev); 1896 int (*suspend)(struct radeon_device *rdev); 1897 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1898 int (*asic_reset)(struct radeon_device *rdev); 1899 /* Flush the HDP cache via MMIO */ 1900 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1901 /* check if 3D engine is idle */ 1902 bool (*gui_idle)(struct radeon_device *rdev); 1903 /* wait for mc_idle */ 1904 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1905 /* get the reference clock */ 1906 u32 (*get_xclk)(struct radeon_device *rdev); 1907 /* get the gpu clock counter */ 1908 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1909 /* get register for info ioctl */ 1910 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1911 /* gart */ 1912 struct { 1913 void (*tlb_flush)(struct radeon_device *rdev); 1914 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1915 void (*set_page)(struct radeon_device *rdev, unsigned i, 1916 uint64_t entry); 1917 } gart; 1918 struct { 1919 int (*init)(struct radeon_device *rdev); 1920 void (*fini)(struct radeon_device *rdev); 1921 void (*copy_pages)(struct radeon_device *rdev, 1922 struct radeon_ib *ib, 1923 uint64_t pe, uint64_t src, 1924 unsigned count); 1925 void (*write_pages)(struct radeon_device *rdev, 1926 struct radeon_ib *ib, 1927 uint64_t pe, 1928 uint64_t addr, unsigned count, 1929 uint32_t incr, uint32_t flags); 1930 void (*set_pages)(struct radeon_device *rdev, 1931 struct radeon_ib *ib, 1932 uint64_t pe, 1933 uint64_t addr, unsigned count, 1934 uint32_t incr, uint32_t flags); 1935 void (*pad_ib)(struct radeon_ib *ib); 1936 } vm; 1937 /* ring specific callbacks */ 1938 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1939 /* irqs */ 1940 struct { 1941 int (*set)(struct radeon_device *rdev); 1942 int (*process)(struct radeon_device *rdev); 1943 } irq; 1944 /* displays */ 1945 struct { 1946 /* display watermarks */ 1947 void (*bandwidth_update)(struct radeon_device *rdev); 1948 /* get frame count */ 1949 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1950 /* wait for vblank */ 1951 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1952 /* set backlight level */ 1953 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1954 /* get backlight level */ 1955 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1956 /* audio callbacks */ 1957 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1958 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1959 } display; 1960 /* copy functions for bo handling */ 1961 struct { 1962 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1963 uint64_t src_offset, 1964 uint64_t dst_offset, 1965 unsigned num_gpu_pages, 1966 struct reservation_object *resv); 1967 u32 blit_ring_index; 1968 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1969 uint64_t src_offset, 1970 uint64_t dst_offset, 1971 unsigned num_gpu_pages, 1972 struct reservation_object *resv); 1973 u32 dma_ring_index; 1974 /* method used for bo copy */ 1975 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1976 uint64_t src_offset, 1977 uint64_t dst_offset, 1978 unsigned num_gpu_pages, 1979 struct reservation_object *resv); 1980 /* ring used for bo copies */ 1981 u32 copy_ring_index; 1982 } copy; 1983 /* surfaces */ 1984 struct { 1985 int (*set_reg)(struct radeon_device *rdev, int reg, 1986 uint32_t tiling_flags, uint32_t pitch, 1987 uint32_t offset, uint32_t obj_size); 1988 void (*clear_reg)(struct radeon_device *rdev, int reg); 1989 } surface; 1990 /* hotplug detect */ 1991 struct { 1992 void (*init)(struct radeon_device *rdev); 1993 void (*fini)(struct radeon_device *rdev); 1994 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1995 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1996 } hpd; 1997 /* static power management */ 1998 struct { 1999 void (*misc)(struct radeon_device *rdev); 2000 void (*prepare)(struct radeon_device *rdev); 2001 void (*finish)(struct radeon_device *rdev); 2002 void (*init_profile)(struct radeon_device *rdev); 2003 void (*get_dynpm_state)(struct radeon_device *rdev); 2004 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 2005 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 2006 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 2007 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 2008 int (*get_pcie_lanes)(struct radeon_device *rdev); 2009 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 2010 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 2011 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 2012 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 2013 int (*get_temperature)(struct radeon_device *rdev); 2014 } pm; 2015 /* dynamic power management */ 2016 struct { 2017 int (*init)(struct radeon_device *rdev); 2018 void (*setup_asic)(struct radeon_device *rdev); 2019 int (*enable)(struct radeon_device *rdev); 2020 int (*late_enable)(struct radeon_device *rdev); 2021 void (*disable)(struct radeon_device *rdev); 2022 int (*pre_set_power_state)(struct radeon_device *rdev); 2023 int (*set_power_state)(struct radeon_device *rdev); 2024 void (*post_set_power_state)(struct radeon_device *rdev); 2025 void (*display_configuration_changed)(struct radeon_device *rdev); 2026 void (*fini)(struct radeon_device *rdev); 2027 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2028 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2029 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2030 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2031 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2032 bool (*vblank_too_short)(struct radeon_device *rdev); 2033 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2034 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2035 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2036 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2037 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2038 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2039 u32 (*get_current_sclk)(struct radeon_device *rdev); 2040 u32 (*get_current_mclk)(struct radeon_device *rdev); 2041 } dpm; 2042 /* pageflipping */ 2043 struct { 2044 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 2045 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2046 } pflip; 2047 }; 2048 2049 /* 2050 * Asic structures 2051 */ 2052 struct r100_asic { 2053 const unsigned *reg_safe_bm; 2054 unsigned reg_safe_bm_size; 2055 u32 hdp_cntl; 2056 }; 2057 2058 struct r300_asic { 2059 const unsigned *reg_safe_bm; 2060 unsigned reg_safe_bm_size; 2061 u32 resync_scratch; 2062 u32 hdp_cntl; 2063 }; 2064 2065 struct r600_asic { 2066 unsigned max_pipes; 2067 unsigned max_tile_pipes; 2068 unsigned max_simds; 2069 unsigned max_backends; 2070 unsigned max_gprs; 2071 unsigned max_threads; 2072 unsigned max_stack_entries; 2073 unsigned max_hw_contexts; 2074 unsigned max_gs_threads; 2075 unsigned sx_max_export_size; 2076 unsigned sx_max_export_pos_size; 2077 unsigned sx_max_export_smx_size; 2078 unsigned sq_num_cf_insts; 2079 unsigned tiling_nbanks; 2080 unsigned tiling_npipes; 2081 unsigned tiling_group_size; 2082 unsigned tile_config; 2083 unsigned backend_map; 2084 unsigned active_simds; 2085 }; 2086 2087 struct rv770_asic { 2088 unsigned max_pipes; 2089 unsigned max_tile_pipes; 2090 unsigned max_simds; 2091 unsigned max_backends; 2092 unsigned max_gprs; 2093 unsigned max_threads; 2094 unsigned max_stack_entries; 2095 unsigned max_hw_contexts; 2096 unsigned max_gs_threads; 2097 unsigned sx_max_export_size; 2098 unsigned sx_max_export_pos_size; 2099 unsigned sx_max_export_smx_size; 2100 unsigned sq_num_cf_insts; 2101 unsigned sx_num_of_sets; 2102 unsigned sc_prim_fifo_size; 2103 unsigned sc_hiz_tile_fifo_size; 2104 unsigned sc_earlyz_tile_fifo_fize; 2105 unsigned tiling_nbanks; 2106 unsigned tiling_npipes; 2107 unsigned tiling_group_size; 2108 unsigned tile_config; 2109 unsigned backend_map; 2110 unsigned active_simds; 2111 }; 2112 2113 struct evergreen_asic { 2114 unsigned num_ses; 2115 unsigned max_pipes; 2116 unsigned max_tile_pipes; 2117 unsigned max_simds; 2118 unsigned max_backends; 2119 unsigned max_gprs; 2120 unsigned max_threads; 2121 unsigned max_stack_entries; 2122 unsigned max_hw_contexts; 2123 unsigned max_gs_threads; 2124 unsigned sx_max_export_size; 2125 unsigned sx_max_export_pos_size; 2126 unsigned sx_max_export_smx_size; 2127 unsigned sq_num_cf_insts; 2128 unsigned sx_num_of_sets; 2129 unsigned sc_prim_fifo_size; 2130 unsigned sc_hiz_tile_fifo_size; 2131 unsigned sc_earlyz_tile_fifo_size; 2132 unsigned tiling_nbanks; 2133 unsigned tiling_npipes; 2134 unsigned tiling_group_size; 2135 unsigned tile_config; 2136 unsigned backend_map; 2137 unsigned active_simds; 2138 }; 2139 2140 struct cayman_asic { 2141 unsigned max_shader_engines; 2142 unsigned max_pipes_per_simd; 2143 unsigned max_tile_pipes; 2144 unsigned max_simds_per_se; 2145 unsigned max_backends_per_se; 2146 unsigned max_texture_channel_caches; 2147 unsigned max_gprs; 2148 unsigned max_threads; 2149 unsigned max_gs_threads; 2150 unsigned max_stack_entries; 2151 unsigned sx_num_of_sets; 2152 unsigned sx_max_export_size; 2153 unsigned sx_max_export_pos_size; 2154 unsigned sx_max_export_smx_size; 2155 unsigned max_hw_contexts; 2156 unsigned sq_num_cf_insts; 2157 unsigned sc_prim_fifo_size; 2158 unsigned sc_hiz_tile_fifo_size; 2159 unsigned sc_earlyz_tile_fifo_size; 2160 2161 unsigned num_shader_engines; 2162 unsigned num_shader_pipes_per_simd; 2163 unsigned num_tile_pipes; 2164 unsigned num_simds_per_se; 2165 unsigned num_backends_per_se; 2166 unsigned backend_disable_mask_per_asic; 2167 unsigned backend_map; 2168 unsigned num_texture_channel_caches; 2169 unsigned mem_max_burst_length_bytes; 2170 unsigned mem_row_size_in_kb; 2171 unsigned shader_engine_tile_size; 2172 unsigned num_gpus; 2173 unsigned multi_gpu_tile_size; 2174 2175 unsigned tile_config; 2176 unsigned active_simds; 2177 }; 2178 2179 struct si_asic { 2180 unsigned max_shader_engines; 2181 unsigned max_tile_pipes; 2182 unsigned max_cu_per_sh; 2183 unsigned max_sh_per_se; 2184 unsigned max_backends_per_se; 2185 unsigned max_texture_channel_caches; 2186 unsigned max_gprs; 2187 unsigned max_gs_threads; 2188 unsigned max_hw_contexts; 2189 unsigned sc_prim_fifo_size_frontend; 2190 unsigned sc_prim_fifo_size_backend; 2191 unsigned sc_hiz_tile_fifo_size; 2192 unsigned sc_earlyz_tile_fifo_size; 2193 2194 unsigned num_tile_pipes; 2195 unsigned backend_enable_mask; 2196 unsigned backend_disable_mask_per_asic; 2197 unsigned backend_map; 2198 unsigned num_texture_channel_caches; 2199 unsigned mem_max_burst_length_bytes; 2200 unsigned mem_row_size_in_kb; 2201 unsigned shader_engine_tile_size; 2202 unsigned num_gpus; 2203 unsigned multi_gpu_tile_size; 2204 2205 unsigned tile_config; 2206 uint32_t tile_mode_array[32]; 2207 uint32_t active_cus; 2208 }; 2209 2210 struct cik_asic { 2211 unsigned max_shader_engines; 2212 unsigned max_tile_pipes; 2213 unsigned max_cu_per_sh; 2214 unsigned max_sh_per_se; 2215 unsigned max_backends_per_se; 2216 unsigned max_texture_channel_caches; 2217 unsigned max_gprs; 2218 unsigned max_gs_threads; 2219 unsigned max_hw_contexts; 2220 unsigned sc_prim_fifo_size_frontend; 2221 unsigned sc_prim_fifo_size_backend; 2222 unsigned sc_hiz_tile_fifo_size; 2223 unsigned sc_earlyz_tile_fifo_size; 2224 2225 unsigned num_tile_pipes; 2226 unsigned backend_enable_mask; 2227 unsigned backend_disable_mask_per_asic; 2228 unsigned backend_map; 2229 unsigned num_texture_channel_caches; 2230 unsigned mem_max_burst_length_bytes; 2231 unsigned mem_row_size_in_kb; 2232 unsigned shader_engine_tile_size; 2233 unsigned num_gpus; 2234 unsigned multi_gpu_tile_size; 2235 2236 unsigned tile_config; 2237 uint32_t tile_mode_array[32]; 2238 uint32_t macrotile_mode_array[16]; 2239 uint32_t active_cus; 2240 }; 2241 2242 union radeon_asic_config { 2243 struct r300_asic r300; 2244 struct r100_asic r100; 2245 struct r600_asic r600; 2246 struct rv770_asic rv770; 2247 struct evergreen_asic evergreen; 2248 struct cayman_asic cayman; 2249 struct si_asic si; 2250 struct cik_asic cik; 2251 }; 2252 2253 /* 2254 * asic initizalization from radeon_asic.c 2255 */ 2256 void radeon_agp_disable(struct radeon_device *rdev); 2257 int radeon_asic_init(struct radeon_device *rdev); 2258 2259 2260 /* 2261 * IOCTL. 2262 */ 2263 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2264 struct drm_file *filp); 2265 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2266 struct drm_file *filp); 2267 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2268 struct drm_file *filp); 2269 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2270 struct drm_file *file_priv); 2271 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2272 struct drm_file *file_priv); 2273 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2274 struct drm_file *file_priv); 2275 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2276 struct drm_file *file_priv); 2277 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2278 struct drm_file *filp); 2279 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2280 struct drm_file *filp); 2281 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2282 struct drm_file *filp); 2283 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2284 struct drm_file *filp); 2285 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2286 struct drm_file *filp); 2287 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2288 struct drm_file *filp); 2289 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2290 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2291 struct drm_file *filp); 2292 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2293 struct drm_file *filp); 2294 2295 /* VRAM scratch page for HDP bug, default vram page */ 2296 struct r600_vram_scratch { 2297 struct radeon_bo *robj; 2298 volatile uint32_t *ptr; 2299 u64 gpu_addr; 2300 }; 2301 2302 /* 2303 * ACPI 2304 */ 2305 struct radeon_atif_notification_cfg { 2306 bool enabled; 2307 int command_code; 2308 }; 2309 2310 struct radeon_atif_notifications { 2311 bool display_switch; 2312 bool expansion_mode_change; 2313 bool thermal_state; 2314 bool forced_power_state; 2315 bool system_power_state; 2316 bool display_conf_change; 2317 bool px_gfx_switch; 2318 bool brightness_change; 2319 bool dgpu_display_event; 2320 }; 2321 2322 struct radeon_atif_functions { 2323 bool system_params; 2324 bool sbios_requests; 2325 bool select_active_disp; 2326 bool lid_state; 2327 bool get_tv_standard; 2328 bool set_tv_standard; 2329 bool get_panel_expansion_mode; 2330 bool set_panel_expansion_mode; 2331 bool temperature_change; 2332 bool graphics_device_types; 2333 }; 2334 2335 struct radeon_atif { 2336 struct radeon_atif_notifications notifications; 2337 struct radeon_atif_functions functions; 2338 struct radeon_atif_notification_cfg notification_cfg; 2339 struct radeon_encoder *encoder_for_bl; 2340 }; 2341 2342 struct radeon_atcs_functions { 2343 bool get_ext_state; 2344 bool pcie_perf_req; 2345 bool pcie_dev_rdy; 2346 bool pcie_bus_width; 2347 }; 2348 2349 struct radeon_atcs { 2350 struct radeon_atcs_functions functions; 2351 }; 2352 2353 /* 2354 * Core structure, functions and helpers. 2355 */ 2356 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2357 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2358 2359 struct radeon_device { 2360 struct device *dev; 2361 struct drm_device *ddev; 2362 struct pci_dev *pdev; 2363 struct rw_semaphore exclusive_lock; 2364 /* ASIC */ 2365 union radeon_asic_config config; 2366 enum radeon_family family; 2367 unsigned long flags; 2368 int usec_timeout; 2369 enum radeon_pll_errata pll_errata; 2370 int num_gb_pipes; 2371 int num_z_pipes; 2372 int disp_priority; 2373 /* BIOS */ 2374 uint8_t *bios; 2375 bool is_atom_bios; 2376 uint16_t bios_header_start; 2377 struct radeon_bo *stollen_vga_memory; 2378 /* Register mmio */ 2379 #ifndef __NetBSD__ 2380 resource_size_t rmmio_base; 2381 resource_size_t rmmio_size; 2382 #endif 2383 /* protects concurrent MM_INDEX/DATA based register access */ 2384 spinlock_t mmio_idx_lock; 2385 /* protects concurrent SMC based register access */ 2386 spinlock_t smc_idx_lock; 2387 /* protects concurrent PLL register access */ 2388 spinlock_t pll_idx_lock; 2389 /* protects concurrent MC register access */ 2390 spinlock_t mc_idx_lock; 2391 /* protects concurrent PCIE register access */ 2392 spinlock_t pcie_idx_lock; 2393 /* protects concurrent PCIE_PORT register access */ 2394 spinlock_t pciep_idx_lock; 2395 /* protects concurrent PIF register access */ 2396 spinlock_t pif_idx_lock; 2397 /* protects concurrent CG register access */ 2398 spinlock_t cg_idx_lock; 2399 /* protects concurrent UVD register access */ 2400 spinlock_t uvd_idx_lock; 2401 /* protects concurrent RCU register access */ 2402 spinlock_t rcu_idx_lock; 2403 /* protects concurrent DIDT register access */ 2404 spinlock_t didt_idx_lock; 2405 /* protects concurrent ENDPOINT (audio) register access */ 2406 spinlock_t end_idx_lock; 2407 #ifdef __NetBSD__ 2408 bus_space_tag_t rmmio_bst; 2409 bus_space_handle_t rmmio_bsh; 2410 bus_addr_t rmmio_addr; 2411 bus_size_t rmmio_size; 2412 #else 2413 void __iomem *rmmio; 2414 #endif 2415 radeon_rreg_t mc_rreg; 2416 radeon_wreg_t mc_wreg; 2417 radeon_rreg_t pll_rreg; 2418 radeon_wreg_t pll_wreg; 2419 uint32_t pcie_reg_mask; 2420 radeon_rreg_t pciep_rreg; 2421 radeon_wreg_t pciep_wreg; 2422 /* io port */ 2423 #ifdef __NetBSD__ 2424 bus_space_tag_t rio_mem_bst; 2425 bus_space_handle_t rio_mem_bsh; 2426 bus_size_t rio_mem_size; 2427 #else 2428 void __iomem *rio_mem; 2429 resource_size_t rio_mem_size; 2430 #endif 2431 struct radeon_clock clock; 2432 struct radeon_mc mc; 2433 struct radeon_gart gart; 2434 struct radeon_mode_info mode_info; 2435 struct radeon_scratch scratch; 2436 struct radeon_doorbell doorbell; 2437 struct radeon_mman mman; 2438 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2439 #ifdef __NetBSD__ 2440 spinlock_t fence_lock; 2441 drm_waitqueue_t fence_queue; 2442 TAILQ_HEAD(, radeon_fence) fence_check; 2443 #else 2444 wait_queue_head_t fence_queue; 2445 #endif 2446 unsigned fence_context; 2447 struct mutex ring_lock; 2448 struct radeon_ring ring[RADEON_NUM_RINGS]; 2449 bool ib_pool_ready; 2450 struct radeon_sa_manager ring_tmp_bo; 2451 struct radeon_irq irq; 2452 struct radeon_asic *asic; 2453 struct radeon_gem gem; 2454 struct radeon_pm pm; 2455 struct radeon_uvd uvd; 2456 struct radeon_vce vce; 2457 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2458 struct radeon_wb wb; 2459 struct radeon_dummy_page dummy_page; 2460 bool shutdown; 2461 bool suspend; 2462 bool need_dma32; 2463 bool accel_working; 2464 bool fastfb_working; /* IGP feature*/ 2465 bool needs_reset, in_reset; 2466 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2467 const struct firmware *me_fw; /* all family ME firmware */ 2468 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2469 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2470 const struct firmware *mc_fw; /* NI MC firmware */ 2471 const struct firmware *ce_fw; /* SI CE firmware */ 2472 const struct firmware *mec_fw; /* CIK MEC firmware */ 2473 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2474 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2475 const struct firmware *smc_fw; /* SMC firmware */ 2476 const struct firmware *uvd_fw; /* UVD firmware */ 2477 const struct firmware *vce_fw; /* VCE firmware */ 2478 bool new_fw; 2479 struct r600_vram_scratch vram_scratch; 2480 int msi_enabled; /* msi enabled */ 2481 struct r600_ih ih; /* r6/700 interrupt ring */ 2482 struct radeon_rlc rlc; 2483 struct radeon_mec mec; 2484 struct delayed_work hotplug_work; 2485 struct work_struct dp_work; 2486 struct work_struct audio_work; 2487 int num_crtc; /* number of crtcs */ 2488 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2489 bool has_uvd; 2490 struct r600_audio audio; /* audio stuff */ 2491 struct notifier_block acpi_nb; 2492 /* only one userspace can use Hyperz features or CMASK at a time */ 2493 struct drm_file *hyperz_filp; 2494 struct drm_file *cmask_filp; 2495 /* i2c buses */ 2496 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2497 /* debugfs */ 2498 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2499 unsigned debugfs_count; 2500 /* virtual memory */ 2501 struct radeon_vm_manager vm_manager; 2502 struct mutex gpu_clock_mutex; 2503 /* memory stats */ 2504 atomic64_t vram_usage; 2505 atomic64_t gtt_usage; 2506 atomic64_t num_bytes_moved; 2507 atomic_t gpu_reset_counter; 2508 /* ACPI interface */ 2509 struct radeon_atif atif; 2510 struct radeon_atcs atcs; 2511 /* srbm instance registers */ 2512 struct mutex srbm_mutex; 2513 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2514 struct mutex grbm_idx_mutex; 2515 /* clock, powergating flags */ 2516 u32 cg_flags; 2517 u32 pg_flags; 2518 2519 struct dev_pm_domain vga_pm_domain; 2520 bool have_disp_power_ref; 2521 u32 px_quirk_flags; 2522 2523 /* tracking pinned memory */ 2524 u64 vram_pin_size; 2525 u64 gart_pin_size; 2526 2527 /* amdkfd interface */ 2528 struct kfd_dev *kfd; 2529 2530 struct mutex mn_lock; 2531 DECLARE_HASHTABLE(mn_hash, 7); 2532 }; 2533 2534 bool radeon_is_px(struct drm_device *dev); 2535 int radeon_device_init(struct radeon_device *rdev, 2536 struct drm_device *ddev, 2537 struct pci_dev *pdev, 2538 uint32_t flags); 2539 void radeon_device_fini(struct radeon_device *rdev); 2540 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2541 2542 #define RADEON_MIN_MMIO_SIZE 0x10000 2543 2544 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2545 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2546 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2547 bool always_indirect) 2548 { 2549 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2550 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2551 #ifdef __NetBSD__ 2552 return bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg); 2553 #else 2554 return readl(((void __iomem *)rdev->rmmio) + reg); 2555 #endif 2556 else 2557 return r100_mm_rreg_slow(rdev, reg); 2558 } 2559 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2560 bool always_indirect) 2561 { 2562 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2563 #ifdef __NetBSD__ 2564 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg, v); 2565 #else 2566 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2567 #endif 2568 else 2569 r100_mm_wreg_slow(rdev, reg, v); 2570 } 2571 2572 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2573 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2574 2575 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2576 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2577 2578 /* 2579 * Cast helper 2580 */ 2581 extern const struct fence_ops radeon_fence_ops; 2582 2583 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2584 { 2585 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2586 2587 if (__f->base.ops == &radeon_fence_ops) 2588 return __f; 2589 2590 return NULL; 2591 } 2592 2593 /* 2594 * Registers read & write functions. 2595 */ 2596 #ifdef __NetBSD__ 2597 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2598 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2599 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) 2600 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) 2601 #else 2602 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2603 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2604 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2605 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2606 #endif 2607 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2608 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2609 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2610 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2611 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2612 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2613 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2614 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2615 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2616 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2617 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2618 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2619 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2620 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2621 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2622 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2623 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2624 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2625 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2626 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2627 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2628 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2629 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2630 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2631 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2632 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2633 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2634 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2635 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2636 #define WREG32_P(reg, val, mask) \ 2637 do { \ 2638 uint32_t tmp_ = RREG32(reg); \ 2639 tmp_ &= (mask); \ 2640 tmp_ |= ((val) & ~(mask)); \ 2641 WREG32(reg, tmp_); \ 2642 } while (0) 2643 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2644 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2645 #define WREG32_PLL_P(reg, val, mask) \ 2646 do { \ 2647 uint32_t tmp_ = RREG32_PLL(reg); \ 2648 tmp_ &= (mask); \ 2649 tmp_ |= ((val) & ~(mask)); \ 2650 WREG32_PLL(reg, tmp_); \ 2651 } while (0) 2652 #define WREG32_SMC_P(reg, val, mask) \ 2653 do { \ 2654 uint32_t tmp_ = RREG32_SMC(reg); \ 2655 tmp_ &= (mask); \ 2656 tmp_ |= ((val) & ~(mask)); \ 2657 WREG32_SMC(reg, tmp_); \ 2658 } while (0) 2659 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2660 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2661 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2662 2663 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2664 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2665 2666 /* 2667 * Indirect registers accessors. 2668 * They used to be inlined, but this increases code size by ~65 kbytes. 2669 * Since each performs a pair of MMIO ops 2670 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2671 * the cost of call+ret is almost negligible. MMIO and locking 2672 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2673 */ 2674 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2675 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2676 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2677 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2678 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2679 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2680 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2681 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2682 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2683 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2684 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2685 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2686 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2687 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2688 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2689 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2690 2691 void r100_pll_errata_after_index(struct radeon_device *rdev); 2692 2693 2694 /* 2695 * ASICs helpers. 2696 */ 2697 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2698 (rdev->pdev->device == 0x5969)) 2699 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2700 (rdev->family == CHIP_RV200) || \ 2701 (rdev->family == CHIP_RS100) || \ 2702 (rdev->family == CHIP_RS200) || \ 2703 (rdev->family == CHIP_RV250) || \ 2704 (rdev->family == CHIP_RV280) || \ 2705 (rdev->family == CHIP_RS300)) 2706 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2707 (rdev->family == CHIP_RV350) || \ 2708 (rdev->family == CHIP_R350) || \ 2709 (rdev->family == CHIP_RV380) || \ 2710 (rdev->family == CHIP_R420) || \ 2711 (rdev->family == CHIP_R423) || \ 2712 (rdev->family == CHIP_RV410) || \ 2713 (rdev->family == CHIP_RS400) || \ 2714 (rdev->family == CHIP_RS480)) 2715 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2716 (rdev->ddev->pdev->device == 0x9443) || \ 2717 (rdev->ddev->pdev->device == 0x944B) || \ 2718 (rdev->ddev->pdev->device == 0x9506) || \ 2719 (rdev->ddev->pdev->device == 0x9509) || \ 2720 (rdev->ddev->pdev->device == 0x950F) || \ 2721 (rdev->ddev->pdev->device == 0x689C) || \ 2722 (rdev->ddev->pdev->device == 0x689D)) 2723 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2724 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2725 (rdev->family == CHIP_RS690) || \ 2726 (rdev->family == CHIP_RS740) || \ 2727 (rdev->family >= CHIP_R600)) 2728 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2729 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2730 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2731 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2732 (rdev->flags & RADEON_IS_IGP)) 2733 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2734 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2735 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2736 (rdev->flags & RADEON_IS_IGP)) 2737 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2738 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2739 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2740 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2741 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2742 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2743 (rdev->family == CHIP_MULLINS)) 2744 2745 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2746 (rdev->ddev->pdev->device == 0x6850) || \ 2747 (rdev->ddev->pdev->device == 0x6858) || \ 2748 (rdev->ddev->pdev->device == 0x6859) || \ 2749 (rdev->ddev->pdev->device == 0x6840) || \ 2750 (rdev->ddev->pdev->device == 0x6841) || \ 2751 (rdev->ddev->pdev->device == 0x6842) || \ 2752 (rdev->ddev->pdev->device == 0x6843)) 2753 2754 /* 2755 * BIOS helpers. 2756 */ 2757 #define RBIOS8(i) (rdev->bios[i]) 2758 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2759 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2760 2761 int radeon_combios_init(struct radeon_device *rdev); 2762 void radeon_combios_fini(struct radeon_device *rdev); 2763 int radeon_atombios_init(struct radeon_device *rdev); 2764 void radeon_atombios_fini(struct radeon_device *rdev); 2765 2766 2767 /* 2768 * RING helpers. 2769 */ 2770 2771 /** 2772 * radeon_ring_write - write a value to the ring 2773 * 2774 * @ring: radeon_ring structure holding ring information 2775 * @v: dword (dw) value to write 2776 * 2777 * Write a value to the requested ring buffer (all asics). 2778 */ 2779 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2780 { 2781 if (ring->count_dw <= 0) 2782 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2783 2784 ring->ring[ring->wptr++] = v; 2785 ring->wptr &= ring->ptr_mask; 2786 ring->count_dw--; 2787 ring->ring_free_dw--; 2788 } 2789 2790 /* 2791 * ASICs macro. 2792 */ 2793 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2794 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2795 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2796 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2797 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2798 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2799 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2800 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2801 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2802 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2803 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2804 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2805 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2806 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2807 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2808 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2809 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2810 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2811 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2812 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2813 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2814 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2815 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2816 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2817 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2818 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2819 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2820 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2821 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2822 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2823 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2824 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2825 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2826 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2827 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2828 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2829 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2830 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2831 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2832 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2833 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2834 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2835 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2836 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2837 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2838 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2839 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2840 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2841 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2842 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2843 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2844 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2845 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2846 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2847 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2848 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2849 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2850 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2851 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2852 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2853 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2854 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2855 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2856 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2857 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2858 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2859 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2860 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2861 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2862 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2863 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2864 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2865 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2866 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2867 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2868 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2869 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2870 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2871 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2872 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2873 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2874 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2875 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2876 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2877 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2878 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2879 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2880 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2881 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2882 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2883 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2884 2885 /* Common functions */ 2886 /* AGP */ 2887 extern int radeon_gpu_reset(struct radeon_device *rdev); 2888 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2889 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2890 extern void radeon_agp_disable(struct radeon_device *rdev); 2891 extern int radeon_modeset_init(struct radeon_device *rdev); 2892 extern void radeon_modeset_fini(struct radeon_device *rdev); 2893 extern bool radeon_card_posted(struct radeon_device *rdev); 2894 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2895 extern void radeon_update_display_priority(struct radeon_device *rdev); 2896 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2897 extern void radeon_scratch_init(struct radeon_device *rdev); 2898 extern void radeon_wb_fini(struct radeon_device *rdev); 2899 extern int radeon_wb_init(struct radeon_device *rdev); 2900 extern void radeon_wb_disable(struct radeon_device *rdev); 2901 extern void radeon_surface_init(struct radeon_device *rdev); 2902 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2903 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2904 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2905 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2906 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2907 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2908 uint32_t flags); 2909 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2910 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2911 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2912 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2913 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2914 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2915 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2916 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2917 const u32 *registers, 2918 const u32 array_size); 2919 2920 /* 2921 * vm 2922 */ 2923 int radeon_vm_manager_init(struct radeon_device *rdev); 2924 void radeon_vm_manager_fini(struct radeon_device *rdev); 2925 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2926 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2927 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2928 struct radeon_vm *vm, 2929 struct list_head *head); 2930 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2931 struct radeon_vm *vm, int ring); 2932 void radeon_vm_flush(struct radeon_device *rdev, 2933 struct radeon_vm *vm, 2934 int ring, struct radeon_fence *fence); 2935 void radeon_vm_fence(struct radeon_device *rdev, 2936 struct radeon_vm *vm, 2937 struct radeon_fence *fence); 2938 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2939 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2940 struct radeon_vm *vm); 2941 int radeon_vm_clear_freed(struct radeon_device *rdev, 2942 struct radeon_vm *vm); 2943 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2944 struct radeon_vm *vm); 2945 int radeon_vm_bo_update(struct radeon_device *rdev, 2946 struct radeon_bo_va *bo_va, 2947 struct ttm_mem_reg *mem); 2948 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2949 struct radeon_bo *bo); 2950 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2951 struct radeon_bo *bo); 2952 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2953 struct radeon_vm *vm, 2954 struct radeon_bo *bo); 2955 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2956 struct radeon_bo_va *bo_va, 2957 uint64_t offset, 2958 uint32_t flags); 2959 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2960 struct radeon_bo_va *bo_va); 2961 2962 /* audio */ 2963 void r600_audio_update_hdmi(struct work_struct *work); 2964 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2965 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2966 void r600_audio_enable(struct radeon_device *rdev, 2967 struct r600_audio_pin *pin, 2968 u8 enable_mask); 2969 void dce6_audio_enable(struct radeon_device *rdev, 2970 struct r600_audio_pin *pin, 2971 u8 enable_mask); 2972 2973 /* 2974 * R600 vram scratch functions 2975 */ 2976 int r600_vram_scratch_init(struct radeon_device *rdev); 2977 void r600_vram_scratch_fini(struct radeon_device *rdev); 2978 2979 /* 2980 * r600 cs checking helper 2981 */ 2982 unsigned r600_mip_minify(unsigned size, unsigned level); 2983 bool r600_fmt_is_valid_color(u32 format); 2984 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2985 int r600_fmt_get_blocksize(u32 format); 2986 int r600_fmt_get_nblocksx(u32 format, u32 w); 2987 int r600_fmt_get_nblocksy(u32 format, u32 h); 2988 2989 /* 2990 * r600 functions used by radeon_encoder.c 2991 */ 2992 struct radeon_hdmi_acr { 2993 u32 clock; 2994 2995 int n_32khz; 2996 int cts_32khz; 2997 2998 int n_44_1khz; 2999 int cts_44_1khz; 3000 3001 int n_48khz; 3002 int cts_48khz; 3003 3004 }; 3005 3006 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3007 3008 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3009 u32 tiling_pipe_num, 3010 u32 max_rb_num, 3011 u32 total_max_rb_num, 3012 u32 enabled_rb_mask); 3013 3014 /* 3015 * evergreen functions used by radeon_encoder.c 3016 */ 3017 3018 extern int ni_init_microcode(struct radeon_device *rdev); 3019 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3020 3021 /* radeon_acpi.c */ 3022 #if defined(CONFIG_ACPI) 3023 extern int radeon_acpi_init(struct radeon_device *rdev); 3024 extern void radeon_acpi_fini(struct radeon_device *rdev); 3025 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3026 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3027 u8 perf_req, bool advertise); 3028 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3029 #else 3030 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3031 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3032 #endif 3033 3034 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3035 struct radeon_cs_packet *pkt, 3036 unsigned idx); 3037 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3038 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3039 struct radeon_cs_packet *pkt); 3040 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3041 struct radeon_bo_list **cs_reloc, 3042 int nomm); 3043 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3044 uint32_t *vline_start_end, 3045 uint32_t *vline_status); 3046 3047 #include "radeon_object.h" 3048 3049 #endif 3050
Indexes created Mon Oct 27 08:10:08 GMT 2025