radeon_bios.c revision 1.1.1.2
1 /* $NetBSD: radeon_bios.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "atom.h" 37 38 #include <linux/slab.h> 39 #include <linux/acpi.h> 40 /* 41 * BIOS. 42 */ 43 44 /* If you boot an IGP board with a discrete card as the primary, 45 * the IGP rom is not accessible via the rom bar as the IGP rom is 46 * part of the system bios. On boot, the system bios puts a 47 * copy of the igp rom at the start of vram if a discrete card is 48 * present. 49 */ 50 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 51 { 52 uint8_t __iomem *bios; 53 resource_size_t vram_base; 54 resource_size_t size = 256 * 1024; /* ??? */ 55 56 if (!(rdev->flags & RADEON_IS_IGP)) 57 if (!radeon_card_posted(rdev)) 58 return false; 59 60 rdev->bios = NULL; 61 vram_base = pci_resource_start(rdev->pdev, 0); 62 bios = ioremap(vram_base, size); 63 if (!bios) { 64 return false; 65 } 66 67 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 68 iounmap(bios); 69 return false; 70 } 71 rdev->bios = kmalloc(size, GFP_KERNEL); 72 if (rdev->bios == NULL) { 73 iounmap(bios); 74 return false; 75 } 76 memcpy_fromio(rdev->bios, bios, size); 77 iounmap(bios); 78 return true; 79 } 80 81 static bool radeon_read_bios(struct radeon_device *rdev) 82 { 83 uint8_t __iomem *bios, val1, val2; 84 size_t size; 85 86 rdev->bios = NULL; 87 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 88 bios = pci_map_rom(rdev->pdev, &size); 89 if (!bios) { 90 return false; 91 } 92 93 val1 = readb(&bios[0]); 94 val2 = readb(&bios[1]); 95 96 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 97 pci_unmap_rom(rdev->pdev, bios); 98 return false; 99 } 100 rdev->bios = kzalloc(size, GFP_KERNEL); 101 if (rdev->bios == NULL) { 102 pci_unmap_rom(rdev->pdev, bios); 103 return false; 104 } 105 memcpy_fromio(rdev->bios, bios, size); 106 pci_unmap_rom(rdev->pdev, bios); 107 return true; 108 } 109 110 static bool radeon_read_platform_bios(struct radeon_device *rdev) 111 { 112 uint8_t __iomem *bios; 113 size_t size; 114 115 rdev->bios = NULL; 116 117 bios = pci_platform_rom(rdev->pdev, &size); 118 if (!bios) { 119 return false; 120 } 121 122 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 123 return false; 124 } 125 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 126 if (rdev->bios == NULL) { 127 return false; 128 } 129 130 return true; 131 } 132 133 #ifdef CONFIG_ACPI 134 /* ATRM is used to get the BIOS on the discrete cards in 135 * dual-gpu systems. 136 */ 137 /* retrieve the ROM in 4k blocks */ 138 #define ATRM_BIOS_PAGE 4096 139 /** 140 * radeon_atrm_call - fetch a chunk of the vbios 141 * 142 * @atrm_handle: acpi ATRM handle 143 * @bios: vbios image pointer 144 * @offset: offset of vbios image data to fetch 145 * @len: length of vbios image data to fetch 146 * 147 * Executes ATRM to fetch a chunk of the discrete 148 * vbios image on PX systems (all asics). 149 * Returns the length of the buffer fetched. 150 */ 151 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 152 int offset, int len) 153 { 154 acpi_status status; 155 union acpi_object atrm_arg_elements[2], *obj; 156 struct acpi_object_list atrm_arg; 157 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 158 159 atrm_arg.count = 2; 160 atrm_arg.pointer = &atrm_arg_elements[0]; 161 162 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 163 atrm_arg_elements[0].integer.value = offset; 164 165 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 166 atrm_arg_elements[1].integer.value = len; 167 168 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 169 if (ACPI_FAILURE(status)) { 170 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 171 return -ENODEV; 172 } 173 174 obj = (union acpi_object *)buffer.pointer; 175 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 176 len = obj->buffer.length; 177 kfree(buffer.pointer); 178 return len; 179 } 180 181 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 182 { 183 int ret; 184 int size = 256 * 1024; 185 int i; 186 struct pci_dev *pdev = NULL; 187 acpi_handle dhandle, atrm_handle; 188 acpi_status status; 189 bool found = false; 190 191 /* ATRM is for the discrete card only */ 192 if (rdev->flags & RADEON_IS_IGP) 193 return false; 194 195 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 196 dhandle = ACPI_HANDLE(&pdev->dev); 197 if (!dhandle) 198 continue; 199 200 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 201 if (!ACPI_FAILURE(status)) { 202 found = true; 203 break; 204 } 205 } 206 207 if (!found) { 208 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 209 dhandle = ACPI_HANDLE(&pdev->dev); 210 if (!dhandle) 211 continue; 212 213 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 214 if (!ACPI_FAILURE(status)) { 215 found = true; 216 break; 217 } 218 } 219 } 220 221 if (!found) 222 return false; 223 224 rdev->bios = kmalloc(size, GFP_KERNEL); 225 if (!rdev->bios) { 226 DRM_ERROR("Unable to allocate bios\n"); 227 return false; 228 } 229 230 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 231 ret = radeon_atrm_call(atrm_handle, 232 rdev->bios, 233 (i * ATRM_BIOS_PAGE), 234 ATRM_BIOS_PAGE); 235 if (ret < ATRM_BIOS_PAGE) 236 break; 237 } 238 239 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 240 kfree(rdev->bios); 241 return false; 242 } 243 return true; 244 } 245 #else 246 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 247 { 248 return false; 249 } 250 #endif 251 252 static bool ni_read_disabled_bios(struct radeon_device *rdev) 253 { 254 u32 bus_cntl; 255 u32 d1vga_control; 256 u32 d2vga_control; 257 u32 vga_render_control; 258 u32 rom_cntl; 259 bool r; 260 261 bus_cntl = RREG32(R600_BUS_CNTL); 262 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 263 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 264 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 265 rom_cntl = RREG32(R600_ROM_CNTL); 266 267 /* enable the rom */ 268 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 269 if (!ASIC_IS_NODCE(rdev)) { 270 /* Disable VGA mode */ 271 WREG32(AVIVO_D1VGA_CONTROL, 272 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 273 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 274 WREG32(AVIVO_D2VGA_CONTROL, 275 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 276 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 277 WREG32(AVIVO_VGA_RENDER_CONTROL, 278 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 279 } 280 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 281 282 r = radeon_read_bios(rdev); 283 284 /* restore regs */ 285 WREG32(R600_BUS_CNTL, bus_cntl); 286 if (!ASIC_IS_NODCE(rdev)) { 287 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 288 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 289 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 290 } 291 WREG32(R600_ROM_CNTL, rom_cntl); 292 return r; 293 } 294 295 static bool r700_read_disabled_bios(struct radeon_device *rdev) 296 { 297 uint32_t viph_control; 298 uint32_t bus_cntl; 299 uint32_t d1vga_control; 300 uint32_t d2vga_control; 301 uint32_t vga_render_control; 302 uint32_t rom_cntl; 303 uint32_t cg_spll_func_cntl = 0; 304 uint32_t cg_spll_status; 305 bool r; 306 307 viph_control = RREG32(RADEON_VIPH_CONTROL); 308 bus_cntl = RREG32(R600_BUS_CNTL); 309 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 310 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 311 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 312 rom_cntl = RREG32(R600_ROM_CNTL); 313 314 /* disable VIP */ 315 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 316 /* enable the rom */ 317 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 318 /* Disable VGA mode */ 319 WREG32(AVIVO_D1VGA_CONTROL, 320 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 321 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 322 WREG32(AVIVO_D2VGA_CONTROL, 323 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 324 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 325 WREG32(AVIVO_VGA_RENDER_CONTROL, 326 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 327 328 if (rdev->family == CHIP_RV730) { 329 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 330 331 /* enable bypass mode */ 332 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 333 R600_SPLL_BYPASS_EN)); 334 335 /* wait for SPLL_CHG_STATUS to change to 1 */ 336 cg_spll_status = 0; 337 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 338 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 339 340 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 341 } else 342 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 343 344 r = radeon_read_bios(rdev); 345 346 /* restore regs */ 347 if (rdev->family == CHIP_RV730) { 348 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 349 350 /* wait for SPLL_CHG_STATUS to change to 1 */ 351 cg_spll_status = 0; 352 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 353 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 354 } 355 WREG32(RADEON_VIPH_CONTROL, viph_control); 356 WREG32(R600_BUS_CNTL, bus_cntl); 357 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 358 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 359 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 360 WREG32(R600_ROM_CNTL, rom_cntl); 361 return r; 362 } 363 364 static bool r600_read_disabled_bios(struct radeon_device *rdev) 365 { 366 uint32_t viph_control; 367 uint32_t bus_cntl; 368 uint32_t d1vga_control; 369 uint32_t d2vga_control; 370 uint32_t vga_render_control; 371 uint32_t rom_cntl; 372 uint32_t general_pwrmgt; 373 uint32_t low_vid_lower_gpio_cntl; 374 uint32_t medium_vid_lower_gpio_cntl; 375 uint32_t high_vid_lower_gpio_cntl; 376 uint32_t ctxsw_vid_lower_gpio_cntl; 377 uint32_t lower_gpio_enable; 378 bool r; 379 380 viph_control = RREG32(RADEON_VIPH_CONTROL); 381 bus_cntl = RREG32(R600_BUS_CNTL); 382 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 383 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 384 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 385 rom_cntl = RREG32(R600_ROM_CNTL); 386 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 387 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 388 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 389 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 390 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 391 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 392 393 /* disable VIP */ 394 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 395 /* enable the rom */ 396 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 397 /* Disable VGA mode */ 398 WREG32(AVIVO_D1VGA_CONTROL, 399 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 400 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 401 WREG32(AVIVO_D2VGA_CONTROL, 402 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 403 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 404 WREG32(AVIVO_VGA_RENDER_CONTROL, 405 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 406 407 WREG32(R600_ROM_CNTL, 408 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 409 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 410 R600_SCK_OVERWRITE)); 411 412 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 413 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 414 (low_vid_lower_gpio_cntl & ~0x400)); 415 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 416 (medium_vid_lower_gpio_cntl & ~0x400)); 417 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 418 (high_vid_lower_gpio_cntl & ~0x400)); 419 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 420 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 421 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 422 423 r = radeon_read_bios(rdev); 424 425 /* restore regs */ 426 WREG32(RADEON_VIPH_CONTROL, viph_control); 427 WREG32(R600_BUS_CNTL, bus_cntl); 428 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 429 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 430 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 431 WREG32(R600_ROM_CNTL, rom_cntl); 432 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 433 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 434 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 435 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 436 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 437 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 438 return r; 439 } 440 441 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 442 { 443 uint32_t seprom_cntl1; 444 uint32_t viph_control; 445 uint32_t bus_cntl; 446 uint32_t d1vga_control; 447 uint32_t d2vga_control; 448 uint32_t vga_render_control; 449 uint32_t gpiopad_a; 450 uint32_t gpiopad_en; 451 uint32_t gpiopad_mask; 452 bool r; 453 454 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 455 viph_control = RREG32(RADEON_VIPH_CONTROL); 456 bus_cntl = RREG32(RV370_BUS_CNTL); 457 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 458 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 459 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 460 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 461 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 462 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 463 464 WREG32(RADEON_SEPROM_CNTL1, 465 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 466 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 467 WREG32(RADEON_GPIOPAD_A, 0); 468 WREG32(RADEON_GPIOPAD_EN, 0); 469 WREG32(RADEON_GPIOPAD_MASK, 0); 470 471 /* disable VIP */ 472 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 473 474 /* enable the rom */ 475 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 476 477 /* Disable VGA mode */ 478 WREG32(AVIVO_D1VGA_CONTROL, 479 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 480 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 481 WREG32(AVIVO_D2VGA_CONTROL, 482 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 483 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 484 WREG32(AVIVO_VGA_RENDER_CONTROL, 485 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 486 487 r = radeon_read_bios(rdev); 488 489 /* restore regs */ 490 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 491 WREG32(RADEON_VIPH_CONTROL, viph_control); 492 WREG32(RV370_BUS_CNTL, bus_cntl); 493 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 494 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 495 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 496 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 497 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 498 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 499 return r; 500 } 501 502 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 503 { 504 uint32_t seprom_cntl1; 505 uint32_t viph_control; 506 uint32_t bus_cntl; 507 uint32_t crtc_gen_cntl; 508 uint32_t crtc2_gen_cntl; 509 uint32_t crtc_ext_cntl; 510 uint32_t fp2_gen_cntl; 511 bool r; 512 513 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 514 viph_control = RREG32(RADEON_VIPH_CONTROL); 515 if (rdev->flags & RADEON_IS_PCIE) 516 bus_cntl = RREG32(RV370_BUS_CNTL); 517 else 518 bus_cntl = RREG32(RADEON_BUS_CNTL); 519 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 520 crtc2_gen_cntl = 0; 521 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 522 fp2_gen_cntl = 0; 523 524 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 525 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 526 } 527 528 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 529 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 530 } 531 532 WREG32(RADEON_SEPROM_CNTL1, 533 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 534 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 535 536 /* disable VIP */ 537 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 538 539 /* enable the rom */ 540 if (rdev->flags & RADEON_IS_PCIE) 541 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 542 else 543 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 544 545 /* Turn off mem requests and CRTC for both controllers */ 546 WREG32(RADEON_CRTC_GEN_CNTL, 547 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 548 (RADEON_CRTC_DISP_REQ_EN_B | 549 RADEON_CRTC_EXT_DISP_EN))); 550 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 551 WREG32(RADEON_CRTC2_GEN_CNTL, 552 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 553 RADEON_CRTC2_DISP_REQ_EN_B)); 554 } 555 /* Turn off CRTC */ 556 WREG32(RADEON_CRTC_EXT_CNTL, 557 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 558 (RADEON_CRTC_SYNC_TRISTAT | 559 RADEON_CRTC_DISPLAY_DIS))); 560 561 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 562 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 563 } 564 565 r = radeon_read_bios(rdev); 566 567 /* restore regs */ 568 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 569 WREG32(RADEON_VIPH_CONTROL, viph_control); 570 if (rdev->flags & RADEON_IS_PCIE) 571 WREG32(RV370_BUS_CNTL, bus_cntl); 572 else 573 WREG32(RADEON_BUS_CNTL, bus_cntl); 574 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 575 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 576 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 577 } 578 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 579 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 580 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 581 } 582 return r; 583 } 584 585 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 586 { 587 if (rdev->flags & RADEON_IS_IGP) 588 return igp_read_bios_from_vram(rdev); 589 else if (rdev->family >= CHIP_BARTS) 590 return ni_read_disabled_bios(rdev); 591 else if (rdev->family >= CHIP_RV770) 592 return r700_read_disabled_bios(rdev); 593 else if (rdev->family >= CHIP_R600) 594 return r600_read_disabled_bios(rdev); 595 else if (rdev->family >= CHIP_RS600) 596 return avivo_read_disabled_bios(rdev); 597 else 598 return legacy_read_disabled_bios(rdev); 599 } 600 601 #ifdef CONFIG_ACPI 602 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 603 { 604 bool ret = false; 605 struct acpi_table_header *hdr; 606 acpi_size tbl_size; 607 UEFI_ACPI_VFCT *vfct; 608 GOP_VBIOS_CONTENT *vbios; 609 VFCT_IMAGE_HEADER *vhdr; 610 611 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 612 return false; 613 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 614 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 615 goto out_unmap; 616 } 617 618 vfct = (UEFI_ACPI_VFCT *)hdr; 619 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 620 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 621 goto out_unmap; 622 } 623 624 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 625 vhdr = &vbios->VbiosHeader; 626 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 627 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 628 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 629 630 if (vhdr->PCIBus != rdev->pdev->bus->number || 631 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 632 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 633 vhdr->VendorID != rdev->pdev->vendor || 634 vhdr->DeviceID != rdev->pdev->device) { 635 DRM_INFO("ACPI VFCT table is not for this card\n"); 636 goto out_unmap; 637 } 638 639 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 640 DRM_ERROR("ACPI VFCT image truncated\n"); 641 goto out_unmap; 642 } 643 644 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 645 ret = !!rdev->bios; 646 647 out_unmap: 648 return ret; 649 } 650 #else 651 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 652 { 653 return false; 654 } 655 #endif 656 657 bool radeon_get_bios(struct radeon_device *rdev) 658 { 659 bool r; 660 uint16_t tmp; 661 662 r = radeon_atrm_get_bios(rdev); 663 if (r == false) 664 r = radeon_acpi_vfct_bios(rdev); 665 if (r == false) 666 r = igp_read_bios_from_vram(rdev); 667 if (r == false) 668 r = radeon_read_bios(rdev); 669 if (r == false) 670 r = radeon_read_disabled_bios(rdev); 671 if (r == false) 672 r = radeon_read_platform_bios(rdev); 673 if (r == false || rdev->bios == NULL) { 674 DRM_ERROR("Unable to locate a BIOS ROM\n"); 675 rdev->bios = NULL; 676 return false; 677 } 678 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 679 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 680 goto free_bios; 681 } 682 683 tmp = RBIOS16(0x18); 684 if (RBIOS8(tmp + 0x14) != 0x0) { 685 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 686 goto free_bios; 687 } 688 689 rdev->bios_header_start = RBIOS16(0x48); 690 if (!rdev->bios_header_start) { 691 goto free_bios; 692 } 693 tmp = rdev->bios_header_start + 4; 694 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 695 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 696 rdev->is_atom_bios = true; 697 } else { 698 rdev->is_atom_bios = false; 699 } 700 701 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 702 return true; 703 free_bios: 704 kfree(rdev->bios); 705 rdev->bios = NULL; 706 return false; 707 } 708
Indexes created Sun Oct 26 17:10:13 GMT 2025