radeon_bios.c revision 1.1.1.3
1 /* $NetBSD: radeon_bios.c,v 1.1.1.3 2021/12/18 20:15:46 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.1.1.3 2021/12/18 20:15:46 riastradh Exp $"); 33 34 #include <linux/acpi.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_device.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_reg.h" 43 44 /* 45 * BIOS. 46 */ 47 48 /* If you boot an IGP board with a discrete card as the primary, 49 * the IGP rom is not accessible via the rom bar as the IGP rom is 50 * part of the system bios. On boot, the system bios puts a 51 * copy of the igp rom at the start of vram if a discrete card is 52 * present. 53 */ 54 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 55 { 56 uint8_t __iomem *bios; 57 resource_size_t vram_base; 58 resource_size_t size = 256 * 1024; /* ??? */ 59 60 if (!(rdev->flags & RADEON_IS_IGP)) 61 if (!radeon_card_posted(rdev)) 62 return false; 63 64 rdev->bios = NULL; 65 vram_base = pci_resource_start(rdev->pdev, 0); 66 bios = ioremap(vram_base, size); 67 if (!bios) { 68 return false; 69 } 70 71 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 72 iounmap(bios); 73 return false; 74 } 75 rdev->bios = kmalloc(size, GFP_KERNEL); 76 if (rdev->bios == NULL) { 77 iounmap(bios); 78 return false; 79 } 80 memcpy_fromio(rdev->bios, bios, size); 81 iounmap(bios); 82 return true; 83 } 84 85 static bool radeon_read_bios(struct radeon_device *rdev) 86 { 87 uint8_t __iomem *bios, val1, val2; 88 size_t size; 89 90 rdev->bios = NULL; 91 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 92 bios = pci_map_rom(rdev->pdev, &size); 93 if (!bios) { 94 return false; 95 } 96 97 val1 = readb(&bios[0]); 98 val2 = readb(&bios[1]); 99 100 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 101 pci_unmap_rom(rdev->pdev, bios); 102 return false; 103 } 104 rdev->bios = kzalloc(size, GFP_KERNEL); 105 if (rdev->bios == NULL) { 106 pci_unmap_rom(rdev->pdev, bios); 107 return false; 108 } 109 memcpy_fromio(rdev->bios, bios, size); 110 pci_unmap_rom(rdev->pdev, bios); 111 return true; 112 } 113 114 static bool radeon_read_platform_bios(struct radeon_device *rdev) 115 { 116 uint8_t __iomem *bios; 117 size_t size; 118 119 rdev->bios = NULL; 120 121 bios = pci_platform_rom(rdev->pdev, &size); 122 if (!bios) { 123 return false; 124 } 125 126 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 127 return false; 128 } 129 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 130 if (rdev->bios == NULL) { 131 return false; 132 } 133 134 return true; 135 } 136 137 #ifdef CONFIG_ACPI 138 /* ATRM is used to get the BIOS on the discrete cards in 139 * dual-gpu systems. 140 */ 141 /* retrieve the ROM in 4k blocks */ 142 #define ATRM_BIOS_PAGE 4096 143 /** 144 * radeon_atrm_call - fetch a chunk of the vbios 145 * 146 * @atrm_handle: acpi ATRM handle 147 * @bios: vbios image pointer 148 * @offset: offset of vbios image data to fetch 149 * @len: length of vbios image data to fetch 150 * 151 * Executes ATRM to fetch a chunk of the discrete 152 * vbios image on PX systems (all asics). 153 * Returns the length of the buffer fetched. 154 */ 155 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 156 int offset, int len) 157 { 158 acpi_status status; 159 union acpi_object atrm_arg_elements[2], *obj; 160 struct acpi_object_list atrm_arg; 161 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 162 163 atrm_arg.count = 2; 164 atrm_arg.pointer = &atrm_arg_elements[0]; 165 166 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 167 atrm_arg_elements[0].integer.value = offset; 168 169 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 170 atrm_arg_elements[1].integer.value = len; 171 172 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 173 if (ACPI_FAILURE(status)) { 174 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 175 return -ENODEV; 176 } 177 178 obj = (union acpi_object *)buffer.pointer; 179 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 180 len = obj->buffer.length; 181 kfree(buffer.pointer); 182 return len; 183 } 184 185 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 186 { 187 int ret; 188 int size = 256 * 1024; 189 int i; 190 struct pci_dev *pdev = NULL; 191 acpi_handle dhandle, atrm_handle; 192 acpi_status status; 193 bool found = false; 194 195 /* ATRM is for the discrete card only */ 196 if (rdev->flags & RADEON_IS_IGP) 197 return false; 198 199 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 200 dhandle = ACPI_HANDLE(&pdev->dev); 201 if (!dhandle) 202 continue; 203 204 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 205 if (!ACPI_FAILURE(status)) { 206 found = true; 207 break; 208 } 209 } 210 211 if (!found) { 212 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 213 dhandle = ACPI_HANDLE(&pdev->dev); 214 if (!dhandle) 215 continue; 216 217 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 218 if (!ACPI_FAILURE(status)) { 219 found = true; 220 break; 221 } 222 } 223 } 224 225 if (!found) 226 return false; 227 228 rdev->bios = kmalloc(size, GFP_KERNEL); 229 if (!rdev->bios) { 230 DRM_ERROR("Unable to allocate bios\n"); 231 return false; 232 } 233 234 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 235 ret = radeon_atrm_call(atrm_handle, 236 rdev->bios, 237 (i * ATRM_BIOS_PAGE), 238 ATRM_BIOS_PAGE); 239 if (ret < ATRM_BIOS_PAGE) 240 break; 241 } 242 243 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 244 kfree(rdev->bios); 245 return false; 246 } 247 return true; 248 } 249 #else 250 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 251 { 252 return false; 253 } 254 #endif 255 256 static bool ni_read_disabled_bios(struct radeon_device *rdev) 257 { 258 u32 bus_cntl; 259 u32 d1vga_control; 260 u32 d2vga_control; 261 u32 vga_render_control; 262 u32 rom_cntl; 263 bool r; 264 265 bus_cntl = RREG32(R600_BUS_CNTL); 266 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 267 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 268 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 269 rom_cntl = RREG32(R600_ROM_CNTL); 270 271 /* enable the rom */ 272 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 273 if (!ASIC_IS_NODCE(rdev)) { 274 /* Disable VGA mode */ 275 WREG32(AVIVO_D1VGA_CONTROL, 276 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 277 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 278 WREG32(AVIVO_D2VGA_CONTROL, 279 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 280 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 281 WREG32(AVIVO_VGA_RENDER_CONTROL, 282 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 283 } 284 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 285 286 r = radeon_read_bios(rdev); 287 288 /* restore regs */ 289 WREG32(R600_BUS_CNTL, bus_cntl); 290 if (!ASIC_IS_NODCE(rdev)) { 291 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 292 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 293 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 294 } 295 WREG32(R600_ROM_CNTL, rom_cntl); 296 return r; 297 } 298 299 static bool r700_read_disabled_bios(struct radeon_device *rdev) 300 { 301 uint32_t viph_control; 302 uint32_t bus_cntl; 303 uint32_t d1vga_control; 304 uint32_t d2vga_control; 305 uint32_t vga_render_control; 306 uint32_t rom_cntl; 307 uint32_t cg_spll_func_cntl = 0; 308 uint32_t cg_spll_status; 309 bool r; 310 311 viph_control = RREG32(RADEON_VIPH_CONTROL); 312 bus_cntl = RREG32(R600_BUS_CNTL); 313 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 314 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 315 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 316 rom_cntl = RREG32(R600_ROM_CNTL); 317 318 /* disable VIP */ 319 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 320 /* enable the rom */ 321 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 322 /* Disable VGA mode */ 323 WREG32(AVIVO_D1VGA_CONTROL, 324 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 325 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 326 WREG32(AVIVO_D2VGA_CONTROL, 327 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 328 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 329 WREG32(AVIVO_VGA_RENDER_CONTROL, 330 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 331 332 if (rdev->family == CHIP_RV730) { 333 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 334 335 /* enable bypass mode */ 336 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 337 R600_SPLL_BYPASS_EN)); 338 339 /* wait for SPLL_CHG_STATUS to change to 1 */ 340 cg_spll_status = 0; 341 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 342 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 343 344 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 345 } else 346 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 347 348 r = radeon_read_bios(rdev); 349 350 /* restore regs */ 351 if (rdev->family == CHIP_RV730) { 352 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 353 354 /* wait for SPLL_CHG_STATUS to change to 1 */ 355 cg_spll_status = 0; 356 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 357 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 358 } 359 WREG32(RADEON_VIPH_CONTROL, viph_control); 360 WREG32(R600_BUS_CNTL, bus_cntl); 361 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 362 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 363 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 364 WREG32(R600_ROM_CNTL, rom_cntl); 365 return r; 366 } 367 368 static bool r600_read_disabled_bios(struct radeon_device *rdev) 369 { 370 uint32_t viph_control; 371 uint32_t bus_cntl; 372 uint32_t d1vga_control; 373 uint32_t d2vga_control; 374 uint32_t vga_render_control; 375 uint32_t rom_cntl; 376 uint32_t general_pwrmgt; 377 uint32_t low_vid_lower_gpio_cntl; 378 uint32_t medium_vid_lower_gpio_cntl; 379 uint32_t high_vid_lower_gpio_cntl; 380 uint32_t ctxsw_vid_lower_gpio_cntl; 381 uint32_t lower_gpio_enable; 382 bool r; 383 384 viph_control = RREG32(RADEON_VIPH_CONTROL); 385 bus_cntl = RREG32(R600_BUS_CNTL); 386 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 387 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 388 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 389 rom_cntl = RREG32(R600_ROM_CNTL); 390 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 391 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 392 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 393 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 394 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 395 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 396 397 /* disable VIP */ 398 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 399 /* enable the rom */ 400 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 401 /* Disable VGA mode */ 402 WREG32(AVIVO_D1VGA_CONTROL, 403 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 404 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 405 WREG32(AVIVO_D2VGA_CONTROL, 406 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 407 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 408 WREG32(AVIVO_VGA_RENDER_CONTROL, 409 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 410 411 WREG32(R600_ROM_CNTL, 412 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 413 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 414 R600_SCK_OVERWRITE)); 415 416 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 417 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 418 (low_vid_lower_gpio_cntl & ~0x400)); 419 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 420 (medium_vid_lower_gpio_cntl & ~0x400)); 421 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 422 (high_vid_lower_gpio_cntl & ~0x400)); 423 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 424 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 425 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 426 427 r = radeon_read_bios(rdev); 428 429 /* restore regs */ 430 WREG32(RADEON_VIPH_CONTROL, viph_control); 431 WREG32(R600_BUS_CNTL, bus_cntl); 432 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 433 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 434 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 435 WREG32(R600_ROM_CNTL, rom_cntl); 436 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 437 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 438 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 439 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 440 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 441 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 442 return r; 443 } 444 445 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 446 { 447 uint32_t seprom_cntl1; 448 uint32_t viph_control; 449 uint32_t bus_cntl; 450 uint32_t d1vga_control; 451 uint32_t d2vga_control; 452 uint32_t vga_render_control; 453 uint32_t gpiopad_a; 454 uint32_t gpiopad_en; 455 uint32_t gpiopad_mask; 456 bool r; 457 458 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 459 viph_control = RREG32(RADEON_VIPH_CONTROL); 460 bus_cntl = RREG32(RV370_BUS_CNTL); 461 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 462 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 463 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 464 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 465 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 466 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 467 468 WREG32(RADEON_SEPROM_CNTL1, 469 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 470 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 471 WREG32(RADEON_GPIOPAD_A, 0); 472 WREG32(RADEON_GPIOPAD_EN, 0); 473 WREG32(RADEON_GPIOPAD_MASK, 0); 474 475 /* disable VIP */ 476 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 477 478 /* enable the rom */ 479 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 480 481 /* Disable VGA mode */ 482 WREG32(AVIVO_D1VGA_CONTROL, 483 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 484 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 485 WREG32(AVIVO_D2VGA_CONTROL, 486 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 487 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 488 WREG32(AVIVO_VGA_RENDER_CONTROL, 489 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 490 491 r = radeon_read_bios(rdev); 492 493 /* restore regs */ 494 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 495 WREG32(RADEON_VIPH_CONTROL, viph_control); 496 WREG32(RV370_BUS_CNTL, bus_cntl); 497 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 498 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 499 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 500 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 501 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 502 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 503 return r; 504 } 505 506 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 507 { 508 uint32_t seprom_cntl1; 509 uint32_t viph_control; 510 uint32_t bus_cntl; 511 uint32_t crtc_gen_cntl; 512 uint32_t crtc2_gen_cntl; 513 uint32_t crtc_ext_cntl; 514 uint32_t fp2_gen_cntl; 515 bool r; 516 517 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 518 viph_control = RREG32(RADEON_VIPH_CONTROL); 519 if (rdev->flags & RADEON_IS_PCIE) 520 bus_cntl = RREG32(RV370_BUS_CNTL); 521 else 522 bus_cntl = RREG32(RADEON_BUS_CNTL); 523 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 524 crtc2_gen_cntl = 0; 525 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 526 fp2_gen_cntl = 0; 527 528 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 529 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 530 } 531 532 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 533 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 534 } 535 536 WREG32(RADEON_SEPROM_CNTL1, 537 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 538 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 539 540 /* disable VIP */ 541 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 542 543 /* enable the rom */ 544 if (rdev->flags & RADEON_IS_PCIE) 545 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 546 else 547 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 548 549 /* Turn off mem requests and CRTC for both controllers */ 550 WREG32(RADEON_CRTC_GEN_CNTL, 551 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 552 (RADEON_CRTC_DISP_REQ_EN_B | 553 RADEON_CRTC_EXT_DISP_EN))); 554 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 555 WREG32(RADEON_CRTC2_GEN_CNTL, 556 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 557 RADEON_CRTC2_DISP_REQ_EN_B)); 558 } 559 /* Turn off CRTC */ 560 WREG32(RADEON_CRTC_EXT_CNTL, 561 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 562 (RADEON_CRTC_SYNC_TRISTAT | 563 RADEON_CRTC_DISPLAY_DIS))); 564 565 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 566 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 567 } 568 569 r = radeon_read_bios(rdev); 570 571 /* restore regs */ 572 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 573 WREG32(RADEON_VIPH_CONTROL, viph_control); 574 if (rdev->flags & RADEON_IS_PCIE) 575 WREG32(RV370_BUS_CNTL, bus_cntl); 576 else 577 WREG32(RADEON_BUS_CNTL, bus_cntl); 578 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 579 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 580 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 581 } 582 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 583 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 584 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 585 } 586 return r; 587 } 588 589 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 590 { 591 if (rdev->flags & RADEON_IS_IGP) 592 return igp_read_bios_from_vram(rdev); 593 else if (rdev->family >= CHIP_BARTS) 594 return ni_read_disabled_bios(rdev); 595 else if (rdev->family >= CHIP_RV770) 596 return r700_read_disabled_bios(rdev); 597 else if (rdev->family >= CHIP_R600) 598 return r600_read_disabled_bios(rdev); 599 else if (rdev->family >= CHIP_RS600) 600 return avivo_read_disabled_bios(rdev); 601 else 602 return legacy_read_disabled_bios(rdev); 603 } 604 605 #ifdef CONFIG_ACPI 606 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 607 { 608 struct acpi_table_header *hdr; 609 acpi_size tbl_size; 610 UEFI_ACPI_VFCT *vfct; 611 unsigned offset; 612 613 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 614 return false; 615 tbl_size = hdr->length; 616 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 617 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 618 return false; 619 } 620 621 vfct = (UEFI_ACPI_VFCT *)hdr; 622 offset = vfct->VBIOSImageOffset; 623 624 while (offset < tbl_size) { 625 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 626 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 627 628 offset += sizeof(VFCT_IMAGE_HEADER); 629 if (offset > tbl_size) { 630 DRM_ERROR("ACPI VFCT image header truncated\n"); 631 return false; 632 } 633 634 offset += vhdr->ImageLength; 635 if (offset > tbl_size) { 636 DRM_ERROR("ACPI VFCT image truncated\n"); 637 return false; 638 } 639 640 if (vhdr->ImageLength && 641 vhdr->PCIBus == rdev->pdev->bus->number && 642 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 643 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 644 vhdr->VendorID == rdev->pdev->vendor && 645 vhdr->DeviceID == rdev->pdev->device) { 646 rdev->bios = kmemdup(&vbios->VbiosContent, 647 vhdr->ImageLength, 648 GFP_KERNEL); 649 650 if (!rdev->bios) 651 return false; 652 return true; 653 } 654 } 655 656 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 657 return false; 658 } 659 #else 660 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 661 { 662 return false; 663 } 664 #endif 665 666 bool radeon_get_bios(struct radeon_device *rdev) 667 { 668 bool r; 669 uint16_t tmp; 670 671 r = radeon_atrm_get_bios(rdev); 672 if (!r) 673 r = radeon_acpi_vfct_bios(rdev); 674 if (!r) 675 r = igp_read_bios_from_vram(rdev); 676 if (!r) 677 r = radeon_read_bios(rdev); 678 if (!r) 679 r = radeon_read_disabled_bios(rdev); 680 if (!r) 681 r = radeon_read_platform_bios(rdev); 682 if (!r || rdev->bios == NULL) { 683 DRM_ERROR("Unable to locate a BIOS ROM\n"); 684 rdev->bios = NULL; 685 return false; 686 } 687 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 688 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 689 goto free_bios; 690 } 691 692 tmp = RBIOS16(0x18); 693 if (RBIOS8(tmp + 0x14) != 0x0) { 694 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 695 goto free_bios; 696 } 697 698 rdev->bios_header_start = RBIOS16(0x48); 699 if (!rdev->bios_header_start) { 700 goto free_bios; 701 } 702 tmp = rdev->bios_header_start + 4; 703 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 704 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 705 rdev->is_atom_bios = true; 706 } else { 707 rdev->is_atom_bios = false; 708 } 709 710 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 711 return true; 712 free_bios: 713 kfree(rdev->bios); 714 rdev->bios = NULL; 715 return false; 716 } 717
Indexes created Tue Oct 28 12:10:06 GMT 2025