radeon_bios.c revision 1.12
1 /* $NetBSD: radeon_bios.c,v 1.12 2022/05/28 01:07:47 manu Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.12 2022/05/28 01:07:47 manu Exp $"); 33 34 #include <linux/acpi.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_device.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_reg.h" 43 44 #if defined(__NetBSD__) && NACPICA > 0 45 #include <dev/acpi/acpireg.h> 46 #define _COMPONENT ACPI_DISPLAY_COMPONENT 47 ACPI_MODULE_NAME("radeon_acpi") 48 #include <linux/nbsd-namespace-acpi.h> 49 #endif 50 51 /* 52 * BIOS. 53 */ 54 55 /* If you boot an IGP board with a discrete card as the primary, 56 * the IGP rom is not accessible via the rom bar as the IGP rom is 57 * part of the system bios. On boot, the system bios puts a 58 * copy of the igp rom at the start of vram if a discrete card is 59 * present. 60 */ 61 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 62 { 63 #ifdef __NetBSD__ 64 bus_space_tag_t bst; 65 bus_space_handle_t bsh; 66 bus_size_t size; 67 #else 68 uint8_t __iomem *bios; 69 resource_size_t vram_base; 70 resource_size_t size = 256 * 1024; /* ??? */ 71 #endif 72 73 if (!(rdev->flags & RADEON_IS_IGP)) 74 if (!radeon_card_posted(rdev)) 75 return false; 76 77 rdev->bios = NULL; 78 #ifdef __NetBSD__ 79 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 80 /* XXX Dunno what type to expect here; fill me in... */ 81 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 82 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 83 0, &bst, &bsh, NULL, &size)) 84 return false; 85 if ((size == 0) || 86 (size < 256 * 1024) || 87 (bus_space_read_1(bst, bsh, 0) != 0x55) || 88 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 89 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 90 bus_space_unmap(bst, bsh, size); 91 return false; 92 } 93 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 94 bus_space_unmap(bst, bsh, size); 95 #else 96 vram_base = pci_resource_start(rdev->pdev, 0); 97 bios = ioremap(vram_base, size); 98 if (!bios) { 99 return false; 100 } 101 102 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 103 iounmap(bios); 104 return false; 105 } 106 rdev->bios = kmalloc(size, GFP_KERNEL); 107 if (rdev->bios == NULL) { 108 iounmap(bios); 109 return false; 110 } 111 memcpy_fromio(rdev->bios, bios, size); 112 iounmap(bios); 113 #endif 114 return true; 115 } 116 117 #ifdef __NetBSD__ 118 #define __iomem __pci_rom_iomem 119 #endif 120 121 static bool radeon_read_bios(struct radeon_device *rdev) 122 { 123 uint8_t __iomem *bios, val1, val2; 124 size_t size; 125 126 rdev->bios = NULL; 127 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 128 bios = pci_map_rom(rdev->pdev, &size); 129 if (!bios) { 130 return false; 131 } 132 133 #ifdef __NetBSD__ 134 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 135 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 136 137 val1 = bus_space_read_1(bst, bsh, 0); 138 val2 = bus_space_read_1(bst, bsh, 1); 139 #else 140 val1 = readb(&bios[0]); 141 val2 = readb(&bios[1]); 142 #endif 143 144 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 145 pci_unmap_rom(rdev->pdev, bios); 146 return false; 147 } 148 rdev->bios = kzalloc(size, GFP_KERNEL); 149 if (rdev->bios == NULL) { 150 pci_unmap_rom(rdev->pdev, bios); 151 return false; 152 } 153 #ifdef __NetBSD__ 154 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 155 #else 156 memcpy_fromio(rdev->bios, bios, size); 157 #endif 158 pci_unmap_rom(rdev->pdev, bios); 159 return true; 160 } 161 162 #ifdef __NetBSD__ 163 #undef __iomem 164 #endif 165 166 static bool radeon_read_platform_bios(struct radeon_device *rdev) 167 { 168 #ifdef __NetBSD__ /* XXX radeon platform bios */ 169 return false; 170 #else 171 uint8_t __iomem *bios; 172 size_t size; 173 174 rdev->bios = NULL; 175 176 bios = pci_platform_rom(rdev->pdev, &size); 177 if (!bios) { 178 return false; 179 } 180 181 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 182 return false; 183 } 184 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 185 if (rdev->bios == NULL) { 186 return false; 187 } 188 189 return true; 190 #endif 191 } 192 193 #ifdef CONFIG_ACPI 194 /* ATRM is used to get the BIOS on the discrete cards in 195 * dual-gpu systems. 196 */ 197 /* retrieve the ROM in 4k blocks */ 198 #define ATRM_BIOS_PAGE 4096 199 /** 200 * radeon_atrm_call - fetch a chunk of the vbios 201 * 202 * @atrm_handle: acpi ATRM handle 203 * @bios: vbios image pointer 204 * @offset: offset of vbios image data to fetch 205 * @len: length of vbios image data to fetch 206 * 207 * Executes ATRM to fetch a chunk of the discrete 208 * vbios image on PX systems (all asics). 209 * Returns the length of the buffer fetched. 210 */ 211 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 212 int offset, int len) 213 { 214 acpi_status status; 215 union acpi_object atrm_arg_elements[2], *obj; 216 struct acpi_object_list atrm_arg; 217 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 218 219 atrm_arg.count = 2; 220 atrm_arg.pointer = &atrm_arg_elements[0]; 221 222 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 223 atrm_arg_elements[0].integer.value = offset; 224 225 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 226 atrm_arg_elements[1].integer.value = len; 227 228 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 229 if (ACPI_FAILURE(status)) { 230 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 231 return -ENODEV; 232 } 233 234 obj = (union acpi_object *)buffer.pointer; 235 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 236 len = obj->buffer.length; 237 ACPI_FREE(buffer.pointer); 238 return len; 239 } 240 241 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 242 { 243 int ret; 244 int size = 256 * 1024; 245 int i; 246 struct pci_dev *pdev = NULL; 247 acpi_handle dhandle, atrm_handle; 248 acpi_status status; 249 bool found = false; 250 251 /* ATRM is for the discrete card only */ 252 if (rdev->flags & RADEON_IS_IGP) 253 return false; 254 255 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 256 #ifdef __NetBSD__ 257 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle : NULL); 258 #else 259 dhandle = ACPI_HANDLE(&pdev->dev); 260 #endif 261 if (!dhandle) 262 continue; 263 264 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 265 if (!ACPI_FAILURE(status)) { 266 found = true; 267 break; 268 } 269 } 270 271 if (!found) { 272 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 273 #ifdef __NetBSD__ 274 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle 275 : NULL); 276 #else 277 dhandle = ACPI_HANDLE(&pdev->dev); 278 #endif 279 if (!dhandle) 280 continue; 281 282 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 283 if (!ACPI_FAILURE(status)) { 284 found = true; 285 break; 286 } 287 } 288 } 289 290 if (!found) 291 return false; 292 293 rdev->bios = kmalloc(size, GFP_KERNEL); 294 if (!rdev->bios) { 295 DRM_ERROR("Unable to allocate bios\n"); 296 return false; 297 } 298 299 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 300 ret = radeon_atrm_call(atrm_handle, 301 rdev->bios, 302 (i * ATRM_BIOS_PAGE), 303 ATRM_BIOS_PAGE); 304 if (ret < ATRM_BIOS_PAGE) 305 break; 306 } 307 308 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 309 kfree(rdev->bios); 310 return false; 311 } 312 return true; 313 } 314 #else 315 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 316 { 317 return false; 318 } 319 #endif 320 321 static bool ni_read_disabled_bios(struct radeon_device *rdev) 322 { 323 u32 bus_cntl; 324 u32 d1vga_control; 325 u32 d2vga_control; 326 u32 vga_render_control; 327 u32 rom_cntl; 328 bool r; 329 330 bus_cntl = RREG32(R600_BUS_CNTL); 331 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 332 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 333 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 334 rom_cntl = RREG32(R600_ROM_CNTL); 335 336 /* enable the rom */ 337 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 338 if (!ASIC_IS_NODCE(rdev)) { 339 /* Disable VGA mode */ 340 WREG32(AVIVO_D1VGA_CONTROL, 341 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 342 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 343 WREG32(AVIVO_D2VGA_CONTROL, 344 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 345 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 346 WREG32(AVIVO_VGA_RENDER_CONTROL, 347 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 348 } 349 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 350 351 r = radeon_read_bios(rdev); 352 353 /* restore regs */ 354 WREG32(R600_BUS_CNTL, bus_cntl); 355 if (!ASIC_IS_NODCE(rdev)) { 356 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 357 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 358 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 359 } 360 WREG32(R600_ROM_CNTL, rom_cntl); 361 return r; 362 } 363 364 static bool r700_read_disabled_bios(struct radeon_device *rdev) 365 { 366 uint32_t viph_control; 367 uint32_t bus_cntl; 368 uint32_t d1vga_control; 369 uint32_t d2vga_control; 370 uint32_t vga_render_control; 371 uint32_t rom_cntl; 372 uint32_t cg_spll_func_cntl = 0; 373 uint32_t cg_spll_status; 374 bool r; 375 376 viph_control = RREG32(RADEON_VIPH_CONTROL); 377 bus_cntl = RREG32(R600_BUS_CNTL); 378 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 379 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 380 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 381 rom_cntl = RREG32(R600_ROM_CNTL); 382 383 /* disable VIP */ 384 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 385 /* enable the rom */ 386 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 387 /* Disable VGA mode */ 388 WREG32(AVIVO_D1VGA_CONTROL, 389 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 390 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 391 WREG32(AVIVO_D2VGA_CONTROL, 392 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 393 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 394 WREG32(AVIVO_VGA_RENDER_CONTROL, 395 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 396 397 if (rdev->family == CHIP_RV730) { 398 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 399 400 /* enable bypass mode */ 401 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 402 R600_SPLL_BYPASS_EN)); 403 404 /* wait for SPLL_CHG_STATUS to change to 1 */ 405 cg_spll_status = 0; 406 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 407 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 408 409 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 410 } else 411 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 412 413 r = radeon_read_bios(rdev); 414 415 /* restore regs */ 416 if (rdev->family == CHIP_RV730) { 417 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 418 419 /* wait for SPLL_CHG_STATUS to change to 1 */ 420 cg_spll_status = 0; 421 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 422 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 423 } 424 WREG32(RADEON_VIPH_CONTROL, viph_control); 425 WREG32(R600_BUS_CNTL, bus_cntl); 426 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 427 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 428 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 429 WREG32(R600_ROM_CNTL, rom_cntl); 430 return r; 431 } 432 433 static bool r600_read_disabled_bios(struct radeon_device *rdev) 434 { 435 uint32_t viph_control; 436 uint32_t bus_cntl; 437 uint32_t d1vga_control; 438 uint32_t d2vga_control; 439 uint32_t vga_render_control; 440 uint32_t rom_cntl; 441 uint32_t general_pwrmgt; 442 uint32_t low_vid_lower_gpio_cntl; 443 uint32_t medium_vid_lower_gpio_cntl; 444 uint32_t high_vid_lower_gpio_cntl; 445 uint32_t ctxsw_vid_lower_gpio_cntl; 446 uint32_t lower_gpio_enable; 447 bool r; 448 449 viph_control = RREG32(RADEON_VIPH_CONTROL); 450 bus_cntl = RREG32(R600_BUS_CNTL); 451 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 452 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 453 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 454 rom_cntl = RREG32(R600_ROM_CNTL); 455 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 456 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 457 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 458 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 459 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 460 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 461 462 /* disable VIP */ 463 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 464 /* enable the rom */ 465 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 466 /* Disable VGA mode */ 467 WREG32(AVIVO_D1VGA_CONTROL, 468 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 469 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 470 WREG32(AVIVO_D2VGA_CONTROL, 471 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 472 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 473 WREG32(AVIVO_VGA_RENDER_CONTROL, 474 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 475 476 WREG32(R600_ROM_CNTL, 477 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 478 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 479 R600_SCK_OVERWRITE)); 480 481 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 482 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 483 (low_vid_lower_gpio_cntl & ~0x400)); 484 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 485 (medium_vid_lower_gpio_cntl & ~0x400)); 486 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 487 (high_vid_lower_gpio_cntl & ~0x400)); 488 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 489 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 490 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 491 492 r = radeon_read_bios(rdev); 493 494 /* restore regs */ 495 WREG32(RADEON_VIPH_CONTROL, viph_control); 496 WREG32(R600_BUS_CNTL, bus_cntl); 497 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 498 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 499 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 500 WREG32(R600_ROM_CNTL, rom_cntl); 501 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 502 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 503 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 504 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 505 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 506 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 507 return r; 508 } 509 510 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 511 { 512 uint32_t seprom_cntl1; 513 uint32_t viph_control; 514 uint32_t bus_cntl; 515 uint32_t d1vga_control; 516 uint32_t d2vga_control; 517 uint32_t vga_render_control; 518 uint32_t gpiopad_a; 519 uint32_t gpiopad_en; 520 uint32_t gpiopad_mask; 521 bool r; 522 523 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 524 viph_control = RREG32(RADEON_VIPH_CONTROL); 525 bus_cntl = RREG32(RV370_BUS_CNTL); 526 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 527 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 528 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 529 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 530 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 531 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 532 533 WREG32(RADEON_SEPROM_CNTL1, 534 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 535 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 536 WREG32(RADEON_GPIOPAD_A, 0); 537 WREG32(RADEON_GPIOPAD_EN, 0); 538 WREG32(RADEON_GPIOPAD_MASK, 0); 539 540 /* disable VIP */ 541 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 542 543 /* enable the rom */ 544 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 545 546 /* Disable VGA mode */ 547 WREG32(AVIVO_D1VGA_CONTROL, 548 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 549 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 550 WREG32(AVIVO_D2VGA_CONTROL, 551 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 552 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 553 WREG32(AVIVO_VGA_RENDER_CONTROL, 554 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 555 556 r = radeon_read_bios(rdev); 557 558 /* restore regs */ 559 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 560 WREG32(RADEON_VIPH_CONTROL, viph_control); 561 WREG32(RV370_BUS_CNTL, bus_cntl); 562 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 563 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 564 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 565 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 566 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 567 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 568 return r; 569 } 570 571 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 572 { 573 uint32_t seprom_cntl1; 574 uint32_t viph_control; 575 uint32_t bus_cntl; 576 uint32_t crtc_gen_cntl; 577 uint32_t crtc2_gen_cntl; 578 uint32_t crtc_ext_cntl; 579 uint32_t fp2_gen_cntl; 580 bool r; 581 582 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 583 viph_control = RREG32(RADEON_VIPH_CONTROL); 584 if (rdev->flags & RADEON_IS_PCIE) 585 bus_cntl = RREG32(RV370_BUS_CNTL); 586 else 587 bus_cntl = RREG32(RADEON_BUS_CNTL); 588 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 589 crtc2_gen_cntl = 0; 590 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 591 fp2_gen_cntl = 0; 592 593 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 594 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 595 } 596 597 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 598 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 599 } 600 601 WREG32(RADEON_SEPROM_CNTL1, 602 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 603 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 604 605 /* disable VIP */ 606 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 607 608 /* enable the rom */ 609 if (rdev->flags & RADEON_IS_PCIE) 610 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 611 else 612 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 613 614 /* Turn off mem requests and CRTC for both controllers */ 615 WREG32(RADEON_CRTC_GEN_CNTL, 616 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 617 (RADEON_CRTC_DISP_REQ_EN_B | 618 RADEON_CRTC_EXT_DISP_EN))); 619 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 620 WREG32(RADEON_CRTC2_GEN_CNTL, 621 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 622 RADEON_CRTC2_DISP_REQ_EN_B)); 623 } 624 /* Turn off CRTC */ 625 WREG32(RADEON_CRTC_EXT_CNTL, 626 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 627 (RADEON_CRTC_SYNC_TRISTAT | 628 RADEON_CRTC_DISPLAY_DIS))); 629 630 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 631 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 632 } 633 634 r = radeon_read_bios(rdev); 635 636 /* restore regs */ 637 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 638 WREG32(RADEON_VIPH_CONTROL, viph_control); 639 if (rdev->flags & RADEON_IS_PCIE) 640 WREG32(RV370_BUS_CNTL, bus_cntl); 641 else 642 WREG32(RADEON_BUS_CNTL, bus_cntl); 643 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 644 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 645 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 646 } 647 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 648 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 649 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 650 } 651 return r; 652 } 653 654 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 655 { 656 if (rdev->flags & RADEON_IS_IGP) 657 return igp_read_bios_from_vram(rdev); 658 else if (rdev->family >= CHIP_BARTS) 659 return ni_read_disabled_bios(rdev); 660 else if (rdev->family >= CHIP_RV770) 661 return r700_read_disabled_bios(rdev); 662 else if (rdev->family >= CHIP_R600) 663 return r600_read_disabled_bios(rdev); 664 else if (rdev->family >= CHIP_RS600) 665 return avivo_read_disabled_bios(rdev); 666 else 667 return legacy_read_disabled_bios(rdev); 668 } 669 670 #ifdef CONFIG_ACPI 671 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 672 { 673 struct acpi_table_header *hdr; 674 acpi_size tbl_size; 675 UEFI_ACPI_VFCT *vfct; 676 unsigned offset; 677 678 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 679 return false; 680 tbl_size = hdr->length; 681 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 682 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 683 return false; 684 } 685 686 vfct = (UEFI_ACPI_VFCT *)hdr; 687 offset = vfct->VBIOSImageOffset; 688 689 while (offset < tbl_size) { 690 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 691 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 692 693 offset += sizeof(VFCT_IMAGE_HEADER); 694 if (offset > tbl_size) { 695 DRM_ERROR("ACPI VFCT image header truncated\n"); 696 return false; 697 } 698 699 offset += vhdr->ImageLength; 700 if (offset > tbl_size) { 701 DRM_ERROR("ACPI VFCT image truncated\n"); 702 return false; 703 } 704 705 if (vhdr->ImageLength && 706 vhdr->PCIBus == rdev->pdev->bus->number && 707 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 708 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 709 vhdr->VendorID == rdev->pdev->vendor && 710 vhdr->DeviceID == rdev->pdev->device) { 711 rdev->bios = kmemdup(&vbios->VbiosContent, 712 vhdr->ImageLength, 713 GFP_KERNEL); 714 715 if (!rdev->bios) 716 return false; 717 return true; 718 } 719 } 720 721 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 722 return false; 723 } 724 #else 725 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 726 { 727 return false; 728 } 729 #endif 730 731 bool radeon_get_bios(struct radeon_device *rdev) 732 { 733 bool r; 734 uint16_t tmp; 735 736 r = radeon_atrm_get_bios(rdev); 737 if (!r) 738 r = radeon_acpi_vfct_bios(rdev); 739 if (!r) 740 r = igp_read_bios_from_vram(rdev); 741 if (!r) 742 r = radeon_read_bios(rdev); 743 if (!r) 744 r = radeon_read_disabled_bios(rdev); 745 if (!r) 746 r = radeon_read_platform_bios(rdev); 747 if (!r || rdev->bios == NULL) { 748 DRM_ERROR("Unable to locate a BIOS ROM\n"); 749 rdev->bios = NULL; 750 return false; 751 } 752 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 753 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 754 goto free_bios; 755 } 756 757 tmp = RBIOS16(0x18); 758 if (RBIOS8(tmp + 0x14) != 0x0) { 759 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 760 goto free_bios; 761 } 762 763 rdev->bios_header_start = RBIOS16(0x48); 764 if (!rdev->bios_header_start) { 765 goto free_bios; 766 } 767 tmp = rdev->bios_header_start + 4; 768 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 769 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 770 rdev->is_atom_bios = true; 771 } else { 772 rdev->is_atom_bios = false; 773 } 774 775 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 776 return true; 777 free_bios: 778 kfree(rdev->bios); 779 rdev->bios = NULL; 780 return false; 781 } 782
Indexes created Mon Oct 27 08:10:08 GMT 2025