radeon_bios.c revision 1.12.4.1
1 /* $NetBSD: radeon_bios.c,v 1.12.4.1 2024/10/04 11:40:48 martin Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.12.4.1 2024/10/04 11:40:48 martin Exp $"); 33 34 #include <linux/acpi.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_device.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_reg.h" 43 44 #if defined(__NetBSD__) && defined(CONFIG_ACPI) 45 #include <dev/acpi/acpireg.h> 46 #define _COMPONENT ACPI_DISPLAY_COMPONENT 47 ACPI_MODULE_NAME("radeon_acpi") 48 #include <linux/nbsd-namespace-acpi.h> 49 #endif 50 51 /* 52 * BIOS. 53 */ 54 55 /* If you boot an IGP board with a discrete card as the primary, 56 * the IGP rom is not accessible via the rom bar as the IGP rom is 57 * part of the system bios. On boot, the system bios puts a 58 * copy of the igp rom at the start of vram if a discrete card is 59 * present. 60 */ 61 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 62 { 63 #ifdef __NetBSD__ 64 bus_space_tag_t bst; 65 bus_space_handle_t bsh; 66 bus_size_t size; 67 #else 68 uint8_t __iomem *bios; 69 resource_size_t vram_base; 70 resource_size_t size = 256 * 1024; /* ??? */ 71 #endif 72 73 if (!(rdev->flags & RADEON_IS_IGP)) 74 if (!radeon_card_posted(rdev)) 75 return false; 76 77 rdev->bios = NULL; 78 #ifdef __NetBSD__ 79 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 80 /* XXX Dunno what type to expect here; fill me in... */ 81 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 82 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 83 0, &bst, &bsh, NULL, &size)) 84 return false; 85 if ((size == 0) || 86 (size < 256 * 1024) || 87 (bus_space_read_1(bst, bsh, 0) != 0x55) || 88 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 89 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 90 bus_space_unmap(bst, bsh, size); 91 return false; 92 } 93 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 94 bus_space_unmap(bst, bsh, size); 95 #else 96 vram_base = pci_resource_start(rdev->pdev, 0); 97 bios = ioremap(vram_base, size); 98 if (!bios) { 99 return false; 100 } 101 102 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 103 iounmap(bios); 104 return false; 105 } 106 rdev->bios = kmalloc(size, GFP_KERNEL); 107 if (rdev->bios == NULL) { 108 iounmap(bios); 109 return false; 110 } 111 memcpy_fromio(rdev->bios, bios, size); 112 iounmap(bios); 113 #endif 114 return true; 115 } 116 117 #ifdef __NetBSD__ 118 #define __iomem __pci_rom_iomem 119 #endif 120 121 static bool radeon_read_bios(struct radeon_device *rdev) 122 { 123 uint8_t __iomem *bios, val1, val2; 124 size_t size; 125 126 rdev->bios = NULL; 127 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 128 bios = pci_map_rom(rdev->pdev, &size); 129 if (!bios) { 130 return false; 131 } 132 133 #ifdef __NetBSD__ 134 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 135 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 136 137 val1 = bus_space_read_1(bst, bsh, 0); 138 val2 = bus_space_read_1(bst, bsh, 1); 139 #else 140 val1 = readb(&bios[0]); 141 val2 = readb(&bios[1]); 142 #endif 143 144 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 145 pci_unmap_rom(rdev->pdev, bios); 146 return false; 147 } 148 rdev->bios = kzalloc(size, GFP_KERNEL); 149 if (rdev->bios == NULL) { 150 pci_unmap_rom(rdev->pdev, bios); 151 return false; 152 } 153 #ifdef __NetBSD__ 154 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 155 #else 156 memcpy_fromio(rdev->bios, bios, size); 157 #endif 158 pci_unmap_rom(rdev->pdev, bios); 159 return true; 160 } 161 162 #ifdef __NetBSD__ 163 #undef __iomem 164 #endif 165 166 static bool radeon_read_platform_bios(struct radeon_device *rdev) 167 { 168 #ifdef __NetBSD__ /* XXX radeon platform bios */ 169 return false; 170 #else 171 uint8_t __iomem *bios; 172 size_t size; 173 174 rdev->bios = NULL; 175 176 bios = pci_platform_rom(rdev->pdev, &size); 177 if (!bios) { 178 return false; 179 } 180 181 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 182 return false; 183 } 184 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 185 if (rdev->bios == NULL) { 186 return false; 187 } 188 189 return true; 190 #endif 191 } 192 193 #ifdef CONFIG_ACPI 194 /* ATRM is used to get the BIOS on the discrete cards in 195 * dual-gpu systems. 196 */ 197 /* retrieve the ROM in 4k blocks */ 198 #define ATRM_BIOS_PAGE 4096 199 /** 200 * radeon_atrm_call - fetch a chunk of the vbios 201 * 202 * @atrm_handle: acpi ATRM handle 203 * @bios: vbios image pointer 204 * @offset: offset of vbios image data to fetch 205 * @len: length of vbios image data to fetch 206 * 207 * Executes ATRM to fetch a chunk of the discrete 208 * vbios image on PX systems (all asics). 209 * Returns the length of the buffer fetched. 210 */ 211 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 212 int offset, int len) 213 { 214 acpi_status status; 215 union acpi_object atrm_arg_elements[2], *obj; 216 struct acpi_object_list atrm_arg; 217 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 218 219 atrm_arg.count = 2; 220 atrm_arg.pointer = &atrm_arg_elements[0]; 221 222 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 223 atrm_arg_elements[0].integer.value = offset; 224 225 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 226 atrm_arg_elements[1].integer.value = len; 227 228 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 229 if (ACPI_FAILURE(status)) { 230 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 231 return -ENODEV; 232 } 233 234 obj = (union acpi_object *)buffer.pointer; 235 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 236 len = obj->buffer.length; 237 ACPI_FREE(buffer.pointer); 238 return len; 239 } 240 241 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 242 { 243 int ret; 244 int size = 256 * 1024; 245 int i; 246 struct pci_dev *pdev = NULL; 247 acpi_handle dhandle, atrm_handle; 248 acpi_status status; 249 bool found = false; 250 251 /* ATRM is for the discrete card only */ 252 if (rdev->flags & RADEON_IS_IGP) 253 return false; 254 255 #ifdef __NetBSD__ 256 pdev = rdev->pdev; 257 while (pdev != NULL) { 258 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle : NULL); 259 pdev = NULL; 260 if (rdev->pdev->class != PCI_CLASS_DISPLAY_VGA) 261 continue; 262 #else 263 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 264 dhandle = ACPI_HANDLE(&pdev->dev); 265 #endif 266 if (!dhandle) 267 continue; 268 269 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 270 if (!ACPI_FAILURE(status)) { 271 found = true; 272 break; 273 } 274 } 275 276 if (!found) { 277 #ifdef __NetBSD__ 278 pdev = rdev->pdev; 279 while (pdev != NULL) { 280 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle 281 : NULL); 282 pdev = NULL; 283 if (rdev->pdev->class != PCI_CLASS_DISPLAY_OTHER) 284 continue; 285 #else 286 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 287 dhandle = ACPI_HANDLE(&pdev->dev); 288 #endif 289 if (!dhandle) 290 continue; 291 292 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 293 if (!ACPI_FAILURE(status)) { 294 found = true; 295 break; 296 } 297 } 298 } 299 300 if (!found) 301 return false; 302 303 rdev->bios = kmalloc(size, GFP_KERNEL); 304 if (!rdev->bios) { 305 DRM_ERROR("Unable to allocate bios\n"); 306 return false; 307 } 308 309 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 310 ret = radeon_atrm_call(atrm_handle, 311 rdev->bios, 312 (i * ATRM_BIOS_PAGE), 313 ATRM_BIOS_PAGE); 314 if (ret < ATRM_BIOS_PAGE) 315 break; 316 } 317 318 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 319 kfree(rdev->bios); 320 return false; 321 } 322 return true; 323 } 324 #else 325 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 326 { 327 return false; 328 } 329 #endif 330 331 static bool ni_read_disabled_bios(struct radeon_device *rdev) 332 { 333 u32 bus_cntl; 334 u32 d1vga_control; 335 u32 d2vga_control; 336 u32 vga_render_control; 337 u32 rom_cntl; 338 bool r; 339 340 bus_cntl = RREG32(R600_BUS_CNTL); 341 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 342 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 343 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 344 rom_cntl = RREG32(R600_ROM_CNTL); 345 346 /* enable the rom */ 347 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 348 if (!ASIC_IS_NODCE(rdev)) { 349 /* Disable VGA mode */ 350 WREG32(AVIVO_D1VGA_CONTROL, 351 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 352 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 353 WREG32(AVIVO_D2VGA_CONTROL, 354 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 355 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 356 WREG32(AVIVO_VGA_RENDER_CONTROL, 357 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 358 } 359 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 360 361 r = radeon_read_bios(rdev); 362 363 /* restore regs */ 364 WREG32(R600_BUS_CNTL, bus_cntl); 365 if (!ASIC_IS_NODCE(rdev)) { 366 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 367 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 368 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 369 } 370 WREG32(R600_ROM_CNTL, rom_cntl); 371 return r; 372 } 373 374 static bool r700_read_disabled_bios(struct radeon_device *rdev) 375 { 376 uint32_t viph_control; 377 uint32_t bus_cntl; 378 uint32_t d1vga_control; 379 uint32_t d2vga_control; 380 uint32_t vga_render_control; 381 uint32_t rom_cntl; 382 uint32_t cg_spll_func_cntl = 0; 383 uint32_t cg_spll_status; 384 bool r; 385 386 viph_control = RREG32(RADEON_VIPH_CONTROL); 387 bus_cntl = RREG32(R600_BUS_CNTL); 388 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 389 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 390 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 391 rom_cntl = RREG32(R600_ROM_CNTL); 392 393 /* disable VIP */ 394 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 395 /* enable the rom */ 396 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 397 /* Disable VGA mode */ 398 WREG32(AVIVO_D1VGA_CONTROL, 399 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 400 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 401 WREG32(AVIVO_D2VGA_CONTROL, 402 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 403 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 404 WREG32(AVIVO_VGA_RENDER_CONTROL, 405 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 406 407 if (rdev->family == CHIP_RV730) { 408 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 409 410 /* enable bypass mode */ 411 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 412 R600_SPLL_BYPASS_EN)); 413 414 /* wait for SPLL_CHG_STATUS to change to 1 */ 415 cg_spll_status = 0; 416 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 417 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 418 419 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 420 } else 421 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 422 423 r = radeon_read_bios(rdev); 424 425 /* restore regs */ 426 if (rdev->family == CHIP_RV730) { 427 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 428 429 /* wait for SPLL_CHG_STATUS to change to 1 */ 430 cg_spll_status = 0; 431 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 432 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 433 } 434 WREG32(RADEON_VIPH_CONTROL, viph_control); 435 WREG32(R600_BUS_CNTL, bus_cntl); 436 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 437 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 438 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 439 WREG32(R600_ROM_CNTL, rom_cntl); 440 return r; 441 } 442 443 static bool r600_read_disabled_bios(struct radeon_device *rdev) 444 { 445 uint32_t viph_control; 446 uint32_t bus_cntl; 447 uint32_t d1vga_control; 448 uint32_t d2vga_control; 449 uint32_t vga_render_control; 450 uint32_t rom_cntl; 451 uint32_t general_pwrmgt; 452 uint32_t low_vid_lower_gpio_cntl; 453 uint32_t medium_vid_lower_gpio_cntl; 454 uint32_t high_vid_lower_gpio_cntl; 455 uint32_t ctxsw_vid_lower_gpio_cntl; 456 uint32_t lower_gpio_enable; 457 bool r; 458 459 viph_control = RREG32(RADEON_VIPH_CONTROL); 460 bus_cntl = RREG32(R600_BUS_CNTL); 461 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 462 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 463 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 464 rom_cntl = RREG32(R600_ROM_CNTL); 465 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 466 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 467 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 468 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 469 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 470 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 471 472 /* disable VIP */ 473 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 474 /* enable the rom */ 475 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 476 /* Disable VGA mode */ 477 WREG32(AVIVO_D1VGA_CONTROL, 478 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 479 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 480 WREG32(AVIVO_D2VGA_CONTROL, 481 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 482 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 483 WREG32(AVIVO_VGA_RENDER_CONTROL, 484 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 485 486 WREG32(R600_ROM_CNTL, 487 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 488 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 489 R600_SCK_OVERWRITE)); 490 491 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 492 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 493 (low_vid_lower_gpio_cntl & ~0x400)); 494 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 495 (medium_vid_lower_gpio_cntl & ~0x400)); 496 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 497 (high_vid_lower_gpio_cntl & ~0x400)); 498 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 499 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 500 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 501 502 r = radeon_read_bios(rdev); 503 504 /* restore regs */ 505 WREG32(RADEON_VIPH_CONTROL, viph_control); 506 WREG32(R600_BUS_CNTL, bus_cntl); 507 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 508 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 509 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 510 WREG32(R600_ROM_CNTL, rom_cntl); 511 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 512 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 513 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 514 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 515 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 516 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 517 return r; 518 } 519 520 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 521 { 522 uint32_t seprom_cntl1; 523 uint32_t viph_control; 524 uint32_t bus_cntl; 525 uint32_t d1vga_control; 526 uint32_t d2vga_control; 527 uint32_t vga_render_control; 528 uint32_t gpiopad_a; 529 uint32_t gpiopad_en; 530 uint32_t gpiopad_mask; 531 bool r; 532 533 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 534 viph_control = RREG32(RADEON_VIPH_CONTROL); 535 bus_cntl = RREG32(RV370_BUS_CNTL); 536 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 537 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 538 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 539 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 540 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 541 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 542 543 WREG32(RADEON_SEPROM_CNTL1, 544 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 545 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 546 WREG32(RADEON_GPIOPAD_A, 0); 547 WREG32(RADEON_GPIOPAD_EN, 0); 548 WREG32(RADEON_GPIOPAD_MASK, 0); 549 550 /* disable VIP */ 551 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 552 553 /* enable the rom */ 554 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 555 556 /* Disable VGA mode */ 557 WREG32(AVIVO_D1VGA_CONTROL, 558 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 559 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 560 WREG32(AVIVO_D2VGA_CONTROL, 561 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 562 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 563 WREG32(AVIVO_VGA_RENDER_CONTROL, 564 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 565 566 r = radeon_read_bios(rdev); 567 568 /* restore regs */ 569 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 570 WREG32(RADEON_VIPH_CONTROL, viph_control); 571 WREG32(RV370_BUS_CNTL, bus_cntl); 572 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 573 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 574 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 575 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 576 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 577 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 578 return r; 579 } 580 581 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 582 { 583 uint32_t seprom_cntl1; 584 uint32_t viph_control; 585 uint32_t bus_cntl; 586 uint32_t crtc_gen_cntl; 587 uint32_t crtc2_gen_cntl; 588 uint32_t crtc_ext_cntl; 589 uint32_t fp2_gen_cntl; 590 bool r; 591 592 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 593 viph_control = RREG32(RADEON_VIPH_CONTROL); 594 if (rdev->flags & RADEON_IS_PCIE) 595 bus_cntl = RREG32(RV370_BUS_CNTL); 596 else 597 bus_cntl = RREG32(RADEON_BUS_CNTL); 598 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 599 crtc2_gen_cntl = 0; 600 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 601 fp2_gen_cntl = 0; 602 603 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 604 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 605 } 606 607 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 608 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 609 } 610 611 WREG32(RADEON_SEPROM_CNTL1, 612 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 613 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 614 615 /* disable VIP */ 616 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 617 618 /* enable the rom */ 619 if (rdev->flags & RADEON_IS_PCIE) 620 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 621 else 622 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 623 624 /* Turn off mem requests and CRTC for both controllers */ 625 WREG32(RADEON_CRTC_GEN_CNTL, 626 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 627 (RADEON_CRTC_DISP_REQ_EN_B | 628 RADEON_CRTC_EXT_DISP_EN))); 629 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 630 WREG32(RADEON_CRTC2_GEN_CNTL, 631 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 632 RADEON_CRTC2_DISP_REQ_EN_B)); 633 } 634 /* Turn off CRTC */ 635 WREG32(RADEON_CRTC_EXT_CNTL, 636 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 637 (RADEON_CRTC_SYNC_TRISTAT | 638 RADEON_CRTC_DISPLAY_DIS))); 639 640 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 641 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 642 } 643 644 r = radeon_read_bios(rdev); 645 646 /* restore regs */ 647 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 648 WREG32(RADEON_VIPH_CONTROL, viph_control); 649 if (rdev->flags & RADEON_IS_PCIE) 650 WREG32(RV370_BUS_CNTL, bus_cntl); 651 else 652 WREG32(RADEON_BUS_CNTL, bus_cntl); 653 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 654 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 655 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 656 } 657 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 658 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 659 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 660 } 661 return r; 662 } 663 664 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 665 { 666 if (rdev->flags & RADEON_IS_IGP) 667 return igp_read_bios_from_vram(rdev); 668 else if (rdev->family >= CHIP_BARTS) 669 return ni_read_disabled_bios(rdev); 670 else if (rdev->family >= CHIP_RV770) 671 return r700_read_disabled_bios(rdev); 672 else if (rdev->family >= CHIP_R600) 673 return r600_read_disabled_bios(rdev); 674 else if (rdev->family >= CHIP_RS600) 675 return avivo_read_disabled_bios(rdev); 676 else 677 return legacy_read_disabled_bios(rdev); 678 } 679 680 #ifdef CONFIG_ACPI 681 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 682 { 683 struct acpi_table_header *hdr; 684 acpi_size tbl_size; 685 UEFI_ACPI_VFCT *vfct; 686 unsigned offset; 687 688 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 689 return false; 690 tbl_size = hdr->length; 691 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 692 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 693 return false; 694 } 695 696 vfct = (UEFI_ACPI_VFCT *)hdr; 697 offset = vfct->VBIOSImageOffset; 698 699 while (offset < tbl_size) { 700 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 701 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 702 703 offset += sizeof(VFCT_IMAGE_HEADER); 704 if (offset > tbl_size) { 705 DRM_ERROR("ACPI VFCT image header truncated\n"); 706 return false; 707 } 708 709 offset += vhdr->ImageLength; 710 if (offset > tbl_size) { 711 DRM_ERROR("ACPI VFCT image truncated\n"); 712 return false; 713 } 714 715 if (vhdr->ImageLength && 716 vhdr->PCIBus == rdev->pdev->bus->number && 717 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 718 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 719 vhdr->VendorID == rdev->pdev->vendor && 720 vhdr->DeviceID == rdev->pdev->device) { 721 rdev->bios = kmemdup(&vbios->VbiosContent, 722 vhdr->ImageLength, 723 GFP_KERNEL); 724 725 if (!rdev->bios) 726 return false; 727 return true; 728 } 729 } 730 731 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 732 return false; 733 } 734 #else 735 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 736 { 737 return false; 738 } 739 #endif 740 741 bool radeon_get_bios(struct radeon_device *rdev) 742 { 743 bool r; 744 uint16_t tmp; 745 746 r = radeon_atrm_get_bios(rdev); 747 if (!r) 748 r = radeon_acpi_vfct_bios(rdev); 749 if (!r) 750 r = igp_read_bios_from_vram(rdev); 751 if (!r) 752 r = radeon_read_bios(rdev); 753 if (!r) 754 r = radeon_read_disabled_bios(rdev); 755 if (!r) 756 r = radeon_read_platform_bios(rdev); 757 if (!r || rdev->bios == NULL) { 758 DRM_ERROR("Unable to locate a BIOS ROM\n"); 759 rdev->bios = NULL; 760 return false; 761 } 762 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 763 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 764 goto free_bios; 765 } 766 767 tmp = RBIOS16(0x18); 768 if (RBIOS8(tmp + 0x14) != 0x0) { 769 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 770 goto free_bios; 771 } 772 773 rdev->bios_header_start = RBIOS16(0x48); 774 if (!rdev->bios_header_start) { 775 goto free_bios; 776 } 777 tmp = rdev->bios_header_start + 4; 778 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 779 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 780 rdev->is_atom_bios = true; 781 } else { 782 rdev->is_atom_bios = false; 783 } 784 785 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 786 return true; 787 free_bios: 788 kfree(rdev->bios); 789 rdev->bios = NULL; 790 return false; 791 } 792
Indexes created Mon Oct 27 08:10:08 GMT 2025