radeon_bios.c revision 1.13
1 /* $NetBSD: radeon_bios.c,v 1.13 2023/11/06 14:33:51 tnn Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.13 2023/11/06 14:33:51 tnn Exp $"); 33 34 #include <linux/acpi.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_device.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_reg.h" 43 44 #if defined(__NetBSD__) && NACPICA > 0 45 #define CONFIG_ACPI 46 #include <dev/acpi/acpireg.h> 47 #define _COMPONENT ACPI_DISPLAY_COMPONENT 48 ACPI_MODULE_NAME("radeon_acpi") 49 #include <linux/nbsd-namespace-acpi.h> 50 #endif 51 52 /* 53 * BIOS. 54 */ 55 56 /* If you boot an IGP board with a discrete card as the primary, 57 * the IGP rom is not accessible via the rom bar as the IGP rom is 58 * part of the system bios. On boot, the system bios puts a 59 * copy of the igp rom at the start of vram if a discrete card is 60 * present. 61 */ 62 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 63 { 64 #ifdef __NetBSD__ 65 bus_space_tag_t bst; 66 bus_space_handle_t bsh; 67 bus_size_t size; 68 #else 69 uint8_t __iomem *bios; 70 resource_size_t vram_base; 71 resource_size_t size = 256 * 1024; /* ??? */ 72 #endif 73 74 if (!(rdev->flags & RADEON_IS_IGP)) 75 if (!radeon_card_posted(rdev)) 76 return false; 77 78 rdev->bios = NULL; 79 #ifdef __NetBSD__ 80 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 81 /* XXX Dunno what type to expect here; fill me in... */ 82 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 83 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 84 0, &bst, &bsh, NULL, &size)) 85 return false; 86 if ((size == 0) || 87 (size < 256 * 1024) || 88 (bus_space_read_1(bst, bsh, 0) != 0x55) || 89 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 90 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 91 bus_space_unmap(bst, bsh, size); 92 return false; 93 } 94 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 95 bus_space_unmap(bst, bsh, size); 96 #else 97 vram_base = pci_resource_start(rdev->pdev, 0); 98 bios = ioremap(vram_base, size); 99 if (!bios) { 100 return false; 101 } 102 103 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 104 iounmap(bios); 105 return false; 106 } 107 rdev->bios = kmalloc(size, GFP_KERNEL); 108 if (rdev->bios == NULL) { 109 iounmap(bios); 110 return false; 111 } 112 memcpy_fromio(rdev->bios, bios, size); 113 iounmap(bios); 114 #endif 115 return true; 116 } 117 118 #ifdef __NetBSD__ 119 #define __iomem __pci_rom_iomem 120 #endif 121 122 static bool radeon_read_bios(struct radeon_device *rdev) 123 { 124 uint8_t __iomem *bios, val1, val2; 125 size_t size; 126 127 rdev->bios = NULL; 128 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 129 bios = pci_map_rom(rdev->pdev, &size); 130 if (!bios) { 131 return false; 132 } 133 134 #ifdef __NetBSD__ 135 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 136 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 137 138 val1 = bus_space_read_1(bst, bsh, 0); 139 val2 = bus_space_read_1(bst, bsh, 1); 140 #else 141 val1 = readb(&bios[0]); 142 val2 = readb(&bios[1]); 143 #endif 144 145 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 146 pci_unmap_rom(rdev->pdev, bios); 147 return false; 148 } 149 rdev->bios = kzalloc(size, GFP_KERNEL); 150 if (rdev->bios == NULL) { 151 pci_unmap_rom(rdev->pdev, bios); 152 return false; 153 } 154 #ifdef __NetBSD__ 155 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 156 #else 157 memcpy_fromio(rdev->bios, bios, size); 158 #endif 159 pci_unmap_rom(rdev->pdev, bios); 160 return true; 161 } 162 163 #ifdef __NetBSD__ 164 #undef __iomem 165 #endif 166 167 static bool radeon_read_platform_bios(struct radeon_device *rdev) 168 { 169 #ifdef __NetBSD__ /* XXX radeon platform bios */ 170 return false; 171 #else 172 uint8_t __iomem *bios; 173 size_t size; 174 175 rdev->bios = NULL; 176 177 bios = pci_platform_rom(rdev->pdev, &size); 178 if (!bios) { 179 return false; 180 } 181 182 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 183 return false; 184 } 185 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 186 if (rdev->bios == NULL) { 187 return false; 188 } 189 190 return true; 191 #endif 192 } 193 194 #ifdef CONFIG_ACPI 195 /* ATRM is used to get the BIOS on the discrete cards in 196 * dual-gpu systems. 197 */ 198 /* retrieve the ROM in 4k blocks */ 199 #define ATRM_BIOS_PAGE 4096 200 /** 201 * radeon_atrm_call - fetch a chunk of the vbios 202 * 203 * @atrm_handle: acpi ATRM handle 204 * @bios: vbios image pointer 205 * @offset: offset of vbios image data to fetch 206 * @len: length of vbios image data to fetch 207 * 208 * Executes ATRM to fetch a chunk of the discrete 209 * vbios image on PX systems (all asics). 210 * Returns the length of the buffer fetched. 211 */ 212 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 213 int offset, int len) 214 { 215 acpi_status status; 216 union acpi_object atrm_arg_elements[2], *obj; 217 struct acpi_object_list atrm_arg; 218 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 219 220 atrm_arg.count = 2; 221 atrm_arg.pointer = &atrm_arg_elements[0]; 222 223 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 224 atrm_arg_elements[0].integer.value = offset; 225 226 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 227 atrm_arg_elements[1].integer.value = len; 228 229 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 230 if (ACPI_FAILURE(status)) { 231 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 232 return -ENODEV; 233 } 234 235 obj = (union acpi_object *)buffer.pointer; 236 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 237 len = obj->buffer.length; 238 ACPI_FREE(buffer.pointer); 239 return len; 240 } 241 242 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 243 { 244 int ret; 245 int size = 256 * 1024; 246 int i; 247 struct pci_dev *pdev = NULL; 248 acpi_handle dhandle, atrm_handle; 249 acpi_status status; 250 bool found = false; 251 252 /* ATRM is for the discrete card only */ 253 if (rdev->flags & RADEON_IS_IGP) 254 return false; 255 256 #ifdef __NetBSD__ 257 pdev = rdev->pdev; 258 while (pdev != NULL) { 259 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle : NULL); 260 pdev = NULL; 261 if (rdev->pdev->class != PCI_CLASS_DISPLAY_VGA) 262 continue; 263 #else 264 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 265 dhandle = ACPI_HANDLE(&pdev->dev); 266 #endif 267 if (!dhandle) 268 continue; 269 270 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 271 if (!ACPI_FAILURE(status)) { 272 found = true; 273 break; 274 } 275 } 276 277 if (!found) { 278 #ifdef __NetBSD__ 279 pdev = rdev->pdev; 280 while (pdev != NULL) { 281 dhandle = (pdev->pd_ad ? pdev->pd_ad->ad_handle 282 : NULL); 283 pdev = NULL; 284 if (rdev->pdev->class != PCI_CLASS_DISPLAY_OTHER) 285 continue; 286 #else 287 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 288 dhandle = ACPI_HANDLE(&pdev->dev); 289 #endif 290 if (!dhandle) 291 continue; 292 293 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 294 if (!ACPI_FAILURE(status)) { 295 found = true; 296 break; 297 } 298 } 299 } 300 301 if (!found) 302 return false; 303 304 rdev->bios = kmalloc(size, GFP_KERNEL); 305 if (!rdev->bios) { 306 DRM_ERROR("Unable to allocate bios\n"); 307 return false; 308 } 309 310 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 311 ret = radeon_atrm_call(atrm_handle, 312 rdev->bios, 313 (i * ATRM_BIOS_PAGE), 314 ATRM_BIOS_PAGE); 315 if (ret < ATRM_BIOS_PAGE) 316 break; 317 } 318 319 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 320 kfree(rdev->bios); 321 return false; 322 } 323 return true; 324 } 325 #else 326 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 327 { 328 return false; 329 } 330 #endif 331 332 static bool ni_read_disabled_bios(struct radeon_device *rdev) 333 { 334 u32 bus_cntl; 335 u32 d1vga_control; 336 u32 d2vga_control; 337 u32 vga_render_control; 338 u32 rom_cntl; 339 bool r; 340 341 bus_cntl = RREG32(R600_BUS_CNTL); 342 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 343 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 344 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 345 rom_cntl = RREG32(R600_ROM_CNTL); 346 347 /* enable the rom */ 348 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 349 if (!ASIC_IS_NODCE(rdev)) { 350 /* Disable VGA mode */ 351 WREG32(AVIVO_D1VGA_CONTROL, 352 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 353 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 354 WREG32(AVIVO_D2VGA_CONTROL, 355 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 356 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 357 WREG32(AVIVO_VGA_RENDER_CONTROL, 358 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 359 } 360 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 361 362 r = radeon_read_bios(rdev); 363 364 /* restore regs */ 365 WREG32(R600_BUS_CNTL, bus_cntl); 366 if (!ASIC_IS_NODCE(rdev)) { 367 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 368 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 369 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 370 } 371 WREG32(R600_ROM_CNTL, rom_cntl); 372 return r; 373 } 374 375 static bool r700_read_disabled_bios(struct radeon_device *rdev) 376 { 377 uint32_t viph_control; 378 uint32_t bus_cntl; 379 uint32_t d1vga_control; 380 uint32_t d2vga_control; 381 uint32_t vga_render_control; 382 uint32_t rom_cntl; 383 uint32_t cg_spll_func_cntl = 0; 384 uint32_t cg_spll_status; 385 bool r; 386 387 viph_control = RREG32(RADEON_VIPH_CONTROL); 388 bus_cntl = RREG32(R600_BUS_CNTL); 389 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 390 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 391 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 392 rom_cntl = RREG32(R600_ROM_CNTL); 393 394 /* disable VIP */ 395 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 396 /* enable the rom */ 397 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 398 /* Disable VGA mode */ 399 WREG32(AVIVO_D1VGA_CONTROL, 400 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 401 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 402 WREG32(AVIVO_D2VGA_CONTROL, 403 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 404 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 405 WREG32(AVIVO_VGA_RENDER_CONTROL, 406 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 407 408 if (rdev->family == CHIP_RV730) { 409 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 410 411 /* enable bypass mode */ 412 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 413 R600_SPLL_BYPASS_EN)); 414 415 /* wait for SPLL_CHG_STATUS to change to 1 */ 416 cg_spll_status = 0; 417 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 418 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 419 420 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 421 } else 422 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 423 424 r = radeon_read_bios(rdev); 425 426 /* restore regs */ 427 if (rdev->family == CHIP_RV730) { 428 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 429 430 /* wait for SPLL_CHG_STATUS to change to 1 */ 431 cg_spll_status = 0; 432 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 433 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 434 } 435 WREG32(RADEON_VIPH_CONTROL, viph_control); 436 WREG32(R600_BUS_CNTL, bus_cntl); 437 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 438 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 439 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 440 WREG32(R600_ROM_CNTL, rom_cntl); 441 return r; 442 } 443 444 static bool r600_read_disabled_bios(struct radeon_device *rdev) 445 { 446 uint32_t viph_control; 447 uint32_t bus_cntl; 448 uint32_t d1vga_control; 449 uint32_t d2vga_control; 450 uint32_t vga_render_control; 451 uint32_t rom_cntl; 452 uint32_t general_pwrmgt; 453 uint32_t low_vid_lower_gpio_cntl; 454 uint32_t medium_vid_lower_gpio_cntl; 455 uint32_t high_vid_lower_gpio_cntl; 456 uint32_t ctxsw_vid_lower_gpio_cntl; 457 uint32_t lower_gpio_enable; 458 bool r; 459 460 viph_control = RREG32(RADEON_VIPH_CONTROL); 461 bus_cntl = RREG32(R600_BUS_CNTL); 462 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 463 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 464 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 465 rom_cntl = RREG32(R600_ROM_CNTL); 466 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 467 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 468 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 469 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 470 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 471 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 472 473 /* disable VIP */ 474 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 475 /* enable the rom */ 476 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 477 /* Disable VGA mode */ 478 WREG32(AVIVO_D1VGA_CONTROL, 479 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 480 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 481 WREG32(AVIVO_D2VGA_CONTROL, 482 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 483 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 484 WREG32(AVIVO_VGA_RENDER_CONTROL, 485 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 486 487 WREG32(R600_ROM_CNTL, 488 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 489 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 490 R600_SCK_OVERWRITE)); 491 492 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 493 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 494 (low_vid_lower_gpio_cntl & ~0x400)); 495 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 496 (medium_vid_lower_gpio_cntl & ~0x400)); 497 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 498 (high_vid_lower_gpio_cntl & ~0x400)); 499 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 500 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 501 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 502 503 r = radeon_read_bios(rdev); 504 505 /* restore regs */ 506 WREG32(RADEON_VIPH_CONTROL, viph_control); 507 WREG32(R600_BUS_CNTL, bus_cntl); 508 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 509 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 510 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 511 WREG32(R600_ROM_CNTL, rom_cntl); 512 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 513 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 514 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 515 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 516 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 517 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 518 return r; 519 } 520 521 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 522 { 523 uint32_t seprom_cntl1; 524 uint32_t viph_control; 525 uint32_t bus_cntl; 526 uint32_t d1vga_control; 527 uint32_t d2vga_control; 528 uint32_t vga_render_control; 529 uint32_t gpiopad_a; 530 uint32_t gpiopad_en; 531 uint32_t gpiopad_mask; 532 bool r; 533 534 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 535 viph_control = RREG32(RADEON_VIPH_CONTROL); 536 bus_cntl = RREG32(RV370_BUS_CNTL); 537 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 538 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 539 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 540 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 541 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 542 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 543 544 WREG32(RADEON_SEPROM_CNTL1, 545 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 546 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 547 WREG32(RADEON_GPIOPAD_A, 0); 548 WREG32(RADEON_GPIOPAD_EN, 0); 549 WREG32(RADEON_GPIOPAD_MASK, 0); 550 551 /* disable VIP */ 552 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 553 554 /* enable the rom */ 555 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 556 557 /* Disable VGA mode */ 558 WREG32(AVIVO_D1VGA_CONTROL, 559 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 560 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 561 WREG32(AVIVO_D2VGA_CONTROL, 562 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 563 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 564 WREG32(AVIVO_VGA_RENDER_CONTROL, 565 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 566 567 r = radeon_read_bios(rdev); 568 569 /* restore regs */ 570 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 571 WREG32(RADEON_VIPH_CONTROL, viph_control); 572 WREG32(RV370_BUS_CNTL, bus_cntl); 573 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 574 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 575 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 576 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 577 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 578 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 579 return r; 580 } 581 582 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 583 { 584 uint32_t seprom_cntl1; 585 uint32_t viph_control; 586 uint32_t bus_cntl; 587 uint32_t crtc_gen_cntl; 588 uint32_t crtc2_gen_cntl; 589 uint32_t crtc_ext_cntl; 590 uint32_t fp2_gen_cntl; 591 bool r; 592 593 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 594 viph_control = RREG32(RADEON_VIPH_CONTROL); 595 if (rdev->flags & RADEON_IS_PCIE) 596 bus_cntl = RREG32(RV370_BUS_CNTL); 597 else 598 bus_cntl = RREG32(RADEON_BUS_CNTL); 599 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 600 crtc2_gen_cntl = 0; 601 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 602 fp2_gen_cntl = 0; 603 604 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 605 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 606 } 607 608 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 609 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 610 } 611 612 WREG32(RADEON_SEPROM_CNTL1, 613 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 614 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 615 616 /* disable VIP */ 617 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 618 619 /* enable the rom */ 620 if (rdev->flags & RADEON_IS_PCIE) 621 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 622 else 623 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 624 625 /* Turn off mem requests and CRTC for both controllers */ 626 WREG32(RADEON_CRTC_GEN_CNTL, 627 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 628 (RADEON_CRTC_DISP_REQ_EN_B | 629 RADEON_CRTC_EXT_DISP_EN))); 630 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 631 WREG32(RADEON_CRTC2_GEN_CNTL, 632 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 633 RADEON_CRTC2_DISP_REQ_EN_B)); 634 } 635 /* Turn off CRTC */ 636 WREG32(RADEON_CRTC_EXT_CNTL, 637 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 638 (RADEON_CRTC_SYNC_TRISTAT | 639 RADEON_CRTC_DISPLAY_DIS))); 640 641 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 642 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 643 } 644 645 r = radeon_read_bios(rdev); 646 647 /* restore regs */ 648 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 649 WREG32(RADEON_VIPH_CONTROL, viph_control); 650 if (rdev->flags & RADEON_IS_PCIE) 651 WREG32(RV370_BUS_CNTL, bus_cntl); 652 else 653 WREG32(RADEON_BUS_CNTL, bus_cntl); 654 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 655 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 656 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 657 } 658 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 659 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 660 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 661 } 662 return r; 663 } 664 665 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 666 { 667 if (rdev->flags & RADEON_IS_IGP) 668 return igp_read_bios_from_vram(rdev); 669 else if (rdev->family >= CHIP_BARTS) 670 return ni_read_disabled_bios(rdev); 671 else if (rdev->family >= CHIP_RV770) 672 return r700_read_disabled_bios(rdev); 673 else if (rdev->family >= CHIP_R600) 674 return r600_read_disabled_bios(rdev); 675 else if (rdev->family >= CHIP_RS600) 676 return avivo_read_disabled_bios(rdev); 677 else 678 return legacy_read_disabled_bios(rdev); 679 } 680 681 #ifdef CONFIG_ACPI 682 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 683 { 684 struct acpi_table_header *hdr; 685 acpi_size tbl_size; 686 UEFI_ACPI_VFCT *vfct; 687 unsigned offset; 688 689 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 690 return false; 691 tbl_size = hdr->length; 692 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 693 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 694 return false; 695 } 696 697 vfct = (UEFI_ACPI_VFCT *)hdr; 698 offset = vfct->VBIOSImageOffset; 699 700 while (offset < tbl_size) { 701 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 702 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 703 704 offset += sizeof(VFCT_IMAGE_HEADER); 705 if (offset > tbl_size) { 706 DRM_ERROR("ACPI VFCT image header truncated\n"); 707 return false; 708 } 709 710 offset += vhdr->ImageLength; 711 if (offset > tbl_size) { 712 DRM_ERROR("ACPI VFCT image truncated\n"); 713 return false; 714 } 715 716 if (vhdr->ImageLength && 717 vhdr->PCIBus == rdev->pdev->bus->number && 718 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 719 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 720 vhdr->VendorID == rdev->pdev->vendor && 721 vhdr->DeviceID == rdev->pdev->device) { 722 rdev->bios = kmemdup(&vbios->VbiosContent, 723 vhdr->ImageLength, 724 GFP_KERNEL); 725 726 if (!rdev->bios) 727 return false; 728 return true; 729 } 730 } 731 732 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 733 return false; 734 } 735 #else 736 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 737 { 738 return false; 739 } 740 #endif 741 742 bool radeon_get_bios(struct radeon_device *rdev) 743 { 744 bool r; 745 uint16_t tmp; 746 747 r = radeon_atrm_get_bios(rdev); 748 if (!r) 749 r = radeon_acpi_vfct_bios(rdev); 750 if (!r) 751 r = igp_read_bios_from_vram(rdev); 752 if (!r) 753 r = radeon_read_bios(rdev); 754 if (!r) 755 r = radeon_read_disabled_bios(rdev); 756 if (!r) 757 r = radeon_read_platform_bios(rdev); 758 if (!r || rdev->bios == NULL) { 759 DRM_ERROR("Unable to locate a BIOS ROM\n"); 760 rdev->bios = NULL; 761 return false; 762 } 763 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 764 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 765 goto free_bios; 766 } 767 768 tmp = RBIOS16(0x18); 769 if (RBIOS8(tmp + 0x14) != 0x0) { 770 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 771 goto free_bios; 772 } 773 774 rdev->bios_header_start = RBIOS16(0x48); 775 if (!rdev->bios_header_start) { 776 goto free_bios; 777 } 778 tmp = rdev->bios_header_start + 4; 779 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 780 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 781 rdev->is_atom_bios = true; 782 } else { 783 rdev->is_atom_bios = false; 784 } 785 786 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 787 return true; 788 free_bios: 789 kfree(rdev->bios); 790 rdev->bios = NULL; 791 return false; 792 } 793
Indexes created Wed Oct 29 20:09:47 GMT 2025