radeon_bios.c revision 1.2.2.2
1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "atom.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 #include <linux/acpi.h> 36 #include <linux/string.h> 37 /* 38 * BIOS. 39 */ 40 41 /* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48 { 49 #ifdef __NetBSD__ 50 bus_space_tag_t bst; 51 bus_space_handle_t bsh; 52 bus_size_t size; 53 #else 54 uint8_t __iomem *bios; 55 resource_size_t vram_base; 56 resource_size_t size = 256 * 1024; /* ??? */ 57 #endif 58 59 if (!(rdev->flags & RADEON_IS_IGP)) 60 if (!radeon_card_posted(rdev)) 61 return false; 62 63 rdev->bios = NULL; 64 #ifdef __NetBSD__ 65 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 66 /* XXX Dunno what type to expect here; fill me in... */ 67 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 68 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 69 0, &bst, &bsh, NULL, &size)) 70 return false; 71 if ((size == 0) || 72 (size < 256 * 1024) || 73 (bus_space_read_1(bst, bsh, 0) != 0x55) || 74 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 75 ((rdev = kmalloc(size, GFP_KERNEL)) != NULL)) { 76 bus_space_unmap(bst, bsh, size); 77 return false; 78 } 79 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 80 bus_space_unmap(bst, bsh, size); 81 #else 82 vram_base = pci_resource_start(rdev->pdev, 0); 83 bios = ioremap(vram_base, size); 84 if (!bios) { 85 return false; 86 } 87 88 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 89 iounmap(bios); 90 return false; 91 } 92 rdev->bios = kmalloc(size, GFP_KERNEL); 93 if (rdev->bios == NULL) { 94 iounmap(bios); 95 return false; 96 } 97 memcpy_fromio(rdev->bios, bios, size); 98 iounmap(bios); 99 #endif 100 return true; 101 } 102 103 #ifdef __NetBSD__ 104 #define __iomem __pci_rom_iomem 105 #endif 106 107 static bool radeon_read_bios(struct radeon_device *rdev) 108 { 109 uint8_t __iomem *bios; 110 size_t size; 111 112 rdev->bios = NULL; 113 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 114 bios = pci_map_rom(rdev->pdev, &size); 115 if (!bios) { 116 return false; 117 } 118 119 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 120 pci_unmap_rom(rdev->pdev, bios); 121 return false; 122 } 123 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 124 if (rdev->bios == NULL) { 125 pci_unmap_rom(rdev->pdev, bios); 126 return false; 127 } 128 pci_unmap_rom(rdev->pdev, bios); 129 return true; 130 } 131 132 #ifdef __NetBSD__ 133 #undef __iomem 134 #endif 135 136 static bool radeon_read_platform_bios(struct radeon_device *rdev) 137 { 138 #ifdef __NetBSD__ /* XXX radeon platform bios */ 139 return false; 140 #else 141 uint8_t __iomem *bios; 142 size_t size; 143 144 rdev->bios = NULL; 145 146 bios = pci_platform_rom(rdev->pdev, &size); 147 if (!bios) { 148 return false; 149 } 150 151 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 152 return false; 153 } 154 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 155 if (rdev->bios == NULL) { 156 return false; 157 } 158 159 return true; 160 #endif 161 } 162 163 /* XXX radeon acpi */ 164 #ifdef CONFIG_ACPI 165 /* ATRM is used to get the BIOS on the discrete cards in 166 * dual-gpu systems. 167 */ 168 /* retrieve the ROM in 4k blocks */ 169 #define ATRM_BIOS_PAGE 4096 170 /** 171 * radeon_atrm_call - fetch a chunk of the vbios 172 * 173 * @atrm_handle: acpi ATRM handle 174 * @bios: vbios image pointer 175 * @offset: offset of vbios image data to fetch 176 * @len: length of vbios image data to fetch 177 * 178 * Executes ATRM to fetch a chunk of the discrete 179 * vbios image on PX systems (all asics). 180 * Returns the length of the buffer fetched. 181 */ 182 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 183 int offset, int len) 184 { 185 acpi_status status; 186 union acpi_object atrm_arg_elements[2], *obj; 187 struct acpi_object_list atrm_arg; 188 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 189 190 atrm_arg.count = 2; 191 atrm_arg.pointer = &atrm_arg_elements[0]; 192 193 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 194 atrm_arg_elements[0].integer.value = offset; 195 196 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 197 atrm_arg_elements[1].integer.value = len; 198 199 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 200 if (ACPI_FAILURE(status)) { 201 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 202 return -ENODEV; 203 } 204 205 obj = (union acpi_object *)buffer.pointer; 206 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 207 len = obj->buffer.length; 208 kfree(buffer.pointer); 209 return len; 210 } 211 212 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 213 { 214 int ret; 215 int size = 256 * 1024; 216 int i; 217 struct pci_dev *pdev = NULL; 218 acpi_handle dhandle, atrm_handle; 219 acpi_status status; 220 bool found = false; 221 222 /* ATRM is for the discrete card only */ 223 if (rdev->flags & RADEON_IS_IGP) 224 return false; 225 226 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 227 dhandle = ACPI_HANDLE(&pdev->dev); 228 if (!dhandle) 229 continue; 230 231 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 232 if (!ACPI_FAILURE(status)) { 233 found = true; 234 break; 235 } 236 } 237 238 if (!found) { 239 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 240 dhandle = ACPI_HANDLE(&pdev->dev); 241 if (!dhandle) 242 continue; 243 244 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 245 if (!ACPI_FAILURE(status)) { 246 found = true; 247 break; 248 } 249 } 250 } 251 252 if (!found) 253 return false; 254 255 rdev->bios = kmalloc(size, GFP_KERNEL); 256 if (!rdev->bios) { 257 DRM_ERROR("Unable to allocate bios\n"); 258 return false; 259 } 260 261 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 262 ret = radeon_atrm_call(atrm_handle, 263 rdev->bios, 264 (i * ATRM_BIOS_PAGE), 265 ATRM_BIOS_PAGE); 266 if (ret < ATRM_BIOS_PAGE) 267 break; 268 } 269 270 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 271 kfree(rdev->bios); 272 return false; 273 } 274 return true; 275 } 276 #else 277 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 278 { 279 return false; 280 } 281 #endif 282 283 static bool ni_read_disabled_bios(struct radeon_device *rdev) 284 { 285 u32 bus_cntl; 286 u32 d1vga_control; 287 u32 d2vga_control; 288 u32 vga_render_control; 289 u32 rom_cntl; 290 bool r; 291 292 bus_cntl = RREG32(R600_BUS_CNTL); 293 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 294 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 295 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 296 rom_cntl = RREG32(R600_ROM_CNTL); 297 298 /* enable the rom */ 299 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 300 if (!ASIC_IS_NODCE(rdev)) { 301 /* Disable VGA mode */ 302 WREG32(AVIVO_D1VGA_CONTROL, 303 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 304 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 305 WREG32(AVIVO_D2VGA_CONTROL, 306 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 307 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 308 WREG32(AVIVO_VGA_RENDER_CONTROL, 309 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 310 } 311 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 312 313 r = radeon_read_bios(rdev); 314 315 /* restore regs */ 316 WREG32(R600_BUS_CNTL, bus_cntl); 317 if (!ASIC_IS_NODCE(rdev)) { 318 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 319 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 320 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 321 } 322 WREG32(R600_ROM_CNTL, rom_cntl); 323 return r; 324 } 325 326 static bool r700_read_disabled_bios(struct radeon_device *rdev) 327 { 328 uint32_t viph_control; 329 uint32_t bus_cntl; 330 uint32_t d1vga_control; 331 uint32_t d2vga_control; 332 uint32_t vga_render_control; 333 uint32_t rom_cntl; 334 uint32_t cg_spll_func_cntl = 0; 335 uint32_t cg_spll_status; 336 bool r; 337 338 viph_control = RREG32(RADEON_VIPH_CONTROL); 339 bus_cntl = RREG32(R600_BUS_CNTL); 340 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 341 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 342 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 343 rom_cntl = RREG32(R600_ROM_CNTL); 344 345 /* disable VIP */ 346 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 347 /* enable the rom */ 348 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 349 /* Disable VGA mode */ 350 WREG32(AVIVO_D1VGA_CONTROL, 351 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 352 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 353 WREG32(AVIVO_D2VGA_CONTROL, 354 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 355 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 356 WREG32(AVIVO_VGA_RENDER_CONTROL, 357 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 358 359 if (rdev->family == CHIP_RV730) { 360 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 361 362 /* enable bypass mode */ 363 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 364 R600_SPLL_BYPASS_EN)); 365 366 /* wait for SPLL_CHG_STATUS to change to 1 */ 367 cg_spll_status = 0; 368 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 369 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 370 371 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 372 } else 373 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 374 375 r = radeon_read_bios(rdev); 376 377 /* restore regs */ 378 if (rdev->family == CHIP_RV730) { 379 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 380 381 /* wait for SPLL_CHG_STATUS to change to 1 */ 382 cg_spll_status = 0; 383 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 384 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 385 } 386 WREG32(RADEON_VIPH_CONTROL, viph_control); 387 WREG32(R600_BUS_CNTL, bus_cntl); 388 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 389 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 390 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 391 WREG32(R600_ROM_CNTL, rom_cntl); 392 return r; 393 } 394 395 static bool r600_read_disabled_bios(struct radeon_device *rdev) 396 { 397 uint32_t viph_control; 398 uint32_t bus_cntl; 399 uint32_t d1vga_control; 400 uint32_t d2vga_control; 401 uint32_t vga_render_control; 402 uint32_t rom_cntl; 403 uint32_t general_pwrmgt; 404 uint32_t low_vid_lower_gpio_cntl; 405 uint32_t medium_vid_lower_gpio_cntl; 406 uint32_t high_vid_lower_gpio_cntl; 407 uint32_t ctxsw_vid_lower_gpio_cntl; 408 uint32_t lower_gpio_enable; 409 bool r; 410 411 viph_control = RREG32(RADEON_VIPH_CONTROL); 412 bus_cntl = RREG32(R600_BUS_CNTL); 413 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 414 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 415 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 416 rom_cntl = RREG32(R600_ROM_CNTL); 417 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 418 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 419 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 420 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 421 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 422 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 423 424 /* disable VIP */ 425 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 426 /* enable the rom */ 427 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 428 /* Disable VGA mode */ 429 WREG32(AVIVO_D1VGA_CONTROL, 430 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 431 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 432 WREG32(AVIVO_D2VGA_CONTROL, 433 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 434 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 435 WREG32(AVIVO_VGA_RENDER_CONTROL, 436 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 437 438 WREG32(R600_ROM_CNTL, 439 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 440 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 441 R600_SCK_OVERWRITE)); 442 443 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 444 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 445 (low_vid_lower_gpio_cntl & ~0x400)); 446 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 447 (medium_vid_lower_gpio_cntl & ~0x400)); 448 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 449 (high_vid_lower_gpio_cntl & ~0x400)); 450 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 451 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 452 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 453 454 r = radeon_read_bios(rdev); 455 456 /* restore regs */ 457 WREG32(RADEON_VIPH_CONTROL, viph_control); 458 WREG32(R600_BUS_CNTL, bus_cntl); 459 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 460 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 461 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 462 WREG32(R600_ROM_CNTL, rom_cntl); 463 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 464 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 465 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 466 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 467 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 468 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 469 return r; 470 } 471 472 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 473 { 474 uint32_t seprom_cntl1; 475 uint32_t viph_control; 476 uint32_t bus_cntl; 477 uint32_t d1vga_control; 478 uint32_t d2vga_control; 479 uint32_t vga_render_control; 480 uint32_t gpiopad_a; 481 uint32_t gpiopad_en; 482 uint32_t gpiopad_mask; 483 bool r; 484 485 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 486 viph_control = RREG32(RADEON_VIPH_CONTROL); 487 bus_cntl = RREG32(RV370_BUS_CNTL); 488 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 489 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 490 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 491 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 492 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 493 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 494 495 WREG32(RADEON_SEPROM_CNTL1, 496 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 497 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 498 WREG32(RADEON_GPIOPAD_A, 0); 499 WREG32(RADEON_GPIOPAD_EN, 0); 500 WREG32(RADEON_GPIOPAD_MASK, 0); 501 502 /* disable VIP */ 503 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 504 505 /* enable the rom */ 506 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 507 508 /* Disable VGA mode */ 509 WREG32(AVIVO_D1VGA_CONTROL, 510 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 511 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 512 WREG32(AVIVO_D2VGA_CONTROL, 513 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 514 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 515 WREG32(AVIVO_VGA_RENDER_CONTROL, 516 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 517 518 r = radeon_read_bios(rdev); 519 520 /* restore regs */ 521 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 522 WREG32(RADEON_VIPH_CONTROL, viph_control); 523 WREG32(RV370_BUS_CNTL, bus_cntl); 524 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 525 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 526 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 527 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 528 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 529 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 530 return r; 531 } 532 533 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 534 { 535 uint32_t seprom_cntl1; 536 uint32_t viph_control; 537 uint32_t bus_cntl; 538 uint32_t crtc_gen_cntl; 539 uint32_t crtc2_gen_cntl; 540 uint32_t crtc_ext_cntl; 541 uint32_t fp2_gen_cntl; 542 bool r; 543 544 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 545 viph_control = RREG32(RADEON_VIPH_CONTROL); 546 if (rdev->flags & RADEON_IS_PCIE) 547 bus_cntl = RREG32(RV370_BUS_CNTL); 548 else 549 bus_cntl = RREG32(RADEON_BUS_CNTL); 550 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 551 crtc2_gen_cntl = 0; 552 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 553 fp2_gen_cntl = 0; 554 555 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 556 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 557 } 558 559 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 560 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 561 } 562 563 WREG32(RADEON_SEPROM_CNTL1, 564 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 565 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 566 567 /* disable VIP */ 568 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 569 570 /* enable the rom */ 571 if (rdev->flags & RADEON_IS_PCIE) 572 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 573 else 574 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 575 576 /* Turn off mem requests and CRTC for both controllers */ 577 WREG32(RADEON_CRTC_GEN_CNTL, 578 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 579 (RADEON_CRTC_DISP_REQ_EN_B | 580 RADEON_CRTC_EXT_DISP_EN))); 581 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 582 WREG32(RADEON_CRTC2_GEN_CNTL, 583 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 584 RADEON_CRTC2_DISP_REQ_EN_B)); 585 } 586 /* Turn off CRTC */ 587 WREG32(RADEON_CRTC_EXT_CNTL, 588 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 589 (RADEON_CRTC_SYNC_TRISTAT | 590 RADEON_CRTC_DISPLAY_DIS))); 591 592 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 593 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 594 } 595 596 r = radeon_read_bios(rdev); 597 598 /* restore regs */ 599 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 600 WREG32(RADEON_VIPH_CONTROL, viph_control); 601 if (rdev->flags & RADEON_IS_PCIE) 602 WREG32(RV370_BUS_CNTL, bus_cntl); 603 else 604 WREG32(RADEON_BUS_CNTL, bus_cntl); 605 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 606 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 607 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 608 } 609 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 610 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 611 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 612 } 613 return r; 614 } 615 616 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 617 { 618 if (rdev->flags & RADEON_IS_IGP) 619 return igp_read_bios_from_vram(rdev); 620 else if (rdev->family >= CHIP_BARTS) 621 return ni_read_disabled_bios(rdev); 622 else if (rdev->family >= CHIP_RV770) 623 return r700_read_disabled_bios(rdev); 624 else if (rdev->family >= CHIP_R600) 625 return r600_read_disabled_bios(rdev); 626 else if (rdev->family >= CHIP_RS600) 627 return avivo_read_disabled_bios(rdev); 628 else 629 return legacy_read_disabled_bios(rdev); 630 } 631 632 #ifdef CONFIG_ACPI 633 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 634 { 635 bool ret = false; 636 struct acpi_table_header *hdr; 637 acpi_size tbl_size; 638 UEFI_ACPI_VFCT *vfct; 639 GOP_VBIOS_CONTENT *vbios; 640 VFCT_IMAGE_HEADER *vhdr; 641 642 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 643 return false; 644 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 645 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 646 goto out_unmap; 647 } 648 649 vfct = (UEFI_ACPI_VFCT *)hdr; 650 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 651 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 652 goto out_unmap; 653 } 654 655 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 656 vhdr = &vbios->VbiosHeader; 657 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 658 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 659 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 660 661 if (vhdr->PCIBus != rdev->pdev->bus->number || 662 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 663 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 664 vhdr->VendorID != rdev->pdev->vendor || 665 vhdr->DeviceID != rdev->pdev->device) { 666 DRM_INFO("ACPI VFCT table is not for this card\n"); 667 goto out_unmap; 668 }; 669 670 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 671 DRM_ERROR("ACPI VFCT image truncated\n"); 672 goto out_unmap; 673 } 674 675 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 676 ret = !!rdev->bios; 677 678 out_unmap: 679 return ret; 680 } 681 #else 682 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 683 { 684 return false; 685 } 686 #endif 687 688 bool radeon_get_bios(struct radeon_device *rdev) 689 { 690 bool r; 691 uint16_t tmp; 692 693 r = radeon_atrm_get_bios(rdev); 694 if (r == false) 695 r = radeon_acpi_vfct_bios(rdev); 696 if (r == false) 697 r = igp_read_bios_from_vram(rdev); 698 if (r == false) 699 r = radeon_read_bios(rdev); 700 if (r == false) { 701 r = radeon_read_disabled_bios(rdev); 702 } 703 if (r == false) { 704 r = radeon_read_platform_bios(rdev); 705 } 706 if (r == false || rdev->bios == NULL) { 707 DRM_ERROR("Unable to locate a BIOS ROM\n"); 708 rdev->bios = NULL; 709 return false; 710 } 711 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 712 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 713 goto free_bios; 714 } 715 716 tmp = RBIOS16(0x18); 717 if (RBIOS8(tmp + 0x14) != 0x0) { 718 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 719 goto free_bios; 720 } 721 722 rdev->bios_header_start = RBIOS16(0x48); 723 if (!rdev->bios_header_start) { 724 goto free_bios; 725 } 726 tmp = rdev->bios_header_start + 4; 727 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 728 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 729 rdev->is_atom_bios = true; 730 } else { 731 rdev->is_atom_bios = false; 732 } 733 734 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 735 return true; 736 free_bios: 737 kfree(rdev->bios); 738 rdev->bios = NULL; 739 return false; 740 } 741
Indexes created Sun Oct 26 17:10:13 GMT 2025