radeon_bios.c revision 1.2.8.1
1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "atom.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 #include <linux/acpi.h> 36 #include <linux/string.h> 37 /* 38 * BIOS. 39 */ 40 41 /* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48 { 49 #ifdef __NetBSD__ 50 bus_space_tag_t bst; 51 bus_space_handle_t bsh; 52 bus_size_t size; 53 #else 54 uint8_t __iomem *bios; 55 resource_size_t vram_base; 56 resource_size_t size = 256 * 1024; /* ??? */ 57 #endif 58 59 if (!(rdev->flags & RADEON_IS_IGP)) 60 if (!radeon_card_posted(rdev)) 61 return false; 62 63 rdev->bios = NULL; 64 #ifdef __NetBSD__ 65 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 66 /* XXX Dunno what type to expect here; fill me in... */ 67 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 68 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 69 0, &bst, &bsh, NULL, &size)) 70 return false; 71 if ((size == 0) || 72 (size < 256 * 1024) || 73 (bus_space_read_1(bst, bsh, 0) != 0x55) || 74 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 75 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 76 bus_space_unmap(bst, bsh, size); 77 return false; 78 } 79 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 80 bus_space_unmap(bst, bsh, size); 81 #else 82 vram_base = pci_resource_start(rdev->pdev, 0); 83 bios = ioremap(vram_base, size); 84 if (!bios) { 85 return false; 86 } 87 88 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 89 iounmap(bios); 90 return false; 91 } 92 rdev->bios = kmalloc(size, GFP_KERNEL); 93 if (rdev->bios == NULL) { 94 iounmap(bios); 95 return false; 96 } 97 memcpy_fromio(rdev->bios, bios, size); 98 iounmap(bios); 99 #endif 100 return true; 101 } 102 103 #ifdef __NetBSD__ 104 #define __iomem __pci_rom_iomem 105 #endif 106 107 static bool radeon_read_bios(struct radeon_device *rdev) 108 { 109 uint8_t __iomem *bios; 110 size_t size; 111 112 rdev->bios = NULL; 113 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 114 bios = pci_map_rom(rdev->pdev, &size); 115 if (!bios) { 116 return false; 117 } 118 119 #ifdef __NetBSD__ 120 /* 121 * Using kmemdup results in >4-byte memory access on 64-bit 122 * systems, which yields bogus answers on some devices. So we 123 * use bus_space(9) to do guaranteed byte access with 124 * bus_space_read_region_1 which seems to work better. 125 */ 126 { 127 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 128 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 129 130 if (size == 0 || 131 bus_space_read_1(bst, bsh, 0) != 0x55 || 132 bus_space_read_1(bst, bsh, 1) != 0xaa) { 133 pci_unmap_rom(rdev->pdev, bios); 134 return false; 135 } 136 rdev->bios = kmalloc(size, GFP_KERNEL); 137 if (rdev->bios == NULL) { 138 pci_unmap_rom(rdev->pdev, bios); 139 return false; 140 } 141 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 142 } 143 #else 144 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 145 pci_unmap_rom(rdev->pdev, bios); 146 return false; 147 } 148 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 149 if (rdev->bios == NULL) { 150 pci_unmap_rom(rdev->pdev, bios); 151 return false; 152 } 153 #endif 154 pci_unmap_rom(rdev->pdev, bios); 155 return true; 156 } 157 158 #ifdef __NetBSD__ 159 #undef __iomem 160 #endif 161 162 static bool radeon_read_platform_bios(struct radeon_device *rdev) 163 { 164 #ifdef __NetBSD__ /* XXX radeon platform bios */ 165 return false; 166 #else 167 uint8_t __iomem *bios; 168 size_t size; 169 170 rdev->bios = NULL; 171 172 bios = pci_platform_rom(rdev->pdev, &size); 173 if (!bios) { 174 return false; 175 } 176 177 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 178 return false; 179 } 180 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 181 if (rdev->bios == NULL) { 182 return false; 183 } 184 185 return true; 186 #endif 187 } 188 189 /* XXX radeon acpi */ 190 #ifdef CONFIG_ACPI 191 /* ATRM is used to get the BIOS on the discrete cards in 192 * dual-gpu systems. 193 */ 194 /* retrieve the ROM in 4k blocks */ 195 #define ATRM_BIOS_PAGE 4096 196 /** 197 * radeon_atrm_call - fetch a chunk of the vbios 198 * 199 * @atrm_handle: acpi ATRM handle 200 * @bios: vbios image pointer 201 * @offset: offset of vbios image data to fetch 202 * @len: length of vbios image data to fetch 203 * 204 * Executes ATRM to fetch a chunk of the discrete 205 * vbios image on PX systems (all asics). 206 * Returns the length of the buffer fetched. 207 */ 208 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 209 int offset, int len) 210 { 211 acpi_status status; 212 union acpi_object atrm_arg_elements[2], *obj; 213 struct acpi_object_list atrm_arg; 214 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 215 216 atrm_arg.count = 2; 217 atrm_arg.pointer = &atrm_arg_elements[0]; 218 219 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 220 atrm_arg_elements[0].integer.value = offset; 221 222 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 223 atrm_arg_elements[1].integer.value = len; 224 225 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 226 if (ACPI_FAILURE(status)) { 227 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 228 return -ENODEV; 229 } 230 231 obj = (union acpi_object *)buffer.pointer; 232 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 233 len = obj->buffer.length; 234 kfree(buffer.pointer); 235 return len; 236 } 237 238 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 239 { 240 int ret; 241 int size = 256 * 1024; 242 int i; 243 struct pci_dev *pdev = NULL; 244 acpi_handle dhandle, atrm_handle; 245 acpi_status status; 246 bool found = false; 247 248 /* ATRM is for the discrete card only */ 249 if (rdev->flags & RADEON_IS_IGP) 250 return false; 251 252 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 253 dhandle = ACPI_HANDLE(&pdev->dev); 254 if (!dhandle) 255 continue; 256 257 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 258 if (!ACPI_FAILURE(status)) { 259 found = true; 260 break; 261 } 262 } 263 264 if (!found) { 265 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 266 dhandle = ACPI_HANDLE(&pdev->dev); 267 if (!dhandle) 268 continue; 269 270 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 271 if (!ACPI_FAILURE(status)) { 272 found = true; 273 break; 274 } 275 } 276 } 277 278 if (!found) 279 return false; 280 281 rdev->bios = kmalloc(size, GFP_KERNEL); 282 if (!rdev->bios) { 283 DRM_ERROR("Unable to allocate bios\n"); 284 return false; 285 } 286 287 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 288 ret = radeon_atrm_call(atrm_handle, 289 rdev->bios, 290 (i * ATRM_BIOS_PAGE), 291 ATRM_BIOS_PAGE); 292 if (ret < ATRM_BIOS_PAGE) 293 break; 294 } 295 296 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 297 kfree(rdev->bios); 298 return false; 299 } 300 return true; 301 } 302 #else 303 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 304 { 305 return false; 306 } 307 #endif 308 309 static bool ni_read_disabled_bios(struct radeon_device *rdev) 310 { 311 u32 bus_cntl; 312 u32 d1vga_control; 313 u32 d2vga_control; 314 u32 vga_render_control; 315 u32 rom_cntl; 316 bool r; 317 318 bus_cntl = RREG32(R600_BUS_CNTL); 319 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 320 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 321 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 322 rom_cntl = RREG32(R600_ROM_CNTL); 323 324 /* enable the rom */ 325 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 326 if (!ASIC_IS_NODCE(rdev)) { 327 /* Disable VGA mode */ 328 WREG32(AVIVO_D1VGA_CONTROL, 329 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 330 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 331 WREG32(AVIVO_D2VGA_CONTROL, 332 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 333 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 334 WREG32(AVIVO_VGA_RENDER_CONTROL, 335 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 336 } 337 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 338 339 r = radeon_read_bios(rdev); 340 341 /* restore regs */ 342 WREG32(R600_BUS_CNTL, bus_cntl); 343 if (!ASIC_IS_NODCE(rdev)) { 344 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 345 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 346 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 347 } 348 WREG32(R600_ROM_CNTL, rom_cntl); 349 return r; 350 } 351 352 static bool r700_read_disabled_bios(struct radeon_device *rdev) 353 { 354 uint32_t viph_control; 355 uint32_t bus_cntl; 356 uint32_t d1vga_control; 357 uint32_t d2vga_control; 358 uint32_t vga_render_control; 359 uint32_t rom_cntl; 360 uint32_t cg_spll_func_cntl = 0; 361 uint32_t cg_spll_status; 362 bool r; 363 364 viph_control = RREG32(RADEON_VIPH_CONTROL); 365 bus_cntl = RREG32(R600_BUS_CNTL); 366 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 367 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 368 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 369 rom_cntl = RREG32(R600_ROM_CNTL); 370 371 /* disable VIP */ 372 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 373 /* enable the rom */ 374 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 375 /* Disable VGA mode */ 376 WREG32(AVIVO_D1VGA_CONTROL, 377 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 378 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 379 WREG32(AVIVO_D2VGA_CONTROL, 380 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 381 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 382 WREG32(AVIVO_VGA_RENDER_CONTROL, 383 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 384 385 if (rdev->family == CHIP_RV730) { 386 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 387 388 /* enable bypass mode */ 389 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 390 R600_SPLL_BYPASS_EN)); 391 392 /* wait for SPLL_CHG_STATUS to change to 1 */ 393 cg_spll_status = 0; 394 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 395 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 396 397 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 398 } else 399 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 400 401 r = radeon_read_bios(rdev); 402 403 /* restore regs */ 404 if (rdev->family == CHIP_RV730) { 405 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 406 407 /* wait for SPLL_CHG_STATUS to change to 1 */ 408 cg_spll_status = 0; 409 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 410 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 411 } 412 WREG32(RADEON_VIPH_CONTROL, viph_control); 413 WREG32(R600_BUS_CNTL, bus_cntl); 414 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 415 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 416 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 417 WREG32(R600_ROM_CNTL, rom_cntl); 418 return r; 419 } 420 421 static bool r600_read_disabled_bios(struct radeon_device *rdev) 422 { 423 uint32_t viph_control; 424 uint32_t bus_cntl; 425 uint32_t d1vga_control; 426 uint32_t d2vga_control; 427 uint32_t vga_render_control; 428 uint32_t rom_cntl; 429 uint32_t general_pwrmgt; 430 uint32_t low_vid_lower_gpio_cntl; 431 uint32_t medium_vid_lower_gpio_cntl; 432 uint32_t high_vid_lower_gpio_cntl; 433 uint32_t ctxsw_vid_lower_gpio_cntl; 434 uint32_t lower_gpio_enable; 435 bool r; 436 437 viph_control = RREG32(RADEON_VIPH_CONTROL); 438 bus_cntl = RREG32(R600_BUS_CNTL); 439 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 440 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 441 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 442 rom_cntl = RREG32(R600_ROM_CNTL); 443 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 444 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 445 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 446 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 447 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 448 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 449 450 /* disable VIP */ 451 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 452 /* enable the rom */ 453 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 454 /* Disable VGA mode */ 455 WREG32(AVIVO_D1VGA_CONTROL, 456 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 457 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 458 WREG32(AVIVO_D2VGA_CONTROL, 459 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 460 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 461 WREG32(AVIVO_VGA_RENDER_CONTROL, 462 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 463 464 WREG32(R600_ROM_CNTL, 465 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 466 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 467 R600_SCK_OVERWRITE)); 468 469 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 470 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 471 (low_vid_lower_gpio_cntl & ~0x400)); 472 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 473 (medium_vid_lower_gpio_cntl & ~0x400)); 474 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 475 (high_vid_lower_gpio_cntl & ~0x400)); 476 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 477 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 478 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 479 480 r = radeon_read_bios(rdev); 481 482 /* restore regs */ 483 WREG32(RADEON_VIPH_CONTROL, viph_control); 484 WREG32(R600_BUS_CNTL, bus_cntl); 485 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 486 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 487 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 488 WREG32(R600_ROM_CNTL, rom_cntl); 489 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 490 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 491 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 492 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 493 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 494 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 495 return r; 496 } 497 498 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 499 { 500 uint32_t seprom_cntl1; 501 uint32_t viph_control; 502 uint32_t bus_cntl; 503 uint32_t d1vga_control; 504 uint32_t d2vga_control; 505 uint32_t vga_render_control; 506 uint32_t gpiopad_a; 507 uint32_t gpiopad_en; 508 uint32_t gpiopad_mask; 509 bool r; 510 511 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 512 viph_control = RREG32(RADEON_VIPH_CONTROL); 513 bus_cntl = RREG32(RV370_BUS_CNTL); 514 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 515 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 516 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 517 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 518 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 519 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 520 521 WREG32(RADEON_SEPROM_CNTL1, 522 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 523 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 524 WREG32(RADEON_GPIOPAD_A, 0); 525 WREG32(RADEON_GPIOPAD_EN, 0); 526 WREG32(RADEON_GPIOPAD_MASK, 0); 527 528 /* disable VIP */ 529 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 530 531 /* enable the rom */ 532 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 533 534 /* Disable VGA mode */ 535 WREG32(AVIVO_D1VGA_CONTROL, 536 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 537 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 538 WREG32(AVIVO_D2VGA_CONTROL, 539 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 540 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 541 WREG32(AVIVO_VGA_RENDER_CONTROL, 542 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 543 544 r = radeon_read_bios(rdev); 545 546 /* restore regs */ 547 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 548 WREG32(RADEON_VIPH_CONTROL, viph_control); 549 WREG32(RV370_BUS_CNTL, bus_cntl); 550 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 551 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 552 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 553 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 554 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 555 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 556 return r; 557 } 558 559 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 560 { 561 uint32_t seprom_cntl1; 562 uint32_t viph_control; 563 uint32_t bus_cntl; 564 uint32_t crtc_gen_cntl; 565 uint32_t crtc2_gen_cntl; 566 uint32_t crtc_ext_cntl; 567 uint32_t fp2_gen_cntl; 568 bool r; 569 570 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 571 viph_control = RREG32(RADEON_VIPH_CONTROL); 572 if (rdev->flags & RADEON_IS_PCIE) 573 bus_cntl = RREG32(RV370_BUS_CNTL); 574 else 575 bus_cntl = RREG32(RADEON_BUS_CNTL); 576 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 577 crtc2_gen_cntl = 0; 578 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 579 fp2_gen_cntl = 0; 580 581 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 582 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 583 } 584 585 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 586 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 587 } 588 589 WREG32(RADEON_SEPROM_CNTL1, 590 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 591 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 592 593 /* disable VIP */ 594 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 595 596 /* enable the rom */ 597 if (rdev->flags & RADEON_IS_PCIE) 598 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 599 else 600 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 601 602 /* Turn off mem requests and CRTC for both controllers */ 603 WREG32(RADEON_CRTC_GEN_CNTL, 604 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 605 (RADEON_CRTC_DISP_REQ_EN_B | 606 RADEON_CRTC_EXT_DISP_EN))); 607 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 608 WREG32(RADEON_CRTC2_GEN_CNTL, 609 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 610 RADEON_CRTC2_DISP_REQ_EN_B)); 611 } 612 /* Turn off CRTC */ 613 WREG32(RADEON_CRTC_EXT_CNTL, 614 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 615 (RADEON_CRTC_SYNC_TRISTAT | 616 RADEON_CRTC_DISPLAY_DIS))); 617 618 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 619 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 620 } 621 622 r = radeon_read_bios(rdev); 623 624 /* restore regs */ 625 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 626 WREG32(RADEON_VIPH_CONTROL, viph_control); 627 if (rdev->flags & RADEON_IS_PCIE) 628 WREG32(RV370_BUS_CNTL, bus_cntl); 629 else 630 WREG32(RADEON_BUS_CNTL, bus_cntl); 631 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 632 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 633 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 634 } 635 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 636 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 637 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 638 } 639 return r; 640 } 641 642 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 643 { 644 if (rdev->flags & RADEON_IS_IGP) 645 return igp_read_bios_from_vram(rdev); 646 else if (rdev->family >= CHIP_BARTS) 647 return ni_read_disabled_bios(rdev); 648 else if (rdev->family >= CHIP_RV770) 649 return r700_read_disabled_bios(rdev); 650 else if (rdev->family >= CHIP_R600) 651 return r600_read_disabled_bios(rdev); 652 else if (rdev->family >= CHIP_RS600) 653 return avivo_read_disabled_bios(rdev); 654 else 655 return legacy_read_disabled_bios(rdev); 656 } 657 658 #ifdef CONFIG_ACPI 659 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 660 { 661 bool ret = false; 662 struct acpi_table_header *hdr; 663 acpi_size tbl_size; 664 UEFI_ACPI_VFCT *vfct; 665 GOP_VBIOS_CONTENT *vbios; 666 VFCT_IMAGE_HEADER *vhdr; 667 668 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 669 return false; 670 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 671 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 672 goto out_unmap; 673 } 674 675 vfct = (UEFI_ACPI_VFCT *)hdr; 676 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 677 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 678 goto out_unmap; 679 } 680 681 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 682 vhdr = &vbios->VbiosHeader; 683 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 684 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 685 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 686 687 if (vhdr->PCIBus != rdev->pdev->bus->number || 688 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 689 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 690 vhdr->VendorID != rdev->pdev->vendor || 691 vhdr->DeviceID != rdev->pdev->device) { 692 DRM_INFO("ACPI VFCT table is not for this card\n"); 693 goto out_unmap; 694 }; 695 696 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 697 DRM_ERROR("ACPI VFCT image truncated\n"); 698 goto out_unmap; 699 } 700 701 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 702 ret = !!rdev->bios; 703 704 out_unmap: 705 return ret; 706 } 707 #else 708 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 709 { 710 return false; 711 } 712 #endif 713 714 bool radeon_get_bios(struct radeon_device *rdev) 715 { 716 bool r; 717 uint16_t tmp; 718 719 r = radeon_atrm_get_bios(rdev); 720 if (r == false) 721 r = radeon_acpi_vfct_bios(rdev); 722 if (r == false) 723 r = igp_read_bios_from_vram(rdev); 724 if (r == false) 725 r = radeon_read_bios(rdev); 726 if (r == false) { 727 r = radeon_read_disabled_bios(rdev); 728 } 729 if (r == false) { 730 r = radeon_read_platform_bios(rdev); 731 } 732 if (r == false || rdev->bios == NULL) { 733 DRM_ERROR("Unable to locate a BIOS ROM\n"); 734 rdev->bios = NULL; 735 return false; 736 } 737 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 738 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 739 goto free_bios; 740 } 741 742 tmp = RBIOS16(0x18); 743 if (RBIOS8(tmp + 0x14) != 0x0) { 744 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 745 goto free_bios; 746 } 747 748 rdev->bios_header_start = RBIOS16(0x48); 749 if (!rdev->bios_header_start) { 750 goto free_bios; 751 } 752 tmp = rdev->bios_header_start + 4; 753 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 754 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 755 rdev->is_atom_bios = true; 756 } else { 757 rdev->is_atom_bios = false; 758 } 759 760 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 761 return true; 762 free_bios: 763 kfree(rdev->bios); 764 rdev->bios = NULL; 765 return false; 766 } 767
Indexes created Sun Oct 26 20:09:54 GMT 2025