radeon_bios.c revision 1.4.16.1
1 /* $NetBSD: radeon_bios.c,v 1.4.16.1 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.4.16.1 2018/09/06 06:56:32 pgoyette Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "atom.h" 37 38 #include <linux/slab.h> 39 #include <linux/acpi.h> 40 #include <linux/string.h> 41 /* 42 * BIOS. 43 */ 44 45 /* If you boot an IGP board with a discrete card as the primary, 46 * the IGP rom is not accessible via the rom bar as the IGP rom is 47 * part of the system bios. On boot, the system bios puts a 48 * copy of the igp rom at the start of vram if a discrete card is 49 * present. 50 */ 51 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 52 { 53 #ifdef __NetBSD__ 54 bus_space_tag_t bst; 55 bus_space_handle_t bsh; 56 bus_size_t size; 57 #else 58 uint8_t __iomem *bios; 59 resource_size_t vram_base; 60 resource_size_t size = 256 * 1024; /* ??? */ 61 #endif 62 63 if (!(rdev->flags & RADEON_IS_IGP)) 64 if (!radeon_card_posted(rdev)) 65 return false; 66 67 rdev->bios = NULL; 68 #ifdef __NetBSD__ 69 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 70 /* XXX Dunno what type to expect here; fill me in... */ 71 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 72 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 73 0, &bst, &bsh, NULL, &size)) 74 return false; 75 if ((size == 0) || 76 (size < 256 * 1024) || 77 (bus_space_read_1(bst, bsh, 0) != 0x55) || 78 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 79 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 80 bus_space_unmap(bst, bsh, size); 81 return false; 82 } 83 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 84 bus_space_unmap(bst, bsh, size); 85 #else 86 vram_base = pci_resource_start(rdev->pdev, 0); 87 bios = ioremap(vram_base, size); 88 if (!bios) { 89 return false; 90 } 91 92 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 93 iounmap(bios); 94 return false; 95 } 96 rdev->bios = kmalloc(size, GFP_KERNEL); 97 if (rdev->bios == NULL) { 98 iounmap(bios); 99 return false; 100 } 101 memcpy_fromio(rdev->bios, bios, size); 102 iounmap(bios); 103 #endif 104 return true; 105 } 106 107 #ifdef __NetBSD__ 108 #define __iomem __pci_rom_iomem 109 #endif 110 111 static bool radeon_read_bios(struct radeon_device *rdev) 112 { 113 uint8_t __iomem *bios, val1, val2; 114 size_t size; 115 116 rdev->bios = NULL; 117 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 118 bios = pci_map_rom(rdev->pdev, &size); 119 if (!bios) { 120 return false; 121 } 122 123 #ifdef __NetBSD__ 124 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 125 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 126 127 val1 = bus_space_read_1(bst, bsh, 0); 128 val2 = bus_space_read_1(bst, bsh, 1); 129 #else 130 val1 = readb(&bios[0]); 131 val2 = readb(&bios[1]); 132 #endif 133 134 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 135 pci_unmap_rom(rdev->pdev, bios); 136 return false; 137 } 138 rdev->bios = kzalloc(size, GFP_KERNEL); 139 if (rdev->bios == NULL) { 140 pci_unmap_rom(rdev->pdev, bios); 141 return false; 142 } 143 #ifdef __NetBSD__ 144 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 145 #else 146 memcpy_fromio(rdev->bios, bios, size); 147 #endif 148 pci_unmap_rom(rdev->pdev, bios); 149 return true; 150 } 151 152 #ifdef __NetBSD__ 153 #undef __iomem 154 #endif 155 156 static bool radeon_read_platform_bios(struct radeon_device *rdev) 157 { 158 #ifdef __NetBSD__ /* XXX radeon platform bios */ 159 return false; 160 #else 161 uint8_t __iomem *bios; 162 size_t size; 163 164 rdev->bios = NULL; 165 166 bios = pci_platform_rom(rdev->pdev, &size); 167 if (!bios) { 168 return false; 169 } 170 171 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 172 return false; 173 } 174 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 175 if (rdev->bios == NULL) { 176 return false; 177 } 178 179 return true; 180 #endif 181 } 182 183 /* XXX radeon acpi */ 184 #ifdef CONFIG_ACPI 185 /* ATRM is used to get the BIOS on the discrete cards in 186 * dual-gpu systems. 187 */ 188 /* retrieve the ROM in 4k blocks */ 189 #define ATRM_BIOS_PAGE 4096 190 /** 191 * radeon_atrm_call - fetch a chunk of the vbios 192 * 193 * @atrm_handle: acpi ATRM handle 194 * @bios: vbios image pointer 195 * @offset: offset of vbios image data to fetch 196 * @len: length of vbios image data to fetch 197 * 198 * Executes ATRM to fetch a chunk of the discrete 199 * vbios image on PX systems (all asics). 200 * Returns the length of the buffer fetched. 201 */ 202 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 203 int offset, int len) 204 { 205 acpi_status status; 206 union acpi_object atrm_arg_elements[2], *obj; 207 struct acpi_object_list atrm_arg; 208 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 209 210 atrm_arg.count = 2; 211 atrm_arg.pointer = &atrm_arg_elements[0]; 212 213 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 214 atrm_arg_elements[0].integer.value = offset; 215 216 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 217 atrm_arg_elements[1].integer.value = len; 218 219 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 220 if (ACPI_FAILURE(status)) { 221 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 222 return -ENODEV; 223 } 224 225 obj = (union acpi_object *)buffer.pointer; 226 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 227 len = obj->buffer.length; 228 kfree(buffer.pointer); 229 return len; 230 } 231 232 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 233 { 234 int ret; 235 int size = 256 * 1024; 236 int i; 237 struct pci_dev *pdev = NULL; 238 acpi_handle dhandle, atrm_handle; 239 acpi_status status; 240 bool found = false; 241 242 /* ATRM is for the discrete card only */ 243 if (rdev->flags & RADEON_IS_IGP) 244 return false; 245 246 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 247 dhandle = ACPI_HANDLE(&pdev->dev); 248 if (!dhandle) 249 continue; 250 251 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 252 if (!ACPI_FAILURE(status)) { 253 found = true; 254 break; 255 } 256 } 257 258 if (!found) { 259 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 260 dhandle = ACPI_HANDLE(&pdev->dev); 261 if (!dhandle) 262 continue; 263 264 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 265 if (!ACPI_FAILURE(status)) { 266 found = true; 267 break; 268 } 269 } 270 } 271 272 if (!found) 273 return false; 274 275 rdev->bios = kmalloc(size, GFP_KERNEL); 276 if (!rdev->bios) { 277 DRM_ERROR("Unable to allocate bios\n"); 278 return false; 279 } 280 281 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 282 ret = radeon_atrm_call(atrm_handle, 283 rdev->bios, 284 (i * ATRM_BIOS_PAGE), 285 ATRM_BIOS_PAGE); 286 if (ret < ATRM_BIOS_PAGE) 287 break; 288 } 289 290 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 291 kfree(rdev->bios); 292 return false; 293 } 294 return true; 295 } 296 #else 297 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 298 { 299 return false; 300 } 301 #endif 302 303 static bool ni_read_disabled_bios(struct radeon_device *rdev) 304 { 305 u32 bus_cntl; 306 u32 d1vga_control; 307 u32 d2vga_control; 308 u32 vga_render_control; 309 u32 rom_cntl; 310 bool r; 311 312 bus_cntl = RREG32(R600_BUS_CNTL); 313 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 314 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 315 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 316 rom_cntl = RREG32(R600_ROM_CNTL); 317 318 /* enable the rom */ 319 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 320 if (!ASIC_IS_NODCE(rdev)) { 321 /* Disable VGA mode */ 322 WREG32(AVIVO_D1VGA_CONTROL, 323 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 324 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 325 WREG32(AVIVO_D2VGA_CONTROL, 326 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 327 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 328 WREG32(AVIVO_VGA_RENDER_CONTROL, 329 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 330 } 331 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 332 333 r = radeon_read_bios(rdev); 334 335 /* restore regs */ 336 WREG32(R600_BUS_CNTL, bus_cntl); 337 if (!ASIC_IS_NODCE(rdev)) { 338 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 339 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 340 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 341 } 342 WREG32(R600_ROM_CNTL, rom_cntl); 343 return r; 344 } 345 346 static bool r700_read_disabled_bios(struct radeon_device *rdev) 347 { 348 uint32_t viph_control; 349 uint32_t bus_cntl; 350 uint32_t d1vga_control; 351 uint32_t d2vga_control; 352 uint32_t vga_render_control; 353 uint32_t rom_cntl; 354 uint32_t cg_spll_func_cntl = 0; 355 uint32_t cg_spll_status; 356 bool r; 357 358 viph_control = RREG32(RADEON_VIPH_CONTROL); 359 bus_cntl = RREG32(R600_BUS_CNTL); 360 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 361 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 362 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 363 rom_cntl = RREG32(R600_ROM_CNTL); 364 365 /* disable VIP */ 366 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 367 /* enable the rom */ 368 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 369 /* Disable VGA mode */ 370 WREG32(AVIVO_D1VGA_CONTROL, 371 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 372 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 373 WREG32(AVIVO_D2VGA_CONTROL, 374 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 375 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 376 WREG32(AVIVO_VGA_RENDER_CONTROL, 377 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 378 379 if (rdev->family == CHIP_RV730) { 380 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 381 382 /* enable bypass mode */ 383 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 384 R600_SPLL_BYPASS_EN)); 385 386 /* wait for SPLL_CHG_STATUS to change to 1 */ 387 cg_spll_status = 0; 388 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 389 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 390 391 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 392 } else 393 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 394 395 r = radeon_read_bios(rdev); 396 397 /* restore regs */ 398 if (rdev->family == CHIP_RV730) { 399 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 400 401 /* wait for SPLL_CHG_STATUS to change to 1 */ 402 cg_spll_status = 0; 403 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 404 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 405 } 406 WREG32(RADEON_VIPH_CONTROL, viph_control); 407 WREG32(R600_BUS_CNTL, bus_cntl); 408 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 409 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 410 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 411 WREG32(R600_ROM_CNTL, rom_cntl); 412 return r; 413 } 414 415 static bool r600_read_disabled_bios(struct radeon_device *rdev) 416 { 417 uint32_t viph_control; 418 uint32_t bus_cntl; 419 uint32_t d1vga_control; 420 uint32_t d2vga_control; 421 uint32_t vga_render_control; 422 uint32_t rom_cntl; 423 uint32_t general_pwrmgt; 424 uint32_t low_vid_lower_gpio_cntl; 425 uint32_t medium_vid_lower_gpio_cntl; 426 uint32_t high_vid_lower_gpio_cntl; 427 uint32_t ctxsw_vid_lower_gpio_cntl; 428 uint32_t lower_gpio_enable; 429 bool r; 430 431 viph_control = RREG32(RADEON_VIPH_CONTROL); 432 bus_cntl = RREG32(R600_BUS_CNTL); 433 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 434 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 435 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 436 rom_cntl = RREG32(R600_ROM_CNTL); 437 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 438 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 439 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 440 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 441 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 442 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 443 444 /* disable VIP */ 445 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 446 /* enable the rom */ 447 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 448 /* Disable VGA mode */ 449 WREG32(AVIVO_D1VGA_CONTROL, 450 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 451 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 452 WREG32(AVIVO_D2VGA_CONTROL, 453 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 454 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 455 WREG32(AVIVO_VGA_RENDER_CONTROL, 456 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 457 458 WREG32(R600_ROM_CNTL, 459 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 460 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 461 R600_SCK_OVERWRITE)); 462 463 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 464 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 465 (low_vid_lower_gpio_cntl & ~0x400)); 466 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 467 (medium_vid_lower_gpio_cntl & ~0x400)); 468 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 469 (high_vid_lower_gpio_cntl & ~0x400)); 470 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 471 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 472 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 473 474 r = radeon_read_bios(rdev); 475 476 /* restore regs */ 477 WREG32(RADEON_VIPH_CONTROL, viph_control); 478 WREG32(R600_BUS_CNTL, bus_cntl); 479 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 480 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 481 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 482 WREG32(R600_ROM_CNTL, rom_cntl); 483 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 484 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 485 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 486 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 487 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 488 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 489 return r; 490 } 491 492 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 493 { 494 uint32_t seprom_cntl1; 495 uint32_t viph_control; 496 uint32_t bus_cntl; 497 uint32_t d1vga_control; 498 uint32_t d2vga_control; 499 uint32_t vga_render_control; 500 uint32_t gpiopad_a; 501 uint32_t gpiopad_en; 502 uint32_t gpiopad_mask; 503 bool r; 504 505 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 506 viph_control = RREG32(RADEON_VIPH_CONTROL); 507 bus_cntl = RREG32(RV370_BUS_CNTL); 508 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 509 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 510 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 511 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 512 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 513 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 514 515 WREG32(RADEON_SEPROM_CNTL1, 516 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 517 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 518 WREG32(RADEON_GPIOPAD_A, 0); 519 WREG32(RADEON_GPIOPAD_EN, 0); 520 WREG32(RADEON_GPIOPAD_MASK, 0); 521 522 /* disable VIP */ 523 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 524 525 /* enable the rom */ 526 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 527 528 /* Disable VGA mode */ 529 WREG32(AVIVO_D1VGA_CONTROL, 530 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 531 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 532 WREG32(AVIVO_D2VGA_CONTROL, 533 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 534 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 535 WREG32(AVIVO_VGA_RENDER_CONTROL, 536 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 537 538 r = radeon_read_bios(rdev); 539 540 /* restore regs */ 541 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 542 WREG32(RADEON_VIPH_CONTROL, viph_control); 543 WREG32(RV370_BUS_CNTL, bus_cntl); 544 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 545 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 546 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 547 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 548 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 549 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 550 return r; 551 } 552 553 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 554 { 555 uint32_t seprom_cntl1; 556 uint32_t viph_control; 557 uint32_t bus_cntl; 558 uint32_t crtc_gen_cntl; 559 uint32_t crtc2_gen_cntl; 560 uint32_t crtc_ext_cntl; 561 uint32_t fp2_gen_cntl; 562 bool r; 563 564 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 565 viph_control = RREG32(RADEON_VIPH_CONTROL); 566 if (rdev->flags & RADEON_IS_PCIE) 567 bus_cntl = RREG32(RV370_BUS_CNTL); 568 else 569 bus_cntl = RREG32(RADEON_BUS_CNTL); 570 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 571 crtc2_gen_cntl = 0; 572 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 573 fp2_gen_cntl = 0; 574 575 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 576 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 577 } 578 579 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 580 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 581 } 582 583 WREG32(RADEON_SEPROM_CNTL1, 584 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 585 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 586 587 /* disable VIP */ 588 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 589 590 /* enable the rom */ 591 if (rdev->flags & RADEON_IS_PCIE) 592 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 593 else 594 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 595 596 /* Turn off mem requests and CRTC for both controllers */ 597 WREG32(RADEON_CRTC_GEN_CNTL, 598 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 599 (RADEON_CRTC_DISP_REQ_EN_B | 600 RADEON_CRTC_EXT_DISP_EN))); 601 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 602 WREG32(RADEON_CRTC2_GEN_CNTL, 603 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 604 RADEON_CRTC2_DISP_REQ_EN_B)); 605 } 606 /* Turn off CRTC */ 607 WREG32(RADEON_CRTC_EXT_CNTL, 608 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 609 (RADEON_CRTC_SYNC_TRISTAT | 610 RADEON_CRTC_DISPLAY_DIS))); 611 612 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 613 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 614 } 615 616 r = radeon_read_bios(rdev); 617 618 /* restore regs */ 619 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 620 WREG32(RADEON_VIPH_CONTROL, viph_control); 621 if (rdev->flags & RADEON_IS_PCIE) 622 WREG32(RV370_BUS_CNTL, bus_cntl); 623 else 624 WREG32(RADEON_BUS_CNTL, bus_cntl); 625 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 626 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 627 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 628 } 629 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 630 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 631 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 632 } 633 return r; 634 } 635 636 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 637 { 638 if (rdev->flags & RADEON_IS_IGP) 639 return igp_read_bios_from_vram(rdev); 640 else if (rdev->family >= CHIP_BARTS) 641 return ni_read_disabled_bios(rdev); 642 else if (rdev->family >= CHIP_RV770) 643 return r700_read_disabled_bios(rdev); 644 else if (rdev->family >= CHIP_R600) 645 return r600_read_disabled_bios(rdev); 646 else if (rdev->family >= CHIP_RS600) 647 return avivo_read_disabled_bios(rdev); 648 else 649 return legacy_read_disabled_bios(rdev); 650 } 651 652 #ifdef CONFIG_ACPI 653 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 654 { 655 bool ret = false; 656 struct acpi_table_header *hdr; 657 acpi_size tbl_size; 658 UEFI_ACPI_VFCT *vfct; 659 GOP_VBIOS_CONTENT *vbios; 660 VFCT_IMAGE_HEADER *vhdr; 661 662 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 663 return false; 664 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 665 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 666 goto out_unmap; 667 } 668 669 vfct = (UEFI_ACPI_VFCT *)hdr; 670 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 671 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 672 goto out_unmap; 673 } 674 675 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 676 vhdr = &vbios->VbiosHeader; 677 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 678 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 679 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 680 681 if (vhdr->PCIBus != rdev->pdev->bus->number || 682 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 683 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 684 vhdr->VendorID != rdev->pdev->vendor || 685 vhdr->DeviceID != rdev->pdev->device) { 686 DRM_INFO("ACPI VFCT table is not for this card\n"); 687 goto out_unmap; 688 } 689 690 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 691 DRM_ERROR("ACPI VFCT image truncated\n"); 692 goto out_unmap; 693 } 694 695 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 696 ret = !!rdev->bios; 697 698 out_unmap: 699 return ret; 700 } 701 #else 702 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 703 { 704 return false; 705 } 706 #endif 707 708 bool radeon_get_bios(struct radeon_device *rdev) 709 { 710 bool r; 711 uint16_t tmp; 712 713 r = radeon_atrm_get_bios(rdev); 714 if (r == false) 715 r = radeon_acpi_vfct_bios(rdev); 716 if (r == false) 717 r = igp_read_bios_from_vram(rdev); 718 if (r == false) 719 r = radeon_read_bios(rdev); 720 if (r == false) 721 r = radeon_read_disabled_bios(rdev); 722 if (r == false) 723 r = radeon_read_platform_bios(rdev); 724 if (r == false || rdev->bios == NULL) { 725 DRM_ERROR("Unable to locate a BIOS ROM\n"); 726 rdev->bios = NULL; 727 return false; 728 } 729 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 730 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 731 goto free_bios; 732 } 733 734 tmp = RBIOS16(0x18); 735 if (RBIOS8(tmp + 0x14) != 0x0) { 736 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 737 goto free_bios; 738 } 739 740 rdev->bios_header_start = RBIOS16(0x48); 741 if (!rdev->bios_header_start) { 742 goto free_bios; 743 } 744 tmp = rdev->bios_header_start + 4; 745 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 746 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 747 rdev->is_atom_bios = true; 748 } else { 749 rdev->is_atom_bios = false; 750 } 751 752 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 753 return true; 754 free_bios: 755 kfree(rdev->bios); 756 rdev->bios = NULL; 757 return false; 758 } 759
Indexes created Sun Oct 26 20:09:54 GMT 2025