radeon_bios.c revision 1.4.18.2
1 /* $NetBSD: radeon_bios.c,v 1.4.18.2 2020/04/08 14:08:26 martin Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.4.18.2 2020/04/08 14:08:26 martin Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "atom.h" 37 38 #include <linux/slab.h> 39 #include <linux/acpi.h> 40 /* 41 * BIOS. 42 */ 43 44 /* If you boot an IGP board with a discrete card as the primary, 45 * the IGP rom is not accessible via the rom bar as the IGP rom is 46 * part of the system bios. On boot, the system bios puts a 47 * copy of the igp rom at the start of vram if a discrete card is 48 * present. 49 */ 50 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 51 { 52 #ifdef __NetBSD__ 53 bus_space_tag_t bst; 54 bus_space_handle_t bsh; 55 bus_size_t size; 56 #else 57 uint8_t __iomem *bios; 58 resource_size_t vram_base; 59 resource_size_t size = 256 * 1024; /* ??? */ 60 #endif 61 62 if (!(rdev->flags & RADEON_IS_IGP)) 63 if (!radeon_card_posted(rdev)) 64 return false; 65 66 rdev->bios = NULL; 67 #ifdef __NetBSD__ 68 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 69 /* XXX Dunno what type to expect here; fill me in... */ 70 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 71 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 72 0, &bst, &bsh, NULL, &size)) 73 return false; 74 if ((size == 0) || 75 (size < 256 * 1024) || 76 (bus_space_read_1(bst, bsh, 0) != 0x55) || 77 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 78 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 79 bus_space_unmap(bst, bsh, size); 80 return false; 81 } 82 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 83 bus_space_unmap(bst, bsh, size); 84 #else 85 vram_base = pci_resource_start(rdev->pdev, 0); 86 bios = ioremap(vram_base, size); 87 if (!bios) { 88 return false; 89 } 90 91 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 92 iounmap(bios); 93 return false; 94 } 95 rdev->bios = kmalloc(size, GFP_KERNEL); 96 if (rdev->bios == NULL) { 97 iounmap(bios); 98 return false; 99 } 100 memcpy_fromio(rdev->bios, bios, size); 101 iounmap(bios); 102 #endif 103 return true; 104 } 105 106 #ifdef __NetBSD__ 107 #define __iomem __pci_rom_iomem 108 #endif 109 110 static bool radeon_read_bios(struct radeon_device *rdev) 111 { 112 uint8_t __iomem *bios, val1, val2; 113 size_t size; 114 115 rdev->bios = NULL; 116 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 117 bios = pci_map_rom(rdev->pdev, &size); 118 if (!bios) { 119 return false; 120 } 121 122 #ifdef __NetBSD__ 123 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 124 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 125 126 val1 = bus_space_read_1(bst, bsh, 0); 127 val2 = bus_space_read_1(bst, bsh, 1); 128 #else 129 val1 = readb(&bios[0]); 130 val2 = readb(&bios[1]); 131 #endif 132 133 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 134 pci_unmap_rom(rdev->pdev, bios); 135 return false; 136 } 137 rdev->bios = kzalloc(size, GFP_KERNEL); 138 if (rdev->bios == NULL) { 139 pci_unmap_rom(rdev->pdev, bios); 140 return false; 141 } 142 #ifdef __NetBSD__ 143 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 144 #else 145 memcpy_fromio(rdev->bios, bios, size); 146 #endif 147 pci_unmap_rom(rdev->pdev, bios); 148 return true; 149 } 150 151 #ifdef __NetBSD__ 152 #undef __iomem 153 #endif 154 155 static bool radeon_read_platform_bios(struct radeon_device *rdev) 156 { 157 #ifdef __NetBSD__ /* XXX radeon platform bios */ 158 return false; 159 #else 160 uint8_t __iomem *bios; 161 size_t size; 162 163 rdev->bios = NULL; 164 165 bios = pci_platform_rom(rdev->pdev, &size); 166 if (!bios) { 167 return false; 168 } 169 170 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 171 return false; 172 } 173 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 174 if (rdev->bios == NULL) { 175 return false; 176 } 177 178 return true; 179 #endif 180 } 181 182 /* XXX radeon acpi */ 183 #ifdef CONFIG_ACPI 184 /* ATRM is used to get the BIOS on the discrete cards in 185 * dual-gpu systems. 186 */ 187 /* retrieve the ROM in 4k blocks */ 188 #define ATRM_BIOS_PAGE 4096 189 /** 190 * radeon_atrm_call - fetch a chunk of the vbios 191 * 192 * @atrm_handle: acpi ATRM handle 193 * @bios: vbios image pointer 194 * @offset: offset of vbios image data to fetch 195 * @len: length of vbios image data to fetch 196 * 197 * Executes ATRM to fetch a chunk of the discrete 198 * vbios image on PX systems (all asics). 199 * Returns the length of the buffer fetched. 200 */ 201 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 202 int offset, int len) 203 { 204 acpi_status status; 205 union acpi_object atrm_arg_elements[2], *obj; 206 struct acpi_object_list atrm_arg; 207 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 208 209 atrm_arg.count = 2; 210 atrm_arg.pointer = &atrm_arg_elements[0]; 211 212 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 213 atrm_arg_elements[0].integer.value = offset; 214 215 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 216 atrm_arg_elements[1].integer.value = len; 217 218 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 219 if (ACPI_FAILURE(status)) { 220 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 221 return -ENODEV; 222 } 223 224 obj = (union acpi_object *)buffer.pointer; 225 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 226 len = obj->buffer.length; 227 kfree(buffer.pointer); 228 return len; 229 } 230 231 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 232 { 233 int ret; 234 int size = 256 * 1024; 235 int i; 236 struct pci_dev *pdev = NULL; 237 acpi_handle dhandle, atrm_handle; 238 acpi_status status; 239 bool found = false; 240 241 /* ATRM is for the discrete card only */ 242 if (rdev->flags & RADEON_IS_IGP) 243 return false; 244 245 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 246 dhandle = ACPI_HANDLE(&pdev->dev); 247 if (!dhandle) 248 continue; 249 250 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 251 if (!ACPI_FAILURE(status)) { 252 found = true; 253 break; 254 } 255 } 256 257 if (!found) { 258 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 259 dhandle = ACPI_HANDLE(&pdev->dev); 260 if (!dhandle) 261 continue; 262 263 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 264 if (!ACPI_FAILURE(status)) { 265 found = true; 266 break; 267 } 268 } 269 } 270 271 if (!found) 272 return false; 273 274 rdev->bios = kmalloc(size, GFP_KERNEL); 275 if (!rdev->bios) { 276 DRM_ERROR("Unable to allocate bios\n"); 277 return false; 278 } 279 280 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 281 ret = radeon_atrm_call(atrm_handle, 282 rdev->bios, 283 (i * ATRM_BIOS_PAGE), 284 ATRM_BIOS_PAGE); 285 if (ret < ATRM_BIOS_PAGE) 286 break; 287 } 288 289 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 290 kfree(rdev->bios); 291 return false; 292 } 293 return true; 294 } 295 #else 296 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 297 { 298 return false; 299 } 300 #endif 301 302 static bool ni_read_disabled_bios(struct radeon_device *rdev) 303 { 304 u32 bus_cntl; 305 u32 d1vga_control; 306 u32 d2vga_control; 307 u32 vga_render_control; 308 u32 rom_cntl; 309 bool r; 310 311 bus_cntl = RREG32(R600_BUS_CNTL); 312 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 313 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 314 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 315 rom_cntl = RREG32(R600_ROM_CNTL); 316 317 /* enable the rom */ 318 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 319 if (!ASIC_IS_NODCE(rdev)) { 320 /* Disable VGA mode */ 321 WREG32(AVIVO_D1VGA_CONTROL, 322 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 323 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 324 WREG32(AVIVO_D2VGA_CONTROL, 325 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 326 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 327 WREG32(AVIVO_VGA_RENDER_CONTROL, 328 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 329 } 330 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 331 332 r = radeon_read_bios(rdev); 333 334 /* restore regs */ 335 WREG32(R600_BUS_CNTL, bus_cntl); 336 if (!ASIC_IS_NODCE(rdev)) { 337 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 338 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 339 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 340 } 341 WREG32(R600_ROM_CNTL, rom_cntl); 342 return r; 343 } 344 345 static bool r700_read_disabled_bios(struct radeon_device *rdev) 346 { 347 uint32_t viph_control; 348 uint32_t bus_cntl; 349 uint32_t d1vga_control; 350 uint32_t d2vga_control; 351 uint32_t vga_render_control; 352 uint32_t rom_cntl; 353 uint32_t cg_spll_func_cntl = 0; 354 uint32_t cg_spll_status; 355 bool r; 356 357 viph_control = RREG32(RADEON_VIPH_CONTROL); 358 bus_cntl = RREG32(R600_BUS_CNTL); 359 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 360 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 361 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 362 rom_cntl = RREG32(R600_ROM_CNTL); 363 364 /* disable VIP */ 365 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 366 /* enable the rom */ 367 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 368 /* Disable VGA mode */ 369 WREG32(AVIVO_D1VGA_CONTROL, 370 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 371 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 372 WREG32(AVIVO_D2VGA_CONTROL, 373 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 374 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 375 WREG32(AVIVO_VGA_RENDER_CONTROL, 376 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 377 378 if (rdev->family == CHIP_RV730) { 379 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 380 381 /* enable bypass mode */ 382 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 383 R600_SPLL_BYPASS_EN)); 384 385 /* wait for SPLL_CHG_STATUS to change to 1 */ 386 cg_spll_status = 0; 387 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 388 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 389 390 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 391 } else 392 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 393 394 r = radeon_read_bios(rdev); 395 396 /* restore regs */ 397 if (rdev->family == CHIP_RV730) { 398 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 399 400 /* wait for SPLL_CHG_STATUS to change to 1 */ 401 cg_spll_status = 0; 402 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 403 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 404 } 405 WREG32(RADEON_VIPH_CONTROL, viph_control); 406 WREG32(R600_BUS_CNTL, bus_cntl); 407 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 408 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 409 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 410 WREG32(R600_ROM_CNTL, rom_cntl); 411 return r; 412 } 413 414 static bool r600_read_disabled_bios(struct radeon_device *rdev) 415 { 416 uint32_t viph_control; 417 uint32_t bus_cntl; 418 uint32_t d1vga_control; 419 uint32_t d2vga_control; 420 uint32_t vga_render_control; 421 uint32_t rom_cntl; 422 uint32_t general_pwrmgt; 423 uint32_t low_vid_lower_gpio_cntl; 424 uint32_t medium_vid_lower_gpio_cntl; 425 uint32_t high_vid_lower_gpio_cntl; 426 uint32_t ctxsw_vid_lower_gpio_cntl; 427 uint32_t lower_gpio_enable; 428 bool r; 429 430 viph_control = RREG32(RADEON_VIPH_CONTROL); 431 bus_cntl = RREG32(R600_BUS_CNTL); 432 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 433 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 434 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 435 rom_cntl = RREG32(R600_ROM_CNTL); 436 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 437 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 438 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 439 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 440 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 441 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 442 443 /* disable VIP */ 444 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 445 /* enable the rom */ 446 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 447 /* Disable VGA mode */ 448 WREG32(AVIVO_D1VGA_CONTROL, 449 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 450 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 451 WREG32(AVIVO_D2VGA_CONTROL, 452 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 453 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 454 WREG32(AVIVO_VGA_RENDER_CONTROL, 455 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 456 457 WREG32(R600_ROM_CNTL, 458 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 459 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 460 R600_SCK_OVERWRITE)); 461 462 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 463 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 464 (low_vid_lower_gpio_cntl & ~0x400)); 465 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 466 (medium_vid_lower_gpio_cntl & ~0x400)); 467 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 468 (high_vid_lower_gpio_cntl & ~0x400)); 469 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 470 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 471 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 472 473 r = radeon_read_bios(rdev); 474 475 /* restore regs */ 476 WREG32(RADEON_VIPH_CONTROL, viph_control); 477 WREG32(R600_BUS_CNTL, bus_cntl); 478 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 479 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 480 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 481 WREG32(R600_ROM_CNTL, rom_cntl); 482 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 483 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 484 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 485 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 486 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 487 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 488 return r; 489 } 490 491 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 492 { 493 uint32_t seprom_cntl1; 494 uint32_t viph_control; 495 uint32_t bus_cntl; 496 uint32_t d1vga_control; 497 uint32_t d2vga_control; 498 uint32_t vga_render_control; 499 uint32_t gpiopad_a; 500 uint32_t gpiopad_en; 501 uint32_t gpiopad_mask; 502 bool r; 503 504 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 505 viph_control = RREG32(RADEON_VIPH_CONTROL); 506 bus_cntl = RREG32(RV370_BUS_CNTL); 507 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 508 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 509 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 510 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 511 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 512 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 513 514 WREG32(RADEON_SEPROM_CNTL1, 515 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 516 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 517 WREG32(RADEON_GPIOPAD_A, 0); 518 WREG32(RADEON_GPIOPAD_EN, 0); 519 WREG32(RADEON_GPIOPAD_MASK, 0); 520 521 /* disable VIP */ 522 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 523 524 /* enable the rom */ 525 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 526 527 /* Disable VGA mode */ 528 WREG32(AVIVO_D1VGA_CONTROL, 529 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 530 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 531 WREG32(AVIVO_D2VGA_CONTROL, 532 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 533 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 534 WREG32(AVIVO_VGA_RENDER_CONTROL, 535 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 536 537 r = radeon_read_bios(rdev); 538 539 /* restore regs */ 540 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 541 WREG32(RADEON_VIPH_CONTROL, viph_control); 542 WREG32(RV370_BUS_CNTL, bus_cntl); 543 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 544 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 545 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 546 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 547 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 548 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 549 return r; 550 } 551 552 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 553 { 554 uint32_t seprom_cntl1; 555 uint32_t viph_control; 556 uint32_t bus_cntl; 557 uint32_t crtc_gen_cntl; 558 uint32_t crtc2_gen_cntl; 559 uint32_t crtc_ext_cntl; 560 uint32_t fp2_gen_cntl; 561 bool r; 562 563 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 564 viph_control = RREG32(RADEON_VIPH_CONTROL); 565 if (rdev->flags & RADEON_IS_PCIE) 566 bus_cntl = RREG32(RV370_BUS_CNTL); 567 else 568 bus_cntl = RREG32(RADEON_BUS_CNTL); 569 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 570 crtc2_gen_cntl = 0; 571 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 572 fp2_gen_cntl = 0; 573 574 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 575 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 576 } 577 578 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 579 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 580 } 581 582 WREG32(RADEON_SEPROM_CNTL1, 583 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 584 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 585 586 /* disable VIP */ 587 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 588 589 /* enable the rom */ 590 if (rdev->flags & RADEON_IS_PCIE) 591 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 592 else 593 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 594 595 /* Turn off mem requests and CRTC for both controllers */ 596 WREG32(RADEON_CRTC_GEN_CNTL, 597 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 598 (RADEON_CRTC_DISP_REQ_EN_B | 599 RADEON_CRTC_EXT_DISP_EN))); 600 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 601 WREG32(RADEON_CRTC2_GEN_CNTL, 602 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 603 RADEON_CRTC2_DISP_REQ_EN_B)); 604 } 605 /* Turn off CRTC */ 606 WREG32(RADEON_CRTC_EXT_CNTL, 607 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 608 (RADEON_CRTC_SYNC_TRISTAT | 609 RADEON_CRTC_DISPLAY_DIS))); 610 611 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 612 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 613 } 614 615 r = radeon_read_bios(rdev); 616 617 /* restore regs */ 618 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 619 WREG32(RADEON_VIPH_CONTROL, viph_control); 620 if (rdev->flags & RADEON_IS_PCIE) 621 WREG32(RV370_BUS_CNTL, bus_cntl); 622 else 623 WREG32(RADEON_BUS_CNTL, bus_cntl); 624 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 625 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 626 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 627 } 628 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 629 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 630 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 631 } 632 return r; 633 } 634 635 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 636 { 637 if (rdev->flags & RADEON_IS_IGP) 638 return igp_read_bios_from_vram(rdev); 639 else if (rdev->family >= CHIP_BARTS) 640 return ni_read_disabled_bios(rdev); 641 else if (rdev->family >= CHIP_RV770) 642 return r700_read_disabled_bios(rdev); 643 else if (rdev->family >= CHIP_R600) 644 return r600_read_disabled_bios(rdev); 645 else if (rdev->family >= CHIP_RS600) 646 return avivo_read_disabled_bios(rdev); 647 else 648 return legacy_read_disabled_bios(rdev); 649 } 650 651 #ifdef CONFIG_ACPI 652 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 653 { 654 bool ret = false; 655 struct acpi_table_header *hdr; 656 acpi_size tbl_size; 657 UEFI_ACPI_VFCT *vfct; 658 GOP_VBIOS_CONTENT *vbios; 659 VFCT_IMAGE_HEADER *vhdr; 660 661 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 662 return false; 663 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 664 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 665 goto out_unmap; 666 } 667 668 vfct = (UEFI_ACPI_VFCT *)hdr; 669 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 670 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 671 goto out_unmap; 672 } 673 674 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 675 vhdr = &vbios->VbiosHeader; 676 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 677 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 678 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 679 680 if (vhdr->PCIBus != rdev->pdev->bus->number || 681 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 682 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 683 vhdr->VendorID != rdev->pdev->vendor || 684 vhdr->DeviceID != rdev->pdev->device) { 685 DRM_INFO("ACPI VFCT table is not for this card\n"); 686 goto out_unmap; 687 } 688 689 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 690 DRM_ERROR("ACPI VFCT image truncated\n"); 691 goto out_unmap; 692 } 693 694 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 695 ret = !!rdev->bios; 696 697 out_unmap: 698 return ret; 699 } 700 #else 701 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 702 { 703 return false; 704 } 705 #endif 706 707 bool radeon_get_bios(struct radeon_device *rdev) 708 { 709 bool r; 710 uint16_t tmp; 711 712 r = radeon_atrm_get_bios(rdev); 713 if (r == false) 714 r = radeon_acpi_vfct_bios(rdev); 715 if (r == false) 716 r = igp_read_bios_from_vram(rdev); 717 if (r == false) 718 r = radeon_read_bios(rdev); 719 if (r == false) 720 r = radeon_read_disabled_bios(rdev); 721 if (r == false) 722 r = radeon_read_platform_bios(rdev); 723 if (r == false || rdev->bios == NULL) { 724 DRM_ERROR("Unable to locate a BIOS ROM\n"); 725 rdev->bios = NULL; 726 return false; 727 } 728 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 729 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 730 goto free_bios; 731 } 732 733 tmp = RBIOS16(0x18); 734 if (RBIOS8(tmp + 0x14) != 0x0) { 735 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 736 goto free_bios; 737 } 738 739 rdev->bios_header_start = RBIOS16(0x48); 740 if (!rdev->bios_header_start) { 741 goto free_bios; 742 } 743 tmp = rdev->bios_header_start + 4; 744 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 745 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 746 rdev->is_atom_bios = true; 747 } else { 748 rdev->is_atom_bios = false; 749 } 750 751 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 752 return true; 753 free_bios: 754 kfree(rdev->bios); 755 rdev->bios = NULL; 756 return false; 757 } 758
Indexes created Sun Oct 26 20:09:54 GMT 2025