radeon_bios.c revision 1.5
1 /* $NetBSD: radeon_bios.c,v 1.5 2018/08/27 04:58:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.5 2018/08/27 04:58:36 riastradh Exp $"); 32 33 #include <drm/drmP.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "atom.h" 37 38 #include <linux/slab.h> 39 #include <linux/acpi.h> 40 #include <linux/string.h> 41 /* 42 * BIOS. 43 */ 44 45 /* If you boot an IGP board with a discrete card as the primary, 46 * the IGP rom is not accessible via the rom bar as the IGP rom is 47 * part of the system bios. On boot, the system bios puts a 48 * copy of the igp rom at the start of vram if a discrete card is 49 * present. 50 */ 51 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 52 { 53 #ifdef __NetBSD__ 54 bus_space_tag_t bst; 55 bus_space_handle_t bsh; 56 bus_size_t size; 57 #else 58 uint8_t __iomem *bios; 59 resource_size_t vram_base; 60 resource_size_t size = 256 * 1024; /* ??? */ 61 #endif 62 63 if (!(rdev->flags & RADEON_IS_IGP)) 64 if (!radeon_card_posted(rdev)) 65 return false; 66 67 rdev->bios = NULL; 68 #ifdef __NetBSD__ 69 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 70 /* XXX Dunno what type to expect here; fill me in... */ 71 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 72 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 73 0, &bst, &bsh, NULL, &size)) 74 return false; 75 if ((size == 0) || 76 (size < 256 * 1024) || 77 (bus_space_read_1(bst, bsh, 0) != 0x55) || 78 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 79 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 80 bus_space_unmap(bst, bsh, size); 81 return false; 82 } 83 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 84 bus_space_unmap(bst, bsh, size); 85 #else 86 vram_base = pci_resource_start(rdev->pdev, 0); 87 bios = ioremap(vram_base, size); 88 if (!bios) { 89 return false; 90 } 91 92 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 93 iounmap(bios); 94 return false; 95 } 96 rdev->bios = kmalloc(size, GFP_KERNEL); 97 if (rdev->bios == NULL) { 98 iounmap(bios); 99 return false; 100 } 101 memcpy_fromio(rdev->bios, bios, size); 102 iounmap(bios); 103 #endif 104 return true; 105 } 106 107 #ifdef __NetBSD__ 108 #define __iomem __pci_rom_iomem 109 #endif 110 111 static bool radeon_read_bios(struct radeon_device *rdev) 112 { 113 #ifdef __NetBSD__ 114 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 115 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 116 #endif 117 uint8_t __iomem *bios, val1, val2; 118 size_t size; 119 120 rdev->bios = NULL; 121 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 122 bios = pci_map_rom(rdev->pdev, &size); 123 if (!bios) { 124 return false; 125 } 126 127 #ifdef __NetBSD__ 128 val1 = bus_space_read_1(bst, bsh, 0); 129 val2 = bus_space_read_1(bst, bsh, 1); 130 #else 131 val1 = readb(&bios[0]); 132 val2 = readb(&bios[1]); 133 #endif 134 135 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 136 pci_unmap_rom(rdev->pdev, bios); 137 return false; 138 } 139 rdev->bios = kzalloc(size, GFP_KERNEL); 140 if (rdev->bios == NULL) { 141 pci_unmap_rom(rdev->pdev, bios); 142 return false; 143 } 144 #ifdef __NetBSD__ 145 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 146 #else 147 memcpy_fromio(rdev->bios, bios, size); 148 #endif 149 pci_unmap_rom(rdev->pdev, bios); 150 return true; 151 } 152 153 #ifdef __NetBSD__ 154 #undef __iomem 155 #endif 156 157 static bool radeon_read_platform_bios(struct radeon_device *rdev) 158 { 159 #ifdef __NetBSD__ /* XXX radeon platform bios */ 160 return false; 161 #else 162 uint8_t __iomem *bios; 163 size_t size; 164 165 rdev->bios = NULL; 166 167 bios = pci_platform_rom(rdev->pdev, &size); 168 if (!bios) { 169 return false; 170 } 171 172 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 173 return false; 174 } 175 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 176 if (rdev->bios == NULL) { 177 return false; 178 } 179 180 return true; 181 #endif 182 } 183 184 /* XXX radeon acpi */ 185 #ifdef CONFIG_ACPI 186 /* ATRM is used to get the BIOS on the discrete cards in 187 * dual-gpu systems. 188 */ 189 /* retrieve the ROM in 4k blocks */ 190 #define ATRM_BIOS_PAGE 4096 191 /** 192 * radeon_atrm_call - fetch a chunk of the vbios 193 * 194 * @atrm_handle: acpi ATRM handle 195 * @bios: vbios image pointer 196 * @offset: offset of vbios image data to fetch 197 * @len: length of vbios image data to fetch 198 * 199 * Executes ATRM to fetch a chunk of the discrete 200 * vbios image on PX systems (all asics). 201 * Returns the length of the buffer fetched. 202 */ 203 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 204 int offset, int len) 205 { 206 acpi_status status; 207 union acpi_object atrm_arg_elements[2], *obj; 208 struct acpi_object_list atrm_arg; 209 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 210 211 atrm_arg.count = 2; 212 atrm_arg.pointer = &atrm_arg_elements[0]; 213 214 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 215 atrm_arg_elements[0].integer.value = offset; 216 217 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 218 atrm_arg_elements[1].integer.value = len; 219 220 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 221 if (ACPI_FAILURE(status)) { 222 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 223 return -ENODEV; 224 } 225 226 obj = (union acpi_object *)buffer.pointer; 227 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 228 len = obj->buffer.length; 229 kfree(buffer.pointer); 230 return len; 231 } 232 233 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 234 { 235 int ret; 236 int size = 256 * 1024; 237 int i; 238 struct pci_dev *pdev = NULL; 239 acpi_handle dhandle, atrm_handle; 240 acpi_status status; 241 bool found = false; 242 243 /* ATRM is for the discrete card only */ 244 if (rdev->flags & RADEON_IS_IGP) 245 return false; 246 247 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 248 dhandle = ACPI_HANDLE(&pdev->dev); 249 if (!dhandle) 250 continue; 251 252 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 253 if (!ACPI_FAILURE(status)) { 254 found = true; 255 break; 256 } 257 } 258 259 if (!found) { 260 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 261 dhandle = ACPI_HANDLE(&pdev->dev); 262 if (!dhandle) 263 continue; 264 265 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 266 if (!ACPI_FAILURE(status)) { 267 found = true; 268 break; 269 } 270 } 271 } 272 273 if (!found) 274 return false; 275 276 rdev->bios = kmalloc(size, GFP_KERNEL); 277 if (!rdev->bios) { 278 DRM_ERROR("Unable to allocate bios\n"); 279 return false; 280 } 281 282 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 283 ret = radeon_atrm_call(atrm_handle, 284 rdev->bios, 285 (i * ATRM_BIOS_PAGE), 286 ATRM_BIOS_PAGE); 287 if (ret < ATRM_BIOS_PAGE) 288 break; 289 } 290 291 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 292 kfree(rdev->bios); 293 return false; 294 } 295 return true; 296 } 297 #else 298 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 299 { 300 return false; 301 } 302 #endif 303 304 static bool ni_read_disabled_bios(struct radeon_device *rdev) 305 { 306 u32 bus_cntl; 307 u32 d1vga_control; 308 u32 d2vga_control; 309 u32 vga_render_control; 310 u32 rom_cntl; 311 bool r; 312 313 bus_cntl = RREG32(R600_BUS_CNTL); 314 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 315 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 316 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 317 rom_cntl = RREG32(R600_ROM_CNTL); 318 319 /* enable the rom */ 320 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 321 if (!ASIC_IS_NODCE(rdev)) { 322 /* Disable VGA mode */ 323 WREG32(AVIVO_D1VGA_CONTROL, 324 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 325 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 326 WREG32(AVIVO_D2VGA_CONTROL, 327 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 328 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 329 WREG32(AVIVO_VGA_RENDER_CONTROL, 330 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 331 } 332 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 333 334 r = radeon_read_bios(rdev); 335 336 /* restore regs */ 337 WREG32(R600_BUS_CNTL, bus_cntl); 338 if (!ASIC_IS_NODCE(rdev)) { 339 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 340 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 341 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 342 } 343 WREG32(R600_ROM_CNTL, rom_cntl); 344 return r; 345 } 346 347 static bool r700_read_disabled_bios(struct radeon_device *rdev) 348 { 349 uint32_t viph_control; 350 uint32_t bus_cntl; 351 uint32_t d1vga_control; 352 uint32_t d2vga_control; 353 uint32_t vga_render_control; 354 uint32_t rom_cntl; 355 uint32_t cg_spll_func_cntl = 0; 356 uint32_t cg_spll_status; 357 bool r; 358 359 viph_control = RREG32(RADEON_VIPH_CONTROL); 360 bus_cntl = RREG32(R600_BUS_CNTL); 361 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 362 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 363 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 364 rom_cntl = RREG32(R600_ROM_CNTL); 365 366 /* disable VIP */ 367 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 368 /* enable the rom */ 369 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 370 /* Disable VGA mode */ 371 WREG32(AVIVO_D1VGA_CONTROL, 372 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 373 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 374 WREG32(AVIVO_D2VGA_CONTROL, 375 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 376 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 377 WREG32(AVIVO_VGA_RENDER_CONTROL, 378 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 379 380 if (rdev->family == CHIP_RV730) { 381 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 382 383 /* enable bypass mode */ 384 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 385 R600_SPLL_BYPASS_EN)); 386 387 /* wait for SPLL_CHG_STATUS to change to 1 */ 388 cg_spll_status = 0; 389 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 390 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 391 392 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 393 } else 394 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 395 396 r = radeon_read_bios(rdev); 397 398 /* restore regs */ 399 if (rdev->family == CHIP_RV730) { 400 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 401 402 /* wait for SPLL_CHG_STATUS to change to 1 */ 403 cg_spll_status = 0; 404 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 405 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 406 } 407 WREG32(RADEON_VIPH_CONTROL, viph_control); 408 WREG32(R600_BUS_CNTL, bus_cntl); 409 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 410 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 411 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 412 WREG32(R600_ROM_CNTL, rom_cntl); 413 return r; 414 } 415 416 static bool r600_read_disabled_bios(struct radeon_device *rdev) 417 { 418 uint32_t viph_control; 419 uint32_t bus_cntl; 420 uint32_t d1vga_control; 421 uint32_t d2vga_control; 422 uint32_t vga_render_control; 423 uint32_t rom_cntl; 424 uint32_t general_pwrmgt; 425 uint32_t low_vid_lower_gpio_cntl; 426 uint32_t medium_vid_lower_gpio_cntl; 427 uint32_t high_vid_lower_gpio_cntl; 428 uint32_t ctxsw_vid_lower_gpio_cntl; 429 uint32_t lower_gpio_enable; 430 bool r; 431 432 viph_control = RREG32(RADEON_VIPH_CONTROL); 433 bus_cntl = RREG32(R600_BUS_CNTL); 434 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 435 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 436 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 437 rom_cntl = RREG32(R600_ROM_CNTL); 438 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 439 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 440 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 441 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 442 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 443 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 444 445 /* disable VIP */ 446 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 447 /* enable the rom */ 448 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 449 /* Disable VGA mode */ 450 WREG32(AVIVO_D1VGA_CONTROL, 451 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 452 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 453 WREG32(AVIVO_D2VGA_CONTROL, 454 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 455 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 456 WREG32(AVIVO_VGA_RENDER_CONTROL, 457 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 458 459 WREG32(R600_ROM_CNTL, 460 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 461 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 462 R600_SCK_OVERWRITE)); 463 464 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 465 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 466 (low_vid_lower_gpio_cntl & ~0x400)); 467 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 468 (medium_vid_lower_gpio_cntl & ~0x400)); 469 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 470 (high_vid_lower_gpio_cntl & ~0x400)); 471 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 472 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 473 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 474 475 r = radeon_read_bios(rdev); 476 477 /* restore regs */ 478 WREG32(RADEON_VIPH_CONTROL, viph_control); 479 WREG32(R600_BUS_CNTL, bus_cntl); 480 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 481 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 482 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 483 WREG32(R600_ROM_CNTL, rom_cntl); 484 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 485 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 486 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 487 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 488 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 489 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 490 return r; 491 } 492 493 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 494 { 495 uint32_t seprom_cntl1; 496 uint32_t viph_control; 497 uint32_t bus_cntl; 498 uint32_t d1vga_control; 499 uint32_t d2vga_control; 500 uint32_t vga_render_control; 501 uint32_t gpiopad_a; 502 uint32_t gpiopad_en; 503 uint32_t gpiopad_mask; 504 bool r; 505 506 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 507 viph_control = RREG32(RADEON_VIPH_CONTROL); 508 bus_cntl = RREG32(RV370_BUS_CNTL); 509 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 510 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 511 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 512 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 513 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 514 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 515 516 WREG32(RADEON_SEPROM_CNTL1, 517 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 518 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 519 WREG32(RADEON_GPIOPAD_A, 0); 520 WREG32(RADEON_GPIOPAD_EN, 0); 521 WREG32(RADEON_GPIOPAD_MASK, 0); 522 523 /* disable VIP */ 524 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 525 526 /* enable the rom */ 527 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 528 529 /* Disable VGA mode */ 530 WREG32(AVIVO_D1VGA_CONTROL, 531 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 532 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 533 WREG32(AVIVO_D2VGA_CONTROL, 534 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 535 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 536 WREG32(AVIVO_VGA_RENDER_CONTROL, 537 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 538 539 r = radeon_read_bios(rdev); 540 541 /* restore regs */ 542 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 543 WREG32(RADEON_VIPH_CONTROL, viph_control); 544 WREG32(RV370_BUS_CNTL, bus_cntl); 545 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 546 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 547 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 548 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 549 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 550 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 551 return r; 552 } 553 554 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 555 { 556 uint32_t seprom_cntl1; 557 uint32_t viph_control; 558 uint32_t bus_cntl; 559 uint32_t crtc_gen_cntl; 560 uint32_t crtc2_gen_cntl; 561 uint32_t crtc_ext_cntl; 562 uint32_t fp2_gen_cntl; 563 bool r; 564 565 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 566 viph_control = RREG32(RADEON_VIPH_CONTROL); 567 if (rdev->flags & RADEON_IS_PCIE) 568 bus_cntl = RREG32(RV370_BUS_CNTL); 569 else 570 bus_cntl = RREG32(RADEON_BUS_CNTL); 571 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 572 crtc2_gen_cntl = 0; 573 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 574 fp2_gen_cntl = 0; 575 576 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 577 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 578 } 579 580 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 581 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 582 } 583 584 WREG32(RADEON_SEPROM_CNTL1, 585 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 586 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 587 588 /* disable VIP */ 589 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 590 591 /* enable the rom */ 592 if (rdev->flags & RADEON_IS_PCIE) 593 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 594 else 595 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 596 597 /* Turn off mem requests and CRTC for both controllers */ 598 WREG32(RADEON_CRTC_GEN_CNTL, 599 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 600 (RADEON_CRTC_DISP_REQ_EN_B | 601 RADEON_CRTC_EXT_DISP_EN))); 602 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 603 WREG32(RADEON_CRTC2_GEN_CNTL, 604 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 605 RADEON_CRTC2_DISP_REQ_EN_B)); 606 } 607 /* Turn off CRTC */ 608 WREG32(RADEON_CRTC_EXT_CNTL, 609 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 610 (RADEON_CRTC_SYNC_TRISTAT | 611 RADEON_CRTC_DISPLAY_DIS))); 612 613 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 614 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 615 } 616 617 r = radeon_read_bios(rdev); 618 619 /* restore regs */ 620 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 621 WREG32(RADEON_VIPH_CONTROL, viph_control); 622 if (rdev->flags & RADEON_IS_PCIE) 623 WREG32(RV370_BUS_CNTL, bus_cntl); 624 else 625 WREG32(RADEON_BUS_CNTL, bus_cntl); 626 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 627 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 628 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 629 } 630 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 631 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 632 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 633 } 634 return r; 635 } 636 637 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 638 { 639 if (rdev->flags & RADEON_IS_IGP) 640 return igp_read_bios_from_vram(rdev); 641 else if (rdev->family >= CHIP_BARTS) 642 return ni_read_disabled_bios(rdev); 643 else if (rdev->family >= CHIP_RV770) 644 return r700_read_disabled_bios(rdev); 645 else if (rdev->family >= CHIP_R600) 646 return r600_read_disabled_bios(rdev); 647 else if (rdev->family >= CHIP_RS600) 648 return avivo_read_disabled_bios(rdev); 649 else 650 return legacy_read_disabled_bios(rdev); 651 } 652 653 #ifdef CONFIG_ACPI 654 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 655 { 656 bool ret = false; 657 struct acpi_table_header *hdr; 658 acpi_size tbl_size; 659 UEFI_ACPI_VFCT *vfct; 660 GOP_VBIOS_CONTENT *vbios; 661 VFCT_IMAGE_HEADER *vhdr; 662 663 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 664 return false; 665 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 666 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 667 goto out_unmap; 668 } 669 670 vfct = (UEFI_ACPI_VFCT *)hdr; 671 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 672 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 673 goto out_unmap; 674 } 675 676 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 677 vhdr = &vbios->VbiosHeader; 678 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 679 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 680 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 681 682 if (vhdr->PCIBus != rdev->pdev->bus->number || 683 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 684 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 685 vhdr->VendorID != rdev->pdev->vendor || 686 vhdr->DeviceID != rdev->pdev->device) { 687 DRM_INFO("ACPI VFCT table is not for this card\n"); 688 goto out_unmap; 689 } 690 691 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 692 DRM_ERROR("ACPI VFCT image truncated\n"); 693 goto out_unmap; 694 } 695 696 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 697 ret = !!rdev->bios; 698 699 out_unmap: 700 return ret; 701 } 702 #else 703 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 704 { 705 return false; 706 } 707 #endif 708 709 bool radeon_get_bios(struct radeon_device *rdev) 710 { 711 bool r; 712 uint16_t tmp; 713 714 r = radeon_atrm_get_bios(rdev); 715 if (r == false) 716 r = radeon_acpi_vfct_bios(rdev); 717 if (r == false) 718 r = igp_read_bios_from_vram(rdev); 719 if (r == false) 720 r = radeon_read_bios(rdev); 721 if (r == false) 722 r = radeon_read_disabled_bios(rdev); 723 if (r == false) 724 r = radeon_read_platform_bios(rdev); 725 if (r == false || rdev->bios == NULL) { 726 DRM_ERROR("Unable to locate a BIOS ROM\n"); 727 rdev->bios = NULL; 728 return false; 729 } 730 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 731 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 732 goto free_bios; 733 } 734 735 tmp = RBIOS16(0x18); 736 if (RBIOS8(tmp + 0x14) != 0x0) { 737 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 738 goto free_bios; 739 } 740 741 rdev->bios_header_start = RBIOS16(0x48); 742 if (!rdev->bios_header_start) { 743 goto free_bios; 744 } 745 tmp = rdev->bios_header_start + 4; 746 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 747 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 748 rdev->is_atom_bios = true; 749 } else { 750 rdev->is_atom_bios = false; 751 } 752 753 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 754 return true; 755 free_bios: 756 kfree(rdev->bios); 757 rdev->bios = NULL; 758 return false; 759 } 760
Indexes created Tue Oct 28 12:10:06 GMT 2025