radeon_bios.c revision 1.8
1 /* $NetBSD: radeon_bios.c,v 1.8 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_bios.c,v 1.8 2021/12/18 23:45:43 riastradh Exp $"); 33 34 #include <linux/acpi.h> 35 #include <linux/pci.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_device.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_reg.h" 43 44 /* 45 * BIOS. 46 */ 47 48 /* If you boot an IGP board with a discrete card as the primary, 49 * the IGP rom is not accessible via the rom bar as the IGP rom is 50 * part of the system bios. On boot, the system bios puts a 51 * copy of the igp rom at the start of vram if a discrete card is 52 * present. 53 */ 54 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 55 { 56 #ifdef __NetBSD__ 57 bus_space_tag_t bst; 58 bus_space_handle_t bsh; 59 bus_size_t size; 60 #else 61 uint8_t __iomem *bios; 62 resource_size_t vram_base; 63 resource_size_t size = 256 * 1024; /* ??? */ 64 #endif 65 66 if (!(rdev->flags & RADEON_IS_IGP)) 67 if (!radeon_card_posted(rdev)) 68 return false; 69 70 rdev->bios = NULL; 71 #ifdef __NetBSD__ 72 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(0), 73 /* XXX Dunno what type to expect here; fill me in... */ 74 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 75 rdev->pdev->pd_pa.pa_tag, PCI_BAR(0)), 76 0, &bst, &bsh, NULL, &size)) 77 return false; 78 if ((size == 0) || 79 (size < 256 * 1024) || 80 (bus_space_read_1(bst, bsh, 0) != 0x55) || 81 (bus_space_read_1(bst, bsh, 1) != 0xaa) || 82 ((rdev->bios = kmalloc(size, GFP_KERNEL)) == NULL)) { 83 bus_space_unmap(bst, bsh, size); 84 return false; 85 } 86 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 87 bus_space_unmap(bst, bsh, size); 88 #else 89 vram_base = pci_resource_start(rdev->pdev, 0); 90 bios = ioremap(vram_base, size); 91 if (!bios) { 92 return false; 93 } 94 95 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 96 iounmap(bios); 97 return false; 98 } 99 rdev->bios = kmalloc(size, GFP_KERNEL); 100 if (rdev->bios == NULL) { 101 iounmap(bios); 102 return false; 103 } 104 memcpy_fromio(rdev->bios, bios, size); 105 iounmap(bios); 106 #endif 107 return true; 108 } 109 110 #ifdef __NetBSD__ 111 #define __iomem __pci_rom_iomem 112 #endif 113 114 static bool radeon_read_bios(struct radeon_device *rdev) 115 { 116 uint8_t __iomem *bios, val1, val2; 117 size_t size; 118 119 rdev->bios = NULL; 120 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 121 bios = pci_map_rom(rdev->pdev, &size); 122 if (!bios) { 123 return false; 124 } 125 126 #ifdef __NetBSD__ 127 const bus_space_tag_t bst = rdev->pdev->pd_rom_bst; 128 const bus_space_handle_t bsh = rdev->pdev->pd_rom_found_bsh; 129 130 val1 = bus_space_read_1(bst, bsh, 0); 131 val2 = bus_space_read_1(bst, bsh, 1); 132 #else 133 val1 = readb(&bios[0]); 134 val2 = readb(&bios[1]); 135 #endif 136 137 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 138 pci_unmap_rom(rdev->pdev, bios); 139 return false; 140 } 141 rdev->bios = kzalloc(size, GFP_KERNEL); 142 if (rdev->bios == NULL) { 143 pci_unmap_rom(rdev->pdev, bios); 144 return false; 145 } 146 #ifdef __NetBSD__ 147 bus_space_read_region_1(bst, bsh, 0, rdev->bios, size); 148 #else 149 memcpy_fromio(rdev->bios, bios, size); 150 #endif 151 pci_unmap_rom(rdev->pdev, bios); 152 return true; 153 } 154 155 #ifdef __NetBSD__ 156 #undef __iomem 157 #endif 158 159 static bool radeon_read_platform_bios(struct radeon_device *rdev) 160 { 161 #ifdef __NetBSD__ /* XXX radeon platform bios */ 162 return false; 163 #else 164 uint8_t __iomem *bios; 165 size_t size; 166 167 rdev->bios = NULL; 168 169 bios = pci_platform_rom(rdev->pdev, &size); 170 if (!bios) { 171 return false; 172 } 173 174 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 175 return false; 176 } 177 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 178 if (rdev->bios == NULL) { 179 return false; 180 } 181 182 return true; 183 #endif 184 } 185 186 /* XXX radeon acpi */ 187 #ifdef CONFIG_ACPI 188 /* ATRM is used to get the BIOS on the discrete cards in 189 * dual-gpu systems. 190 */ 191 /* retrieve the ROM in 4k blocks */ 192 #define ATRM_BIOS_PAGE 4096 193 /** 194 * radeon_atrm_call - fetch a chunk of the vbios 195 * 196 * @atrm_handle: acpi ATRM handle 197 * @bios: vbios image pointer 198 * @offset: offset of vbios image data to fetch 199 * @len: length of vbios image data to fetch 200 * 201 * Executes ATRM to fetch a chunk of the discrete 202 * vbios image on PX systems (all asics). 203 * Returns the length of the buffer fetched. 204 */ 205 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 206 int offset, int len) 207 { 208 acpi_status status; 209 union acpi_object atrm_arg_elements[2], *obj; 210 struct acpi_object_list atrm_arg; 211 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 212 213 atrm_arg.count = 2; 214 atrm_arg.pointer = &atrm_arg_elements[0]; 215 216 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 217 atrm_arg_elements[0].integer.value = offset; 218 219 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 220 atrm_arg_elements[1].integer.value = len; 221 222 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 223 if (ACPI_FAILURE(status)) { 224 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 225 return -ENODEV; 226 } 227 228 obj = (union acpi_object *)buffer.pointer; 229 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 230 len = obj->buffer.length; 231 kfree(buffer.pointer); 232 return len; 233 } 234 235 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 236 { 237 int ret; 238 int size = 256 * 1024; 239 int i; 240 struct pci_dev *pdev = NULL; 241 acpi_handle dhandle, atrm_handle; 242 acpi_status status; 243 bool found = false; 244 245 /* ATRM is for the discrete card only */ 246 if (rdev->flags & RADEON_IS_IGP) 247 return false; 248 249 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 250 dhandle = ACPI_HANDLE(&pdev->dev); 251 if (!dhandle) 252 continue; 253 254 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 255 if (!ACPI_FAILURE(status)) { 256 found = true; 257 break; 258 } 259 } 260 261 if (!found) { 262 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 263 dhandle = ACPI_HANDLE(&pdev->dev); 264 if (!dhandle) 265 continue; 266 267 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 268 if (!ACPI_FAILURE(status)) { 269 found = true; 270 break; 271 } 272 } 273 } 274 275 if (!found) 276 return false; 277 278 rdev->bios = kmalloc(size, GFP_KERNEL); 279 if (!rdev->bios) { 280 DRM_ERROR("Unable to allocate bios\n"); 281 return false; 282 } 283 284 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 285 ret = radeon_atrm_call(atrm_handle, 286 rdev->bios, 287 (i * ATRM_BIOS_PAGE), 288 ATRM_BIOS_PAGE); 289 if (ret < ATRM_BIOS_PAGE) 290 break; 291 } 292 293 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 294 kfree(rdev->bios); 295 return false; 296 } 297 return true; 298 } 299 #else 300 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 301 { 302 return false; 303 } 304 #endif 305 306 static bool ni_read_disabled_bios(struct radeon_device *rdev) 307 { 308 u32 bus_cntl; 309 u32 d1vga_control; 310 u32 d2vga_control; 311 u32 vga_render_control; 312 u32 rom_cntl; 313 bool r; 314 315 bus_cntl = RREG32(R600_BUS_CNTL); 316 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 317 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 318 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 319 rom_cntl = RREG32(R600_ROM_CNTL); 320 321 /* enable the rom */ 322 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 323 if (!ASIC_IS_NODCE(rdev)) { 324 /* Disable VGA mode */ 325 WREG32(AVIVO_D1VGA_CONTROL, 326 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 327 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 328 WREG32(AVIVO_D2VGA_CONTROL, 329 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 330 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 331 WREG32(AVIVO_VGA_RENDER_CONTROL, 332 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 333 } 334 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 335 336 r = radeon_read_bios(rdev); 337 338 /* restore regs */ 339 WREG32(R600_BUS_CNTL, bus_cntl); 340 if (!ASIC_IS_NODCE(rdev)) { 341 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 342 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 343 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 344 } 345 WREG32(R600_ROM_CNTL, rom_cntl); 346 return r; 347 } 348 349 static bool r700_read_disabled_bios(struct radeon_device *rdev) 350 { 351 uint32_t viph_control; 352 uint32_t bus_cntl; 353 uint32_t d1vga_control; 354 uint32_t d2vga_control; 355 uint32_t vga_render_control; 356 uint32_t rom_cntl; 357 uint32_t cg_spll_func_cntl = 0; 358 uint32_t cg_spll_status; 359 bool r; 360 361 viph_control = RREG32(RADEON_VIPH_CONTROL); 362 bus_cntl = RREG32(R600_BUS_CNTL); 363 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 364 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 365 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 366 rom_cntl = RREG32(R600_ROM_CNTL); 367 368 /* disable VIP */ 369 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 370 /* enable the rom */ 371 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 372 /* Disable VGA mode */ 373 WREG32(AVIVO_D1VGA_CONTROL, 374 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 375 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 376 WREG32(AVIVO_D2VGA_CONTROL, 377 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 378 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 379 WREG32(AVIVO_VGA_RENDER_CONTROL, 380 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 381 382 if (rdev->family == CHIP_RV730) { 383 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 384 385 /* enable bypass mode */ 386 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 387 R600_SPLL_BYPASS_EN)); 388 389 /* wait for SPLL_CHG_STATUS to change to 1 */ 390 cg_spll_status = 0; 391 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 392 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 393 394 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 395 } else 396 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 397 398 r = radeon_read_bios(rdev); 399 400 /* restore regs */ 401 if (rdev->family == CHIP_RV730) { 402 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 403 404 /* wait for SPLL_CHG_STATUS to change to 1 */ 405 cg_spll_status = 0; 406 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 407 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 408 } 409 WREG32(RADEON_VIPH_CONTROL, viph_control); 410 WREG32(R600_BUS_CNTL, bus_cntl); 411 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 412 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 413 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 414 WREG32(R600_ROM_CNTL, rom_cntl); 415 return r; 416 } 417 418 static bool r600_read_disabled_bios(struct radeon_device *rdev) 419 { 420 uint32_t viph_control; 421 uint32_t bus_cntl; 422 uint32_t d1vga_control; 423 uint32_t d2vga_control; 424 uint32_t vga_render_control; 425 uint32_t rom_cntl; 426 uint32_t general_pwrmgt; 427 uint32_t low_vid_lower_gpio_cntl; 428 uint32_t medium_vid_lower_gpio_cntl; 429 uint32_t high_vid_lower_gpio_cntl; 430 uint32_t ctxsw_vid_lower_gpio_cntl; 431 uint32_t lower_gpio_enable; 432 bool r; 433 434 viph_control = RREG32(RADEON_VIPH_CONTROL); 435 bus_cntl = RREG32(R600_BUS_CNTL); 436 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 437 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 438 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 439 rom_cntl = RREG32(R600_ROM_CNTL); 440 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 441 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 442 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 443 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 444 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 445 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 446 447 /* disable VIP */ 448 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 449 /* enable the rom */ 450 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 451 /* Disable VGA mode */ 452 WREG32(AVIVO_D1VGA_CONTROL, 453 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 454 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 455 WREG32(AVIVO_D2VGA_CONTROL, 456 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 457 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 458 WREG32(AVIVO_VGA_RENDER_CONTROL, 459 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 460 461 WREG32(R600_ROM_CNTL, 462 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 463 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 464 R600_SCK_OVERWRITE)); 465 466 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 467 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 468 (low_vid_lower_gpio_cntl & ~0x400)); 469 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 470 (medium_vid_lower_gpio_cntl & ~0x400)); 471 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 472 (high_vid_lower_gpio_cntl & ~0x400)); 473 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 474 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 475 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 476 477 r = radeon_read_bios(rdev); 478 479 /* restore regs */ 480 WREG32(RADEON_VIPH_CONTROL, viph_control); 481 WREG32(R600_BUS_CNTL, bus_cntl); 482 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 483 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 484 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 485 WREG32(R600_ROM_CNTL, rom_cntl); 486 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 487 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 488 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 489 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 490 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 491 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 492 return r; 493 } 494 495 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 496 { 497 uint32_t seprom_cntl1; 498 uint32_t viph_control; 499 uint32_t bus_cntl; 500 uint32_t d1vga_control; 501 uint32_t d2vga_control; 502 uint32_t vga_render_control; 503 uint32_t gpiopad_a; 504 uint32_t gpiopad_en; 505 uint32_t gpiopad_mask; 506 bool r; 507 508 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 509 viph_control = RREG32(RADEON_VIPH_CONTROL); 510 bus_cntl = RREG32(RV370_BUS_CNTL); 511 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 512 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 513 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 514 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 515 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 516 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 517 518 WREG32(RADEON_SEPROM_CNTL1, 519 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 520 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 521 WREG32(RADEON_GPIOPAD_A, 0); 522 WREG32(RADEON_GPIOPAD_EN, 0); 523 WREG32(RADEON_GPIOPAD_MASK, 0); 524 525 /* disable VIP */ 526 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 527 528 /* enable the rom */ 529 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 530 531 /* Disable VGA mode */ 532 WREG32(AVIVO_D1VGA_CONTROL, 533 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 534 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 535 WREG32(AVIVO_D2VGA_CONTROL, 536 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 537 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 538 WREG32(AVIVO_VGA_RENDER_CONTROL, 539 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 540 541 r = radeon_read_bios(rdev); 542 543 /* restore regs */ 544 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 545 WREG32(RADEON_VIPH_CONTROL, viph_control); 546 WREG32(RV370_BUS_CNTL, bus_cntl); 547 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 548 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 549 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 550 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 551 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 552 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 553 return r; 554 } 555 556 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 557 { 558 uint32_t seprom_cntl1; 559 uint32_t viph_control; 560 uint32_t bus_cntl; 561 uint32_t crtc_gen_cntl; 562 uint32_t crtc2_gen_cntl; 563 uint32_t crtc_ext_cntl; 564 uint32_t fp2_gen_cntl; 565 bool r; 566 567 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 568 viph_control = RREG32(RADEON_VIPH_CONTROL); 569 if (rdev->flags & RADEON_IS_PCIE) 570 bus_cntl = RREG32(RV370_BUS_CNTL); 571 else 572 bus_cntl = RREG32(RADEON_BUS_CNTL); 573 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 574 crtc2_gen_cntl = 0; 575 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 576 fp2_gen_cntl = 0; 577 578 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 579 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 580 } 581 582 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 583 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 584 } 585 586 WREG32(RADEON_SEPROM_CNTL1, 587 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 588 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 589 590 /* disable VIP */ 591 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 592 593 /* enable the rom */ 594 if (rdev->flags & RADEON_IS_PCIE) 595 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 596 else 597 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 598 599 /* Turn off mem requests and CRTC for both controllers */ 600 WREG32(RADEON_CRTC_GEN_CNTL, 601 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 602 (RADEON_CRTC_DISP_REQ_EN_B | 603 RADEON_CRTC_EXT_DISP_EN))); 604 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 605 WREG32(RADEON_CRTC2_GEN_CNTL, 606 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 607 RADEON_CRTC2_DISP_REQ_EN_B)); 608 } 609 /* Turn off CRTC */ 610 WREG32(RADEON_CRTC_EXT_CNTL, 611 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 612 (RADEON_CRTC_SYNC_TRISTAT | 613 RADEON_CRTC_DISPLAY_DIS))); 614 615 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 616 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 617 } 618 619 r = radeon_read_bios(rdev); 620 621 /* restore regs */ 622 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 623 WREG32(RADEON_VIPH_CONTROL, viph_control); 624 if (rdev->flags & RADEON_IS_PCIE) 625 WREG32(RV370_BUS_CNTL, bus_cntl); 626 else 627 WREG32(RADEON_BUS_CNTL, bus_cntl); 628 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 629 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 630 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 631 } 632 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 633 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 634 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 635 } 636 return r; 637 } 638 639 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 640 { 641 if (rdev->flags & RADEON_IS_IGP) 642 return igp_read_bios_from_vram(rdev); 643 else if (rdev->family >= CHIP_BARTS) 644 return ni_read_disabled_bios(rdev); 645 else if (rdev->family >= CHIP_RV770) 646 return r700_read_disabled_bios(rdev); 647 else if (rdev->family >= CHIP_R600) 648 return r600_read_disabled_bios(rdev); 649 else if (rdev->family >= CHIP_RS600) 650 return avivo_read_disabled_bios(rdev); 651 else 652 return legacy_read_disabled_bios(rdev); 653 } 654 655 #ifdef CONFIG_ACPI 656 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 657 { 658 struct acpi_table_header *hdr; 659 acpi_size tbl_size; 660 UEFI_ACPI_VFCT *vfct; 661 unsigned offset; 662 663 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 664 return false; 665 tbl_size = hdr->length; 666 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 667 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 668 return false; 669 } 670 671 vfct = (UEFI_ACPI_VFCT *)hdr; 672 offset = vfct->VBIOSImageOffset; 673 674 while (offset < tbl_size) { 675 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 676 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 677 678 offset += sizeof(VFCT_IMAGE_HEADER); 679 if (offset > tbl_size) { 680 DRM_ERROR("ACPI VFCT image header truncated\n"); 681 return false; 682 } 683 684 offset += vhdr->ImageLength; 685 if (offset > tbl_size) { 686 DRM_ERROR("ACPI VFCT image truncated\n"); 687 return false; 688 } 689 690 if (vhdr->ImageLength && 691 vhdr->PCIBus == rdev->pdev->bus->number && 692 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 693 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 694 vhdr->VendorID == rdev->pdev->vendor && 695 vhdr->DeviceID == rdev->pdev->device) { 696 rdev->bios = kmemdup(&vbios->VbiosContent, 697 vhdr->ImageLength, 698 GFP_KERNEL); 699 700 if (!rdev->bios) 701 return false; 702 return true; 703 } 704 } 705 706 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 707 return false; 708 } 709 #else 710 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 711 { 712 return false; 713 } 714 #endif 715 716 bool radeon_get_bios(struct radeon_device *rdev) 717 { 718 bool r; 719 uint16_t tmp; 720 721 r = radeon_atrm_get_bios(rdev); 722 if (!r) 723 r = radeon_acpi_vfct_bios(rdev); 724 if (!r) 725 r = igp_read_bios_from_vram(rdev); 726 if (!r) 727 r = radeon_read_bios(rdev); 728 if (!r) 729 r = radeon_read_disabled_bios(rdev); 730 if (!r) 731 r = radeon_read_platform_bios(rdev); 732 if (!r || rdev->bios == NULL) { 733 DRM_ERROR("Unable to locate a BIOS ROM\n"); 734 rdev->bios = NULL; 735 return false; 736 } 737 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 738 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 739 goto free_bios; 740 } 741 742 tmp = RBIOS16(0x18); 743 if (RBIOS8(tmp + 0x14) != 0x0) { 744 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 745 goto free_bios; 746 } 747 748 rdev->bios_header_start = RBIOS16(0x48); 749 if (!rdev->bios_header_start) { 750 goto free_bios; 751 } 752 tmp = rdev->bios_header_start + 4; 753 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 754 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 755 rdev->is_atom_bios = true; 756 } else { 757 rdev->is_atom_bios = false; 758 } 759 760 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 761 return true; 762 free_bios: 763 kfree(rdev->bios); 764 rdev->bios = NULL; 765 return false; 766 } 767
Indexes created Wed Oct 29 03:09:52 GMT 2025