radeon_ci_smc.c revision 1.1.2.2
1 /* $NetBSD: radeon_ci_smc.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_ci_smc.c,v 1.1.2.2 2018/09/06 06:56:32 pgoyette Exp $"); 29 30 #include <linux/firmware.h> 31 #include "drmP.h" 32 #include "radeon.h" 33 #include "cikd.h" 34 #include "ppsmc.h" 35 #include "radeon_ucode.h" 36 #include "ci_dpm.h" 37 38 static int ci_set_smc_sram_address(struct radeon_device *rdev, 39 u32 smc_address, u32 limit) 40 { 41 if (smc_address & 3) 42 return -EINVAL; 43 if ((smc_address + 3) > limit) 44 return -EINVAL; 45 46 WREG32(SMC_IND_INDEX_0, smc_address); 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 48 49 return 0; 50 } 51 52 int ci_copy_bytes_to_smc(struct radeon_device *rdev, 53 u32 smc_start_address, 54 const u8 *src, u32 byte_count, u32 limit) 55 { 56 unsigned long flags; 57 u32 data, original_data; 58 u32 addr; 59 u32 extra_shift; 60 int ret = 0; 61 62 if (smc_start_address & 3) 63 return -EINVAL; 64 if ((smc_start_address + byte_count) > limit) 65 return -EINVAL; 66 67 addr = smc_start_address; 68 69 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 70 while (byte_count >= 4) { 71 /* SMC address space is BE */ 72 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 73 74 ret = ci_set_smc_sram_address(rdev, addr, limit); 75 if (ret) 76 goto done; 77 78 WREG32(SMC_IND_DATA_0, data); 79 80 src += 4; 81 byte_count -= 4; 82 addr += 4; 83 } 84 85 /* RMW for the final bytes */ 86 if (byte_count > 0) { 87 data = 0; 88 89 ret = ci_set_smc_sram_address(rdev, addr, limit); 90 if (ret) 91 goto done; 92 93 original_data = RREG32(SMC_IND_DATA_0); 94 95 extra_shift = 8 * (4 - byte_count); 96 97 while (byte_count > 0) { 98 data = (data << 8) + *src++; 99 byte_count--; 100 } 101 102 data <<= extra_shift; 103 104 data |= (original_data & ~((~0UL) << extra_shift)); 105 106 ret = ci_set_smc_sram_address(rdev, addr, limit); 107 if (ret) 108 goto done; 109 110 WREG32(SMC_IND_DATA_0, data); 111 } 112 113 done: 114 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 115 116 return ret; 117 } 118 119 void ci_start_smc(struct radeon_device *rdev) 120 { 121 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 122 123 tmp &= ~RST_REG; 124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 125 } 126 127 void ci_reset_smc(struct radeon_device *rdev) 128 { 129 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 130 131 tmp |= RST_REG; 132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 133 } 134 135 int ci_program_jump_on_start(struct radeon_device *rdev) 136 { 137 static const u8 data[] = { 0xE0, 0x00, 0x80, 0x40 }; 138 139 return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1); 140 } 141 142 void ci_stop_smc_clock(struct radeon_device *rdev) 143 { 144 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 145 146 tmp |= CK_DISABLE; 147 148 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 149 } 150 151 void ci_start_smc_clock(struct radeon_device *rdev) 152 { 153 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 154 155 tmp &= ~CK_DISABLE; 156 157 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 158 } 159 160 bool ci_is_smc_running(struct radeon_device *rdev) 161 { 162 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 163 u32 pc_c = RREG32_SMC(SMC_PC_C); 164 165 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c)) 166 return true; 167 168 return false; 169 } 170 171 PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 172 { 173 u32 tmp; 174 int i; 175 176 if (!ci_is_smc_running(rdev)) 177 return PPSMC_Result_Failed; 178 179 WREG32(SMC_MESSAGE_0, msg); 180 181 for (i = 0; i < rdev->usec_timeout; i++) { 182 tmp = RREG32(SMC_RESP_0); 183 if (tmp != 0) 184 break; 185 udelay(1); 186 } 187 tmp = RREG32(SMC_RESP_0); 188 189 return (PPSMC_Result)tmp; 190 } 191 192 #if 0 193 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) 194 { 195 u32 tmp; 196 int i; 197 198 if (!ci_is_smc_running(rdev)) 199 return PPSMC_Result_OK; 200 201 for (i = 0; i < rdev->usec_timeout; i++) { 202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 203 if ((tmp & CKEN) == 0) 204 break; 205 udelay(1); 206 } 207 208 return PPSMC_Result_OK; 209 } 210 #endif 211 212 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) 213 { 214 unsigned long flags; 215 u32 ucode_start_address; 216 u32 ucode_size; 217 const u8 *src; 218 u32 data; 219 220 if (!rdev->smc_fw) 221 return -EINVAL; 222 223 if (rdev->new_fw) { 224 const struct smc_firmware_header_v1_0 *hdr = 225 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data; 226 227 radeon_ucode_print_smc_hdr(&hdr->header); 228 229 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 230 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 231 src = (const u8 *) 232 (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 233 } else { 234 switch (rdev->family) { 235 case CHIP_BONAIRE: 236 ucode_start_address = BONAIRE_SMC_UCODE_START; 237 ucode_size = BONAIRE_SMC_UCODE_SIZE; 238 break; 239 case CHIP_HAWAII: 240 ucode_start_address = HAWAII_SMC_UCODE_START; 241 ucode_size = HAWAII_SMC_UCODE_SIZE; 242 break; 243 default: 244 DRM_ERROR("unknown asic in smc ucode loader\n"); 245 BUG(); 246 } 247 248 src = (const u8 *)rdev->smc_fw->data; 249 } 250 251 if (ucode_size & 3) 252 return -EINVAL; 253 254 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 255 WREG32(SMC_IND_INDEX_0, ucode_start_address); 256 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); 257 while (ucode_size >= 4) { 258 /* SMC address space is BE */ 259 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 260 261 WREG32(SMC_IND_DATA_0, data); 262 263 src += 4; 264 ucode_size -= 4; 265 } 266 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 267 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 268 269 return 0; 270 } 271 272 int ci_read_smc_sram_dword(struct radeon_device *rdev, 273 u32 smc_address, u32 *value, u32 limit) 274 { 275 unsigned long flags; 276 int ret; 277 278 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 279 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 280 if (ret == 0) 281 *value = RREG32(SMC_IND_DATA_0); 282 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 283 284 return ret; 285 } 286 287 int ci_write_smc_sram_dword(struct radeon_device *rdev, 288 u32 smc_address, u32 value, u32 limit) 289 { 290 unsigned long flags; 291 int ret; 292 293 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 294 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 295 if (ret == 0) 296 WREG32(SMC_IND_DATA_0, value); 297 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 298 299 return ret; 300 } 301
Indexes created Mon Oct 27 02:09:54 GMT 2025