radeon_combios.c revision 1.2.30.1
1 /* $NetBSD: radeon_combios.c,v 1.2.30.1 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 5 * Copyright 2007-8 Advanced Micro Devices, Inc. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_combios.c,v 1.2.30.1 2018/09/06 06:56:32 pgoyette Exp $"); 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 #include "atom.h" 36 37 #ifdef CONFIG_PPC_PMAC 38 /* not sure which of these are needed */ 39 #include <asm/machdep.h> 40 #include <asm/pmac_feature.h> 41 #include <asm/prom.h> 42 #include <asm/pci-bridge.h> 43 #endif /* CONFIG_PPC_PMAC */ 44 45 /* from radeon_legacy_encoder.c */ 46 extern void 47 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 48 uint32_t supported_device); 49 50 /* old legacy ATI BIOS routines */ 51 52 /* COMBIOS table offsets */ 53 enum radeon_combios_table_offset { 54 /* absolute offset tables */ 55 COMBIOS_ASIC_INIT_1_TABLE, 56 COMBIOS_BIOS_SUPPORT_TABLE, 57 COMBIOS_DAC_PROGRAMMING_TABLE, 58 COMBIOS_MAX_COLOR_DEPTH_TABLE, 59 COMBIOS_CRTC_INFO_TABLE, 60 COMBIOS_PLL_INFO_TABLE, 61 COMBIOS_TV_INFO_TABLE, 62 COMBIOS_DFP_INFO_TABLE, 63 COMBIOS_HW_CONFIG_INFO_TABLE, 64 COMBIOS_MULTIMEDIA_INFO_TABLE, 65 COMBIOS_TV_STD_PATCH_TABLE, 66 COMBIOS_LCD_INFO_TABLE, 67 COMBIOS_MOBILE_INFO_TABLE, 68 COMBIOS_PLL_INIT_TABLE, 69 COMBIOS_MEM_CONFIG_TABLE, 70 COMBIOS_SAVE_MASK_TABLE, 71 COMBIOS_HARDCODED_EDID_TABLE, 72 COMBIOS_ASIC_INIT_2_TABLE, 73 COMBIOS_CONNECTOR_INFO_TABLE, 74 COMBIOS_DYN_CLK_1_TABLE, 75 COMBIOS_RESERVED_MEM_TABLE, 76 COMBIOS_EXT_TMDS_INFO_TABLE, 77 COMBIOS_MEM_CLK_INFO_TABLE, 78 COMBIOS_EXT_DAC_INFO_TABLE, 79 COMBIOS_MISC_INFO_TABLE, 80 COMBIOS_CRT_INFO_TABLE, 81 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 82 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 83 COMBIOS_FAN_SPEED_INFO_TABLE, 84 COMBIOS_OVERDRIVE_INFO_TABLE, 85 COMBIOS_OEM_INFO_TABLE, 86 COMBIOS_DYN_CLK_2_TABLE, 87 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 88 COMBIOS_I2C_INFO_TABLE, 89 /* relative offset tables */ 90 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 91 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 92 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 93 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 94 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 95 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 96 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 97 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 98 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 99 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 100 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 101 }; 102 103 enum radeon_combios_ddc { 104 DDC_NONE_DETECTED, 105 DDC_MONID, 106 DDC_DVI, 107 DDC_VGA, 108 DDC_CRT2, 109 DDC_LCD, 110 DDC_GPIO, 111 }; 112 113 enum radeon_combios_connector { 114 CONNECTOR_NONE_LEGACY, 115 CONNECTOR_PROPRIETARY_LEGACY, 116 CONNECTOR_CRT_LEGACY, 117 CONNECTOR_DVI_I_LEGACY, 118 CONNECTOR_DVI_D_LEGACY, 119 CONNECTOR_CTV_LEGACY, 120 CONNECTOR_STV_LEGACY, 121 CONNECTOR_UNSUPPORTED_LEGACY 122 }; 123 124 static const int legacy_connector_convert[] = { 125 DRM_MODE_CONNECTOR_Unknown, 126 DRM_MODE_CONNECTOR_DVID, 127 DRM_MODE_CONNECTOR_VGA, 128 DRM_MODE_CONNECTOR_DVII, 129 DRM_MODE_CONNECTOR_DVID, 130 DRM_MODE_CONNECTOR_Composite, 131 DRM_MODE_CONNECTOR_SVIDEO, 132 DRM_MODE_CONNECTOR_Unknown, 133 }; 134 135 static uint16_t combios_get_table_offset(struct drm_device *dev, 136 enum radeon_combios_table_offset table) 137 { 138 struct radeon_device *rdev = dev->dev_private; 139 int rev, size; 140 uint16_t offset = 0, check_offset; 141 142 if (!rdev->bios) 143 return 0; 144 145 switch (table) { 146 /* absolute offset tables */ 147 case COMBIOS_ASIC_INIT_1_TABLE: 148 check_offset = 0xc; 149 break; 150 case COMBIOS_BIOS_SUPPORT_TABLE: 151 check_offset = 0x14; 152 break; 153 case COMBIOS_DAC_PROGRAMMING_TABLE: 154 check_offset = 0x2a; 155 break; 156 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 157 check_offset = 0x2c; 158 break; 159 case COMBIOS_CRTC_INFO_TABLE: 160 check_offset = 0x2e; 161 break; 162 case COMBIOS_PLL_INFO_TABLE: 163 check_offset = 0x30; 164 break; 165 case COMBIOS_TV_INFO_TABLE: 166 check_offset = 0x32; 167 break; 168 case COMBIOS_DFP_INFO_TABLE: 169 check_offset = 0x34; 170 break; 171 case COMBIOS_HW_CONFIG_INFO_TABLE: 172 check_offset = 0x36; 173 break; 174 case COMBIOS_MULTIMEDIA_INFO_TABLE: 175 check_offset = 0x38; 176 break; 177 case COMBIOS_TV_STD_PATCH_TABLE: 178 check_offset = 0x3e; 179 break; 180 case COMBIOS_LCD_INFO_TABLE: 181 check_offset = 0x40; 182 break; 183 case COMBIOS_MOBILE_INFO_TABLE: 184 check_offset = 0x42; 185 break; 186 case COMBIOS_PLL_INIT_TABLE: 187 check_offset = 0x46; 188 break; 189 case COMBIOS_MEM_CONFIG_TABLE: 190 check_offset = 0x48; 191 break; 192 case COMBIOS_SAVE_MASK_TABLE: 193 check_offset = 0x4a; 194 break; 195 case COMBIOS_HARDCODED_EDID_TABLE: 196 check_offset = 0x4c; 197 break; 198 case COMBIOS_ASIC_INIT_2_TABLE: 199 check_offset = 0x4e; 200 break; 201 case COMBIOS_CONNECTOR_INFO_TABLE: 202 check_offset = 0x50; 203 break; 204 case COMBIOS_DYN_CLK_1_TABLE: 205 check_offset = 0x52; 206 break; 207 case COMBIOS_RESERVED_MEM_TABLE: 208 check_offset = 0x54; 209 break; 210 case COMBIOS_EXT_TMDS_INFO_TABLE: 211 check_offset = 0x58; 212 break; 213 case COMBIOS_MEM_CLK_INFO_TABLE: 214 check_offset = 0x5a; 215 break; 216 case COMBIOS_EXT_DAC_INFO_TABLE: 217 check_offset = 0x5c; 218 break; 219 case COMBIOS_MISC_INFO_TABLE: 220 check_offset = 0x5e; 221 break; 222 case COMBIOS_CRT_INFO_TABLE: 223 check_offset = 0x60; 224 break; 225 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 226 check_offset = 0x62; 227 break; 228 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 229 check_offset = 0x64; 230 break; 231 case COMBIOS_FAN_SPEED_INFO_TABLE: 232 check_offset = 0x66; 233 break; 234 case COMBIOS_OVERDRIVE_INFO_TABLE: 235 check_offset = 0x68; 236 break; 237 case COMBIOS_OEM_INFO_TABLE: 238 check_offset = 0x6a; 239 break; 240 case COMBIOS_DYN_CLK_2_TABLE: 241 check_offset = 0x6c; 242 break; 243 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 244 check_offset = 0x6e; 245 break; 246 case COMBIOS_I2C_INFO_TABLE: 247 check_offset = 0x70; 248 break; 249 /* relative offset tables */ 250 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 251 check_offset = 252 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 253 if (check_offset) { 254 rev = RBIOS8(check_offset); 255 if (rev > 0) { 256 check_offset = RBIOS16(check_offset + 0x3); 257 if (check_offset) 258 offset = check_offset; 259 } 260 } 261 break; 262 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 263 check_offset = 264 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 265 if (check_offset) { 266 rev = RBIOS8(check_offset); 267 if (rev > 0) { 268 check_offset = RBIOS16(check_offset + 0x5); 269 if (check_offset) 270 offset = check_offset; 271 } 272 } 273 break; 274 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 275 check_offset = 276 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 277 if (check_offset) { 278 rev = RBIOS8(check_offset); 279 if (rev > 0) { 280 check_offset = RBIOS16(check_offset + 0x7); 281 if (check_offset) 282 offset = check_offset; 283 } 284 } 285 break; 286 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 287 check_offset = 288 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 289 if (check_offset) { 290 rev = RBIOS8(check_offset); 291 if (rev == 2) { 292 check_offset = RBIOS16(check_offset + 0x9); 293 if (check_offset) 294 offset = check_offset; 295 } 296 } 297 break; 298 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 299 check_offset = 300 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 301 if (check_offset) { 302 while (RBIOS8(check_offset++)); 303 check_offset += 2; 304 if (check_offset) 305 offset = check_offset; 306 } 307 break; 308 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 309 check_offset = 310 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 311 if (check_offset) { 312 check_offset = RBIOS16(check_offset + 0x11); 313 if (check_offset) 314 offset = check_offset; 315 } 316 break; 317 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 318 check_offset = 319 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 320 if (check_offset) { 321 check_offset = RBIOS16(check_offset + 0x13); 322 if (check_offset) 323 offset = check_offset; 324 } 325 break; 326 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 327 check_offset = 328 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 329 if (check_offset) { 330 check_offset = RBIOS16(check_offset + 0x15); 331 if (check_offset) 332 offset = check_offset; 333 } 334 break; 335 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 336 check_offset = 337 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 338 if (check_offset) { 339 check_offset = RBIOS16(check_offset + 0x17); 340 if (check_offset) 341 offset = check_offset; 342 } 343 break; 344 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 345 check_offset = 346 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 347 if (check_offset) { 348 check_offset = RBIOS16(check_offset + 0x2); 349 if (check_offset) 350 offset = check_offset; 351 } 352 break; 353 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 354 check_offset = 355 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 356 if (check_offset) { 357 check_offset = RBIOS16(check_offset + 0x4); 358 if (check_offset) 359 offset = check_offset; 360 } 361 break; 362 default: 363 check_offset = 0; 364 break; 365 } 366 367 size = RBIOS8(rdev->bios_header_start + 0x6); 368 /* check absolute offset tables */ 369 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 370 offset = RBIOS16(rdev->bios_header_start + check_offset); 371 372 return offset; 373 } 374 375 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 376 { 377 int edid_info, size; 378 struct edid *edid; 379 unsigned char *raw; 380 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 381 if (!edid_info) 382 return false; 383 384 raw = rdev->bios + edid_info; 385 size = EDID_LENGTH * (raw[0x7e] + 1); 386 edid = kmalloc(size, GFP_KERNEL); 387 if (edid == NULL) 388 return false; 389 390 memcpy((unsigned char *)edid, raw, size); 391 392 if (!drm_edid_is_valid(edid)) { 393 kfree(edid); 394 return false; 395 } 396 397 rdev->mode_info.bios_hardcoded_edid = edid; 398 rdev->mode_info.bios_hardcoded_edid_size = size; 399 return true; 400 } 401 402 /* this is used for atom LCDs as well */ 403 struct edid * 404 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 405 { 406 struct edid *edid; 407 408 if (rdev->mode_info.bios_hardcoded_edid) { 409 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 410 if (edid) { 411 memcpy((unsigned char *)edid, 412 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 413 rdev->mode_info.bios_hardcoded_edid_size); 414 return edid; 415 } 416 } 417 return NULL; 418 } 419 420 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 421 enum radeon_combios_ddc ddc, 422 u32 clk_mask, 423 u32 data_mask) 424 { 425 struct radeon_i2c_bus_rec i2c; 426 int ddc_line = 0; 427 428 /* ddc id = mask reg 429 * DDC_NONE_DETECTED = none 430 * DDC_DVI = RADEON_GPIO_DVI_DDC 431 * DDC_VGA = RADEON_GPIO_VGA_DDC 432 * DDC_LCD = RADEON_GPIOPAD_MASK 433 * DDC_GPIO = RADEON_MDGPIO_MASK 434 * r1xx 435 * DDC_MONID = RADEON_GPIO_MONID 436 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 437 * r200 438 * DDC_MONID = RADEON_GPIO_MONID 439 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 440 * r300/r350 441 * DDC_MONID = RADEON_GPIO_DVI_DDC 442 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 443 * rv2xx/rv3xx 444 * DDC_MONID = RADEON_GPIO_MONID 445 * DDC_CRT2 = RADEON_GPIO_MONID 446 * rs3xx/rs4xx 447 * DDC_MONID = RADEON_GPIOPAD_MASK 448 * DDC_CRT2 = RADEON_GPIO_MONID 449 */ 450 switch (ddc) { 451 case DDC_NONE_DETECTED: 452 default: 453 ddc_line = 0; 454 break; 455 case DDC_DVI: 456 ddc_line = RADEON_GPIO_DVI_DDC; 457 break; 458 case DDC_VGA: 459 ddc_line = RADEON_GPIO_VGA_DDC; 460 break; 461 case DDC_LCD: 462 ddc_line = RADEON_GPIOPAD_MASK; 463 break; 464 case DDC_GPIO: 465 ddc_line = RADEON_MDGPIO_MASK; 466 break; 467 case DDC_MONID: 468 if (rdev->family == CHIP_RS300 || 469 rdev->family == CHIP_RS400 || 470 rdev->family == CHIP_RS480) 471 ddc_line = RADEON_GPIOPAD_MASK; 472 else if (rdev->family == CHIP_R300 || 473 rdev->family == CHIP_R350) { 474 ddc_line = RADEON_GPIO_DVI_DDC; 475 ddc = DDC_DVI; 476 } else 477 ddc_line = RADEON_GPIO_MONID; 478 break; 479 case DDC_CRT2: 480 if (rdev->family == CHIP_R200 || 481 rdev->family == CHIP_R300 || 482 rdev->family == CHIP_R350) { 483 ddc_line = RADEON_GPIO_DVI_DDC; 484 ddc = DDC_DVI; 485 } else if (rdev->family == CHIP_RS300 || 486 rdev->family == CHIP_RS400 || 487 rdev->family == CHIP_RS480) 488 ddc_line = RADEON_GPIO_MONID; 489 else if (rdev->family >= CHIP_RV350) { 490 ddc_line = RADEON_GPIO_MONID; 491 ddc = DDC_MONID; 492 } else 493 ddc_line = RADEON_GPIO_CRT2_DDC; 494 break; 495 } 496 497 if (ddc_line == RADEON_GPIOPAD_MASK) { 498 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 499 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 500 i2c.a_clk_reg = RADEON_GPIOPAD_A; 501 i2c.a_data_reg = RADEON_GPIOPAD_A; 502 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 503 i2c.en_data_reg = RADEON_GPIOPAD_EN; 504 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 505 i2c.y_data_reg = RADEON_GPIOPAD_Y; 506 } else if (ddc_line == RADEON_MDGPIO_MASK) { 507 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 508 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 509 i2c.a_clk_reg = RADEON_MDGPIO_A; 510 i2c.a_data_reg = RADEON_MDGPIO_A; 511 i2c.en_clk_reg = RADEON_MDGPIO_EN; 512 i2c.en_data_reg = RADEON_MDGPIO_EN; 513 i2c.y_clk_reg = RADEON_MDGPIO_Y; 514 i2c.y_data_reg = RADEON_MDGPIO_Y; 515 } else { 516 i2c.mask_clk_reg = ddc_line; 517 i2c.mask_data_reg = ddc_line; 518 i2c.a_clk_reg = ddc_line; 519 i2c.a_data_reg = ddc_line; 520 i2c.en_clk_reg = ddc_line; 521 i2c.en_data_reg = ddc_line; 522 i2c.y_clk_reg = ddc_line; 523 i2c.y_data_reg = ddc_line; 524 } 525 526 if (clk_mask && data_mask) { 527 /* system specific masks */ 528 i2c.mask_clk_mask = clk_mask; 529 i2c.mask_data_mask = data_mask; 530 i2c.a_clk_mask = clk_mask; 531 i2c.a_data_mask = data_mask; 532 i2c.en_clk_mask = clk_mask; 533 i2c.en_data_mask = data_mask; 534 i2c.y_clk_mask = clk_mask; 535 i2c.y_data_mask = data_mask; 536 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 537 (ddc_line == RADEON_MDGPIO_MASK)) { 538 /* default gpiopad masks */ 539 i2c.mask_clk_mask = (0x20 << 8); 540 i2c.mask_data_mask = 0x80; 541 i2c.a_clk_mask = (0x20 << 8); 542 i2c.a_data_mask = 0x80; 543 i2c.en_clk_mask = (0x20 << 8); 544 i2c.en_data_mask = 0x80; 545 i2c.y_clk_mask = (0x20 << 8); 546 i2c.y_data_mask = 0x80; 547 } else { 548 /* default masks for ddc pads */ 549 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 550 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 551 i2c.a_clk_mask = RADEON_GPIO_A_1; 552 i2c.a_data_mask = RADEON_GPIO_A_0; 553 i2c.en_clk_mask = RADEON_GPIO_EN_1; 554 i2c.en_data_mask = RADEON_GPIO_EN_0; 555 i2c.y_clk_mask = RADEON_GPIO_Y_1; 556 i2c.y_data_mask = RADEON_GPIO_Y_0; 557 } 558 559 switch (rdev->family) { 560 case CHIP_R100: 561 case CHIP_RV100: 562 case CHIP_RS100: 563 case CHIP_RV200: 564 case CHIP_RS200: 565 case CHIP_RS300: 566 switch (ddc_line) { 567 case RADEON_GPIO_DVI_DDC: 568 i2c.hw_capable = true; 569 break; 570 default: 571 i2c.hw_capable = false; 572 break; 573 } 574 break; 575 case CHIP_R200: 576 switch (ddc_line) { 577 case RADEON_GPIO_DVI_DDC: 578 case RADEON_GPIO_MONID: 579 i2c.hw_capable = true; 580 break; 581 default: 582 i2c.hw_capable = false; 583 break; 584 } 585 break; 586 case CHIP_RV250: 587 case CHIP_RV280: 588 switch (ddc_line) { 589 case RADEON_GPIO_VGA_DDC: 590 case RADEON_GPIO_DVI_DDC: 591 case RADEON_GPIO_CRT2_DDC: 592 i2c.hw_capable = true; 593 break; 594 default: 595 i2c.hw_capable = false; 596 break; 597 } 598 break; 599 case CHIP_R300: 600 case CHIP_R350: 601 switch (ddc_line) { 602 case RADEON_GPIO_VGA_DDC: 603 case RADEON_GPIO_DVI_DDC: 604 i2c.hw_capable = true; 605 break; 606 default: 607 i2c.hw_capable = false; 608 break; 609 } 610 break; 611 case CHIP_RV350: 612 case CHIP_RV380: 613 case CHIP_RS400: 614 case CHIP_RS480: 615 switch (ddc_line) { 616 case RADEON_GPIO_VGA_DDC: 617 case RADEON_GPIO_DVI_DDC: 618 i2c.hw_capable = true; 619 break; 620 case RADEON_GPIO_MONID: 621 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 622 * reliably on some pre-r4xx hardware; not sure why. 623 */ 624 i2c.hw_capable = false; 625 break; 626 default: 627 i2c.hw_capable = false; 628 break; 629 } 630 break; 631 default: 632 i2c.hw_capable = false; 633 break; 634 } 635 i2c.mm_i2c = false; 636 637 i2c.i2c_id = ddc; 638 i2c.hpd = RADEON_HPD_NONE; 639 640 if (ddc_line) 641 i2c.valid = true; 642 else 643 i2c.valid = false; 644 645 return i2c; 646 } 647 648 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 649 { 650 struct drm_device *dev = rdev->ddev; 651 struct radeon_i2c_bus_rec i2c; 652 u16 offset; 653 u8 id, blocks, clk, data; 654 int i; 655 656 i2c.valid = false; 657 658 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 659 if (offset) { 660 blocks = RBIOS8(offset + 2); 661 for (i = 0; i < blocks; i++) { 662 id = RBIOS8(offset + 3 + (i * 5) + 0); 663 if (id == 136) { 664 clk = RBIOS8(offset + 3 + (i * 5) + 3); 665 data = RBIOS8(offset + 3 + (i * 5) + 4); 666 /* gpiopad */ 667 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 668 (1 << clk), (1 << data)); 669 break; 670 } 671 } 672 } 673 return i2c; 674 } 675 676 void radeon_combios_i2c_init(struct radeon_device *rdev) 677 { 678 struct drm_device *dev = rdev->ddev; 679 struct radeon_i2c_bus_rec i2c; 680 681 /* actual hw pads 682 * r1xx/rs2xx/rs3xx 683 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 684 * r200 685 * 0x60, 0x64, 0x68, mm 686 * r300/r350 687 * 0x60, 0x64, mm 688 * rv2xx/rv3xx/rs4xx 689 * 0x60, 0x64, 0x68, gpiopads, mm 690 */ 691 692 /* 0x60 */ 693 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 694 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 695 /* 0x64 */ 696 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 697 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 698 699 /* mm i2c */ 700 i2c.valid = true; 701 i2c.hw_capable = true; 702 i2c.mm_i2c = true; 703 i2c.i2c_id = 0xa0; 704 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 705 706 if (rdev->family == CHIP_R300 || 707 rdev->family == CHIP_R350) { 708 /* only 2 sw i2c pads */ 709 } else if (rdev->family == CHIP_RS300 || 710 rdev->family == CHIP_RS400 || 711 rdev->family == CHIP_RS480) { 712 /* 0x68 */ 713 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 714 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 715 716 /* gpiopad */ 717 i2c = radeon_combios_get_i2c_info_from_table(rdev); 718 if (i2c.valid) 719 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 720 } else if ((rdev->family == CHIP_R200) || 721 (rdev->family >= CHIP_R300)) { 722 /* 0x68 */ 723 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 724 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 725 } else { 726 /* 0x68 */ 727 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 728 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 729 /* 0x6c */ 730 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 731 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 732 } 733 } 734 735 bool radeon_combios_get_clock_info(struct drm_device *dev) 736 { 737 struct radeon_device *rdev = dev->dev_private; 738 uint16_t pll_info; 739 struct radeon_pll *p1pll = &rdev->clock.p1pll; 740 struct radeon_pll *p2pll = &rdev->clock.p2pll; 741 struct radeon_pll *spll = &rdev->clock.spll; 742 struct radeon_pll *mpll = &rdev->clock.mpll; 743 int8_t rev; 744 uint16_t sclk, mclk; 745 746 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 747 if (pll_info) { 748 rev = RBIOS8(pll_info); 749 750 /* pixel clocks */ 751 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 752 p1pll->reference_div = RBIOS16(pll_info + 0x10); 753 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 754 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 755 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 756 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 757 758 if (rev > 9) { 759 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 760 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 761 } else { 762 p1pll->pll_in_min = 40; 763 p1pll->pll_in_max = 500; 764 } 765 *p2pll = *p1pll; 766 767 /* system clock */ 768 spll->reference_freq = RBIOS16(pll_info + 0x1a); 769 spll->reference_div = RBIOS16(pll_info + 0x1c); 770 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 771 spll->pll_out_max = RBIOS32(pll_info + 0x22); 772 773 if (rev > 10) { 774 spll->pll_in_min = RBIOS32(pll_info + 0x48); 775 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 776 } else { 777 /* ??? */ 778 spll->pll_in_min = 40; 779 spll->pll_in_max = 500; 780 } 781 782 /* memory clock */ 783 mpll->reference_freq = RBIOS16(pll_info + 0x26); 784 mpll->reference_div = RBIOS16(pll_info + 0x28); 785 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 786 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 787 788 if (rev > 10) { 789 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 790 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 791 } else { 792 /* ??? */ 793 mpll->pll_in_min = 40; 794 mpll->pll_in_max = 500; 795 } 796 797 /* default sclk/mclk */ 798 sclk = RBIOS16(pll_info + 0xa); 799 mclk = RBIOS16(pll_info + 0x8); 800 if (sclk == 0) 801 sclk = 200 * 100; 802 if (mclk == 0) 803 mclk = 200 * 100; 804 805 rdev->clock.default_sclk = sclk; 806 rdev->clock.default_mclk = mclk; 807 808 if (RBIOS32(pll_info + 0x16)) 809 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 810 else 811 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 812 813 return true; 814 } 815 return false; 816 } 817 818 bool radeon_combios_sideport_present(struct radeon_device *rdev) 819 { 820 struct drm_device *dev = rdev->ddev; 821 u16 igp_info; 822 823 /* sideport is AMD only */ 824 if (rdev->family == CHIP_RS400) 825 return false; 826 827 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 828 829 if (igp_info) { 830 if (RBIOS16(igp_info + 0x4)) 831 return true; 832 } 833 return false; 834 } 835 836 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 837 0x00000808, /* r100 */ 838 0x00000808, /* rv100 */ 839 0x00000808, /* rs100 */ 840 0x00000808, /* rv200 */ 841 0x00000808, /* rs200 */ 842 0x00000808, /* r200 */ 843 0x00000808, /* rv250 */ 844 0x00000000, /* rs300 */ 845 0x00000808, /* rv280 */ 846 0x00000808, /* r300 */ 847 0x00000808, /* r350 */ 848 0x00000808, /* rv350 */ 849 0x00000808, /* rv380 */ 850 0x00000808, /* r420 */ 851 0x00000808, /* r423 */ 852 0x00000808, /* rv410 */ 853 0x00000000, /* rs400 */ 854 0x00000000, /* rs480 */ 855 }; 856 857 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 858 struct radeon_encoder_primary_dac *p_dac) 859 { 860 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 861 return; 862 } 863 864 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 865 radeon_encoder 866 *encoder) 867 { 868 struct drm_device *dev = encoder->base.dev; 869 struct radeon_device *rdev = dev->dev_private; 870 uint16_t dac_info; 871 uint8_t rev, bg, dac; 872 struct radeon_encoder_primary_dac *p_dac = NULL; 873 int found = 0; 874 875 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 876 GFP_KERNEL); 877 878 if (!p_dac) 879 return NULL; 880 881 /* check CRT table */ 882 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 883 if (dac_info) { 884 rev = RBIOS8(dac_info) & 0x3; 885 if (rev < 2) { 886 bg = RBIOS8(dac_info + 0x2) & 0xf; 887 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 888 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 889 } else { 890 bg = RBIOS8(dac_info + 0x2) & 0xf; 891 dac = RBIOS8(dac_info + 0x3) & 0xf; 892 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 893 } 894 /* if the values are zeros, use the table */ 895 if ((dac == 0) || (bg == 0)) 896 found = 0; 897 else 898 found = 1; 899 } 900 901 /* quirks */ 902 /* Radeon 7000 (RV100) */ 903 if (((dev->pdev->device == 0x5159) && 904 (dev->pdev->subsystem_vendor == 0x174B) && 905 (dev->pdev->subsystem_device == 0x7c28)) || 906 /* Radeon 9100 (R200) */ 907 ((dev->pdev->device == 0x514D) && 908 (dev->pdev->subsystem_vendor == 0x174B) && 909 (dev->pdev->subsystem_device == 0x7149))) { 910 /* vbios value is bad, use the default */ 911 found = 0; 912 } 913 914 if (!found) /* fallback to defaults */ 915 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 916 917 return p_dac; 918 } 919 920 enum radeon_tv_std 921 radeon_combios_get_tv_info(struct radeon_device *rdev) 922 { 923 struct drm_device *dev = rdev->ddev; 924 uint16_t tv_info; 925 enum radeon_tv_std tv_std = TV_STD_NTSC; 926 927 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 928 if (tv_info) { 929 if (RBIOS8(tv_info + 6) == 'T') { 930 switch (RBIOS8(tv_info + 7) & 0xf) { 931 case 1: 932 tv_std = TV_STD_NTSC; 933 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 934 break; 935 case 2: 936 tv_std = TV_STD_PAL; 937 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 938 break; 939 case 3: 940 tv_std = TV_STD_PAL_M; 941 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 942 break; 943 case 4: 944 tv_std = TV_STD_PAL_60; 945 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 946 break; 947 case 5: 948 tv_std = TV_STD_NTSC_J; 949 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 950 break; 951 case 6: 952 tv_std = TV_STD_SCART_PAL; 953 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 954 break; 955 default: 956 tv_std = TV_STD_NTSC; 957 DRM_DEBUG_KMS 958 ("Unknown TV standard; defaulting to NTSC\n"); 959 break; 960 } 961 962 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 963 case 0: 964 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 965 break; 966 case 1: 967 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 968 break; 969 case 2: 970 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 971 break; 972 case 3: 973 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 974 break; 975 default: 976 break; 977 } 978 } 979 } 980 return tv_std; 981 } 982 983 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 984 0x00000000, /* r100 */ 985 0x00280000, /* rv100 */ 986 0x00000000, /* rs100 */ 987 0x00880000, /* rv200 */ 988 0x00000000, /* rs200 */ 989 0x00000000, /* r200 */ 990 0x00770000, /* rv250 */ 991 0x00290000, /* rs300 */ 992 0x00560000, /* rv280 */ 993 0x00780000, /* r300 */ 994 0x00770000, /* r350 */ 995 0x00780000, /* rv350 */ 996 0x00780000, /* rv380 */ 997 0x01080000, /* r420 */ 998 0x01080000, /* r423 */ 999 0x01080000, /* rv410 */ 1000 0x00780000, /* rs400 */ 1001 0x00780000, /* rs480 */ 1002 }; 1003 1004 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1005 struct radeon_encoder_tv_dac *tv_dac) 1006 { 1007 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1008 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1009 tv_dac->ps2_tvdac_adj = 0x00880000; 1010 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1011 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1012 return; 1013 } 1014 1015 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1016 radeon_encoder 1017 *encoder) 1018 { 1019 struct drm_device *dev = encoder->base.dev; 1020 struct radeon_device *rdev = dev->dev_private; 1021 uint16_t dac_info; 1022 uint8_t rev, bg, dac; 1023 struct radeon_encoder_tv_dac *tv_dac = NULL; 1024 int found = 0; 1025 1026 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1027 if (!tv_dac) 1028 return NULL; 1029 1030 /* first check TV table */ 1031 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1032 if (dac_info) { 1033 rev = RBIOS8(dac_info + 0x3); 1034 if (rev > 4) { 1035 bg = RBIOS8(dac_info + 0xc) & 0xf; 1036 dac = RBIOS8(dac_info + 0xd) & 0xf; 1037 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1038 1039 bg = RBIOS8(dac_info + 0xe) & 0xf; 1040 dac = RBIOS8(dac_info + 0xf) & 0xf; 1041 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1042 1043 bg = RBIOS8(dac_info + 0x10) & 0xf; 1044 dac = RBIOS8(dac_info + 0x11) & 0xf; 1045 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1046 /* if the values are all zeros, use the table */ 1047 if (tv_dac->ps2_tvdac_adj) 1048 found = 1; 1049 } else if (rev > 1) { 1050 bg = RBIOS8(dac_info + 0xc) & 0xf; 1051 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1052 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1053 1054 bg = RBIOS8(dac_info + 0xd) & 0xf; 1055 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1056 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1057 1058 bg = RBIOS8(dac_info + 0xe) & 0xf; 1059 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1060 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1061 /* if the values are all zeros, use the table */ 1062 if (tv_dac->ps2_tvdac_adj) 1063 found = 1; 1064 } 1065 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1066 } 1067 if (!found) { 1068 /* then check CRT table */ 1069 dac_info = 1070 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1071 if (dac_info) { 1072 rev = RBIOS8(dac_info) & 0x3; 1073 if (rev < 2) { 1074 bg = RBIOS8(dac_info + 0x3) & 0xf; 1075 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1076 tv_dac->ps2_tvdac_adj = 1077 (bg << 16) | (dac << 20); 1078 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1079 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1080 /* if the values are all zeros, use the table */ 1081 if (tv_dac->ps2_tvdac_adj) 1082 found = 1; 1083 } else { 1084 bg = RBIOS8(dac_info + 0x4) & 0xf; 1085 dac = RBIOS8(dac_info + 0x5) & 0xf; 1086 tv_dac->ps2_tvdac_adj = 1087 (bg << 16) | (dac << 20); 1088 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1089 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1090 /* if the values are all zeros, use the table */ 1091 if (tv_dac->ps2_tvdac_adj) 1092 found = 1; 1093 } 1094 } else { 1095 DRM_INFO("No TV DAC info found in BIOS\n"); 1096 } 1097 } 1098 1099 if (!found) /* fallback to defaults */ 1100 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1101 1102 return tv_dac; 1103 } 1104 1105 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1106 radeon_device 1107 *rdev) 1108 { 1109 struct radeon_encoder_lvds *lvds = NULL; 1110 uint32_t fp_vert_stretch, fp_horz_stretch; 1111 uint32_t ppll_div_sel, ppll_val; 1112 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1113 1114 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1115 1116 if (!lvds) 1117 return NULL; 1118 1119 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1120 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1121 1122 /* These should be fail-safe defaults, fingers crossed */ 1123 lvds->panel_pwr_delay = 200; 1124 lvds->panel_vcc_delay = 2000; 1125 1126 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1127 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1128 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1129 1130 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1131 lvds->native_mode.vdisplay = 1132 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1133 RADEON_VERT_PANEL_SHIFT) + 1; 1134 else 1135 lvds->native_mode.vdisplay = 1136 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1137 1138 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1139 lvds->native_mode.hdisplay = 1140 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1141 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1142 else 1143 lvds->native_mode.hdisplay = 1144 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1145 1146 if ((lvds->native_mode.hdisplay < 640) || 1147 (lvds->native_mode.vdisplay < 480)) { 1148 lvds->native_mode.hdisplay = 640; 1149 lvds->native_mode.vdisplay = 480; 1150 } 1151 1152 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1153 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1154 if ((ppll_val & 0x000707ff) == 0x1bb) 1155 lvds->use_bios_dividers = false; 1156 else { 1157 lvds->panel_ref_divider = 1158 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1159 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1160 lvds->panel_fb_divider = ppll_val & 0x7ff; 1161 1162 if ((lvds->panel_ref_divider != 0) && 1163 (lvds->panel_fb_divider > 3)) 1164 lvds->use_bios_dividers = true; 1165 } 1166 lvds->panel_vcc_delay = 200; 1167 1168 DRM_INFO("Panel info derived from registers\n"); 1169 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1170 lvds->native_mode.vdisplay); 1171 1172 return lvds; 1173 } 1174 1175 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1176 *encoder) 1177 { 1178 struct drm_device *dev = encoder->base.dev; 1179 struct radeon_device *rdev = dev->dev_private; 1180 uint16_t lcd_info; 1181 uint32_t panel_setup; 1182 char stmp[30]; 1183 int tmp, i; 1184 struct radeon_encoder_lvds *lvds = NULL; 1185 1186 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1187 1188 if (lcd_info) { 1189 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1190 1191 if (!lvds) 1192 return NULL; 1193 1194 for (i = 0; i < 24; i++) 1195 stmp[i] = RBIOS8(lcd_info + i + 1); 1196 stmp[24] = 0; 1197 1198 DRM_INFO("Panel ID String: %s\n", stmp); 1199 1200 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1201 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1202 1203 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1204 lvds->native_mode.vdisplay); 1205 1206 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1207 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1208 1209 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1210 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1211 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1212 1213 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1214 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1215 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1216 if ((lvds->panel_ref_divider != 0) && 1217 (lvds->panel_fb_divider > 3)) 1218 lvds->use_bios_dividers = true; 1219 1220 panel_setup = RBIOS32(lcd_info + 0x39); 1221 lvds->lvds_gen_cntl = 0xff00; 1222 if (panel_setup & 0x1) 1223 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1224 1225 if ((panel_setup >> 4) & 0x1) 1226 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1227 1228 switch ((panel_setup >> 8) & 0x7) { 1229 case 0: 1230 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1231 break; 1232 case 1: 1233 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1234 break; 1235 case 2: 1236 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1237 break; 1238 default: 1239 break; 1240 } 1241 1242 if ((panel_setup >> 16) & 0x1) 1243 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1244 1245 if ((panel_setup >> 17) & 0x1) 1246 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1247 1248 if ((panel_setup >> 18) & 0x1) 1249 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1250 1251 if ((panel_setup >> 23) & 0x1) 1252 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1253 1254 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1255 1256 for (i = 0; i < 32; i++) { 1257 tmp = RBIOS16(lcd_info + 64 + i * 2); 1258 if (tmp == 0) 1259 break; 1260 1261 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1262 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1263 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1264 1265 if (hss > lvds->native_mode.hdisplay) 1266 hss = (10 - 1) * 8; 1267 1268 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1269 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1270 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1271 hss; 1272 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1273 (RBIOS8(tmp + 23) * 8); 1274 1275 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1276 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1277 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1278 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1279 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1280 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1281 1282 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1283 lvds->native_mode.flags = 0; 1284 /* set crtc values */ 1285 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1286 1287 } 1288 } 1289 } else { 1290 DRM_INFO("No panel info found in BIOS\n"); 1291 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1292 } 1293 1294 if (lvds) 1295 encoder->native_mode = lvds->native_mode; 1296 return lvds; 1297 } 1298 1299 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1300 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1301 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1302 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1303 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1304 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1305 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1306 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1307 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1308 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1309 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1310 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1311 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1312 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1313 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1314 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1315 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1316 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1317 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1318 }; 1319 1320 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1321 struct radeon_encoder_int_tmds *tmds) 1322 { 1323 struct drm_device *dev = encoder->base.dev; 1324 struct radeon_device *rdev = dev->dev_private; 1325 int i; 1326 1327 for (i = 0; i < 4; i++) { 1328 tmds->tmds_pll[i].value = 1329 default_tmds_pll[rdev->family][i].value; 1330 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1331 } 1332 1333 return true; 1334 } 1335 1336 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1337 struct radeon_encoder_int_tmds *tmds) 1338 { 1339 struct drm_device *dev = encoder->base.dev; 1340 struct radeon_device *rdev = dev->dev_private; 1341 uint16_t tmds_info; 1342 int i, n; 1343 uint8_t ver; 1344 1345 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1346 1347 if (tmds_info) { 1348 ver = RBIOS8(tmds_info); 1349 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1350 if (ver == 3) { 1351 n = RBIOS8(tmds_info + 5) + 1; 1352 if (n > 4) 1353 n = 4; 1354 for (i = 0; i < n; i++) { 1355 tmds->tmds_pll[i].value = 1356 RBIOS32(tmds_info + i * 10 + 0x08); 1357 tmds->tmds_pll[i].freq = 1358 RBIOS16(tmds_info + i * 10 + 0x10); 1359 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1360 tmds->tmds_pll[i].freq, 1361 tmds->tmds_pll[i].value); 1362 } 1363 } else if (ver == 4) { 1364 int stride = 0; 1365 n = RBIOS8(tmds_info + 5) + 1; 1366 if (n > 4) 1367 n = 4; 1368 for (i = 0; i < n; i++) { 1369 tmds->tmds_pll[i].value = 1370 RBIOS32(tmds_info + stride + 0x08); 1371 tmds->tmds_pll[i].freq = 1372 RBIOS16(tmds_info + stride + 0x10); 1373 if (i == 0) 1374 stride += 10; 1375 else 1376 stride += 6; 1377 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1378 tmds->tmds_pll[i].freq, 1379 tmds->tmds_pll[i].value); 1380 } 1381 } 1382 } else { 1383 DRM_INFO("No TMDS info found in BIOS\n"); 1384 return false; 1385 } 1386 return true; 1387 } 1388 1389 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1390 struct radeon_encoder_ext_tmds *tmds) 1391 { 1392 struct drm_device *dev = encoder->base.dev; 1393 struct radeon_device *rdev = dev->dev_private; 1394 struct radeon_i2c_bus_rec i2c_bus; 1395 1396 /* default for macs */ 1397 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1398 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1399 1400 /* XXX some macs have duallink chips */ 1401 switch (rdev->mode_info.connector_table) { 1402 case CT_POWERBOOK_EXTERNAL: 1403 case CT_MINI_EXTERNAL: 1404 default: 1405 tmds->dvo_chip = DVO_SIL164; 1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1407 break; 1408 } 1409 1410 return true; 1411 } 1412 1413 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1414 struct radeon_encoder_ext_tmds *tmds) 1415 { 1416 struct drm_device *dev = encoder->base.dev; 1417 struct radeon_device *rdev = dev->dev_private; 1418 uint16_t offset; 1419 uint8_t ver; 1420 enum radeon_combios_ddc gpio; 1421 struct radeon_i2c_bus_rec i2c_bus; 1422 1423 tmds->i2c_bus = NULL; 1424 if (rdev->flags & RADEON_IS_IGP) { 1425 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1426 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1427 tmds->dvo_chip = DVO_SIL164; 1428 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1429 } else { 1430 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1431 if (offset) { 1432 ver = RBIOS8(offset); 1433 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1434 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1435 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1436 gpio = RBIOS8(offset + 4 + 3); 1437 if (gpio == DDC_LCD) { 1438 /* MM i2c */ 1439 i2c_bus.valid = true; 1440 i2c_bus.hw_capable = true; 1441 i2c_bus.mm_i2c = true; 1442 i2c_bus.i2c_id = 0xa0; 1443 } else 1444 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1445 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1446 } 1447 } 1448 1449 if (!tmds->i2c_bus) { 1450 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1451 return false; 1452 } 1453 1454 return true; 1455 } 1456 1457 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1458 { 1459 struct radeon_device *rdev = dev->dev_private; 1460 struct radeon_i2c_bus_rec ddc_i2c; 1461 struct radeon_hpd hpd; 1462 1463 rdev->mode_info.connector_table = radeon_connector_table; 1464 if (rdev->mode_info.connector_table == CT_NONE) { 1465 #ifdef CONFIG_PPC_PMAC 1466 if (of_machine_is_compatible("PowerBook3,3")) { 1467 /* powerbook with VGA */ 1468 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1469 } else if (of_machine_is_compatible("PowerBook3,4") || 1470 of_machine_is_compatible("PowerBook3,5")) { 1471 /* powerbook with internal tmds */ 1472 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1473 } else if (of_machine_is_compatible("PowerBook5,1") || 1474 of_machine_is_compatible("PowerBook5,2") || 1475 of_machine_is_compatible("PowerBook5,3") || 1476 of_machine_is_compatible("PowerBook5,4") || 1477 of_machine_is_compatible("PowerBook5,5")) { 1478 /* powerbook with external single link tmds (sil164) */ 1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1480 } else if (of_machine_is_compatible("PowerBook5,6")) { 1481 /* powerbook with external dual or single link tmds */ 1482 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1483 } else if (of_machine_is_compatible("PowerBook5,7") || 1484 of_machine_is_compatible("PowerBook5,8") || 1485 of_machine_is_compatible("PowerBook5,9")) { 1486 /* PowerBook6,2 ? */ 1487 /* powerbook with external dual link tmds (sil1178?) */ 1488 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1489 } else if (of_machine_is_compatible("PowerBook4,1") || 1490 of_machine_is_compatible("PowerBook4,2") || 1491 of_machine_is_compatible("PowerBook4,3") || 1492 of_machine_is_compatible("PowerBook6,3") || 1493 of_machine_is_compatible("PowerBook6,5") || 1494 of_machine_is_compatible("PowerBook6,7")) { 1495 /* ibook */ 1496 rdev->mode_info.connector_table = CT_IBOOK; 1497 } else if (of_machine_is_compatible("PowerMac3,5")) { 1498 /* PowerMac G4 Silver radeon 7500 */ 1499 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1500 } else if (of_machine_is_compatible("PowerMac4,4")) { 1501 /* emac */ 1502 rdev->mode_info.connector_table = CT_EMAC; 1503 } else if (of_machine_is_compatible("PowerMac10,1")) { 1504 /* mini with internal tmds */ 1505 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1506 } else if (of_machine_is_compatible("PowerMac10,2")) { 1507 /* mini with external tmds */ 1508 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1509 } else if (of_machine_is_compatible("PowerMac12,1")) { 1510 /* PowerMac8,1 ? */ 1511 /* imac g5 isight */ 1512 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1513 } else if ((rdev->pdev->device == 0x4a48) && 1514 (rdev->pdev->subsystem_vendor == 0x1002) && 1515 (rdev->pdev->subsystem_device == 0x4a48)) { 1516 /* Mac X800 */ 1517 rdev->mode_info.connector_table = CT_MAC_X800; 1518 } else if ((of_machine_is_compatible("PowerMac7,2") || 1519 of_machine_is_compatible("PowerMac7,3")) && 1520 (rdev->pdev->device == 0x4150) && 1521 (rdev->pdev->subsystem_vendor == 0x1002) && 1522 (rdev->pdev->subsystem_device == 0x4150)) { 1523 /* Mac G5 tower 9600 */ 1524 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1525 } else if ((rdev->pdev->device == 0x4c66) && 1526 (rdev->pdev->subsystem_vendor == 0x1002) && 1527 (rdev->pdev->subsystem_device == 0x4c66)) { 1528 /* SAM440ep RV250 embedded board */ 1529 rdev->mode_info.connector_table = CT_SAM440EP; 1530 } else 1531 #endif /* CONFIG_PPC_PMAC */ 1532 #ifdef CONFIG_PPC64 1533 if (ASIC_IS_RN50(rdev)) 1534 rdev->mode_info.connector_table = CT_RN50_POWER; 1535 else 1536 #endif 1537 rdev->mode_info.connector_table = CT_GENERIC; 1538 } 1539 1540 switch (rdev->mode_info.connector_table) { 1541 case CT_GENERIC: 1542 DRM_INFO("Connector Table: %d (generic)\n", 1543 rdev->mode_info.connector_table); 1544 /* these are the most common settings */ 1545 if (rdev->flags & RADEON_SINGLE_CRTC) { 1546 /* VGA - primary dac */ 1547 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1548 hpd.hpd = RADEON_HPD_NONE; 1549 radeon_add_legacy_encoder(dev, 1550 radeon_get_encoder_enum(dev, 1551 ATOM_DEVICE_CRT1_SUPPORT, 1552 1), 1553 ATOM_DEVICE_CRT1_SUPPORT); 1554 radeon_add_legacy_connector(dev, 0, 1555 ATOM_DEVICE_CRT1_SUPPORT, 1556 DRM_MODE_CONNECTOR_VGA, 1557 &ddc_i2c, 1558 CONNECTOR_OBJECT_ID_VGA, 1559 &hpd); 1560 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1561 /* LVDS */ 1562 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1563 hpd.hpd = RADEON_HPD_NONE; 1564 radeon_add_legacy_encoder(dev, 1565 radeon_get_encoder_enum(dev, 1566 ATOM_DEVICE_LCD1_SUPPORT, 1567 0), 1568 ATOM_DEVICE_LCD1_SUPPORT); 1569 radeon_add_legacy_connector(dev, 0, 1570 ATOM_DEVICE_LCD1_SUPPORT, 1571 DRM_MODE_CONNECTOR_LVDS, 1572 &ddc_i2c, 1573 CONNECTOR_OBJECT_ID_LVDS, 1574 &hpd); 1575 1576 /* VGA - primary dac */ 1577 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1578 hpd.hpd = RADEON_HPD_NONE; 1579 radeon_add_legacy_encoder(dev, 1580 radeon_get_encoder_enum(dev, 1581 ATOM_DEVICE_CRT1_SUPPORT, 1582 1), 1583 ATOM_DEVICE_CRT1_SUPPORT); 1584 radeon_add_legacy_connector(dev, 1, 1585 ATOM_DEVICE_CRT1_SUPPORT, 1586 DRM_MODE_CONNECTOR_VGA, 1587 &ddc_i2c, 1588 CONNECTOR_OBJECT_ID_VGA, 1589 &hpd); 1590 } else { 1591 /* DVI-I - tv dac, int tmds */ 1592 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1593 hpd.hpd = RADEON_HPD_1; 1594 radeon_add_legacy_encoder(dev, 1595 radeon_get_encoder_enum(dev, 1596 ATOM_DEVICE_DFP1_SUPPORT, 1597 0), 1598 ATOM_DEVICE_DFP1_SUPPORT); 1599 radeon_add_legacy_encoder(dev, 1600 radeon_get_encoder_enum(dev, 1601 ATOM_DEVICE_CRT2_SUPPORT, 1602 2), 1603 ATOM_DEVICE_CRT2_SUPPORT); 1604 radeon_add_legacy_connector(dev, 0, 1605 ATOM_DEVICE_DFP1_SUPPORT | 1606 ATOM_DEVICE_CRT2_SUPPORT, 1607 DRM_MODE_CONNECTOR_DVII, 1608 &ddc_i2c, 1609 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1610 &hpd); 1611 1612 /* VGA - primary dac */ 1613 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1614 hpd.hpd = RADEON_HPD_NONE; 1615 radeon_add_legacy_encoder(dev, 1616 radeon_get_encoder_enum(dev, 1617 ATOM_DEVICE_CRT1_SUPPORT, 1618 1), 1619 ATOM_DEVICE_CRT1_SUPPORT); 1620 radeon_add_legacy_connector(dev, 1, 1621 ATOM_DEVICE_CRT1_SUPPORT, 1622 DRM_MODE_CONNECTOR_VGA, 1623 &ddc_i2c, 1624 CONNECTOR_OBJECT_ID_VGA, 1625 &hpd); 1626 } 1627 1628 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1629 /* TV - tv dac */ 1630 ddc_i2c.valid = false; 1631 hpd.hpd = RADEON_HPD_NONE; 1632 radeon_add_legacy_encoder(dev, 1633 radeon_get_encoder_enum(dev, 1634 ATOM_DEVICE_TV1_SUPPORT, 1635 2), 1636 ATOM_DEVICE_TV1_SUPPORT); 1637 radeon_add_legacy_connector(dev, 2, 1638 ATOM_DEVICE_TV1_SUPPORT, 1639 DRM_MODE_CONNECTOR_SVIDEO, 1640 &ddc_i2c, 1641 CONNECTOR_OBJECT_ID_SVIDEO, 1642 &hpd); 1643 } 1644 break; 1645 case CT_IBOOK: 1646 DRM_INFO("Connector Table: %d (ibook)\n", 1647 rdev->mode_info.connector_table); 1648 /* LVDS */ 1649 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1650 hpd.hpd = RADEON_HPD_NONE; 1651 radeon_add_legacy_encoder(dev, 1652 radeon_get_encoder_enum(dev, 1653 ATOM_DEVICE_LCD1_SUPPORT, 1654 0), 1655 ATOM_DEVICE_LCD1_SUPPORT); 1656 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1657 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1658 CONNECTOR_OBJECT_ID_LVDS, 1659 &hpd); 1660 /* VGA - TV DAC */ 1661 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1662 hpd.hpd = RADEON_HPD_NONE; 1663 radeon_add_legacy_encoder(dev, 1664 radeon_get_encoder_enum(dev, 1665 ATOM_DEVICE_CRT2_SUPPORT, 1666 2), 1667 ATOM_DEVICE_CRT2_SUPPORT); 1668 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1669 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1670 CONNECTOR_OBJECT_ID_VGA, 1671 &hpd); 1672 /* TV - TV DAC */ 1673 ddc_i2c.valid = false; 1674 hpd.hpd = RADEON_HPD_NONE; 1675 radeon_add_legacy_encoder(dev, 1676 radeon_get_encoder_enum(dev, 1677 ATOM_DEVICE_TV1_SUPPORT, 1678 2), 1679 ATOM_DEVICE_TV1_SUPPORT); 1680 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1681 DRM_MODE_CONNECTOR_SVIDEO, 1682 &ddc_i2c, 1683 CONNECTOR_OBJECT_ID_SVIDEO, 1684 &hpd); 1685 break; 1686 case CT_POWERBOOK_EXTERNAL: 1687 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1688 rdev->mode_info.connector_table); 1689 /* LVDS */ 1690 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1691 hpd.hpd = RADEON_HPD_NONE; 1692 radeon_add_legacy_encoder(dev, 1693 radeon_get_encoder_enum(dev, 1694 ATOM_DEVICE_LCD1_SUPPORT, 1695 0), 1696 ATOM_DEVICE_LCD1_SUPPORT); 1697 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1698 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1699 CONNECTOR_OBJECT_ID_LVDS, 1700 &hpd); 1701 /* DVI-I - primary dac, ext tmds */ 1702 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1703 hpd.hpd = RADEON_HPD_2; /* ??? */ 1704 radeon_add_legacy_encoder(dev, 1705 radeon_get_encoder_enum(dev, 1706 ATOM_DEVICE_DFP2_SUPPORT, 1707 0), 1708 ATOM_DEVICE_DFP2_SUPPORT); 1709 radeon_add_legacy_encoder(dev, 1710 radeon_get_encoder_enum(dev, 1711 ATOM_DEVICE_CRT1_SUPPORT, 1712 1), 1713 ATOM_DEVICE_CRT1_SUPPORT); 1714 /* XXX some are SL */ 1715 radeon_add_legacy_connector(dev, 1, 1716 ATOM_DEVICE_DFP2_SUPPORT | 1717 ATOM_DEVICE_CRT1_SUPPORT, 1718 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1719 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1720 &hpd); 1721 /* TV - TV DAC */ 1722 ddc_i2c.valid = false; 1723 hpd.hpd = RADEON_HPD_NONE; 1724 radeon_add_legacy_encoder(dev, 1725 radeon_get_encoder_enum(dev, 1726 ATOM_DEVICE_TV1_SUPPORT, 1727 2), 1728 ATOM_DEVICE_TV1_SUPPORT); 1729 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1730 DRM_MODE_CONNECTOR_SVIDEO, 1731 &ddc_i2c, 1732 CONNECTOR_OBJECT_ID_SVIDEO, 1733 &hpd); 1734 break; 1735 case CT_POWERBOOK_INTERNAL: 1736 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1737 rdev->mode_info.connector_table); 1738 /* LVDS */ 1739 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1740 hpd.hpd = RADEON_HPD_NONE; 1741 radeon_add_legacy_encoder(dev, 1742 radeon_get_encoder_enum(dev, 1743 ATOM_DEVICE_LCD1_SUPPORT, 1744 0), 1745 ATOM_DEVICE_LCD1_SUPPORT); 1746 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1747 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1748 CONNECTOR_OBJECT_ID_LVDS, 1749 &hpd); 1750 /* DVI-I - primary dac, int tmds */ 1751 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1752 hpd.hpd = RADEON_HPD_1; /* ??? */ 1753 radeon_add_legacy_encoder(dev, 1754 radeon_get_encoder_enum(dev, 1755 ATOM_DEVICE_DFP1_SUPPORT, 1756 0), 1757 ATOM_DEVICE_DFP1_SUPPORT); 1758 radeon_add_legacy_encoder(dev, 1759 radeon_get_encoder_enum(dev, 1760 ATOM_DEVICE_CRT1_SUPPORT, 1761 1), 1762 ATOM_DEVICE_CRT1_SUPPORT); 1763 radeon_add_legacy_connector(dev, 1, 1764 ATOM_DEVICE_DFP1_SUPPORT | 1765 ATOM_DEVICE_CRT1_SUPPORT, 1766 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1767 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1768 &hpd); 1769 /* TV - TV DAC */ 1770 ddc_i2c.valid = false; 1771 hpd.hpd = RADEON_HPD_NONE; 1772 radeon_add_legacy_encoder(dev, 1773 radeon_get_encoder_enum(dev, 1774 ATOM_DEVICE_TV1_SUPPORT, 1775 2), 1776 ATOM_DEVICE_TV1_SUPPORT); 1777 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1778 DRM_MODE_CONNECTOR_SVIDEO, 1779 &ddc_i2c, 1780 CONNECTOR_OBJECT_ID_SVIDEO, 1781 &hpd); 1782 break; 1783 case CT_POWERBOOK_VGA: 1784 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1785 rdev->mode_info.connector_table); 1786 /* LVDS */ 1787 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1788 hpd.hpd = RADEON_HPD_NONE; 1789 radeon_add_legacy_encoder(dev, 1790 radeon_get_encoder_enum(dev, 1791 ATOM_DEVICE_LCD1_SUPPORT, 1792 0), 1793 ATOM_DEVICE_LCD1_SUPPORT); 1794 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1795 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1796 CONNECTOR_OBJECT_ID_LVDS, 1797 &hpd); 1798 /* VGA - primary dac */ 1799 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1800 hpd.hpd = RADEON_HPD_NONE; 1801 radeon_add_legacy_encoder(dev, 1802 radeon_get_encoder_enum(dev, 1803 ATOM_DEVICE_CRT1_SUPPORT, 1804 1), 1805 ATOM_DEVICE_CRT1_SUPPORT); 1806 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1807 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1808 CONNECTOR_OBJECT_ID_VGA, 1809 &hpd); 1810 /* TV - TV DAC */ 1811 ddc_i2c.valid = false; 1812 hpd.hpd = RADEON_HPD_NONE; 1813 radeon_add_legacy_encoder(dev, 1814 radeon_get_encoder_enum(dev, 1815 ATOM_DEVICE_TV1_SUPPORT, 1816 2), 1817 ATOM_DEVICE_TV1_SUPPORT); 1818 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1819 DRM_MODE_CONNECTOR_SVIDEO, 1820 &ddc_i2c, 1821 CONNECTOR_OBJECT_ID_SVIDEO, 1822 &hpd); 1823 break; 1824 case CT_MINI_EXTERNAL: 1825 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1826 rdev->mode_info.connector_table); 1827 /* DVI-I - tv dac, ext tmds */ 1828 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1829 hpd.hpd = RADEON_HPD_2; /* ??? */ 1830 radeon_add_legacy_encoder(dev, 1831 radeon_get_encoder_enum(dev, 1832 ATOM_DEVICE_DFP2_SUPPORT, 1833 0), 1834 ATOM_DEVICE_DFP2_SUPPORT); 1835 radeon_add_legacy_encoder(dev, 1836 radeon_get_encoder_enum(dev, 1837 ATOM_DEVICE_CRT2_SUPPORT, 1838 2), 1839 ATOM_DEVICE_CRT2_SUPPORT); 1840 /* XXX are any DL? */ 1841 radeon_add_legacy_connector(dev, 0, 1842 ATOM_DEVICE_DFP2_SUPPORT | 1843 ATOM_DEVICE_CRT2_SUPPORT, 1844 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1845 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1846 &hpd); 1847 /* TV - TV DAC */ 1848 ddc_i2c.valid = false; 1849 hpd.hpd = RADEON_HPD_NONE; 1850 radeon_add_legacy_encoder(dev, 1851 radeon_get_encoder_enum(dev, 1852 ATOM_DEVICE_TV1_SUPPORT, 1853 2), 1854 ATOM_DEVICE_TV1_SUPPORT); 1855 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1856 DRM_MODE_CONNECTOR_SVIDEO, 1857 &ddc_i2c, 1858 CONNECTOR_OBJECT_ID_SVIDEO, 1859 &hpd); 1860 break; 1861 case CT_MINI_INTERNAL: 1862 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1863 rdev->mode_info.connector_table); 1864 /* DVI-I - tv dac, int tmds */ 1865 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1866 hpd.hpd = RADEON_HPD_1; /* ??? */ 1867 radeon_add_legacy_encoder(dev, 1868 radeon_get_encoder_enum(dev, 1869 ATOM_DEVICE_DFP1_SUPPORT, 1870 0), 1871 ATOM_DEVICE_DFP1_SUPPORT); 1872 radeon_add_legacy_encoder(dev, 1873 radeon_get_encoder_enum(dev, 1874 ATOM_DEVICE_CRT2_SUPPORT, 1875 2), 1876 ATOM_DEVICE_CRT2_SUPPORT); 1877 radeon_add_legacy_connector(dev, 0, 1878 ATOM_DEVICE_DFP1_SUPPORT | 1879 ATOM_DEVICE_CRT2_SUPPORT, 1880 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1881 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1882 &hpd); 1883 /* TV - TV DAC */ 1884 ddc_i2c.valid = false; 1885 hpd.hpd = RADEON_HPD_NONE; 1886 radeon_add_legacy_encoder(dev, 1887 radeon_get_encoder_enum(dev, 1888 ATOM_DEVICE_TV1_SUPPORT, 1889 2), 1890 ATOM_DEVICE_TV1_SUPPORT); 1891 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1892 DRM_MODE_CONNECTOR_SVIDEO, 1893 &ddc_i2c, 1894 CONNECTOR_OBJECT_ID_SVIDEO, 1895 &hpd); 1896 break; 1897 case CT_IMAC_G5_ISIGHT: 1898 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1899 rdev->mode_info.connector_table); 1900 /* DVI-D - int tmds */ 1901 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1902 hpd.hpd = RADEON_HPD_1; /* ??? */ 1903 radeon_add_legacy_encoder(dev, 1904 radeon_get_encoder_enum(dev, 1905 ATOM_DEVICE_DFP1_SUPPORT, 1906 0), 1907 ATOM_DEVICE_DFP1_SUPPORT); 1908 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1909 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1910 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1911 &hpd); 1912 /* VGA - tv dac */ 1913 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1914 hpd.hpd = RADEON_HPD_NONE; 1915 radeon_add_legacy_encoder(dev, 1916 radeon_get_encoder_enum(dev, 1917 ATOM_DEVICE_CRT2_SUPPORT, 1918 2), 1919 ATOM_DEVICE_CRT2_SUPPORT); 1920 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1921 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1922 CONNECTOR_OBJECT_ID_VGA, 1923 &hpd); 1924 /* TV - TV DAC */ 1925 ddc_i2c.valid = false; 1926 hpd.hpd = RADEON_HPD_NONE; 1927 radeon_add_legacy_encoder(dev, 1928 radeon_get_encoder_enum(dev, 1929 ATOM_DEVICE_TV1_SUPPORT, 1930 2), 1931 ATOM_DEVICE_TV1_SUPPORT); 1932 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1933 DRM_MODE_CONNECTOR_SVIDEO, 1934 &ddc_i2c, 1935 CONNECTOR_OBJECT_ID_SVIDEO, 1936 &hpd); 1937 break; 1938 case CT_EMAC: 1939 DRM_INFO("Connector Table: %d (emac)\n", 1940 rdev->mode_info.connector_table); 1941 /* VGA - primary dac */ 1942 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1943 hpd.hpd = RADEON_HPD_NONE; 1944 radeon_add_legacy_encoder(dev, 1945 radeon_get_encoder_enum(dev, 1946 ATOM_DEVICE_CRT1_SUPPORT, 1947 1), 1948 ATOM_DEVICE_CRT1_SUPPORT); 1949 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1950 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1951 CONNECTOR_OBJECT_ID_VGA, 1952 &hpd); 1953 /* VGA - tv dac */ 1954 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1955 hpd.hpd = RADEON_HPD_NONE; 1956 radeon_add_legacy_encoder(dev, 1957 radeon_get_encoder_enum(dev, 1958 ATOM_DEVICE_CRT2_SUPPORT, 1959 2), 1960 ATOM_DEVICE_CRT2_SUPPORT); 1961 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1962 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1963 CONNECTOR_OBJECT_ID_VGA, 1964 &hpd); 1965 /* TV - TV DAC */ 1966 ddc_i2c.valid = false; 1967 hpd.hpd = RADEON_HPD_NONE; 1968 radeon_add_legacy_encoder(dev, 1969 radeon_get_encoder_enum(dev, 1970 ATOM_DEVICE_TV1_SUPPORT, 1971 2), 1972 ATOM_DEVICE_TV1_SUPPORT); 1973 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1974 DRM_MODE_CONNECTOR_SVIDEO, 1975 &ddc_i2c, 1976 CONNECTOR_OBJECT_ID_SVIDEO, 1977 &hpd); 1978 break; 1979 case CT_RN50_POWER: 1980 DRM_INFO("Connector Table: %d (rn50-power)\n", 1981 rdev->mode_info.connector_table); 1982 /* VGA - primary dac */ 1983 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1984 hpd.hpd = RADEON_HPD_NONE; 1985 radeon_add_legacy_encoder(dev, 1986 radeon_get_encoder_enum(dev, 1987 ATOM_DEVICE_CRT1_SUPPORT, 1988 1), 1989 ATOM_DEVICE_CRT1_SUPPORT); 1990 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1991 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1992 CONNECTOR_OBJECT_ID_VGA, 1993 &hpd); 1994 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1995 hpd.hpd = RADEON_HPD_NONE; 1996 radeon_add_legacy_encoder(dev, 1997 radeon_get_encoder_enum(dev, 1998 ATOM_DEVICE_CRT2_SUPPORT, 1999 2), 2000 ATOM_DEVICE_CRT2_SUPPORT); 2001 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 2002 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2003 CONNECTOR_OBJECT_ID_VGA, 2004 &hpd); 2005 break; 2006 case CT_MAC_X800: 2007 DRM_INFO("Connector Table: %d (mac x800)\n", 2008 rdev->mode_info.connector_table); 2009 /* DVI - primary dac, internal tmds */ 2010 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2011 hpd.hpd = RADEON_HPD_1; /* ??? */ 2012 radeon_add_legacy_encoder(dev, 2013 radeon_get_encoder_enum(dev, 2014 ATOM_DEVICE_DFP1_SUPPORT, 2015 0), 2016 ATOM_DEVICE_DFP1_SUPPORT); 2017 radeon_add_legacy_encoder(dev, 2018 radeon_get_encoder_enum(dev, 2019 ATOM_DEVICE_CRT1_SUPPORT, 2020 1), 2021 ATOM_DEVICE_CRT1_SUPPORT); 2022 radeon_add_legacy_connector(dev, 0, 2023 ATOM_DEVICE_DFP1_SUPPORT | 2024 ATOM_DEVICE_CRT1_SUPPORT, 2025 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2026 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2027 &hpd); 2028 /* DVI - tv dac, dvo */ 2029 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2030 hpd.hpd = RADEON_HPD_2; /* ??? */ 2031 radeon_add_legacy_encoder(dev, 2032 radeon_get_encoder_enum(dev, 2033 ATOM_DEVICE_DFP2_SUPPORT, 2034 0), 2035 ATOM_DEVICE_DFP2_SUPPORT); 2036 radeon_add_legacy_encoder(dev, 2037 radeon_get_encoder_enum(dev, 2038 ATOM_DEVICE_CRT2_SUPPORT, 2039 2), 2040 ATOM_DEVICE_CRT2_SUPPORT); 2041 radeon_add_legacy_connector(dev, 1, 2042 ATOM_DEVICE_DFP2_SUPPORT | 2043 ATOM_DEVICE_CRT2_SUPPORT, 2044 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2045 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2046 &hpd); 2047 break; 2048 case CT_MAC_G5_9600: 2049 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2050 rdev->mode_info.connector_table); 2051 /* DVI - tv dac, dvo */ 2052 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2053 hpd.hpd = RADEON_HPD_1; /* ??? */ 2054 radeon_add_legacy_encoder(dev, 2055 radeon_get_encoder_enum(dev, 2056 ATOM_DEVICE_DFP2_SUPPORT, 2057 0), 2058 ATOM_DEVICE_DFP2_SUPPORT); 2059 radeon_add_legacy_encoder(dev, 2060 radeon_get_encoder_enum(dev, 2061 ATOM_DEVICE_CRT2_SUPPORT, 2062 2), 2063 ATOM_DEVICE_CRT2_SUPPORT); 2064 radeon_add_legacy_connector(dev, 0, 2065 ATOM_DEVICE_DFP2_SUPPORT | 2066 ATOM_DEVICE_CRT2_SUPPORT, 2067 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2068 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2069 &hpd); 2070 /* ADC - primary dac, internal tmds */ 2071 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2072 hpd.hpd = RADEON_HPD_2; /* ??? */ 2073 radeon_add_legacy_encoder(dev, 2074 radeon_get_encoder_enum(dev, 2075 ATOM_DEVICE_DFP1_SUPPORT, 2076 0), 2077 ATOM_DEVICE_DFP1_SUPPORT); 2078 radeon_add_legacy_encoder(dev, 2079 radeon_get_encoder_enum(dev, 2080 ATOM_DEVICE_CRT1_SUPPORT, 2081 1), 2082 ATOM_DEVICE_CRT1_SUPPORT); 2083 radeon_add_legacy_connector(dev, 1, 2084 ATOM_DEVICE_DFP1_SUPPORT | 2085 ATOM_DEVICE_CRT1_SUPPORT, 2086 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2087 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2088 &hpd); 2089 /* TV - TV DAC */ 2090 ddc_i2c.valid = false; 2091 hpd.hpd = RADEON_HPD_NONE; 2092 radeon_add_legacy_encoder(dev, 2093 radeon_get_encoder_enum(dev, 2094 ATOM_DEVICE_TV1_SUPPORT, 2095 2), 2096 ATOM_DEVICE_TV1_SUPPORT); 2097 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2098 DRM_MODE_CONNECTOR_SVIDEO, 2099 &ddc_i2c, 2100 CONNECTOR_OBJECT_ID_SVIDEO, 2101 &hpd); 2102 break; 2103 case CT_SAM440EP: 2104 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2105 rdev->mode_info.connector_table); 2106 /* LVDS */ 2107 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2108 hpd.hpd = RADEON_HPD_NONE; 2109 radeon_add_legacy_encoder(dev, 2110 radeon_get_encoder_enum(dev, 2111 ATOM_DEVICE_LCD1_SUPPORT, 2112 0), 2113 ATOM_DEVICE_LCD1_SUPPORT); 2114 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2115 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2116 CONNECTOR_OBJECT_ID_LVDS, 2117 &hpd); 2118 /* DVI-I - secondary dac, int tmds */ 2119 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2120 hpd.hpd = RADEON_HPD_1; /* ??? */ 2121 radeon_add_legacy_encoder(dev, 2122 radeon_get_encoder_enum(dev, 2123 ATOM_DEVICE_DFP1_SUPPORT, 2124 0), 2125 ATOM_DEVICE_DFP1_SUPPORT); 2126 radeon_add_legacy_encoder(dev, 2127 radeon_get_encoder_enum(dev, 2128 ATOM_DEVICE_CRT2_SUPPORT, 2129 2), 2130 ATOM_DEVICE_CRT2_SUPPORT); 2131 radeon_add_legacy_connector(dev, 1, 2132 ATOM_DEVICE_DFP1_SUPPORT | 2133 ATOM_DEVICE_CRT2_SUPPORT, 2134 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2135 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2136 &hpd); 2137 /* VGA - primary dac */ 2138 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2139 hpd.hpd = RADEON_HPD_NONE; 2140 radeon_add_legacy_encoder(dev, 2141 radeon_get_encoder_enum(dev, 2142 ATOM_DEVICE_CRT1_SUPPORT, 2143 1), 2144 ATOM_DEVICE_CRT1_SUPPORT); 2145 radeon_add_legacy_connector(dev, 2, 2146 ATOM_DEVICE_CRT1_SUPPORT, 2147 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2148 CONNECTOR_OBJECT_ID_VGA, 2149 &hpd); 2150 /* TV - TV DAC */ 2151 ddc_i2c.valid = false; 2152 hpd.hpd = RADEON_HPD_NONE; 2153 radeon_add_legacy_encoder(dev, 2154 radeon_get_encoder_enum(dev, 2155 ATOM_DEVICE_TV1_SUPPORT, 2156 2), 2157 ATOM_DEVICE_TV1_SUPPORT); 2158 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2159 DRM_MODE_CONNECTOR_SVIDEO, 2160 &ddc_i2c, 2161 CONNECTOR_OBJECT_ID_SVIDEO, 2162 &hpd); 2163 break; 2164 case CT_MAC_G4_SILVER: 2165 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2166 rdev->mode_info.connector_table); 2167 /* DVI-I - tv dac, int tmds */ 2168 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2169 hpd.hpd = RADEON_HPD_1; /* ??? */ 2170 radeon_add_legacy_encoder(dev, 2171 radeon_get_encoder_enum(dev, 2172 ATOM_DEVICE_DFP1_SUPPORT, 2173 0), 2174 ATOM_DEVICE_DFP1_SUPPORT); 2175 radeon_add_legacy_encoder(dev, 2176 radeon_get_encoder_enum(dev, 2177 ATOM_DEVICE_CRT2_SUPPORT, 2178 2), 2179 ATOM_DEVICE_CRT2_SUPPORT); 2180 radeon_add_legacy_connector(dev, 0, 2181 ATOM_DEVICE_DFP1_SUPPORT | 2182 ATOM_DEVICE_CRT2_SUPPORT, 2183 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2184 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2185 &hpd); 2186 /* VGA - primary dac */ 2187 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2188 hpd.hpd = RADEON_HPD_NONE; 2189 radeon_add_legacy_encoder(dev, 2190 radeon_get_encoder_enum(dev, 2191 ATOM_DEVICE_CRT1_SUPPORT, 2192 1), 2193 ATOM_DEVICE_CRT1_SUPPORT); 2194 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2195 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2196 CONNECTOR_OBJECT_ID_VGA, 2197 &hpd); 2198 /* TV - TV DAC */ 2199 ddc_i2c.valid = false; 2200 hpd.hpd = RADEON_HPD_NONE; 2201 radeon_add_legacy_encoder(dev, 2202 radeon_get_encoder_enum(dev, 2203 ATOM_DEVICE_TV1_SUPPORT, 2204 2), 2205 ATOM_DEVICE_TV1_SUPPORT); 2206 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2207 DRM_MODE_CONNECTOR_SVIDEO, 2208 &ddc_i2c, 2209 CONNECTOR_OBJECT_ID_SVIDEO, 2210 &hpd); 2211 break; 2212 default: 2213 DRM_INFO("Connector table: %d (invalid)\n", 2214 rdev->mode_info.connector_table); 2215 return false; 2216 } 2217 2218 radeon_link_encoder_connector(dev); 2219 2220 return true; 2221 } 2222 2223 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2224 int bios_index, 2225 enum radeon_combios_connector 2226 *legacy_connector, 2227 struct radeon_i2c_bus_rec *ddc_i2c, 2228 struct radeon_hpd *hpd) 2229 { 2230 2231 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2232 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2233 if (dev->pdev->device == 0x515e && 2234 dev->pdev->subsystem_vendor == 0x1014) { 2235 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2236 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2237 return false; 2238 } 2239 2240 /* X300 card with extra non-existent DVI port */ 2241 if (dev->pdev->device == 0x5B60 && 2242 dev->pdev->subsystem_vendor == 0x17af && 2243 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2244 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2245 return false; 2246 } 2247 2248 return true; 2249 } 2250 2251 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2252 { 2253 /* Acer 5102 has non-existent TV port */ 2254 if (dev->pdev->device == 0x5975 && 2255 dev->pdev->subsystem_vendor == 0x1025 && 2256 dev->pdev->subsystem_device == 0x009f) 2257 return false; 2258 2259 /* HP dc5750 has non-existent TV port */ 2260 if (dev->pdev->device == 0x5974 && 2261 dev->pdev->subsystem_vendor == 0x103c && 2262 dev->pdev->subsystem_device == 0x280a) 2263 return false; 2264 2265 /* MSI S270 has non-existent TV port */ 2266 if (dev->pdev->device == 0x5955 && 2267 dev->pdev->subsystem_vendor == 0x1462 && 2268 dev->pdev->subsystem_device == 0x0131) 2269 return false; 2270 2271 return true; 2272 } 2273 2274 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2275 { 2276 struct radeon_device *rdev = dev->dev_private; 2277 uint32_t ext_tmds_info; 2278 2279 if (rdev->flags & RADEON_IS_IGP) { 2280 if (is_dvi_d) 2281 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2282 else 2283 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2284 } 2285 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2286 if (ext_tmds_info) { 2287 uint8_t rev = RBIOS8(ext_tmds_info); 2288 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2289 if (rev >= 3) { 2290 if (is_dvi_d) 2291 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2292 else 2293 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2294 } else { 2295 if (flags & 1) { 2296 if (is_dvi_d) 2297 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2298 else 2299 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2300 } 2301 } 2302 } 2303 if (is_dvi_d) 2304 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2305 else 2306 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2307 } 2308 2309 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2310 { 2311 struct radeon_device *rdev = dev->dev_private; 2312 uint32_t conn_info, entry, devices; 2313 uint16_t tmp, connector_object_id; 2314 enum radeon_combios_ddc ddc_type; 2315 enum radeon_combios_connector connector; 2316 int i = 0; 2317 struct radeon_i2c_bus_rec ddc_i2c; 2318 struct radeon_hpd hpd; 2319 2320 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2321 if (conn_info) { 2322 for (i = 0; i < 4; i++) { 2323 entry = conn_info + 2 + i * 2; 2324 2325 if (!RBIOS16(entry)) 2326 break; 2327 2328 tmp = RBIOS16(entry); 2329 2330 connector = (tmp >> 12) & 0xf; 2331 2332 ddc_type = (tmp >> 8) & 0xf; 2333 if (ddc_type == 5) 2334 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2335 else 2336 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2337 2338 switch (connector) { 2339 case CONNECTOR_PROPRIETARY_LEGACY: 2340 case CONNECTOR_DVI_I_LEGACY: 2341 case CONNECTOR_DVI_D_LEGACY: 2342 if ((tmp >> 4) & 0x1) 2343 hpd.hpd = RADEON_HPD_2; 2344 else 2345 hpd.hpd = RADEON_HPD_1; 2346 break; 2347 default: 2348 hpd.hpd = RADEON_HPD_NONE; 2349 break; 2350 } 2351 2352 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2353 &ddc_i2c, &hpd)) 2354 continue; 2355 2356 switch (connector) { 2357 case CONNECTOR_PROPRIETARY_LEGACY: 2358 if ((tmp >> 4) & 0x1) 2359 devices = ATOM_DEVICE_DFP2_SUPPORT; 2360 else 2361 devices = ATOM_DEVICE_DFP1_SUPPORT; 2362 radeon_add_legacy_encoder(dev, 2363 radeon_get_encoder_enum 2364 (dev, devices, 0), 2365 devices); 2366 radeon_add_legacy_connector(dev, i, devices, 2367 legacy_connector_convert 2368 [connector], 2369 &ddc_i2c, 2370 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2371 &hpd); 2372 break; 2373 case CONNECTOR_CRT_LEGACY: 2374 if (tmp & 0x1) { 2375 devices = ATOM_DEVICE_CRT2_SUPPORT; 2376 radeon_add_legacy_encoder(dev, 2377 radeon_get_encoder_enum 2378 (dev, 2379 ATOM_DEVICE_CRT2_SUPPORT, 2380 2), 2381 ATOM_DEVICE_CRT2_SUPPORT); 2382 } else { 2383 devices = ATOM_DEVICE_CRT1_SUPPORT; 2384 radeon_add_legacy_encoder(dev, 2385 radeon_get_encoder_enum 2386 (dev, 2387 ATOM_DEVICE_CRT1_SUPPORT, 2388 1), 2389 ATOM_DEVICE_CRT1_SUPPORT); 2390 } 2391 radeon_add_legacy_connector(dev, 2392 i, 2393 devices, 2394 legacy_connector_convert 2395 [connector], 2396 &ddc_i2c, 2397 CONNECTOR_OBJECT_ID_VGA, 2398 &hpd); 2399 break; 2400 case CONNECTOR_DVI_I_LEGACY: 2401 devices = 0; 2402 if (tmp & 0x1) { 2403 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2404 radeon_add_legacy_encoder(dev, 2405 radeon_get_encoder_enum 2406 (dev, 2407 ATOM_DEVICE_CRT2_SUPPORT, 2408 2), 2409 ATOM_DEVICE_CRT2_SUPPORT); 2410 } else { 2411 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2412 radeon_add_legacy_encoder(dev, 2413 radeon_get_encoder_enum 2414 (dev, 2415 ATOM_DEVICE_CRT1_SUPPORT, 2416 1), 2417 ATOM_DEVICE_CRT1_SUPPORT); 2418 } 2419 /* RV100 board with external TDMS bit mis-set. 2420 * Actually uses internal TMDS, clear the bit. 2421 */ 2422 if (dev->pdev->device == 0x5159 && 2423 dev->pdev->subsystem_vendor == 0x1014 && 2424 dev->pdev->subsystem_device == 0x029A) { 2425 tmp &= ~(1 << 4); 2426 } 2427 if ((tmp >> 4) & 0x1) { 2428 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2429 radeon_add_legacy_encoder(dev, 2430 radeon_get_encoder_enum 2431 (dev, 2432 ATOM_DEVICE_DFP2_SUPPORT, 2433 0), 2434 ATOM_DEVICE_DFP2_SUPPORT); 2435 connector_object_id = combios_check_dl_dvi(dev, 0); 2436 } else { 2437 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2438 radeon_add_legacy_encoder(dev, 2439 radeon_get_encoder_enum 2440 (dev, 2441 ATOM_DEVICE_DFP1_SUPPORT, 2442 0), 2443 ATOM_DEVICE_DFP1_SUPPORT); 2444 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2445 } 2446 radeon_add_legacy_connector(dev, 2447 i, 2448 devices, 2449 legacy_connector_convert 2450 [connector], 2451 &ddc_i2c, 2452 connector_object_id, 2453 &hpd); 2454 break; 2455 case CONNECTOR_DVI_D_LEGACY: 2456 if ((tmp >> 4) & 0x1) { 2457 devices = ATOM_DEVICE_DFP2_SUPPORT; 2458 connector_object_id = combios_check_dl_dvi(dev, 1); 2459 } else { 2460 devices = ATOM_DEVICE_DFP1_SUPPORT; 2461 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2462 } 2463 radeon_add_legacy_encoder(dev, 2464 radeon_get_encoder_enum 2465 (dev, devices, 0), 2466 devices); 2467 radeon_add_legacy_connector(dev, i, devices, 2468 legacy_connector_convert 2469 [connector], 2470 &ddc_i2c, 2471 connector_object_id, 2472 &hpd); 2473 break; 2474 case CONNECTOR_CTV_LEGACY: 2475 case CONNECTOR_STV_LEGACY: 2476 radeon_add_legacy_encoder(dev, 2477 radeon_get_encoder_enum 2478 (dev, 2479 ATOM_DEVICE_TV1_SUPPORT, 2480 2), 2481 ATOM_DEVICE_TV1_SUPPORT); 2482 radeon_add_legacy_connector(dev, i, 2483 ATOM_DEVICE_TV1_SUPPORT, 2484 legacy_connector_convert 2485 [connector], 2486 &ddc_i2c, 2487 CONNECTOR_OBJECT_ID_SVIDEO, 2488 &hpd); 2489 break; 2490 default: 2491 DRM_ERROR("Unknown connector type: %d\n", 2492 connector); 2493 continue; 2494 } 2495 2496 } 2497 } else { 2498 uint16_t tmds_info = 2499 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2500 if (tmds_info) { 2501 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2502 2503 radeon_add_legacy_encoder(dev, 2504 radeon_get_encoder_enum(dev, 2505 ATOM_DEVICE_CRT1_SUPPORT, 2506 1), 2507 ATOM_DEVICE_CRT1_SUPPORT); 2508 radeon_add_legacy_encoder(dev, 2509 radeon_get_encoder_enum(dev, 2510 ATOM_DEVICE_DFP1_SUPPORT, 2511 0), 2512 ATOM_DEVICE_DFP1_SUPPORT); 2513 2514 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2515 hpd.hpd = RADEON_HPD_1; 2516 radeon_add_legacy_connector(dev, 2517 0, 2518 ATOM_DEVICE_CRT1_SUPPORT | 2519 ATOM_DEVICE_DFP1_SUPPORT, 2520 DRM_MODE_CONNECTOR_DVII, 2521 &ddc_i2c, 2522 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2523 &hpd); 2524 } else { 2525 uint16_t crt_info = 2526 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2527 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2528 if (crt_info) { 2529 radeon_add_legacy_encoder(dev, 2530 radeon_get_encoder_enum(dev, 2531 ATOM_DEVICE_CRT1_SUPPORT, 2532 1), 2533 ATOM_DEVICE_CRT1_SUPPORT); 2534 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2535 hpd.hpd = RADEON_HPD_NONE; 2536 radeon_add_legacy_connector(dev, 2537 0, 2538 ATOM_DEVICE_CRT1_SUPPORT, 2539 DRM_MODE_CONNECTOR_VGA, 2540 &ddc_i2c, 2541 CONNECTOR_OBJECT_ID_VGA, 2542 &hpd); 2543 } else { 2544 DRM_DEBUG_KMS("No connector info found\n"); 2545 return false; 2546 } 2547 } 2548 } 2549 2550 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2551 uint16_t lcd_info = 2552 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2553 if (lcd_info) { 2554 uint16_t lcd_ddc_info = 2555 combios_get_table_offset(dev, 2556 COMBIOS_LCD_DDC_INFO_TABLE); 2557 2558 radeon_add_legacy_encoder(dev, 2559 radeon_get_encoder_enum(dev, 2560 ATOM_DEVICE_LCD1_SUPPORT, 2561 0), 2562 ATOM_DEVICE_LCD1_SUPPORT); 2563 2564 if (lcd_ddc_info) { 2565 ddc_type = RBIOS8(lcd_ddc_info + 2); 2566 switch (ddc_type) { 2567 case DDC_LCD: 2568 ddc_i2c = 2569 combios_setup_i2c_bus(rdev, 2570 DDC_LCD, 2571 RBIOS32(lcd_ddc_info + 3), 2572 RBIOS32(lcd_ddc_info + 7)); 2573 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2574 break; 2575 case DDC_GPIO: 2576 ddc_i2c = 2577 combios_setup_i2c_bus(rdev, 2578 DDC_GPIO, 2579 RBIOS32(lcd_ddc_info + 3), 2580 RBIOS32(lcd_ddc_info + 7)); 2581 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2582 break; 2583 default: 2584 ddc_i2c = 2585 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2586 break; 2587 } 2588 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2589 } else 2590 ddc_i2c.valid = false; 2591 2592 hpd.hpd = RADEON_HPD_NONE; 2593 radeon_add_legacy_connector(dev, 2594 5, 2595 ATOM_DEVICE_LCD1_SUPPORT, 2596 DRM_MODE_CONNECTOR_LVDS, 2597 &ddc_i2c, 2598 CONNECTOR_OBJECT_ID_LVDS, 2599 &hpd); 2600 } 2601 } 2602 2603 /* check TV table */ 2604 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2605 uint32_t tv_info = 2606 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2607 if (tv_info) { 2608 if (RBIOS8(tv_info + 6) == 'T') { 2609 if (radeon_apply_legacy_tv_quirks(dev)) { 2610 hpd.hpd = RADEON_HPD_NONE; 2611 ddc_i2c.valid = false; 2612 radeon_add_legacy_encoder(dev, 2613 radeon_get_encoder_enum 2614 (dev, 2615 ATOM_DEVICE_TV1_SUPPORT, 2616 2), 2617 ATOM_DEVICE_TV1_SUPPORT); 2618 radeon_add_legacy_connector(dev, 6, 2619 ATOM_DEVICE_TV1_SUPPORT, 2620 DRM_MODE_CONNECTOR_SVIDEO, 2621 &ddc_i2c, 2622 CONNECTOR_OBJECT_ID_SVIDEO, 2623 &hpd); 2624 } 2625 } 2626 } 2627 } 2628 2629 radeon_link_encoder_connector(dev); 2630 2631 return true; 2632 } 2633 2634 static const char *thermal_controller_names[] = { 2635 "NONE", 2636 "lm63", 2637 "adm1032", 2638 }; 2639 2640 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2641 { 2642 struct drm_device *dev = rdev->ddev; 2643 u16 offset, misc, misc2 = 0; 2644 u8 rev, blocks __unused, tmp; 2645 int state_index = 0; 2646 struct radeon_i2c_bus_rec i2c_bus; 2647 2648 rdev->pm.default_power_state_index = -1; 2649 2650 /* allocate 2 power states */ 2651 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); 2652 if (rdev->pm.power_state) { 2653 /* allocate 1 clock mode per state */ 2654 rdev->pm.power_state[0].clock_info = 2655 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2656 rdev->pm.power_state[1].clock_info = 2657 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2658 if (!rdev->pm.power_state[0].clock_info || 2659 !rdev->pm.power_state[1].clock_info) 2660 goto pm_failed; 2661 } else 2662 goto pm_failed; 2663 2664 /* check for a thermal chip */ 2665 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2666 if (offset) { 2667 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2668 2669 rev = RBIOS8(offset); 2670 2671 if (rev == 0) { 2672 thermal_controller = RBIOS8(offset + 3); 2673 gpio = RBIOS8(offset + 4) & 0x3f; 2674 i2c_addr = RBIOS8(offset + 5); 2675 } else if (rev == 1) { 2676 thermal_controller = RBIOS8(offset + 4); 2677 gpio = RBIOS8(offset + 5) & 0x3f; 2678 i2c_addr = RBIOS8(offset + 6); 2679 } else if (rev == 2) { 2680 thermal_controller = RBIOS8(offset + 4); 2681 gpio = RBIOS8(offset + 5) & 0x3f; 2682 i2c_addr = RBIOS8(offset + 6); 2683 clk_bit = RBIOS8(offset + 0xa); 2684 data_bit = RBIOS8(offset + 0xb); 2685 } 2686 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2687 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2688 thermal_controller_names[thermal_controller], 2689 i2c_addr >> 1); 2690 if (gpio == DDC_LCD) { 2691 /* MM i2c */ 2692 i2c_bus.valid = true; 2693 i2c_bus.hw_capable = true; 2694 i2c_bus.mm_i2c = true; 2695 i2c_bus.i2c_id = 0xa0; 2696 } else if (gpio == DDC_GPIO) 2697 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2698 else 2699 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2700 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2701 if (rdev->pm.i2c_bus) { 2702 struct i2c_board_info info = { }; 2703 const char *name = thermal_controller_names[thermal_controller]; 2704 info.addr = i2c_addr >> 1; 2705 strlcpy(info.type, name, sizeof(info.type)); 2706 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2707 } 2708 } 2709 } else { 2710 /* boards with a thermal chip, but no overdrive table */ 2711 2712 /* Asus 9600xt has an f75375 on the monid bus */ 2713 if ((dev->pdev->device == 0x4152) && 2714 (dev->pdev->subsystem_vendor == 0x1043) && 2715 (dev->pdev->subsystem_device == 0xc002)) { 2716 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2717 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2718 if (rdev->pm.i2c_bus) { 2719 struct i2c_board_info info = { }; 2720 const char *name = "f75375"; 2721 info.addr = 0x28; 2722 strlcpy(info.type, name, sizeof(info.type)); 2723 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2724 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2725 name, info.addr); 2726 } 2727 } 2728 } 2729 2730 if (rdev->flags & RADEON_IS_MOBILITY) { 2731 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2732 if (offset) { 2733 rev = RBIOS8(offset); 2734 blocks = RBIOS8(offset + 0x2); 2735 /* power mode 0 tends to be the only valid one */ 2736 rdev->pm.power_state[state_index].num_clock_modes = 1; 2737 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2738 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2739 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2740 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2741 goto default_mode; 2742 rdev->pm.power_state[state_index].type = 2743 POWER_STATE_TYPE_BATTERY; 2744 misc = RBIOS16(offset + 0x5 + 0x0); 2745 if (rev > 4) 2746 misc2 = RBIOS16(offset + 0x5 + 0xe); 2747 rdev->pm.power_state[state_index].misc = misc; 2748 rdev->pm.power_state[state_index].misc2 = misc2; 2749 if (misc & 0x4) { 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2751 if (misc & 0x8) 2752 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2753 true; 2754 else 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2756 false; 2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2758 if (rev < 6) { 2759 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2760 RBIOS16(offset + 0x5 + 0xb) * 4; 2761 tmp = RBIOS8(offset + 0x5 + 0xd); 2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2763 } else { 2764 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2765 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2766 if (entries && voltage_table_offset) { 2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2768 RBIOS16(voltage_table_offset) * 4; 2769 tmp = RBIOS8(voltage_table_offset + 0x2); 2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2771 } else 2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2773 } 2774 switch ((misc2 & 0x700) >> 8) { 2775 case 0: 2776 default: 2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2778 break; 2779 case 1: 2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2781 break; 2782 case 2: 2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2784 break; 2785 case 3: 2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2787 break; 2788 case 4: 2789 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2790 break; 2791 } 2792 } else 2793 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2794 if (rev > 6) 2795 rdev->pm.power_state[state_index].pcie_lanes = 2796 RBIOS8(offset + 0x5 + 0x10); 2797 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2798 state_index++; 2799 } else { 2800 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2801 } 2802 } else { 2803 /* XXX figure out some good default low power mode for desktop cards */ 2804 } 2805 2806 default_mode: 2807 /* add the default mode */ 2808 rdev->pm.power_state[state_index].type = 2809 POWER_STATE_TYPE_DEFAULT; 2810 rdev->pm.power_state[state_index].num_clock_modes = 1; 2811 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2812 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2813 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2814 if ((state_index > 0) && 2815 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2816 rdev->pm.power_state[state_index].clock_info[0].voltage = 2817 rdev->pm.power_state[0].clock_info[0].voltage; 2818 else 2819 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2820 rdev->pm.power_state[state_index].pcie_lanes = 16; 2821 rdev->pm.power_state[state_index].flags = 0; 2822 rdev->pm.default_power_state_index = state_index; 2823 rdev->pm.num_power_states = state_index + 1; 2824 2825 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2826 rdev->pm.current_clock_mode_index = 0; 2827 return; 2828 2829 pm_failed: 2830 rdev->pm.default_power_state_index = state_index; 2831 rdev->pm.num_power_states = 0; 2832 2833 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2834 rdev->pm.current_clock_mode_index = 0; 2835 } 2836 2837 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2838 { 2839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2840 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2841 2842 if (!tmds) 2843 return; 2844 2845 switch (tmds->dvo_chip) { 2846 case DVO_SIL164: 2847 /* sil 164 */ 2848 radeon_i2c_put_byte(tmds->i2c_bus, 2849 tmds->slave_addr, 2850 0x08, 0x30); 2851 radeon_i2c_put_byte(tmds->i2c_bus, 2852 tmds->slave_addr, 2853 0x09, 0x00); 2854 radeon_i2c_put_byte(tmds->i2c_bus, 2855 tmds->slave_addr, 2856 0x0a, 0x90); 2857 radeon_i2c_put_byte(tmds->i2c_bus, 2858 tmds->slave_addr, 2859 0x0c, 0x89); 2860 radeon_i2c_put_byte(tmds->i2c_bus, 2861 tmds->slave_addr, 2862 0x08, 0x3b); 2863 break; 2864 case DVO_SIL1178: 2865 /* sil 1178 - untested */ 2866 /* 2867 * 0x0f, 0x44 2868 * 0x0f, 0x4c 2869 * 0x0e, 0x01 2870 * 0x0a, 0x80 2871 * 0x09, 0x30 2872 * 0x0c, 0xc9 2873 * 0x0d, 0x70 2874 * 0x08, 0x32 2875 * 0x08, 0x33 2876 */ 2877 break; 2878 default: 2879 break; 2880 } 2881 2882 } 2883 2884 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2885 { 2886 struct drm_device *dev = encoder->dev; 2887 struct radeon_device *rdev = dev->dev_private; 2888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2889 uint16_t offset; 2890 uint8_t blocks, slave_addr, rev; 2891 uint32_t index, id; 2892 uint32_t reg, val, and_mask, or_mask; 2893 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2894 2895 if (!tmds) 2896 return false; 2897 2898 if (rdev->flags & RADEON_IS_IGP) { 2899 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2900 rev = RBIOS8(offset); 2901 if (offset) { 2902 rev = RBIOS8(offset); 2903 if (rev > 1) { 2904 blocks = RBIOS8(offset + 3); 2905 index = offset + 4; 2906 while (blocks > 0) { 2907 id = RBIOS16(index); 2908 index += 2; 2909 switch (id >> 13) { 2910 case 0: 2911 reg = (id & 0x1fff) * 4; 2912 val = RBIOS32(index); 2913 index += 4; 2914 WREG32(reg, val); 2915 break; 2916 case 2: 2917 reg = (id & 0x1fff) * 4; 2918 and_mask = RBIOS32(index); 2919 index += 4; 2920 or_mask = RBIOS32(index); 2921 index += 4; 2922 val = RREG32(reg); 2923 val = (val & and_mask) | or_mask; 2924 WREG32(reg, val); 2925 break; 2926 case 3: 2927 val = RBIOS16(index); 2928 index += 2; 2929 udelay(val); 2930 break; 2931 case 4: 2932 val = RBIOS16(index); 2933 index += 2; 2934 mdelay(val); 2935 break; 2936 case 6: 2937 slave_addr = id & 0xff; 2938 slave_addr >>= 1; /* 7 bit addressing */ 2939 index++; 2940 reg = RBIOS8(index); 2941 index++; 2942 val = RBIOS8(index); 2943 index++; 2944 radeon_i2c_put_byte(tmds->i2c_bus, 2945 slave_addr, 2946 reg, val); 2947 break; 2948 default: 2949 DRM_ERROR("Unknown id %d\n", id >> 13); 2950 break; 2951 } 2952 blocks--; 2953 } 2954 return true; 2955 } 2956 } 2957 } else { 2958 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2959 if (offset) { 2960 index = offset + 10; 2961 id = RBIOS16(index); 2962 while (id != 0xffff) { 2963 index += 2; 2964 switch (id >> 13) { 2965 case 0: 2966 reg = (id & 0x1fff) * 4; 2967 val = RBIOS32(index); 2968 WREG32(reg, val); 2969 break; 2970 case 2: 2971 reg = (id & 0x1fff) * 4; 2972 and_mask = RBIOS32(index); 2973 index += 4; 2974 or_mask = RBIOS32(index); 2975 index += 4; 2976 val = RREG32(reg); 2977 val = (val & and_mask) | or_mask; 2978 WREG32(reg, val); 2979 break; 2980 case 4: 2981 val = RBIOS16(index); 2982 index += 2; 2983 udelay(val); 2984 break; 2985 case 5: 2986 reg = id & 0x1fff; 2987 and_mask = RBIOS32(index); 2988 index += 4; 2989 or_mask = RBIOS32(index); 2990 index += 4; 2991 val = RREG32_PLL(reg); 2992 val = (val & and_mask) | or_mask; 2993 WREG32_PLL(reg, val); 2994 break; 2995 case 6: 2996 reg = id & 0x1fff; 2997 val = RBIOS8(index); 2998 index += 1; 2999 radeon_i2c_put_byte(tmds->i2c_bus, 3000 tmds->slave_addr, 3001 reg, val); 3002 break; 3003 default: 3004 DRM_ERROR("Unknown id %d\n", id >> 13); 3005 break; 3006 } 3007 id = RBIOS16(index); 3008 } 3009 return true; 3010 } 3011 } 3012 return false; 3013 } 3014 3015 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3016 { 3017 struct radeon_device *rdev = dev->dev_private; 3018 3019 if (offset) { 3020 while (RBIOS16(offset)) { 3021 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3022 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3023 uint32_t val, and_mask, or_mask; 3024 uint32_t tmp; 3025 3026 offset += 2; 3027 switch (cmd) { 3028 case 0: 3029 val = RBIOS32(offset); 3030 offset += 4; 3031 WREG32(addr, val); 3032 break; 3033 case 1: 3034 val = RBIOS32(offset); 3035 offset += 4; 3036 WREG32(addr, val); 3037 break; 3038 case 2: 3039 and_mask = RBIOS32(offset); 3040 offset += 4; 3041 or_mask = RBIOS32(offset); 3042 offset += 4; 3043 tmp = RREG32(addr); 3044 tmp &= and_mask; 3045 tmp |= or_mask; 3046 WREG32(addr, tmp); 3047 break; 3048 case 3: 3049 and_mask = RBIOS32(offset); 3050 offset += 4; 3051 or_mask = RBIOS32(offset); 3052 offset += 4; 3053 tmp = RREG32(addr); 3054 tmp &= and_mask; 3055 tmp |= or_mask; 3056 WREG32(addr, tmp); 3057 break; 3058 case 4: 3059 val = RBIOS16(offset); 3060 offset += 2; 3061 udelay(val); 3062 break; 3063 case 5: 3064 val = RBIOS16(offset); 3065 offset += 2; 3066 switch (addr) { 3067 case 8: 3068 while (val--) { 3069 if (! 3070 (RREG32_PLL 3071 (RADEON_CLK_PWRMGT_CNTL) & 3072 RADEON_MC_BUSY)) 3073 break; 3074 } 3075 break; 3076 case 9: 3077 while (val--) { 3078 if ((RREG32(RADEON_MC_STATUS) & 3079 RADEON_MC_IDLE)) 3080 break; 3081 } 3082 break; 3083 default: 3084 break; 3085 } 3086 break; 3087 default: 3088 break; 3089 } 3090 } 3091 } 3092 } 3093 3094 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3095 { 3096 struct radeon_device *rdev = dev->dev_private; 3097 3098 if (offset) { 3099 while (RBIOS8(offset)) { 3100 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3101 uint8_t addr = (RBIOS8(offset) & 0x3f); 3102 uint32_t val, shift, tmp; 3103 uint32_t and_mask, or_mask; 3104 3105 offset++; 3106 switch (cmd) { 3107 case 0: 3108 val = RBIOS32(offset); 3109 offset += 4; 3110 WREG32_PLL(addr, val); 3111 break; 3112 case 1: 3113 shift = RBIOS8(offset) * 8; 3114 offset++; 3115 and_mask = RBIOS8(offset) << shift; 3116 and_mask |= ~(0xff << shift); 3117 offset++; 3118 or_mask = RBIOS8(offset) << shift; 3119 offset++; 3120 tmp = RREG32_PLL(addr); 3121 tmp &= and_mask; 3122 tmp |= or_mask; 3123 WREG32_PLL(addr, tmp); 3124 break; 3125 case 2: 3126 case 3: 3127 tmp = 1000; 3128 switch (addr) { 3129 case 1: 3130 udelay(150); 3131 break; 3132 case 2: 3133 mdelay(1); 3134 break; 3135 case 3: 3136 while (tmp--) { 3137 if (! 3138 (RREG32_PLL 3139 (RADEON_CLK_PWRMGT_CNTL) & 3140 RADEON_MC_BUSY)) 3141 break; 3142 } 3143 break; 3144 case 4: 3145 while (tmp--) { 3146 if (RREG32_PLL 3147 (RADEON_CLK_PWRMGT_CNTL) & 3148 RADEON_DLL_READY) 3149 break; 3150 } 3151 break; 3152 case 5: 3153 tmp = 3154 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3155 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3156 #if 0 3157 uint32_t mclk_cntl = 3158 RREG32_PLL 3159 (RADEON_MCLK_CNTL); 3160 mclk_cntl &= 0xffff0000; 3161 /*mclk_cntl |= 0x00001111;*//* ??? */ 3162 WREG32_PLL(RADEON_MCLK_CNTL, 3163 mclk_cntl); 3164 mdelay(10); 3165 #endif 3166 WREG32_PLL 3167 (RADEON_CLK_PWRMGT_CNTL, 3168 tmp & 3169 ~RADEON_CG_NO1_DEBUG_0); 3170 mdelay(10); 3171 } 3172 break; 3173 default: 3174 break; 3175 } 3176 break; 3177 default: 3178 break; 3179 } 3180 } 3181 } 3182 } 3183 3184 static void combios_parse_ram_reset_table(struct drm_device *dev, 3185 uint16_t offset) 3186 { 3187 struct radeon_device *rdev = dev->dev_private; 3188 uint32_t tmp; 3189 3190 if (offset) { 3191 uint8_t val = RBIOS8(offset); 3192 while (val != 0xff) { 3193 offset++; 3194 3195 if (val == 0x0f) { 3196 uint32_t channel_complete_mask; 3197 3198 if (ASIC_IS_R300(rdev)) 3199 channel_complete_mask = 3200 R300_MEM_PWRUP_COMPLETE; 3201 else 3202 channel_complete_mask = 3203 RADEON_MEM_PWRUP_COMPLETE; 3204 tmp = 20000; 3205 while (tmp--) { 3206 if ((RREG32(RADEON_MEM_STR_CNTL) & 3207 channel_complete_mask) == 3208 channel_complete_mask) 3209 break; 3210 } 3211 } else { 3212 uint32_t or_mask = RBIOS16(offset); 3213 offset += 2; 3214 3215 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3216 tmp &= RADEON_SDRAM_MODE_MASK; 3217 tmp |= or_mask; 3218 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3219 3220 or_mask = val << 24; 3221 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3222 tmp &= RADEON_B3MEM_RESET_MASK; 3223 tmp |= or_mask; 3224 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3225 } 3226 val = RBIOS8(offset); 3227 } 3228 } 3229 } 3230 3231 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3232 int mem_addr_mapping) 3233 { 3234 struct radeon_device *rdev = dev->dev_private; 3235 uint32_t mem_cntl; 3236 uint32_t mem_size; 3237 uint32_t addr = 0; 3238 3239 mem_cntl = RREG32(RADEON_MEM_CNTL); 3240 if (mem_cntl & RV100_HALF_MODE) 3241 ram /= 2; 3242 mem_size = ram; 3243 mem_cntl &= ~(0xff << 8); 3244 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3245 WREG32(RADEON_MEM_CNTL, mem_cntl); 3246 RREG32(RADEON_MEM_CNTL); 3247 3248 /* sdram reset ? */ 3249 3250 /* something like this???? */ 3251 while (ram--) { 3252 addr = ram * 1024 * 1024; 3253 /* write to each page */ 3254 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3255 /* read back and verify */ 3256 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3257 return 0; 3258 } 3259 3260 return mem_size; 3261 } 3262 3263 static void combios_write_ram_size(struct drm_device *dev) 3264 { 3265 struct radeon_device *rdev = dev->dev_private; 3266 uint8_t rev; 3267 uint16_t offset; 3268 uint32_t mem_size = 0; 3269 uint32_t mem_cntl = 0; 3270 3271 /* should do something smarter here I guess... */ 3272 if (rdev->flags & RADEON_IS_IGP) 3273 return; 3274 3275 /* first check detected mem table */ 3276 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3277 if (offset) { 3278 rev = RBIOS8(offset); 3279 if (rev < 3) { 3280 mem_cntl = RBIOS32(offset + 1); 3281 mem_size = RBIOS16(offset + 5); 3282 if ((rdev->family < CHIP_R200) && 3283 !ASIC_IS_RN50(rdev)) 3284 WREG32(RADEON_MEM_CNTL, mem_cntl); 3285 } 3286 } 3287 3288 if (!mem_size) { 3289 offset = 3290 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3291 if (offset) { 3292 rev = RBIOS8(offset - 1); 3293 if (rev < 1) { 3294 if ((rdev->family < CHIP_R200) 3295 && !ASIC_IS_RN50(rdev)) { 3296 int ram = 0; 3297 int mem_addr_mapping = 0; 3298 3299 while (RBIOS8(offset)) { 3300 ram = RBIOS8(offset); 3301 mem_addr_mapping = 3302 RBIOS8(offset + 1); 3303 if (mem_addr_mapping != 0x25) 3304 ram *= 2; 3305 mem_size = 3306 combios_detect_ram(dev, ram, 3307 mem_addr_mapping); 3308 if (mem_size) 3309 break; 3310 offset += 2; 3311 } 3312 } else 3313 mem_size = RBIOS8(offset); 3314 } else { 3315 mem_size = RBIOS8(offset); 3316 mem_size *= 2; /* convert to MB */ 3317 } 3318 } 3319 } 3320 3321 mem_size *= (1024 * 1024); /* convert to bytes */ 3322 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3323 } 3324 3325 void radeon_combios_asic_init(struct drm_device *dev) 3326 { 3327 struct radeon_device *rdev = dev->dev_private; 3328 uint16_t table; 3329 3330 /* port hardcoded mac stuff from radeonfb */ 3331 if (rdev->bios == NULL) 3332 return; 3333 3334 /* ASIC INIT 1 */ 3335 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3336 if (table) 3337 combios_parse_mmio_table(dev, table); 3338 3339 /* PLL INIT */ 3340 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3341 if (table) 3342 combios_parse_pll_table(dev, table); 3343 3344 /* ASIC INIT 2 */ 3345 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3346 if (table) 3347 combios_parse_mmio_table(dev, table); 3348 3349 if (!(rdev->flags & RADEON_IS_IGP)) { 3350 /* ASIC INIT 4 */ 3351 table = 3352 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3353 if (table) 3354 combios_parse_mmio_table(dev, table); 3355 3356 /* RAM RESET */ 3357 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3358 if (table) 3359 combios_parse_ram_reset_table(dev, table); 3360 3361 /* ASIC INIT 3 */ 3362 table = 3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3364 if (table) 3365 combios_parse_mmio_table(dev, table); 3366 3367 /* write CONFIG_MEMSIZE */ 3368 combios_write_ram_size(dev); 3369 } 3370 3371 /* quirk for rs4xx HP nx6125 laptop to make it resume 3372 * - it hangs on resume inside the dynclk 1 table. 3373 */ 3374 if (rdev->family == CHIP_RS480 && 3375 rdev->pdev->subsystem_vendor == 0x103c && 3376 rdev->pdev->subsystem_device == 0x308b) 3377 return; 3378 3379 /* quirk for rs4xx HP dv5000 laptop to make it resume 3380 * - it hangs on resume inside the dynclk 1 table. 3381 */ 3382 if (rdev->family == CHIP_RS480 && 3383 rdev->pdev->subsystem_vendor == 0x103c && 3384 rdev->pdev->subsystem_device == 0x30a4) 3385 return; 3386 3387 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3388 * - it hangs on resume inside the dynclk 1 table. 3389 */ 3390 if (rdev->family == CHIP_RS480 && 3391 rdev->pdev->subsystem_vendor == 0x103c && 3392 rdev->pdev->subsystem_device == 0x30ae) 3393 return; 3394 3395 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3396 * - it hangs on resume inside the dynclk 1 table. 3397 */ 3398 if (rdev->family == CHIP_RS480 && 3399 rdev->pdev->subsystem_vendor == 0x103c && 3400 rdev->pdev->subsystem_device == 0x280a) 3401 return; 3402 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3403 * - it hangs on resume inside the dynclk 1 table. 3404 */ 3405 if (rdev->family == CHIP_RS400 && 3406 rdev->pdev->subsystem_vendor == 0x1179 && 3407 rdev->pdev->subsystem_device == 0xff31) 3408 return; 3409 3410 /* DYN CLK 1 */ 3411 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3412 if (table) 3413 combios_parse_pll_table(dev, table); 3414 3415 } 3416 3417 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3418 { 3419 struct radeon_device *rdev = dev->dev_private; 3420 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3421 3422 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3423 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3424 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3425 3426 /* let the bios control the backlight */ 3427 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3428 3429 /* tell the bios not to handle mode switching */ 3430 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3431 RADEON_ACC_MODE_CHANGE); 3432 3433 /* tell the bios a driver is loaded */ 3434 bios_7_scratch |= RADEON_DRV_LOADED; 3435 3436 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3437 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3438 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3439 } 3440 3441 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3442 { 3443 struct drm_device *dev = encoder->dev; 3444 struct radeon_device *rdev = dev->dev_private; 3445 uint32_t bios_6_scratch; 3446 3447 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3448 3449 if (lock) 3450 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3451 else 3452 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3453 3454 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3455 } 3456 3457 void 3458 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3459 struct drm_encoder *encoder, 3460 bool connected) 3461 { 3462 struct drm_device *dev = connector->dev; 3463 struct radeon_device *rdev = dev->dev_private; 3464 struct radeon_connector *radeon_connector = 3465 to_radeon_connector(connector); 3466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3467 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3468 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3469 3470 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3471 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3472 if (connected) { 3473 DRM_DEBUG_KMS("TV1 connected\n"); 3474 /* fix me */ 3475 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3476 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3477 bios_5_scratch |= RADEON_TV1_ON; 3478 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3479 } else { 3480 DRM_DEBUG_KMS("TV1 disconnected\n"); 3481 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3482 bios_5_scratch &= ~RADEON_TV1_ON; 3483 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3484 } 3485 } 3486 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3487 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3488 if (connected) { 3489 DRM_DEBUG_KMS("LCD1 connected\n"); 3490 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3491 bios_5_scratch |= RADEON_LCD1_ON; 3492 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3493 } else { 3494 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3495 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3496 bios_5_scratch &= ~RADEON_LCD1_ON; 3497 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3498 } 3499 } 3500 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3501 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3502 if (connected) { 3503 DRM_DEBUG_KMS("CRT1 connected\n"); 3504 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3505 bios_5_scratch |= RADEON_CRT1_ON; 3506 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3507 } else { 3508 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3509 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3510 bios_5_scratch &= ~RADEON_CRT1_ON; 3511 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3512 } 3513 } 3514 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3515 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3516 if (connected) { 3517 DRM_DEBUG_KMS("CRT2 connected\n"); 3518 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3519 bios_5_scratch |= RADEON_CRT2_ON; 3520 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3521 } else { 3522 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3523 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3524 bios_5_scratch &= ~RADEON_CRT2_ON; 3525 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3526 } 3527 } 3528 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3529 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3530 if (connected) { 3531 DRM_DEBUG_KMS("DFP1 connected\n"); 3532 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3533 bios_5_scratch |= RADEON_DFP1_ON; 3534 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3535 } else { 3536 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3537 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3538 bios_5_scratch &= ~RADEON_DFP1_ON; 3539 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3540 } 3541 } 3542 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3543 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3544 if (connected) { 3545 DRM_DEBUG_KMS("DFP2 connected\n"); 3546 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3547 bios_5_scratch |= RADEON_DFP2_ON; 3548 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3549 } else { 3550 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3551 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3552 bios_5_scratch &= ~RADEON_DFP2_ON; 3553 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3554 } 3555 } 3556 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3557 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3558 } 3559 3560 void 3561 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3562 { 3563 struct drm_device *dev = encoder->dev; 3564 struct radeon_device *rdev = dev->dev_private; 3565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3566 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3567 3568 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3569 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3570 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3571 } 3572 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3573 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3574 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3575 } 3576 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3577 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3578 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3579 } 3580 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3581 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3582 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3583 } 3584 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3585 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3586 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3587 } 3588 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3589 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3590 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3591 } 3592 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3593 } 3594 3595 void 3596 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3597 { 3598 struct drm_device *dev = encoder->dev; 3599 struct radeon_device *rdev = dev->dev_private; 3600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3601 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3602 3603 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3604 if (on) 3605 bios_6_scratch |= RADEON_TV_DPMS_ON; 3606 else 3607 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3608 } 3609 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3610 if (on) 3611 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3612 else 3613 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3614 } 3615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3616 if (on) 3617 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3618 else 3619 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3620 } 3621 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3622 if (on) 3623 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3624 else 3625 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3626 } 3627 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3628 } 3629
Indexes created Wed Oct 22 13:09:56 GMT 2025