radeon_drv.c revision 1.1.1.2
1 /* $NetBSD: radeon_drv.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $ */ 2 3 /** 4 * \file radeon_drv.c 5 * ATI Radeon driver 6 * 7 * \author Gareth Hughes <gareth (at) valinux.com> 8 */ 9 10 /* 11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 12 * All Rights Reserved. 13 * 14 * Permission is hereby granted, free of charge, to any person obtaining a 15 * copy of this software and associated documentation files (the "Software"), 16 * to deal in the Software without restriction, including without limitation 17 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 18 * and/or sell copies of the Software, and to permit persons to whom the 19 * Software is furnished to do so, subject to the following conditions: 20 * 21 * The above copyright notice and this permission notice (including the next 22 * paragraph) shall be included in all copies or substantial portions of the 23 * Software. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 31 * OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: radeon_drv.c,v 1.1.1.2 2018/08/27 01:34:58 riastradh Exp $"); 36 37 #include <drm/drmP.h> 38 #include <drm/radeon_drm.h> 39 #include "radeon_drv.h" 40 41 #include <drm/drm_pciids.h> 42 #include <linux/console.h> 43 #include <linux/module.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/vga_switcheroo.h> 46 #include <drm/drm_gem.h> 47 48 #include "drm_crtc_helper.h" 49 #include "radeon_kfd.h" 50 51 /* 52 * KMS wrapper. 53 * - 2.0.0 - initial interface 54 * - 2.1.0 - add square tiling interface 55 * - 2.2.0 - add r6xx/r7xx const buffer support 56 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 57 * - 2.4.0 - add crtc id query 58 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 59 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 60 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 61 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 62 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 63 * 2.10.0 - fusion 2D tiling 64 * 2.11.0 - backend map, initial compute support for the CS checker 65 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 66 * 2.13.0 - virtual memory support, streamout 67 * 2.14.0 - add evergreen tiling informations 68 * 2.15.0 - add max_pipes query 69 * 2.16.0 - fix evergreen 2D tiled surface calculation 70 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 71 * 2.18.0 - r600-eg: allow "invalid" DB formats 72 * 2.19.0 - r600-eg: MSAA textures 73 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 74 * 2.21.0 - r600-r700: FMASK and CMASK 75 * 2.22.0 - r600 only: RESOLVE_BOX allowed 76 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 77 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 78 * 2.25.0 - eg+: new info request for num SE and num SH 79 * 2.26.0 - r600-eg: fix htile size computation 80 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 81 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 82 * 2.29.0 - R500 FP16 color clear registers 83 * 2.30.0 - fix for FMASK texturing 84 * 2.31.0 - Add fastfb support for rs690 85 * 2.32.0 - new info request for rings working 86 * 2.33.0 - Add SI tiling mode array query 87 * 2.34.0 - Add CIK tiling mode array query 88 * 2.35.0 - Add CIK macrotile mode array query 89 * 2.36.0 - Fix CIK DCE tiling setup 90 * 2.37.0 - allow GS ring setup on r6xx/r7xx 91 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 92 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 93 * 2.39.0 - Add INFO query for number of active CUs 94 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 95 * CS to GPU on >= r600 96 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 97 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 98 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 99 */ 100 #define KMS_DRIVER_MAJOR 2 101 #define KMS_DRIVER_MINOR 43 102 #define KMS_DRIVER_PATCHLEVEL 0 103 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 104 int radeon_driver_unload_kms(struct drm_device *dev); 105 void radeon_driver_lastclose_kms(struct drm_device *dev); 106 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 107 void radeon_driver_postclose_kms(struct drm_device *dev, 108 struct drm_file *file_priv); 109 void radeon_driver_preclose_kms(struct drm_device *dev, 110 struct drm_file *file_priv); 111 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 112 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 113 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 114 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 115 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 116 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 117 int *max_error, 118 struct timeval *vblank_time, 119 unsigned flags); 120 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 121 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 122 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 123 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 124 void radeon_gem_object_free(struct drm_gem_object *obj); 125 int radeon_gem_object_open(struct drm_gem_object *obj, 126 struct drm_file *file_priv); 127 void radeon_gem_object_close(struct drm_gem_object *obj, 128 struct drm_file *file_priv); 129 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 130 struct drm_gem_object *gobj, 131 int flags); 132 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 133 unsigned int flags, int *vpos, int *hpos, 134 ktime_t *stime, ktime_t *etime, 135 const struct drm_display_mode *mode); 136 extern bool radeon_is_px(struct drm_device *dev); 137 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 138 extern int radeon_max_kms_ioctl; 139 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 140 int radeon_mode_dumb_mmap(struct drm_file *filp, 141 struct drm_device *dev, 142 uint32_t handle, uint64_t *offset_p); 143 int radeon_mode_dumb_create(struct drm_file *file_priv, 144 struct drm_device *dev, 145 struct drm_mode_create_dumb *args); 146 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 147 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 148 struct dma_buf_attachment *, 149 struct sg_table *sg); 150 int radeon_gem_prime_pin(struct drm_gem_object *obj); 151 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 152 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 153 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 154 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 155 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 156 unsigned long arg); 157 158 #if defined(CONFIG_DEBUG_FS) 159 int radeon_debugfs_init(struct drm_minor *minor); 160 void radeon_debugfs_cleanup(struct drm_minor *minor); 161 #endif 162 163 /* atpx handler */ 164 #if defined(CONFIG_VGA_SWITCHEROO) 165 void radeon_register_atpx_handler(void); 166 void radeon_unregister_atpx_handler(void); 167 #else 168 static inline void radeon_register_atpx_handler(void) {} 169 static inline void radeon_unregister_atpx_handler(void) {} 170 #endif 171 172 int radeon_no_wb; 173 int radeon_modeset = -1; 174 int radeon_dynclks = -1; 175 int radeon_r4xx_atom = 0; 176 int radeon_agpmode = 0; 177 int radeon_vram_limit = 0; 178 int radeon_gart_size = -1; /* auto */ 179 int radeon_benchmarking = 0; 180 int radeon_testing = 0; 181 int radeon_connector_table = 0; 182 int radeon_tv = 1; 183 int radeon_audio = -1; 184 int radeon_disp_priority = 0; 185 int radeon_hw_i2c = 0; 186 int radeon_pcie_gen2 = -1; 187 int radeon_msi = -1; 188 int radeon_lockup_timeout = 10000; 189 int radeon_fastfb = 0; 190 int radeon_dpm = -1; 191 int radeon_aspm = -1; 192 int radeon_runtime_pm = -1; 193 int radeon_hard_reset = 0; 194 int radeon_vm_size = 8; 195 int radeon_vm_block_size = -1; 196 int radeon_deep_color = 0; 197 int radeon_use_pflipirq = 2; 198 int radeon_bapm = -1; 199 int radeon_backlight = -1; 200 int radeon_auxch = -1; 201 int radeon_mst = 0; 202 203 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 204 module_param_named(no_wb, radeon_no_wb, int, 0444); 205 206 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 207 module_param_named(modeset, radeon_modeset, int, 0400); 208 209 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 210 module_param_named(dynclks, radeon_dynclks, int, 0444); 211 212 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 213 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 214 215 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 216 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 217 218 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 219 module_param_named(agpmode, radeon_agpmode, int, 0444); 220 221 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 222 module_param_named(gartsize, radeon_gart_size, int, 0600); 223 224 MODULE_PARM_DESC(benchmark, "Run benchmark"); 225 module_param_named(benchmark, radeon_benchmarking, int, 0444); 226 227 MODULE_PARM_DESC(test, "Run tests"); 228 module_param_named(test, radeon_testing, int, 0444); 229 230 MODULE_PARM_DESC(connector_table, "Force connector table"); 231 module_param_named(connector_table, radeon_connector_table, int, 0444); 232 233 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 234 module_param_named(tv, radeon_tv, int, 0444); 235 236 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 237 module_param_named(audio, radeon_audio, int, 0444); 238 239 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 240 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 241 242 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 243 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 244 245 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 246 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 247 248 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 249 module_param_named(msi, radeon_msi, int, 0444); 250 251 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 252 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 253 254 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 255 module_param_named(fastfb, radeon_fastfb, int, 0444); 256 257 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 258 module_param_named(dpm, radeon_dpm, int, 0444); 259 260 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 261 module_param_named(aspm, radeon_aspm, int, 0444); 262 263 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 264 module_param_named(runpm, radeon_runtime_pm, int, 0444); 265 266 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 267 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 268 269 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 270 module_param_named(vm_size, radeon_vm_size, int, 0444); 271 272 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 273 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 274 275 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 276 module_param_named(deep_color, radeon_deep_color, int, 0444); 277 278 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 279 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 280 281 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 282 module_param_named(bapm, radeon_bapm, int, 0444); 283 284 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 285 module_param_named(backlight, radeon_backlight, int, 0444); 286 287 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 288 module_param_named(auxch, radeon_auxch, int, 0444); 289 290 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 291 module_param_named(mst, radeon_mst, int, 0444); 292 293 static struct pci_device_id pciidlist[] = { 294 radeon_PCI_IDS 295 }; 296 297 MODULE_DEVICE_TABLE(pci, pciidlist); 298 299 #ifdef CONFIG_DRM_RADEON_UMS 300 301 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 302 { 303 drm_radeon_private_t *dev_priv = dev->dev_private; 304 305 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 306 return 0; 307 308 /* Disable *all* interrupts */ 309 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 310 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 311 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 312 return 0; 313 } 314 315 static int radeon_resume(struct drm_device *dev) 316 { 317 drm_radeon_private_t *dev_priv = dev->dev_private; 318 319 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 320 return 0; 321 322 /* Restore interrupt registers */ 323 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 324 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 325 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 326 return 0; 327 } 328 329 330 static const struct file_operations radeon_driver_old_fops = { 331 .owner = THIS_MODULE, 332 .open = drm_open, 333 .release = drm_release, 334 .unlocked_ioctl = drm_ioctl, 335 .mmap = drm_legacy_mmap, 336 .poll = drm_poll, 337 .read = drm_read, 338 #ifdef CONFIG_COMPAT 339 .compat_ioctl = radeon_compat_ioctl, 340 #endif 341 .llseek = noop_llseek, 342 }; 343 344 static struct drm_driver driver_old = { 345 .driver_features = 346 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 347 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 348 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 349 .load = radeon_driver_load, 350 .firstopen = radeon_driver_firstopen, 351 .open = radeon_driver_open, 352 .preclose = radeon_driver_preclose, 353 .postclose = radeon_driver_postclose, 354 .lastclose = radeon_driver_lastclose, 355 .set_busid = drm_pci_set_busid, 356 .unload = radeon_driver_unload, 357 .suspend = radeon_suspend, 358 .resume = radeon_resume, 359 .get_vblank_counter = radeon_get_vblank_counter, 360 .enable_vblank = radeon_enable_vblank, 361 .disable_vblank = radeon_disable_vblank, 362 .master_create = radeon_master_create, 363 .master_destroy = radeon_master_destroy, 364 .irq_preinstall = radeon_driver_irq_preinstall, 365 .irq_postinstall = radeon_driver_irq_postinstall, 366 .irq_uninstall = radeon_driver_irq_uninstall, 367 .irq_handler = radeon_driver_irq_handler, 368 .ioctls = radeon_ioctls, 369 .dma_ioctl = radeon_cp_buffers, 370 .fops = &radeon_driver_old_fops, 371 .name = DRIVER_NAME, 372 .desc = DRIVER_DESC, 373 .date = DRIVER_DATE, 374 .major = DRIVER_MAJOR, 375 .minor = DRIVER_MINOR, 376 .patchlevel = DRIVER_PATCHLEVEL, 377 }; 378 379 #endif 380 381 static struct drm_driver kms_driver; 382 383 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 384 { 385 struct apertures_struct *ap; 386 bool primary = false; 387 388 ap = alloc_apertures(1); 389 if (!ap) 390 return -ENOMEM; 391 392 ap->ranges[0].base = pci_resource_start(pdev, 0); 393 ap->ranges[0].size = pci_resource_len(pdev, 0); 394 395 #ifdef CONFIG_X86 396 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 397 #endif 398 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 399 kfree(ap); 400 401 return 0; 402 } 403 404 static int radeon_pci_probe(struct pci_dev *pdev, 405 const struct pci_device_id *ent) 406 { 407 int ret; 408 409 /* Get rid of things like offb */ 410 ret = radeon_kick_out_firmware_fb(pdev); 411 if (ret) 412 return ret; 413 414 return drm_get_pci_dev(pdev, ent, &kms_driver); 415 } 416 417 static void 418 radeon_pci_remove(struct pci_dev *pdev) 419 { 420 struct drm_device *dev = pci_get_drvdata(pdev); 421 422 drm_put_dev(dev); 423 } 424 425 static int radeon_pmops_suspend(struct device *dev) 426 { 427 struct pci_dev *pdev = to_pci_dev(dev); 428 struct drm_device *drm_dev = pci_get_drvdata(pdev); 429 return radeon_suspend_kms(drm_dev, true, true); 430 } 431 432 static int radeon_pmops_resume(struct device *dev) 433 { 434 struct pci_dev *pdev = to_pci_dev(dev); 435 struct drm_device *drm_dev = pci_get_drvdata(pdev); 436 return radeon_resume_kms(drm_dev, true, true); 437 } 438 439 static int radeon_pmops_freeze(struct device *dev) 440 { 441 struct pci_dev *pdev = to_pci_dev(dev); 442 struct drm_device *drm_dev = pci_get_drvdata(pdev); 443 return radeon_suspend_kms(drm_dev, false, true); 444 } 445 446 static int radeon_pmops_thaw(struct device *dev) 447 { 448 struct pci_dev *pdev = to_pci_dev(dev); 449 struct drm_device *drm_dev = pci_get_drvdata(pdev); 450 return radeon_resume_kms(drm_dev, false, true); 451 } 452 453 static int radeon_pmops_runtime_suspend(struct device *dev) 454 { 455 struct pci_dev *pdev = to_pci_dev(dev); 456 struct drm_device *drm_dev = pci_get_drvdata(pdev); 457 int ret; 458 459 if (!radeon_is_px(drm_dev)) { 460 pm_runtime_forbid(dev); 461 return -EBUSY; 462 } 463 464 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 465 drm_kms_helper_poll_disable(drm_dev); 466 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 467 468 ret = radeon_suspend_kms(drm_dev, false, false); 469 pci_save_state(pdev); 470 pci_disable_device(pdev); 471 pci_ignore_hotplug(pdev); 472 pci_set_power_state(pdev, PCI_D3cold); 473 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 474 475 return 0; 476 } 477 478 static int radeon_pmops_runtime_resume(struct device *dev) 479 { 480 struct pci_dev *pdev = to_pci_dev(dev); 481 struct drm_device *drm_dev = pci_get_drvdata(pdev); 482 int ret; 483 484 if (!radeon_is_px(drm_dev)) 485 return -EINVAL; 486 487 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 488 489 pci_set_power_state(pdev, PCI_D0); 490 pci_restore_state(pdev); 491 ret = pci_enable_device(pdev); 492 if (ret) 493 return ret; 494 pci_set_master(pdev); 495 496 ret = radeon_resume_kms(drm_dev, false, false); 497 drm_kms_helper_poll_enable(drm_dev); 498 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 499 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 500 return 0; 501 } 502 503 static int radeon_pmops_runtime_idle(struct device *dev) 504 { 505 struct pci_dev *pdev = to_pci_dev(dev); 506 struct drm_device *drm_dev = pci_get_drvdata(pdev); 507 struct drm_crtc *crtc; 508 509 if (!radeon_is_px(drm_dev)) { 510 pm_runtime_forbid(dev); 511 return -EBUSY; 512 } 513 514 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 515 if (crtc->enabled) { 516 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 517 return -EBUSY; 518 } 519 } 520 521 pm_runtime_mark_last_busy(dev); 522 pm_runtime_autosuspend(dev); 523 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 524 return 1; 525 } 526 527 long radeon_drm_ioctl(struct file *filp, 528 unsigned int cmd, unsigned long arg) 529 { 530 struct drm_file *file_priv = filp->private_data; 531 struct drm_device *dev; 532 long ret; 533 dev = file_priv->minor->dev; 534 ret = pm_runtime_get_sync(dev->dev); 535 if (ret < 0) 536 return ret; 537 538 ret = drm_ioctl(filp, cmd, arg); 539 540 pm_runtime_mark_last_busy(dev->dev); 541 pm_runtime_put_autosuspend(dev->dev); 542 return ret; 543 } 544 545 static const struct dev_pm_ops radeon_pm_ops = { 546 .suspend = radeon_pmops_suspend, 547 .resume = radeon_pmops_resume, 548 .freeze = radeon_pmops_freeze, 549 .thaw = radeon_pmops_thaw, 550 .poweroff = radeon_pmops_freeze, 551 .restore = radeon_pmops_resume, 552 .runtime_suspend = radeon_pmops_runtime_suspend, 553 .runtime_resume = radeon_pmops_runtime_resume, 554 .runtime_idle = radeon_pmops_runtime_idle, 555 }; 556 557 static const struct file_operations radeon_driver_kms_fops = { 558 .owner = THIS_MODULE, 559 .open = drm_open, 560 .release = drm_release, 561 .unlocked_ioctl = radeon_drm_ioctl, 562 .mmap = radeon_mmap, 563 .poll = drm_poll, 564 .read = drm_read, 565 #ifdef CONFIG_COMPAT 566 .compat_ioctl = radeon_kms_compat_ioctl, 567 #endif 568 }; 569 570 static struct drm_driver kms_driver = { 571 .driver_features = 572 DRIVER_USE_AGP | 573 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 574 DRIVER_PRIME | DRIVER_RENDER, 575 .load = radeon_driver_load_kms, 576 .open = radeon_driver_open_kms, 577 .preclose = radeon_driver_preclose_kms, 578 .postclose = radeon_driver_postclose_kms, 579 .lastclose = radeon_driver_lastclose_kms, 580 .set_busid = drm_pci_set_busid, 581 .unload = radeon_driver_unload_kms, 582 .get_vblank_counter = radeon_get_vblank_counter_kms, 583 .enable_vblank = radeon_enable_vblank_kms, 584 .disable_vblank = radeon_disable_vblank_kms, 585 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 586 .get_scanout_position = radeon_get_crtc_scanoutpos, 587 #if defined(CONFIG_DEBUG_FS) 588 .debugfs_init = radeon_debugfs_init, 589 .debugfs_cleanup = radeon_debugfs_cleanup, 590 #endif 591 .irq_preinstall = radeon_driver_irq_preinstall_kms, 592 .irq_postinstall = radeon_driver_irq_postinstall_kms, 593 .irq_uninstall = radeon_driver_irq_uninstall_kms, 594 .irq_handler = radeon_driver_irq_handler_kms, 595 .ioctls = radeon_ioctls_kms, 596 .gem_free_object = radeon_gem_object_free, 597 .gem_open_object = radeon_gem_object_open, 598 .gem_close_object = radeon_gem_object_close, 599 .dumb_create = radeon_mode_dumb_create, 600 .dumb_map_offset = radeon_mode_dumb_mmap, 601 .dumb_destroy = drm_gem_dumb_destroy, 602 .fops = &radeon_driver_kms_fops, 603 604 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 605 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 606 .gem_prime_export = radeon_gem_prime_export, 607 .gem_prime_import = drm_gem_prime_import, 608 .gem_prime_pin = radeon_gem_prime_pin, 609 .gem_prime_unpin = radeon_gem_prime_unpin, 610 .gem_prime_res_obj = radeon_gem_prime_res_obj, 611 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 612 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 613 .gem_prime_vmap = radeon_gem_prime_vmap, 614 .gem_prime_vunmap = radeon_gem_prime_vunmap, 615 616 .name = DRIVER_NAME, 617 .desc = DRIVER_DESC, 618 .date = DRIVER_DATE, 619 .major = KMS_DRIVER_MAJOR, 620 .minor = KMS_DRIVER_MINOR, 621 .patchlevel = KMS_DRIVER_PATCHLEVEL, 622 }; 623 624 static struct drm_driver *driver; 625 static struct pci_driver *pdriver; 626 627 #ifdef CONFIG_DRM_RADEON_UMS 628 static struct pci_driver radeon_pci_driver = { 629 .name = DRIVER_NAME, 630 .id_table = pciidlist, 631 }; 632 #endif 633 634 static struct pci_driver radeon_kms_pci_driver = { 635 .name = DRIVER_NAME, 636 .id_table = pciidlist, 637 .probe = radeon_pci_probe, 638 .remove = radeon_pci_remove, 639 .driver.pm = &radeon_pm_ops, 640 }; 641 642 static int __init radeon_init(void) 643 { 644 #ifdef CONFIG_VGA_CONSOLE 645 if (vgacon_text_force() && radeon_modeset == -1) { 646 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 647 radeon_modeset = 0; 648 } 649 #endif 650 /* set to modesetting by default if not nomodeset */ 651 if (radeon_modeset == -1) 652 radeon_modeset = 1; 653 654 if (radeon_modeset == 1) { 655 DRM_INFO("radeon kernel modesetting enabled.\n"); 656 driver = &kms_driver; 657 pdriver = &radeon_kms_pci_driver; 658 driver->driver_features |= DRIVER_MODESET; 659 driver->num_ioctls = radeon_max_kms_ioctl; 660 radeon_register_atpx_handler(); 661 662 } else { 663 #ifdef CONFIG_DRM_RADEON_UMS 664 DRM_INFO("radeon userspace modesetting enabled.\n"); 665 driver = &driver_old; 666 pdriver = &radeon_pci_driver; 667 driver->driver_features &= ~DRIVER_MODESET; 668 driver->num_ioctls = radeon_max_ioctl; 669 #else 670 DRM_ERROR("No UMS support in radeon module!\n"); 671 return -EINVAL; 672 #endif 673 } 674 675 radeon_kfd_init(); 676 677 /* let modprobe override vga console setting */ 678 return drm_pci_init(driver, pdriver); 679 } 680 681 static void __exit radeon_exit(void) 682 { 683 radeon_kfd_fini(); 684 drm_pci_exit(driver, pdriver); 685 radeon_unregister_atpx_handler(); 686 } 687 688 module_init(radeon_init); 689 module_exit(radeon_exit); 690 691 MODULE_AUTHOR(DRIVER_AUTHOR); 692 MODULE_DESCRIPTION(DRIVER_DESC); 693 MODULE_LICENSE("GPL and additional rights"); 694
Indexes created Mon Oct 20 20:10:13 GMT 2025